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You searched for subject:(Full adder). Showing records 1 – 4 of 4 total matches.

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King Abdullah University of Science and Technology

1. Ahmed, Sally. Micro-electromechanical Resonator-based Logic and Interface Circuits for Low Power Applications.

Degree: Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division, 2020, King Abdullah University of Science and Technology

 The notion of mechanical computation has been revived in the past few years, with the advances of nanofabrication techniques. Although electromechanical devices are inherently slow,… (more)

Subjects/Keywords: MEMS Resonators; Mechancial Computing; Logic Gates; Full Adder; Data Converters; Low-power Design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ahmed, S. (2020). Micro-electromechanical Resonator-based Logic and Interface Circuits for Low Power Applications. (Thesis). King Abdullah University of Science and Technology. Retrieved from http://hdl.handle.net/10754/666035

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ahmed, Sally. “Micro-electromechanical Resonator-based Logic and Interface Circuits for Low Power Applications.” 2020. Thesis, King Abdullah University of Science and Technology. Accessed March 08, 2021. http://hdl.handle.net/10754/666035.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ahmed, Sally. “Micro-electromechanical Resonator-based Logic and Interface Circuits for Low Power Applications.” 2020. Web. 08 Mar 2021.

Vancouver:

Ahmed S. Micro-electromechanical Resonator-based Logic and Interface Circuits for Low Power Applications. [Internet] [Thesis]. King Abdullah University of Science and Technology; 2020. [cited 2021 Mar 08]. Available from: http://hdl.handle.net/10754/666035.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ahmed S. Micro-electromechanical Resonator-based Logic and Interface Circuits for Low Power Applications. [Thesis]. King Abdullah University of Science and Technology; 2020. Available from: http://hdl.handle.net/10754/666035

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Linköping University

2. Tesanovic, Goran. Performance Analysis and Implementation of Full Adder Cells Using 0.18 um CMOS Technology.

Degree: Electrical Engineering, 2003, Linköping University

  0.18 um CMOS technology is increasingly used in design and implementation of full adder cells. Hence, there is a need for better understanding of… (more)

Subjects/Keywords: Electronics; CMOS; full-adder cell; time-delay; power dissipation; performance; Elektronik; Electronics; Elektronik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tesanovic, G. (2003). Performance Analysis and Implementation of Full Adder Cells Using 0.18 um CMOS Technology. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2111

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tesanovic, Goran. “Performance Analysis and Implementation of Full Adder Cells Using 0.18 um CMOS Technology.” 2003. Thesis, Linköping University. Accessed March 08, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2111.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tesanovic, Goran. “Performance Analysis and Implementation of Full Adder Cells Using 0.18 um CMOS Technology.” 2003. Web. 08 Mar 2021.

Vancouver:

Tesanovic G. Performance Analysis and Implementation of Full Adder Cells Using 0.18 um CMOS Technology. [Internet] [Thesis]. Linköping University; 2003. [cited 2021 Mar 08]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2111.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tesanovic G. Performance Analysis and Implementation of Full Adder Cells Using 0.18 um CMOS Technology. [Thesis]. Linköping University; 2003. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2111

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

3. CHANDRASEKARAN RAJASEKARAN. The development of building block circuits for high-speed decimation filters.

Degree: 2006, National University of Singapore

Subjects/Keywords: CMOS; Differential logic; Decimation filter; Full adder; Flip-Flop; RF digitization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

RAJASEKARAN, C. (2006). The development of building block circuits for high-speed decimation filters. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/15333

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

RAJASEKARAN, CHANDRASEKARAN. “The development of building block circuits for high-speed decimation filters.” 2006. Thesis, National University of Singapore. Accessed March 08, 2021. http://scholarbank.nus.edu.sg/handle/10635/15333.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

RAJASEKARAN, CHANDRASEKARAN. “The development of building block circuits for high-speed decimation filters.” 2006. Web. 08 Mar 2021.

Vancouver:

RAJASEKARAN C. The development of building block circuits for high-speed decimation filters. [Internet] [Thesis]. National University of Singapore; 2006. [cited 2021 Mar 08]. Available from: http://scholarbank.nus.edu.sg/handle/10635/15333.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

RAJASEKARAN C. The development of building block circuits for high-speed decimation filters. [Thesis]. National University of Singapore; 2006. Available from: http://scholarbank.nus.edu.sg/handle/10635/15333

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety… (more)

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

…ERC End Result Check FA Full Adder FPGA Field Programmable Gate Array FSM Finite… …Unit HA Half Adder HH Hybrid Hashing HLS High-Level Synthesis, also known as behavioral… …P&R Place and Route PSV Post-Silicon Validation QA Quarter Adder QED Quick Error… …silicon validation at full hardware speed. 3.1.1 Hybrid Tracing Prior works such as [15… …for a 32-bit adder [39]) associated with parity prediction across functional… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 08, 2021. http://hdl.handle.net/2142/99294.

MLA Handbook (7th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 08 Mar 2021.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 08]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294

.