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You searched for subject:(Fpga). Showing records 1 – 30 of 2575 total matches.

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University of Debrecen

1. Kistóth, Béla. FPGA programozás (neurális hálózatmodellezés) .

Degree: DE – TEK – Informatikai Kar, 2013, University of Debrecen

 Első körben C-ben írtam meg a Back Propagation algoritmust, egy egyszerű példa alapján. Ezután következett egy XOR betanítása. Itt már előjött sokszor a lokális minimum… (more)

Subjects/Keywords: FPGA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kistóth, B. (2013). FPGA programozás (neurális hálózatmodellezés) . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/156449

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kistóth, Béla. “FPGA programozás (neurális hálózatmodellezés) .” 2013. Thesis, University of Debrecen. Accessed December 01, 2020. http://hdl.handle.net/2437/156449.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kistóth, Béla. “FPGA programozás (neurális hálózatmodellezés) .” 2013. Web. 01 Dec 2020.

Vancouver:

Kistóth B. FPGA programozás (neurális hálózatmodellezés) . [Internet] [Thesis]. University of Debrecen; 2013. [cited 2020 Dec 01]. Available from: http://hdl.handle.net/2437/156449.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kistóth B. FPGA programozás (neurális hálózatmodellezés) . [Thesis]. University of Debrecen; 2013. Available from: http://hdl.handle.net/2437/156449

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. 伊藤, 渓太. FPGA向けアプリケーション依存テストのためのメモリ・ブロックを用いたスキャンBISTアーキテクチャ : Memory Block Based Scan-BIST Architecture for Application-Dependent FPGA Testing; FPGAムケ アプリケーション イゾン テスト ノ タメ ノ メモリ ブロック オ モチイタ スキャン BIST アーキテクチャ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: FPGA

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APA (6th Edition):

伊藤, . (n.d.). FPGA向けアプリケーション依存テストのためのメモリ・ブロックを用いたスキャンBISTアーキテクチャ : Memory Block Based Scan-BIST Architecture for Application-Dependent FPGA Testing; FPGAムケ アプリケーション イゾン テスト ノ タメ ノ メモリ ブロック オ モチイタ スキャン BIST アーキテクチャ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/9363

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

伊藤, 渓太. “FPGA向けアプリケーション依存テストのためのメモリ・ブロックを用いたスキャンBISTアーキテクチャ : Memory Block Based Scan-BIST Architecture for Application-Dependent FPGA Testing; FPGAムケ アプリケーション イゾン テスト ノ タメ ノ メモリ ブロック オ モチイタ スキャン BIST アーキテクチャ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed December 01, 2020. http://hdl.handle.net/10061/9363.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

伊藤, 渓太. “FPGA向けアプリケーション依存テストのためのメモリ・ブロックを用いたスキャンBISTアーキテクチャ : Memory Block Based Scan-BIST Architecture for Application-Dependent FPGA Testing; FPGAムケ アプリケーション イゾン テスト ノ タメ ノ メモリ ブロック オ モチイタ スキャン BIST アーキテクチャ.” Web. 01 Dec 2020.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

伊藤 . FPGA向けアプリケーション依存テストのためのメモリ・ブロックを用いたスキャンBISTアーキテクチャ : Memory Block Based Scan-BIST Architecture for Application-Dependent FPGA Testing; FPGAムケ アプリケーション イゾン テスト ノ タメ ノ メモリ ブロック オ モチイタ スキャン BIST アーキテクチャ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2020 Dec 01]. Available from: http://hdl.handle.net/10061/9363.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

伊藤 . FPGA向けアプリケーション依存テストのためのメモリ・ブロックを用いたスキャンBISTアーキテクチャ : Memory Block Based Scan-BIST Architecture for Application-Dependent FPGA Testing; FPGAムケ アプリケーション イゾン テスト ノ タメ ノ メモリ ブロック オ モチイタ スキャン BIST アーキテクチャ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/9363

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


Universidade do Porto

3. Costa, Tiago José Rocha Alves da. Methods for dynamic identification of program control-flow structures for FPGA-based systems.

Degree: 2009, Universidade do Porto

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major Telecomunicações). Faculdade de Engenharia. Universidade do Porto. 2009 Advisors/Committee Members: Cardoso, João Manuel Paiva, Ferreira, João Paulo de Castro Canas, Universidade do Porto. Faculdade de Engenharia.

Subjects/Keywords: Plataformas FPGA

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APA (6th Edition):

Costa, T. J. R. A. d. (2009). Methods for dynamic identification of program control-flow structures for FPGA-based systems. (Thesis). Universidade do Porto. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/58215

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Costa, Tiago José Rocha Alves da. “Methods for dynamic identification of program control-flow structures for FPGA-based systems.” 2009. Thesis, Universidade do Porto. Accessed December 01, 2020. http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/58215.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Costa, Tiago José Rocha Alves da. “Methods for dynamic identification of program control-flow structures for FPGA-based systems.” 2009. Web. 01 Dec 2020.

Vancouver:

Costa TJRAd. Methods for dynamic identification of program control-flow structures for FPGA-based systems. [Internet] [Thesis]. Universidade do Porto; 2009. [cited 2020 Dec 01]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/58215.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Costa TJRAd. Methods for dynamic identification of program control-flow structures for FPGA-based systems. [Thesis]. Universidade do Porto; 2009. Available from: http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/58215

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

4. Lin, Yen-Ju. FPGA-Based Cascade Support Vector Machine with Integrated Training.

Degree: MS, Computer Engineering, 2016, Texas A&M University

 Machine learning algorithms allow us to reason about and analyze large amounts of data. The support vector machine (SVM) is one popular learning algorithm, which… (more)

Subjects/Keywords: SVM; FPGA

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APA (6th Edition):

Lin, Y. (2016). FPGA-Based Cascade Support Vector Machine with Integrated Training. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/157764

Chicago Manual of Style (16th Edition):

Lin, Yen-Ju. “FPGA-Based Cascade Support Vector Machine with Integrated Training.” 2016. Masters Thesis, Texas A&M University. Accessed December 01, 2020. http://hdl.handle.net/1969.1/157764.

MLA Handbook (7th Edition):

Lin, Yen-Ju. “FPGA-Based Cascade Support Vector Machine with Integrated Training.” 2016. Web. 01 Dec 2020.

Vancouver:

Lin Y. FPGA-Based Cascade Support Vector Machine with Integrated Training. [Internet] [Masters thesis]. Texas A&M University; 2016. [cited 2020 Dec 01]. Available from: http://hdl.handle.net/1969.1/157764.

Council of Science Editors:

Lin Y. FPGA-Based Cascade Support Vector Machine with Integrated Training. [Masters Thesis]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/157764


Université de Neuchâtel

5. Imfeld, Kilian. Acquisition system and signal processing for large-scale high-resolution microelectrode arrays neurointerfaces.

Degree: 2008, Université de Neuchâtel

 Les interfaces neuronales basées sur une matrice de micro-électrodes (MEA) permettent la stimulation et la mesure de réseaux neuronaux <i>in vivo</i> et <i>in vitro</i>. La… (more)

Subjects/Keywords: FPGA

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APA (6th Edition):

Imfeld, K. (2008). Acquisition system and signal processing for large-scale high-resolution microelectrode arrays neurointerfaces. (Thesis). Université de Neuchâtel. Retrieved from http://doc.rero.ch/record/11245

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Imfeld, Kilian. “Acquisition system and signal processing for large-scale high-resolution microelectrode arrays neurointerfaces.” 2008. Thesis, Université de Neuchâtel. Accessed December 01, 2020. http://doc.rero.ch/record/11245.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Imfeld, Kilian. “Acquisition system and signal processing for large-scale high-resolution microelectrode arrays neurointerfaces.” 2008. Web. 01 Dec 2020.

Vancouver:

Imfeld K. Acquisition system and signal processing for large-scale high-resolution microelectrode arrays neurointerfaces. [Internet] [Thesis]. Université de Neuchâtel; 2008. [cited 2020 Dec 01]. Available from: http://doc.rero.ch/record/11245.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Imfeld K. Acquisition system and signal processing for large-scale high-resolution microelectrode arrays neurointerfaces. [Thesis]. Université de Neuchâtel; 2008. Available from: http://doc.rero.ch/record/11245

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


AUT University

6. Xu, Stephen Sheng. System on Chip (SoC): a real time touch screen system on programmable chip .

Degree: 2012, AUT University

 This thesis is involved with the investigation, implementation, verification, validation and optimization of a purpose built on-chip solution customized for a real world touch screen… (more)

Subjects/Keywords: SoC; FPGA

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APA (6th Edition):

Xu, S. S. (2012). System on Chip (SoC): a real time touch screen system on programmable chip . (Thesis). AUT University. Retrieved from http://hdl.handle.net/10292/4412

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xu, Stephen Sheng. “System on Chip (SoC): a real time touch screen system on programmable chip .” 2012. Thesis, AUT University. Accessed December 01, 2020. http://hdl.handle.net/10292/4412.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xu, Stephen Sheng. “System on Chip (SoC): a real time touch screen system on programmable chip .” 2012. Web. 01 Dec 2020.

Vancouver:

Xu SS. System on Chip (SoC): a real time touch screen system on programmable chip . [Internet] [Thesis]. AUT University; 2012. [cited 2020 Dec 01]. Available from: http://hdl.handle.net/10292/4412.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xu SS. System on Chip (SoC): a real time touch screen system on programmable chip . [Thesis]. AUT University; 2012. Available from: http://hdl.handle.net/10292/4412

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


AUT University

7. Li, Kang. Implementation of the CUSUM Algorithm on FPGA for Transient Signal Detection .

Degree: 2012, AUT University

 Radio transient signals are non-periodic and discrete obtained from high energy physical processes in space. Most challenging issues in transient signal detection are the speed… (more)

Subjects/Keywords: FPGA; CUSUM

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APA (6th Edition):

Li, K. (2012). Implementation of the CUSUM Algorithm on FPGA for Transient Signal Detection . (Thesis). AUT University. Retrieved from http://hdl.handle.net/10292/4473

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Kang. “Implementation of the CUSUM Algorithm on FPGA for Transient Signal Detection .” 2012. Thesis, AUT University. Accessed December 01, 2020. http://hdl.handle.net/10292/4473.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Kang. “Implementation of the CUSUM Algorithm on FPGA for Transient Signal Detection .” 2012. Web. 01 Dec 2020.

Vancouver:

Li K. Implementation of the CUSUM Algorithm on FPGA for Transient Signal Detection . [Internet] [Thesis]. AUT University; 2012. [cited 2020 Dec 01]. Available from: http://hdl.handle.net/10292/4473.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li K. Implementation of the CUSUM Algorithm on FPGA for Transient Signal Detection . [Thesis]. AUT University; 2012. Available from: http://hdl.handle.net/10292/4473

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Debrecen

8. Szőke, Zoltán. Egyszerű videojáték implementálása FPGA-ra .

Degree: DE – TEK – Természettudományi és Technológiai Kar – Fizikai Intézet, 2010, University of Debrecen

 Napjainkban a digitális technika fejlődése megköveteli a fejlesztésben való új eszközök használatát. A témaválasztás egy ilyen eszköz megismerésére és használatára irányul. Az FPGA egy olyan… (more)

Subjects/Keywords: FPGA; VHDL

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APA (6th Edition):

Szőke, Z. (2010). Egyszerű videojáték implementálása FPGA-ra . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/100517

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Szőke, Zoltán. “Egyszerű videojáték implementálása FPGA-ra .” 2010. Thesis, University of Debrecen. Accessed December 01, 2020. http://hdl.handle.net/2437/100517.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Szőke, Zoltán. “Egyszerű videojáték implementálása FPGA-ra .” 2010. Web. 01 Dec 2020.

Vancouver:

Szőke Z. Egyszerű videojáték implementálása FPGA-ra . [Internet] [Thesis]. University of Debrecen; 2010. [cited 2020 Dec 01]. Available from: http://hdl.handle.net/2437/100517.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Szőke Z. Egyszerű videojáték implementálása FPGA-ra . [Thesis]. University of Debrecen; 2010. Available from: http://hdl.handle.net/2437/100517

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Debrecen

9. Mokánszki, Ádám. Egyszerű Videójáték Implementálása FPGA-ra .

Degree: DE – TEK – Természettudományi és Technológiai Kar – Fizikai Intézet, 2010, University of Debrecen

 A projekt célja a Xilinx Spartan-3E FPGA család megismerése és a HDL nyelvek alapszintű ismeretének elsajátítása volt. A projekt fejlesztése során két személy dolgozott összhangban… (more)

Subjects/Keywords: FPGA; VHDL

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APA (6th Edition):

Mokánszki, . (2010). Egyszerű Videójáték Implementálása FPGA-ra . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/100529

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mokánszki, Ádám. “Egyszerű Videójáték Implementálása FPGA-ra .” 2010. Thesis, University of Debrecen. Accessed December 01, 2020. http://hdl.handle.net/2437/100529.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mokánszki, Ádám. “Egyszerű Videójáték Implementálása FPGA-ra .” 2010. Web. 01 Dec 2020.

Vancouver:

Mokánszki . Egyszerű Videójáték Implementálása FPGA-ra . [Internet] [Thesis]. University of Debrecen; 2010. [cited 2020 Dec 01]. Available from: http://hdl.handle.net/2437/100529.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mokánszki . Egyszerű Videójáték Implementálása FPGA-ra . [Thesis]. University of Debrecen; 2010. Available from: http://hdl.handle.net/2437/100529

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Debrecen

10. Fazekas, Gergő. Kézmozdulatokkal irányítható hívásrendszer FPGA platformon .

Degree: DE – TEK – Informatikai Kar, 2013, University of Debrecen

Egy intelligens otthon központi vezérlőegységének fejlesztése. A vezérlő egységhez csatlakoztatott vezeték nélküli irányító modul segítségével egy VGA kijelzőn megjelenített menürendszer irányítható, és telefonos hívás indítható. A felhasznált fejlesztési hardverek, technológiák, és protokollok részletes bemutatása. A megírt program részletes dokumentációja. Advisors/Committee Members: Oniga, István (advisor).

Subjects/Keywords: FPGA; Hívásrendszer

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APA (6th Edition):

Fazekas, G. (2013). Kézmozdulatokkal irányítható hívásrendszer FPGA platformon . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/167071

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fazekas, Gergő. “Kézmozdulatokkal irányítható hívásrendszer FPGA platformon .” 2013. Thesis, University of Debrecen. Accessed December 01, 2020. http://hdl.handle.net/2437/167071.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fazekas, Gergő. “Kézmozdulatokkal irányítható hívásrendszer FPGA platformon .” 2013. Web. 01 Dec 2020.

Vancouver:

Fazekas G. Kézmozdulatokkal irányítható hívásrendszer FPGA platformon . [Internet] [Thesis]. University of Debrecen; 2013. [cited 2020 Dec 01]. Available from: http://hdl.handle.net/2437/167071.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fazekas G. Kézmozdulatokkal irányítható hívásrendszer FPGA platformon . [Thesis]. University of Debrecen; 2013. Available from: http://hdl.handle.net/2437/167071

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Debrecen

11. Varga, Máté. Vezérlő készítése négykerekű robothoz FPGA kártyával .

Degree: DE – TEK – Informatikai Kar, 2013, University of Debrecen

 Dolgozatomban egy négykerekű robot, vezérlő rendszerének tervezését mutatom be. A fejlesztést egy kutatócsapat tagjaként végeztem, amely azt tűzte ki céljául, hogy egy táv-vezérelhető négy kerék… (more)

Subjects/Keywords: FPGA; Szenzorok

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APA (6th Edition):

Varga, M. (2013). Vezérlő készítése négykerekű robothoz FPGA kártyával . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/169856

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Varga, Máté. “Vezérlő készítése négykerekű robothoz FPGA kártyával .” 2013. Thesis, University of Debrecen. Accessed December 01, 2020. http://hdl.handle.net/2437/169856.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Varga, Máté. “Vezérlő készítése négykerekű robothoz FPGA kártyával .” 2013. Web. 01 Dec 2020.

Vancouver:

Varga M. Vezérlő készítése négykerekű robothoz FPGA kártyával . [Internet] [Thesis]. University of Debrecen; 2013. [cited 2020 Dec 01]. Available from: http://hdl.handle.net/2437/169856.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Varga M. Vezérlő készítése négykerekű robothoz FPGA kártyával . [Thesis]. University of Debrecen; 2013. Available from: http://hdl.handle.net/2437/169856

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

12. Peters, Christoffer. Evaluation of the Achronix picoPIPE™ Architecture in High Performance Applications.

Degree: The Institute of Technology, 2012, Linköping UniversityLinköping University

  In this thesis the new Speedster HP FPGA from Achronix is analyzed. It makes use of a new type of interconnection technology called picoPIPE™.… (more)

Subjects/Keywords: Achronix; FPGA

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APA (6th Edition):

Peters, C. (2012). Evaluation of the Achronix picoPIPE™ Architecture in High Performance Applications. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Peters, Christoffer. “Evaluation of the Achronix picoPIPE™ Architecture in High Performance Applications.” 2012. Thesis, Linköping UniversityLinköping University. Accessed December 01, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Peters, Christoffer. “Evaluation of the Achronix picoPIPE™ Architecture in High Performance Applications.” 2012. Web. 01 Dec 2020.

Vancouver:

Peters C. Evaluation of the Achronix picoPIPE™ Architecture in High Performance Applications. [Internet] [Thesis]. Linköping UniversityLinköping University; 2012. [cited 2020 Dec 01]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Peters C. Evaluation of the Achronix picoPIPE™ Architecture in High Performance Applications. [Thesis]. Linköping UniversityLinköping University; 2012. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

13. Padmanabharao, P.K. (author). Hardware Acceleration of BWA-MEM Genome Mapping Application.

Degree: 2014, Delft University of Technology

Next Generation Sequencing technologies have had a tremendous impact on our understanding of DNA and its role in living organisms. The cost of DNA sequencing… (more)

Subjects/Keywords: FPGA; HLS

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APA (6th Edition):

Padmanabharao, P. K. (. (2014). Hardware Acceleration of BWA-MEM Genome Mapping Application. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:64ce9217-e5e5-495f-ae0a-858cc1ef5886

Chicago Manual of Style (16th Edition):

Padmanabharao, P K (author). “Hardware Acceleration of BWA-MEM Genome Mapping Application.” 2014. Masters Thesis, Delft University of Technology. Accessed December 01, 2020. http://resolver.tudelft.nl/uuid:64ce9217-e5e5-495f-ae0a-858cc1ef5886.

MLA Handbook (7th Edition):

Padmanabharao, P K (author). “Hardware Acceleration of BWA-MEM Genome Mapping Application.” 2014. Web. 01 Dec 2020.

Vancouver:

Padmanabharao PK(. Hardware Acceleration of BWA-MEM Genome Mapping Application. [Internet] [Masters thesis]. Delft University of Technology; 2014. [cited 2020 Dec 01]. Available from: http://resolver.tudelft.nl/uuid:64ce9217-e5e5-495f-ae0a-858cc1ef5886.

Council of Science Editors:

Padmanabharao PK(. Hardware Acceleration of BWA-MEM Genome Mapping Application. [Masters Thesis]. Delft University of Technology; 2014. Available from: http://resolver.tudelft.nl/uuid:64ce9217-e5e5-495f-ae0a-858cc1ef5886


University of Texas – Austin

14. -9887-5109. Placement algorithms for large-scale heterogeneous FPGAs.

Degree: PhD, Electrical and Computer Engineering, 2019, University of Texas – Austin

 In recent years, the drastically enhanced architecture and capacity of Field-Programmable Gate Array (FPGA) devices have led to the rapid growth of customized hardware acceleration… (more)

Subjects/Keywords: Placement; FPGA

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APA (6th Edition):

-9887-5109. (2019). Placement algorithms for large-scale heterogeneous FPGAs. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/5809

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-9887-5109. “Placement algorithms for large-scale heterogeneous FPGAs.” 2019. Doctoral Dissertation, University of Texas – Austin. Accessed December 01, 2020. http://dx.doi.org/10.26153/tsw/5809.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-9887-5109. “Placement algorithms for large-scale heterogeneous FPGAs.” 2019. Web. 01 Dec 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-9887-5109. Placement algorithms for large-scale heterogeneous FPGAs. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2019. [cited 2020 Dec 01]. Available from: http://dx.doi.org/10.26153/tsw/5809.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-9887-5109. Placement algorithms for large-scale heterogeneous FPGAs. [Doctoral Dissertation]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/5809

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


Brno University of Technology

15. Pišl, Adam. Jádro obvodu FPGA pro zobrazení dat na monitoru prostřednictvím portu VGA: FPGA core for data displaying on computer monitor using VGA port.

Degree: 2019, Brno University of Technology

 The aim of this project is to perform the study of a driver for controlling computer monitor using VGA port. The driver is based on… (more)

Subjects/Keywords: FPGA; Xilinx; VGA; monitor; FPGA VGA modul; FPGA sériový port; FPGA; Xilinx; VGA; monitor; FPGA VGA module; FPGA Serial port interface

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pišl, A. (2019). Jádro obvodu FPGA pro zobrazení dat na monitoru prostřednictvím portu VGA: FPGA core for data displaying on computer monitor using VGA port. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/15218

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pišl, Adam. “Jádro obvodu FPGA pro zobrazení dat na monitoru prostřednictvím portu VGA: FPGA core for data displaying on computer monitor using VGA port.” 2019. Thesis, Brno University of Technology. Accessed December 01, 2020. http://hdl.handle.net/11012/15218.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pišl, Adam. “Jádro obvodu FPGA pro zobrazení dat na monitoru prostřednictvím portu VGA: FPGA core for data displaying on computer monitor using VGA port.” 2019. Web. 01 Dec 2020.

Vancouver:

Pišl A. Jádro obvodu FPGA pro zobrazení dat na monitoru prostřednictvím portu VGA: FPGA core for data displaying on computer monitor using VGA port. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Dec 01]. Available from: http://hdl.handle.net/11012/15218.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pišl A. Jádro obvodu FPGA pro zobrazení dat na monitoru prostřednictvím portu VGA: FPGA core for data displaying on computer monitor using VGA port. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/15218

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

16. Olano, Jimmy Fernando Tarrillo. Exploring the use of multiple modular redundancies for masking accumulated faults in SRAM-based FPGAs.

Degree: 2014, Universidade do Rio Grande do Sul

Soft errors in the configuration memory bits of SRAM-based FPGAs are an important issue due to the persistence effect and its possibility of generating functional… (more)

Subjects/Keywords: Microeletrônica; Fault tolerance; Tolerancia : Falhas; FPGA; Fpga

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Olano, J. F. T. (2014). Exploring the use of multiple modular redundancies for masking accumulated faults in SRAM-based FPGAs. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/103895

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Olano, Jimmy Fernando Tarrillo. “Exploring the use of multiple modular redundancies for masking accumulated faults in SRAM-based FPGAs.” 2014. Thesis, Universidade do Rio Grande do Sul. Accessed December 01, 2020. http://hdl.handle.net/10183/103895.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Olano, Jimmy Fernando Tarrillo. “Exploring the use of multiple modular redundancies for masking accumulated faults in SRAM-based FPGAs.” 2014. Web. 01 Dec 2020.

Vancouver:

Olano JFT. Exploring the use of multiple modular redundancies for masking accumulated faults in SRAM-based FPGAs. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2014. [cited 2020 Dec 01]. Available from: http://hdl.handle.net/10183/103895.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Olano JFT. Exploring the use of multiple modular redundancies for masking accumulated faults in SRAM-based FPGAs. [Thesis]. Universidade do Rio Grande do Sul; 2014. Available from: http://hdl.handle.net/10183/103895

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Câmara, Danilo Januário. Plataforma de ultrassom programável dedicada à pesquisa.

Degree: Mestrado, Física Aplicada à Medicina e Biologia, 2015, University of São Paulo

Para o aperfeiçoamento das técnicas existentes e para o desenvolvimento de novas técnicas de diagnóstico por ultrassom equipamentos dedicados à pesquisa são necessários. Esses equipamentos… (more)

Subjects/Keywords: Fotoacústica; FPGA; FPGA; Photoacoustic; Ultrasound; Ultrassom

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APA (6th Edition):

Câmara, D. J. (2015). Plataforma de ultrassom programável dedicada à pesquisa. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/59/59135/tde-24072015-144954/ ;

Chicago Manual of Style (16th Edition):

Câmara, Danilo Januário. “Plataforma de ultrassom programável dedicada à pesquisa.” 2015. Masters Thesis, University of São Paulo. Accessed December 01, 2020. http://www.teses.usp.br/teses/disponiveis/59/59135/tde-24072015-144954/ ;.

MLA Handbook (7th Edition):

Câmara, Danilo Januário. “Plataforma de ultrassom programável dedicada à pesquisa.” 2015. Web. 01 Dec 2020.

Vancouver:

Câmara DJ. Plataforma de ultrassom programável dedicada à pesquisa. [Internet] [Masters thesis]. University of São Paulo; 2015. [cited 2020 Dec 01]. Available from: http://www.teses.usp.br/teses/disponiveis/59/59135/tde-24072015-144954/ ;.

Council of Science Editors:

Câmara DJ. Plataforma de ultrassom programável dedicada à pesquisa. [Masters Thesis]. University of São Paulo; 2015. Available from: http://www.teses.usp.br/teses/disponiveis/59/59135/tde-24072015-144954/ ;


Universidade do Rio Grande do Norte

18. Silva, Alan Paulo Oliveira da. Uma implementação da análise de componentes independentes em plataforma de hardware reconfigurável .

Degree: 2010, Universidade do Rio Grande do Norte

 Blind Source Separation (BSS) refers to the problem of estimate original signals from observed linear mixtures with no knowledge about the sources or the mixing… (more)

Subjects/Keywords: BSS; ICA; FPGA; ICA; FPGA; signals

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APA (6th Edition):

Silva, A. P. O. d. (2010). Uma implementação da análise de componentes independentes em plataforma de hardware reconfigurável . (Masters Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/15325

Chicago Manual of Style (16th Edition):

Silva, Alan Paulo Oliveira da. “Uma implementação da análise de componentes independentes em plataforma de hardware reconfigurável .” 2010. Masters Thesis, Universidade do Rio Grande do Norte. Accessed December 01, 2020. http://repositorio.ufrn.br/handle/123456789/15325.

MLA Handbook (7th Edition):

Silva, Alan Paulo Oliveira da. “Uma implementação da análise de componentes independentes em plataforma de hardware reconfigurável .” 2010. Web. 01 Dec 2020.

Vancouver:

Silva APOd. Uma implementação da análise de componentes independentes em plataforma de hardware reconfigurável . [Internet] [Masters thesis]. Universidade do Rio Grande do Norte; 2010. [cited 2020 Dec 01]. Available from: http://repositorio.ufrn.br/handle/123456789/15325.

Council of Science Editors:

Silva APOd. Uma implementação da análise de componentes independentes em plataforma de hardware reconfigurável . [Masters Thesis]. Universidade do Rio Grande do Norte; 2010. Available from: http://repositorio.ufrn.br/handle/123456789/15325


Universidade do Rio Grande do Norte

19. Silva, Alan Paulo Oliveira da. Uma implementação da análise de componentes independentes em plataforma de hardware reconfigurável .

Degree: 2010, Universidade do Rio Grande do Norte

 Blind Source Separation (BSS) refers to the problem of estimate original signals from observed linear mixtures with no knowledge about the sources or the mixing… (more)

Subjects/Keywords: BSS; ICA; FPGA; ICA; FPGA; signals

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Silva, A. P. O. d. (2010). Uma implementação da análise de componentes independentes em plataforma de hardware reconfigurável . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/15325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Silva, Alan Paulo Oliveira da. “Uma implementação da análise de componentes independentes em plataforma de hardware reconfigurável .” 2010. Thesis, Universidade do Rio Grande do Norte. Accessed December 01, 2020. http://repositorio.ufrn.br/handle/123456789/15325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Silva, Alan Paulo Oliveira da. “Uma implementação da análise de componentes independentes em plataforma de hardware reconfigurável .” 2010. Web. 01 Dec 2020.

Vancouver:

Silva APOd. Uma implementação da análise de componentes independentes em plataforma de hardware reconfigurável . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2010. [cited 2020 Dec 01]. Available from: http://repositorio.ufrn.br/handle/123456789/15325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Silva APOd. Uma implementação da análise de componentes independentes em plataforma de hardware reconfigurável . [Thesis]. Universidade do Rio Grande do Norte; 2010. Available from: http://repositorio.ufrn.br/handle/123456789/15325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Siauliai University

20. Biliūnas, Ellanas Rokas. Lazerio atšvaito sekimo sistema, panaudojant lauku programuojamą loginę matricą.

Degree: Master, Electronics and Electrical Engineering, 2013, Siauliai University

Pirmajame skyriuje yra nagrinėjama LPLM(Lauku Programuojamos Loginės Matricos) (angl. FPGA) struktūra. Nagrinėjama vidinė LPLM struktūra t.y. trasavimas, loginiai elementai ir įėjimai/išėjimai. Toliau nagrinėjama „Altera“ firmos… (more)

Subjects/Keywords: FPGA; Koordinatės; NiosII; FPGA; Coordinates; NiosII

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APA (6th Edition):

Rokas, B Ellanas. (2013). Lazerio atšvaito sekimo sistema, panaudojant lauku programuojamą loginę matricą. (Masters Thesis). Siauliai University. Retrieved from http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2013~D_20130822_154637-38974 ;

Chicago Manual of Style (16th Edition):

Rokas, Biliūnas, Ellanas. “Lazerio atšvaito sekimo sistema, panaudojant lauku programuojamą loginę matricą.” 2013. Masters Thesis, Siauliai University. Accessed December 01, 2020. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2013~D_20130822_154637-38974 ;.

MLA Handbook (7th Edition):

Rokas, Biliūnas, Ellanas. “Lazerio atšvaito sekimo sistema, panaudojant lauku programuojamą loginę matricą.” 2013. Web. 01 Dec 2020.

Vancouver:

Rokas B Ellanas. Lazerio atšvaito sekimo sistema, panaudojant lauku programuojamą loginę matricą. [Internet] [Masters thesis]. Siauliai University; 2013. [cited 2020 Dec 01]. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2013~D_20130822_154637-38974 ;.

Council of Science Editors:

Rokas B Ellanas. Lazerio atšvaito sekimo sistema, panaudojant lauku programuojamą loginę matricą. [Masters Thesis]. Siauliai University; 2013. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2013~D_20130822_154637-38974 ;


Brno University of Technology

21. Soľanka, Lukáš. Návrh paměti CACHE pro síťové aplikace: CACHE Memory Design for Network Applications.

Degree: 2020, Brno University of Technology

 This thesis deals with design and implementation of generic cache memory for a wide range of network applications. Firstly, aspects with influence on performance are… (more)

Subjects/Keywords: cache; sieť; FPGA; cache; network; FPGA

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APA (6th Edition):

Soľanka, L. (2020). Návrh paměti CACHE pro síťové aplikace: CACHE Memory Design for Network Applications. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/187960

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Soľanka, Lukáš. “Návrh paměti CACHE pro síťové aplikace: CACHE Memory Design for Network Applications.” 2020. Thesis, Brno University of Technology. Accessed December 01, 2020. http://hdl.handle.net/11012/187960.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Soľanka, Lukáš. “Návrh paměti CACHE pro síťové aplikace: CACHE Memory Design for Network Applications.” 2020. Web. 01 Dec 2020.

Vancouver:

Soľanka L. Návrh paměti CACHE pro síťové aplikace: CACHE Memory Design for Network Applications. [Internet] [Thesis]. Brno University of Technology; 2020. [cited 2020 Dec 01]. Available from: http://hdl.handle.net/11012/187960.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Soľanka L. Návrh paměti CACHE pro síťové aplikace: CACHE Memory Design for Network Applications. [Thesis]. Brno University of Technology; 2020. Available from: http://hdl.handle.net/11012/187960

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

22. Soľanka, Lukáš. Návrh paměti CACHE pro síťové aplikace: CACHE Memory Design for Network Applications.

Degree: 2019, Brno University of Technology

 This thesis deals with design and implementation of generic cache memory for a wide range of network applications. Firstly, aspects with influence on performance are… (more)

Subjects/Keywords: cache; sieť; FPGA; cache; network; FPGA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Soľanka, L. (2019). Návrh paměti CACHE pro síťové aplikace: CACHE Memory Design for Network Applications. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/56361

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Soľanka, Lukáš. “Návrh paměti CACHE pro síťové aplikace: CACHE Memory Design for Network Applications.” 2019. Thesis, Brno University of Technology. Accessed December 01, 2020. http://hdl.handle.net/11012/56361.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Soľanka, Lukáš. “Návrh paměti CACHE pro síťové aplikace: CACHE Memory Design for Network Applications.” 2019. Web. 01 Dec 2020.

Vancouver:

Soľanka L. Návrh paměti CACHE pro síťové aplikace: CACHE Memory Design for Network Applications. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Dec 01]. Available from: http://hdl.handle.net/11012/56361.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Soľanka L. Návrh paměti CACHE pro síťové aplikace: CACHE Memory Design for Network Applications. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/56361

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

23. Mazza, James P. Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms.

Degree: MS, Electrical Engineering, 2014, Rochester Institute of Technology

  Data parallel image processing algorithms have numerous uses in many real time applications. Depending on the complexity of the computations involved, these algorithms may… (more)

Subjects/Keywords: FPGA; Hardward; SIMD

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APA (6th Edition):

Mazza, J. P. (2014). Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/8604

Chicago Manual of Style (16th Edition):

Mazza, James P. “Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms.” 2014. Masters Thesis, Rochester Institute of Technology. Accessed December 01, 2020. https://scholarworks.rit.edu/theses/8604.

MLA Handbook (7th Edition):

Mazza, James P. “Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms.” 2014. Web. 01 Dec 2020.

Vancouver:

Mazza JP. Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms. [Internet] [Masters thesis]. Rochester Institute of Technology; 2014. [cited 2020 Dec 01]. Available from: https://scholarworks.rit.edu/theses/8604.

Council of Science Editors:

Mazza JP. Software/Hardware Tradeoffs in the Speedup of Color Image Processing Algorithms. [Masters Thesis]. Rochester Institute of Technology; 2014. Available from: https://scholarworks.rit.edu/theses/8604


University of Alberta

24. Son, Eric Tien Tze. Simulation of quantization noise effects on the performance of a wireless preamble detector and demonstration of a functional FPGA prototype.

Degree: MS, Electrical and Computer Engineering, 2009, University of Alberta

 This thesis describes the implementation of the physical layer for an experimental low-power wireless communication device. The system utilizes differential coherent correlation and threshold-based detection… (more)

Subjects/Keywords: Communication; FPGA; Preamble

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APA (6th Edition):

Son, E. T. T. (2009). Simulation of quantization noise effects on the performance of a wireless preamble detector and demonstration of a functional FPGA prototype. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/mk61rh216

Chicago Manual of Style (16th Edition):

Son, Eric Tien Tze. “Simulation of quantization noise effects on the performance of a wireless preamble detector and demonstration of a functional FPGA prototype.” 2009. Masters Thesis, University of Alberta. Accessed December 01, 2020. https://era.library.ualberta.ca/files/mk61rh216.

MLA Handbook (7th Edition):

Son, Eric Tien Tze. “Simulation of quantization noise effects on the performance of a wireless preamble detector and demonstration of a functional FPGA prototype.” 2009. Web. 01 Dec 2020.

Vancouver:

Son ETT. Simulation of quantization noise effects on the performance of a wireless preamble detector and demonstration of a functional FPGA prototype. [Internet] [Masters thesis]. University of Alberta; 2009. [cited 2020 Dec 01]. Available from: https://era.library.ualberta.ca/files/mk61rh216.

Council of Science Editors:

Son ETT. Simulation of quantization noise effects on the performance of a wireless preamble detector and demonstration of a functional FPGA prototype. [Masters Thesis]. University of Alberta; 2009. Available from: https://era.library.ualberta.ca/files/mk61rh216


University of Alberta

25. Zhu, Pengfei. An FPGA-Based Acceleration Platform for The Auction Algorithm.

Degree: MS, Department of Electrical and Computer Engineering, 2012, University of Alberta

 Auction algorithms have been applied in various linear network problems, such as assignment, transportation, max-flow and shortest path problem. The inherent parallel characteristics of these… (more)

Subjects/Keywords: Auction Algorithm; FPGA

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APA (6th Edition):

Zhu, P. (2012). An FPGA-Based Acceleration Platform for The Auction Algorithm. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/2f75r9400

Chicago Manual of Style (16th Edition):

Zhu, Pengfei. “An FPGA-Based Acceleration Platform for The Auction Algorithm.” 2012. Masters Thesis, University of Alberta. Accessed December 01, 2020. https://era.library.ualberta.ca/files/2f75r9400.

MLA Handbook (7th Edition):

Zhu, Pengfei. “An FPGA-Based Acceleration Platform for The Auction Algorithm.” 2012. Web. 01 Dec 2020.

Vancouver:

Zhu P. An FPGA-Based Acceleration Platform for The Auction Algorithm. [Internet] [Masters thesis]. University of Alberta; 2012. [cited 2020 Dec 01]. Available from: https://era.library.ualberta.ca/files/2f75r9400.

Council of Science Editors:

Zhu P. An FPGA-Based Acceleration Platform for The Auction Algorithm. [Masters Thesis]. University of Alberta; 2012. Available from: https://era.library.ualberta.ca/files/2f75r9400


University of Debrecen

26. Fazekas, Ádám János. Elektronmikroszkópos felvételek hátterének levonása 3D-ben FPGA platformon .

Degree: DE – TEK – Informatikai Kar, 2011, University of Debrecen

 A dolgozatom témája egy képfeldolgozási feladatokra alkalmas célprocesszor fejlesztése, amely elektronmikroszkópos képek zavaró háttér jeleinek kiszűrését képes hatékonyan elvégezni. A célprocesszor fejlesztésére Altera DE2 FPGA(more)

Subjects/Keywords: FPGA; Gyorsító hardver

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fazekas, . J. (2011). Elektronmikroszkópos felvételek hátterének levonása 3D-ben FPGA platformon . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/108842

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fazekas, Ádám János. “Elektronmikroszkópos felvételek hátterének levonása 3D-ben FPGA platformon .” 2011. Thesis, University of Debrecen. Accessed December 01, 2020. http://hdl.handle.net/2437/108842.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fazekas, Ádám János. “Elektronmikroszkópos felvételek hátterének levonása 3D-ben FPGA platformon .” 2011. Web. 01 Dec 2020.

Vancouver:

Fazekas J. Elektronmikroszkópos felvételek hátterének levonása 3D-ben FPGA platformon . [Internet] [Thesis]. University of Debrecen; 2011. [cited 2020 Dec 01]. Available from: http://hdl.handle.net/2437/108842.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fazekas J. Elektronmikroszkópos felvételek hátterének levonása 3D-ben FPGA platformon . [Thesis]. University of Debrecen; 2011. Available from: http://hdl.handle.net/2437/108842

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Debrecen

27. Tóthfalusi, Tamás. Intelligens ház felügyelete és vezérlése FPGA áramkörrel .

Degree: DE – TEK – Informatikai Kar, 2012, University of Debrecen

 Diplomamunkámban egy gyorsulásérzékelő szenzor jeleinek a folyamatos feldolgozását valósítom meg neurális hálózat segítségével, amely neurális hálózatot FPGA-n implementáltam, Verilog hardverleíró nyelven. Az előzetes tesztelések és… (more)

Subjects/Keywords: FPGA; neurális hálózat

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tóthfalusi, T. (2012). Intelligens ház felügyelete és vezérlése FPGA áramkörrel . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/128933

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tóthfalusi, Tamás. “Intelligens ház felügyelete és vezérlése FPGA áramkörrel .” 2012. Thesis, University of Debrecen. Accessed December 01, 2020. http://hdl.handle.net/2437/128933.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tóthfalusi, Tamás. “Intelligens ház felügyelete és vezérlése FPGA áramkörrel .” 2012. Web. 01 Dec 2020.

Vancouver:

Tóthfalusi T. Intelligens ház felügyelete és vezérlése FPGA áramkörrel . [Internet] [Thesis]. University of Debrecen; 2012. [cited 2020 Dec 01]. Available from: http://hdl.handle.net/2437/128933.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tóthfalusi T. Intelligens ház felügyelete és vezérlése FPGA áramkörrel . [Thesis]. University of Debrecen; 2012. Available from: http://hdl.handle.net/2437/128933

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Debrecen

28. Sövegjártó, Ferenc. Neurális hálózatok kialakítása FPGA használatával .

Degree: DE – TEK – Informatikai Kar, 2012, University of Debrecen

FPGA fejlesztői panel használatával kívánok készíteni egy neurális hálózati funkciót ellátó áramkört, amely a bemeneti jel megérkezését követően azonnal meghatározza a tervezéskor rendelkezésre álló ismeretek… (more)

Subjects/Keywords: FPGA; neurális hálózat

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sövegjártó, F. (2012). Neurális hálózatok kialakítása FPGA használatával . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/153656

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sövegjártó, Ferenc. “Neurális hálózatok kialakítása FPGA használatával .” 2012. Thesis, University of Debrecen. Accessed December 01, 2020. http://hdl.handle.net/2437/153656.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sövegjártó, Ferenc. “Neurális hálózatok kialakítása FPGA használatával .” 2012. Web. 01 Dec 2020.

Vancouver:

Sövegjártó F. Neurális hálózatok kialakítása FPGA használatával . [Internet] [Thesis]. University of Debrecen; 2012. [cited 2020 Dec 01]. Available from: http://hdl.handle.net/2437/153656.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sövegjártó F. Neurális hálózatok kialakítása FPGA használatával . [Thesis]. University of Debrecen; 2012. Available from: http://hdl.handle.net/2437/153656

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

29. Gkougkoulias, Konstantinos (author). Porting and Evaluation of Overlay Architectures for FPGAs with Scientific Kernels.

Degree: 2017, Delft University of Technology

 In recent years due to the slow down of Moores Law and Dennard Scaling, alternative architectures are starting to be used instead of plain CPU… (more)

Subjects/Keywords: FPGA Overlays; Zynq

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gkougkoulias, K. (. (2017). Porting and Evaluation of Overlay Architectures for FPGAs with Scientific Kernels. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:f0dc25f1-9edb-4e87-9154-bafc4da58084

Chicago Manual of Style (16th Edition):

Gkougkoulias, Konstantinos (author). “Porting and Evaluation of Overlay Architectures for FPGAs with Scientific Kernels.” 2017. Masters Thesis, Delft University of Technology. Accessed December 01, 2020. http://resolver.tudelft.nl/uuid:f0dc25f1-9edb-4e87-9154-bafc4da58084.

MLA Handbook (7th Edition):

Gkougkoulias, Konstantinos (author). “Porting and Evaluation of Overlay Architectures for FPGAs with Scientific Kernels.” 2017. Web. 01 Dec 2020.

Vancouver:

Gkougkoulias K(. Porting and Evaluation of Overlay Architectures for FPGAs with Scientific Kernels. [Internet] [Masters thesis]. Delft University of Technology; 2017. [cited 2020 Dec 01]. Available from: http://resolver.tudelft.nl/uuid:f0dc25f1-9edb-4e87-9154-bafc4da58084.

Council of Science Editors:

Gkougkoulias K(. Porting and Evaluation of Overlay Architectures for FPGAs with Scientific Kernels. [Masters Thesis]. Delft University of Technology; 2017. Available from: http://resolver.tudelft.nl/uuid:f0dc25f1-9edb-4e87-9154-bafc4da58084


Delft University of Technology

30. Nandy, A. (author). System Level Support for Dynamic Partial Reconfiguration.

Degree: 2011, Delft University of Technology

In this thesis a generic approach for integrating a dynamically reconfigurable device into a general purpose system interconnected with a high-speed interconnect, is described. The… (more)

Subjects/Keywords: FPGA; hypertransport; ROCCC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nandy, A. (. (2011). System Level Support for Dynamic Partial Reconfiguration. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:7e5ccc35-774e-41d6-b12a-a502b1960256

Chicago Manual of Style (16th Edition):

Nandy, A (author). “System Level Support for Dynamic Partial Reconfiguration.” 2011. Masters Thesis, Delft University of Technology. Accessed December 01, 2020. http://resolver.tudelft.nl/uuid:7e5ccc35-774e-41d6-b12a-a502b1960256.

MLA Handbook (7th Edition):

Nandy, A (author). “System Level Support for Dynamic Partial Reconfiguration.” 2011. Web. 01 Dec 2020.

Vancouver:

Nandy A(. System Level Support for Dynamic Partial Reconfiguration. [Internet] [Masters thesis]. Delft University of Technology; 2011. [cited 2020 Dec 01]. Available from: http://resolver.tudelft.nl/uuid:7e5ccc35-774e-41d6-b12a-a502b1960256.

Council of Science Editors:

Nandy A(. System Level Support for Dynamic Partial Reconfiguration. [Masters Thesis]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:7e5ccc35-774e-41d6-b12a-a502b1960256

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