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You searched for subject:(Floating point arithmetic). Showing records 1 – 30 of 51 total matches.

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University of Saskatchewan

1. Zhang, Hao. Single-Precision and Double-Precision Merged Floating-Point Multiplication and Addition Units on FPGA.

Degree: 2015, University of Saskatchewan

Floating-point (FP) operations defined in IEEE 754-2008 Standard for Floating-Point Arithmetic can provide wider dynamic range and higher precision than fixed-point operations. Many scientific computations… (more)

Subjects/Keywords: floating-point arithmetic; floating-point multiplier; floating-point adder; fpga design; Karatsuba algorithm

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APA (6th Edition):

Zhang, H. (2015). Single-Precision and Double-Precision Merged Floating-Point Multiplication and Addition Units on FPGA. (Thesis). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/12611

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhang, Hao. “Single-Precision and Double-Precision Merged Floating-Point Multiplication and Addition Units on FPGA.” 2015. Thesis, University of Saskatchewan. Accessed October 01, 2020. http://hdl.handle.net/10388/12611.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhang, Hao. “Single-Precision and Double-Precision Merged Floating-Point Multiplication and Addition Units on FPGA.” 2015. Web. 01 Oct 2020.

Vancouver:

Zhang H. Single-Precision and Double-Precision Merged Floating-Point Multiplication and Addition Units on FPGA. [Internet] [Thesis]. University of Saskatchewan; 2015. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/10388/12611.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang H. Single-Precision and Double-Precision Merged Floating-Point Multiplication and Addition Units on FPGA. [Thesis]. University of Saskatchewan; 2015. Available from: http://hdl.handle.net/10388/12611

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Sydney

2. Frechtling, Michael Kenneth. Automated Dynamic Error Analysis Methods for Optimization of Computer Arithmetic Systems .

Degree: 2015, University of Sydney

 Computer arithmetic is one of the more important topics within computer science and engineering. The earliest implementations of computer systems were designed to perform arithmetic(more)

Subjects/Keywords: Computer Arithmetic; Floating Point Arithmetic; Numeric Analysis; Monte Carlo Arithmetic

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APA (6th Edition):

Frechtling, M. K. (2015). Automated Dynamic Error Analysis Methods for Optimization of Computer Arithmetic Systems . (Thesis). University of Sydney. Retrieved from http://hdl.handle.net/2123/13928

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Frechtling, Michael Kenneth. “Automated Dynamic Error Analysis Methods for Optimization of Computer Arithmetic Systems .” 2015. Thesis, University of Sydney. Accessed October 01, 2020. http://hdl.handle.net/2123/13928.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Frechtling, Michael Kenneth. “Automated Dynamic Error Analysis Methods for Optimization of Computer Arithmetic Systems .” 2015. Web. 01 Oct 2020.

Vancouver:

Frechtling MK. Automated Dynamic Error Analysis Methods for Optimization of Computer Arithmetic Systems . [Internet] [Thesis]. University of Sydney; 2015. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/2123/13928.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Frechtling MK. Automated Dynamic Error Analysis Methods for Optimization of Computer Arithmetic Systems . [Thesis]. University of Sydney; 2015. Available from: http://hdl.handle.net/2123/13928

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

3. Rajanala, Arunkumar V. IEEE 754 single precision standard compatible floating point processor implemented using silicon compiler technology.

Degree: MS, Electrical and Computer Engineering, 1988, Oregon State University

 Typically, a Floating Point processor will be attached to a general-purpose digital computer to extend and enhance its numeric processing capabilities. In this thesis a… (more)

Subjects/Keywords: Floating-point arithmetic

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APA (6th Edition):

Rajanala, A. V. (1988). IEEE 754 single precision standard compatible floating point processor implemented using silicon compiler technology. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/39940

Chicago Manual of Style (16th Edition):

Rajanala, Arunkumar V. “IEEE 754 single precision standard compatible floating point processor implemented using silicon compiler technology.” 1988. Masters Thesis, Oregon State University. Accessed October 01, 2020. http://hdl.handle.net/1957/39940.

MLA Handbook (7th Edition):

Rajanala, Arunkumar V. “IEEE 754 single precision standard compatible floating point processor implemented using silicon compiler technology.” 1988. Web. 01 Oct 2020.

Vancouver:

Rajanala AV. IEEE 754 single precision standard compatible floating point processor implemented using silicon compiler technology. [Internet] [Masters thesis]. Oregon State University; 1988. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1957/39940.

Council of Science Editors:

Rajanala AV. IEEE 754 single precision standard compatible floating point processor implemented using silicon compiler technology. [Masters Thesis]. Oregon State University; 1988. Available from: http://hdl.handle.net/1957/39940


Rochester Institute of Technology

4. Wagner, Matt. Posits: An Alternative to Floating Point Calculations.

Degree: MS, Electrical Engineering, 2020, Rochester Institute of Technology

Floating point arithmetic is one of several methods of performing computations in digital designs; others include integer and fixed point computations. Fixed point utilizes… (more)

Subjects/Keywords: Unum Arithmetic; Floating-Point Arithmetic; Computer architecture; Hardware; Testing; Timing

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APA (6th Edition):

Wagner, M. (2020). Posits: An Alternative to Floating Point Calculations. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10359

Chicago Manual of Style (16th Edition):

Wagner, Matt. “Posits: An Alternative to Floating Point Calculations.” 2020. Masters Thesis, Rochester Institute of Technology. Accessed October 01, 2020. https://scholarworks.rit.edu/theses/10359.

MLA Handbook (7th Edition):

Wagner, Matt. “Posits: An Alternative to Floating Point Calculations.” 2020. Web. 01 Oct 2020.

Vancouver:

Wagner M. Posits: An Alternative to Floating Point Calculations. [Internet] [Masters thesis]. Rochester Institute of Technology; 2020. [cited 2020 Oct 01]. Available from: https://scholarworks.rit.edu/theses/10359.

Council of Science Editors:

Wagner M. Posits: An Alternative to Floating Point Calculations. [Masters Thesis]. Rochester Institute of Technology; 2020. Available from: https://scholarworks.rit.edu/theses/10359

5. Barrois, Benjamin. Methods to evaluate accuracy-energy trade-off in operator-level approximate computing : Méthodes d'évaluation du compromis précision-énergie pour le calcul approximatif niveau opérateur.

Degree: Docteur es, Traitement du signal et télécommunications, 2017, Rennes 1

Les limites physiques des circuits à base de silicium étant en passe d'être atteintes, de nouveaux moyens doivent être trouvés pour outrepasser la fin de… (more)

Subjects/Keywords: Arithmétique interne des ordinateurs; Arithmétique en virgule fixe; Arithmétique en virgule flottante; Computer arithmetic; Fixed-Point arithmetic; Floating-Point arithmetic

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APA (6th Edition):

Barrois, B. (2017). Methods to evaluate accuracy-energy trade-off in operator-level approximate computing : Méthodes d'évaluation du compromis précision-énergie pour le calcul approximatif niveau opérateur. (Doctoral Dissertation). Rennes 1. Retrieved from http://www.theses.fr/2017REN1S097

Chicago Manual of Style (16th Edition):

Barrois, Benjamin. “Methods to evaluate accuracy-energy trade-off in operator-level approximate computing : Méthodes d'évaluation du compromis précision-énergie pour le calcul approximatif niveau opérateur.” 2017. Doctoral Dissertation, Rennes 1. Accessed October 01, 2020. http://www.theses.fr/2017REN1S097.

MLA Handbook (7th Edition):

Barrois, Benjamin. “Methods to evaluate accuracy-energy trade-off in operator-level approximate computing : Méthodes d'évaluation du compromis précision-énergie pour le calcul approximatif niveau opérateur.” 2017. Web. 01 Oct 2020.

Vancouver:

Barrois B. Methods to evaluate accuracy-energy trade-off in operator-level approximate computing : Méthodes d'évaluation du compromis précision-énergie pour le calcul approximatif niveau opérateur. [Internet] [Doctoral dissertation]. Rennes 1; 2017. [cited 2020 Oct 01]. Available from: http://www.theses.fr/2017REN1S097.

Council of Science Editors:

Barrois B. Methods to evaluate accuracy-energy trade-off in operator-level approximate computing : Méthodes d'évaluation du compromis précision-énergie pour le calcul approximatif niveau opérateur. [Doctoral Dissertation]. Rennes 1; 2017. Available from: http://www.theses.fr/2017REN1S097


Oklahoma State University

6. Underwood, Alex. IEEE floating-point extension for managing error using residual registers.

Degree: Electrical Engineering, 2019, Oklahoma State University

 This thesis discusses modifications to IEEE 754 floating-point units to help researchers and scientists monitor and control errors in scientific applications as well as provide… (more)

Subjects/Keywords: ieee 754 arithmetic; native pairs; residual registers; risc-v floating point

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APA (6th Edition):

Underwood, A. (2019). IEEE floating-point extension for managing error using residual registers. (Thesis). Oklahoma State University. Retrieved from http://hdl.handle.net/11244/324915

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Underwood, Alex. “IEEE floating-point extension for managing error using residual registers.” 2019. Thesis, Oklahoma State University. Accessed October 01, 2020. http://hdl.handle.net/11244/324915.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Underwood, Alex. “IEEE floating-point extension for managing error using residual registers.” 2019. Web. 01 Oct 2020.

Vancouver:

Underwood A. IEEE floating-point extension for managing error using residual registers. [Internet] [Thesis]. Oklahoma State University; 2019. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/11244/324915.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Underwood A. IEEE floating-point extension for managing error using residual registers. [Thesis]. Oklahoma State University; 2019. Available from: http://hdl.handle.net/11244/324915

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

7. Nehmeh, Riham. Quality Evaluation in Fixed-point Systems with Selective Simulation : Evaluation de la qualité des systèmes en virgule fixe avec la simulation sélective.

Degree: Docteur es, Traitement du Signal et de l'Image, 2017, Rennes, INSA

 Le temps de mise sur le marché et les coûts d’implantation sont les deux critères principaux à prendre en compte dans l'automatisation du processus de… (more)

Subjects/Keywords: Optimisation; Applications; Floating-point arithmetic; Embedded computer systems; Computer simulation; Computer hardware description languages; 621.382

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APA (6th Edition):

Nehmeh, R. (2017). Quality Evaluation in Fixed-point Systems with Selective Simulation : Evaluation de la qualité des systèmes en virgule fixe avec la simulation sélective. (Doctoral Dissertation). Rennes, INSA. Retrieved from http://www.theses.fr/2017ISAR0020

Chicago Manual of Style (16th Edition):

Nehmeh, Riham. “Quality Evaluation in Fixed-point Systems with Selective Simulation : Evaluation de la qualité des systèmes en virgule fixe avec la simulation sélective.” 2017. Doctoral Dissertation, Rennes, INSA. Accessed October 01, 2020. http://www.theses.fr/2017ISAR0020.

MLA Handbook (7th Edition):

Nehmeh, Riham. “Quality Evaluation in Fixed-point Systems with Selective Simulation : Evaluation de la qualité des systèmes en virgule fixe avec la simulation sélective.” 2017. Web. 01 Oct 2020.

Vancouver:

Nehmeh R. Quality Evaluation in Fixed-point Systems with Selective Simulation : Evaluation de la qualité des systèmes en virgule fixe avec la simulation sélective. [Internet] [Doctoral dissertation]. Rennes, INSA; 2017. [cited 2020 Oct 01]. Available from: http://www.theses.fr/2017ISAR0020.

Council of Science Editors:

Nehmeh R. Quality Evaluation in Fixed-point Systems with Selective Simulation : Evaluation de la qualité des systèmes en virgule fixe avec la simulation sélective. [Doctoral Dissertation]. Rennes, INSA; 2017. Available from: http://www.theses.fr/2017ISAR0020

8. Keni, Mayuresh Vijay. Design of a Single Precision Floating Point Divider and Multiplier with Pipelined Architecture.

Degree: MS, Electrical Engineering, 2017, Rochester Institute of Technology

  High speed computation is the need of today’s generation of Processors. To accomplish this major task, many functions are implemented inside the hardware of… (more)

Subjects/Keywords: Logic design; Circuits; Design methodology; Hardware description languages; Floating point arithmetic; Equations

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APA (6th Edition):

Keni, M. V. (2017). Design of a Single Precision Floating Point Divider and Multiplier with Pipelined Architecture. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9706

Chicago Manual of Style (16th Edition):

Keni, Mayuresh Vijay. “Design of a Single Precision Floating Point Divider and Multiplier with Pipelined Architecture.” 2017. Masters Thesis, Rochester Institute of Technology. Accessed October 01, 2020. https://scholarworks.rit.edu/theses/9706.

MLA Handbook (7th Edition):

Keni, Mayuresh Vijay. “Design of a Single Precision Floating Point Divider and Multiplier with Pipelined Architecture.” 2017. Web. 01 Oct 2020.

Vancouver:

Keni MV. Design of a Single Precision Floating Point Divider and Multiplier with Pipelined Architecture. [Internet] [Masters thesis]. Rochester Institute of Technology; 2017. [cited 2020 Oct 01]. Available from: https://scholarworks.rit.edu/theses/9706.

Council of Science Editors:

Keni MV. Design of a Single Precision Floating Point Divider and Multiplier with Pipelined Architecture. [Masters Thesis]. Rochester Institute of Technology; 2017. Available from: https://scholarworks.rit.edu/theses/9706


Rhodes University

9. Myburgh, Talon. Finite precision arithmetic in Polyphase Filterbank implementations.

Degree: Faculty of Science, Physics and Electronics, 2020, Rhodes University

 The MeerKAT is the most sensitive radio telescope in its class, and it is important that systematic effects do not limit the dynamic range of… (more)

Subjects/Keywords: Radio interferometers; Interferometry; Radio telescopes; Gate array circuits; Floating-point arithmetic; Python (Computer program language); Polyphase Filterbank; Finite precision arithmetic; MeerKAT

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APA (6th Edition):

Myburgh, T. (2020). Finite precision arithmetic in Polyphase Filterbank implementations. (Thesis). Rhodes University. Retrieved from http://hdl.handle.net/10962/146187

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Myburgh, Talon. “Finite precision arithmetic in Polyphase Filterbank implementations.” 2020. Thesis, Rhodes University. Accessed October 01, 2020. http://hdl.handle.net/10962/146187.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Myburgh, Talon. “Finite precision arithmetic in Polyphase Filterbank implementations.” 2020. Web. 01 Oct 2020.

Vancouver:

Myburgh T. Finite precision arithmetic in Polyphase Filterbank implementations. [Internet] [Thesis]. Rhodes University; 2020. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/10962/146187.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Myburgh T. Finite precision arithmetic in Polyphase Filterbank implementations. [Thesis]. Rhodes University; 2020. Available from: http://hdl.handle.net/10962/146187

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ohio University

10. Robe, Edward D. Simulink TMmodules that emulate digital controllers realized with fixed-point or floating-point arithmetic.

Degree: MS, Electrical Engineering & Computer Science (Engineering and Technology), 1994, Ohio University

Subjects/Keywords: Floating-Point Arithmetic; Fixed-Point Arithmetic; SIMULINK; Hubble Space Telescope

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APA (6th Edition):

Robe, E. D. (1994). Simulink TMmodules that emulate digital controllers realized with fixed-point or floating-point arithmetic. (Masters Thesis). Ohio University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1180120138

Chicago Manual of Style (16th Edition):

Robe, Edward D. “Simulink TMmodules that emulate digital controllers realized with fixed-point or floating-point arithmetic.” 1994. Masters Thesis, Ohio University. Accessed October 01, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1180120138.

MLA Handbook (7th Edition):

Robe, Edward D. “Simulink TMmodules that emulate digital controllers realized with fixed-point or floating-point arithmetic.” 1994. Web. 01 Oct 2020.

Vancouver:

Robe ED. Simulink TMmodules that emulate digital controllers realized with fixed-point or floating-point arithmetic. [Internet] [Masters thesis]. Ohio University; 1994. [cited 2020 Oct 01]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1180120138.

Council of Science Editors:

Robe ED. Simulink TMmodules that emulate digital controllers realized with fixed-point or floating-point arithmetic. [Masters Thesis]. Ohio University; 1994. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1180120138


Brno University of Technology

11. Čambor, Michal. Paralelní řešení parciálních diferenciálnich rovnic: Partial Differential Equations Parallel Solutions.

Degree: 2020, Brno University of Technology

 This thesis deals with the concepts of numerical integrator using floating point arithmetic for solving partial differential equations. The integrator uses Euler method and Taylor… (more)

Subjects/Keywords: Parciální diferenciální rovnice; numerická integrace; simulace; aritmetika pevné řádové čárky; aritmetika plovoucí řádové čárky; Taylorova řada.; Partial differential equation; numerical integration; simulation; fixed point arithmetic; floating point arithmetic; Taylor series.

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APA (6th Edition):

Čambor, M. (2020). Paralelní řešení parciálních diferenciálnich rovnic: Partial Differential Equations Parallel Solutions. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/187618

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Čambor, Michal. “Paralelní řešení parciálních diferenciálnich rovnic: Partial Differential Equations Parallel Solutions.” 2020. Thesis, Brno University of Technology. Accessed October 01, 2020. http://hdl.handle.net/11012/187618.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Čambor, Michal. “Paralelní řešení parciálních diferenciálnich rovnic: Partial Differential Equations Parallel Solutions.” 2020. Web. 01 Oct 2020.

Vancouver:

Čambor M. Paralelní řešení parciálních diferenciálnich rovnic: Partial Differential Equations Parallel Solutions. [Internet] [Thesis]. Brno University of Technology; 2020. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/11012/187618.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Čambor M. Paralelní řešení parciálních diferenciálnich rovnic: Partial Differential Equations Parallel Solutions. [Thesis]. Brno University of Technology; 2020. Available from: http://hdl.handle.net/11012/187618

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

12. Čambor, Michal. Elementární procesor v aritmetice pevné a pohyblivé řádové čárky: Fixed and Floating Point Arithmetic Elementar Processor.

Degree: 2019, Brno University of Technology

 This thesis is about the concept of elementar processor. This processor solves of differential equations using Eulerian equation. The thesis consists of two major parts.… (more)

Subjects/Keywords: Procesor; aritmetika pevné řádové čárky; aritmetika plovoucí řádové čárky; Booth algoritmus; návrh elementárního procesoru.; Processor; fixed point arithmetic; floating point arithmetic; Booth algorithm; the concept of elementar processor.

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APA (6th Edition):

Čambor, M. (2019). Elementární procesor v aritmetice pevné a pohyblivé řádové čárky: Fixed and Floating Point Arithmetic Elementar Processor. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/54723

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Čambor, Michal. “Elementární procesor v aritmetice pevné a pohyblivé řádové čárky: Fixed and Floating Point Arithmetic Elementar Processor.” 2019. Thesis, Brno University of Technology. Accessed October 01, 2020. http://hdl.handle.net/11012/54723.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Čambor, Michal. “Elementární procesor v aritmetice pevné a pohyblivé řádové čárky: Fixed and Floating Point Arithmetic Elementar Processor.” 2019. Web. 01 Oct 2020.

Vancouver:

Čambor M. Elementární procesor v aritmetice pevné a pohyblivé řádové čárky: Fixed and Floating Point Arithmetic Elementar Processor. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/11012/54723.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Čambor M. Elementární procesor v aritmetice pevné a pohyblivé řádové čárky: Fixed and Floating Point Arithmetic Elementar Processor. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/54723

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. GROVER NARESH. FPGA based low power optimal digital system design; -.

Degree: 2015, Manav Rachna International University

 Due to the flexibility, programmability and low end product cycle, Field Programmable newlineGate Arrays, FPGAs, are highly desirable for implementation of digital systems, Since newlinethe… (more)

Subjects/Keywords: Field Programmable Gate Array; VHDL; 32 bit Floating Point Arithmetic Unit; Modelsim; Matlab; Simulink; XPower Estimator

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APA (6th Edition):

NARESH, G. (2015). FPGA based low power optimal digital system design; -. (Thesis). Manav Rachna International University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/33328

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

NARESH, GROVER. “FPGA based low power optimal digital system design; -.” 2015. Thesis, Manav Rachna International University. Accessed October 01, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/33328.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

NARESH, GROVER. “FPGA based low power optimal digital system design; -.” 2015. Web. 01 Oct 2020.

Vancouver:

NARESH G. FPGA based low power optimal digital system design; -. [Internet] [Thesis]. Manav Rachna International University; 2015. [cited 2020 Oct 01]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33328.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

NARESH G. FPGA based low power optimal digital system design; -. [Thesis]. Manav Rachna International University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33328

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

14. Faissole, Florian. Formalisations d’analyses d’erreurs en analyse numérique et en arithmétique à virgule flottante : Formalizations of error analysis in numerical analysis and floating-point arithmetic.

Degree: Docteur es, Informatique, 2019, Université Paris-Saclay (ComUE)

Cette thèse est constituée de trois contributions liées à la formalisation en Coq d'analyses d'erreurs dans les domaines de l'analyse numérique et de l'arithmétique à… (more)

Subjects/Keywords: Arithmétique à virgule flottante; Erreurs d'arrondi; Preuves formelles; Coq; Runge-Kutta; Floating-point arithmetic; Rounding errors; Formal proofs; Coq; Runge-Kutta

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APA (6th Edition):

Faissole, F. (2019). Formalisations d’analyses d’erreurs en analyse numérique et en arithmétique à virgule flottante : Formalizations of error analysis in numerical analysis and floating-point arithmetic. (Doctoral Dissertation). Université Paris-Saclay (ComUE). Retrieved from http://www.theses.fr/2019SACLS594

Chicago Manual of Style (16th Edition):

Faissole, Florian. “Formalisations d’analyses d’erreurs en analyse numérique et en arithmétique à virgule flottante : Formalizations of error analysis in numerical analysis and floating-point arithmetic.” 2019. Doctoral Dissertation, Université Paris-Saclay (ComUE). Accessed October 01, 2020. http://www.theses.fr/2019SACLS594.

MLA Handbook (7th Edition):

Faissole, Florian. “Formalisations d’analyses d’erreurs en analyse numérique et en arithmétique à virgule flottante : Formalizations of error analysis in numerical analysis and floating-point arithmetic.” 2019. Web. 01 Oct 2020.

Vancouver:

Faissole F. Formalisations d’analyses d’erreurs en analyse numérique et en arithmétique à virgule flottante : Formalizations of error analysis in numerical analysis and floating-point arithmetic. [Internet] [Doctoral dissertation]. Université Paris-Saclay (ComUE); 2019. [cited 2020 Oct 01]. Available from: http://www.theses.fr/2019SACLS594.

Council of Science Editors:

Faissole F. Formalisations d’analyses d’erreurs en analyse numérique et en arithmétique à virgule flottante : Formalizations of error analysis in numerical analysis and floating-point arithmetic. [Doctoral Dissertation]. Université Paris-Saclay (ComUE); 2019. Available from: http://www.theses.fr/2019SACLS594


Delft University of Technology

15. Hekstra, G.J. CORDIC for High Performance Numerical Computation.

Degree: 1998, Delft University of Technology

Subjects/Keywords: Computer arithmetic; CORDIC; fast rotations; floating-point computations

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hekstra, G. J. (1998). CORDIC for High Performance Numerical Computation. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:3feb3995-5510-4d0f-9897-91066e2735e7 ; urn:NBN:nl:ui:24-uuid:3feb3995-5510-4d0f-9897-91066e2735e7 ; urn:NBN:nl:ui:24-uuid:3feb3995-5510-4d0f-9897-91066e2735e7 ; http://resolver.tudelft.nl/uuid:3feb3995-5510-4d0f-9897-91066e2735e7

Chicago Manual of Style (16th Edition):

Hekstra, G J. “CORDIC for High Performance Numerical Computation.” 1998. Doctoral Dissertation, Delft University of Technology. Accessed October 01, 2020. http://resolver.tudelft.nl/uuid:3feb3995-5510-4d0f-9897-91066e2735e7 ; urn:NBN:nl:ui:24-uuid:3feb3995-5510-4d0f-9897-91066e2735e7 ; urn:NBN:nl:ui:24-uuid:3feb3995-5510-4d0f-9897-91066e2735e7 ; http://resolver.tudelft.nl/uuid:3feb3995-5510-4d0f-9897-91066e2735e7.

MLA Handbook (7th Edition):

Hekstra, G J. “CORDIC for High Performance Numerical Computation.” 1998. Web. 01 Oct 2020.

Vancouver:

Hekstra GJ. CORDIC for High Performance Numerical Computation. [Internet] [Doctoral dissertation]. Delft University of Technology; 1998. [cited 2020 Oct 01]. Available from: http://resolver.tudelft.nl/uuid:3feb3995-5510-4d0f-9897-91066e2735e7 ; urn:NBN:nl:ui:24-uuid:3feb3995-5510-4d0f-9897-91066e2735e7 ; urn:NBN:nl:ui:24-uuid:3feb3995-5510-4d0f-9897-91066e2735e7 ; http://resolver.tudelft.nl/uuid:3feb3995-5510-4d0f-9897-91066e2735e7.

Council of Science Editors:

Hekstra GJ. CORDIC for High Performance Numerical Computation. [Doctoral Dissertation]. Delft University of Technology; 1998. Available from: http://resolver.tudelft.nl/uuid:3feb3995-5510-4d0f-9897-91066e2735e7 ; urn:NBN:nl:ui:24-uuid:3feb3995-5510-4d0f-9897-91066e2735e7 ; urn:NBN:nl:ui:24-uuid:3feb3995-5510-4d0f-9897-91066e2735e7 ; http://resolver.tudelft.nl/uuid:3feb3995-5510-4d0f-9897-91066e2735e7

16. Torres, Serge. Tools for the Design of Reliable and Efficient Functions Evaluation Libraries : Outils pour la conception de bibliothèques de calcul de fonctions efficaces et fiables.

Degree: Docteur es, Informatique, 2016, Lyon

La conception des bibliothèques d’évaluation de fonctions est un activité complexe qui requiert beaucoup de soin et d’application, particulièrement lorsque l’on vise des niveaux élevés… (more)

Subjects/Keywords: Arithmétique des ordinateurs; Approximation de fonctions; Arithmétique flottante; Dilemme du fabricant de tables; Arrondi correct; Computer arithmetic; Function approximation; Floating-point arithmetic; Table Maker's Dilemma; Correct rounding

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APA (6th Edition):

Torres, S. (2016). Tools for the Design of Reliable and Efficient Functions Evaluation Libraries : Outils pour la conception de bibliothèques de calcul de fonctions efficaces et fiables. (Doctoral Dissertation). Lyon. Retrieved from http://www.theses.fr/2016LYSEN030

Chicago Manual of Style (16th Edition):

Torres, Serge. “Tools for the Design of Reliable and Efficient Functions Evaluation Libraries : Outils pour la conception de bibliothèques de calcul de fonctions efficaces et fiables.” 2016. Doctoral Dissertation, Lyon. Accessed October 01, 2020. http://www.theses.fr/2016LYSEN030.

MLA Handbook (7th Edition):

Torres, Serge. “Tools for the Design of Reliable and Efficient Functions Evaluation Libraries : Outils pour la conception de bibliothèques de calcul de fonctions efficaces et fiables.” 2016. Web. 01 Oct 2020.

Vancouver:

Torres S. Tools for the Design of Reliable and Efficient Functions Evaluation Libraries : Outils pour la conception de bibliothèques de calcul de fonctions efficaces et fiables. [Internet] [Doctoral dissertation]. Lyon; 2016. [cited 2020 Oct 01]. Available from: http://www.theses.fr/2016LYSEN030.

Council of Science Editors:

Torres S. Tools for the Design of Reliable and Efficient Functions Evaluation Libraries : Outils pour la conception de bibliothèques de calcul de fonctions efficaces et fiables. [Doctoral Dissertation]. Lyon; 2016. Available from: http://www.theses.fr/2016LYSEN030


Oklahoma State University

17. Castellanos, Ivan Dario. Analysis and Implementation of Decimal Arithmetic Hardware in Nanometer Cmos Technology.

Degree: School of Electrical & Computer Engineering, 2008, Oklahoma State University

 In today's society, decimal arithmetic is growing considerably in importance given its relevance in financial and commercial applications. Decimal calculations on binary hardware significantly impact… (more)

Subjects/Keywords: decimal arithmetic; vlsi; arithmetic; decimal multiplication; decimal addition; decimal floating-point

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APA (6th Edition):

Castellanos, I. D. (2008). Analysis and Implementation of Decimal Arithmetic Hardware in Nanometer Cmos Technology. (Thesis). Oklahoma State University. Retrieved from http://hdl.handle.net/11244/7847

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Castellanos, Ivan Dario. “Analysis and Implementation of Decimal Arithmetic Hardware in Nanometer Cmos Technology.” 2008. Thesis, Oklahoma State University. Accessed October 01, 2020. http://hdl.handle.net/11244/7847.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Castellanos, Ivan Dario. “Analysis and Implementation of Decimal Arithmetic Hardware in Nanometer Cmos Technology.” 2008. Web. 01 Oct 2020.

Vancouver:

Castellanos ID. Analysis and Implementation of Decimal Arithmetic Hardware in Nanometer Cmos Technology. [Internet] [Thesis]. Oklahoma State University; 2008. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/11244/7847.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Castellanos ID. Analysis and Implementation of Decimal Arithmetic Hardware in Nanometer Cmos Technology. [Thesis]. Oklahoma State University; 2008. Available from: http://hdl.handle.net/11244/7847

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. Min, Jae Hong. Fused floating-point arithmetic for application specific processors.

Degree: PhD, Electrical & Computer Engineering, 2013, University of Texas – Austin

Floating-point computer arithmetic units are used for modern-day computers for 2D/3D graphic and scientific applications due to their wider dynamic range than a fixed-point number… (more)

Subjects/Keywords: Floating point arithmetic; Digital arithmetic; Low power design

…5 Floating Point Arithmetic Unit – Floating-Point Adder .................................7… …Floating Point Arithmetic Unit – Floating-Point Multiplier .........................12 CHAPTER 2… …arithmetic unit. It has become a big issue to design low-power floating-point arithmetic units to… …operations, fused floating-point arithmetic units such as a fused multiplyadd unit (FMA)… …applications. The floating-point arithmetic unit can be implemented as a part of the general purpose… 

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APA (6th Edition):

Min, J. H. (2013). Fused floating-point arithmetic for application specific processors. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/23342

Chicago Manual of Style (16th Edition):

Min, Jae Hong. “Fused floating-point arithmetic for application specific processors.” 2013. Doctoral Dissertation, University of Texas – Austin. Accessed October 01, 2020. http://hdl.handle.net/2152/23342.

MLA Handbook (7th Edition):

Min, Jae Hong. “Fused floating-point arithmetic for application specific processors.” 2013. Web. 01 Oct 2020.

Vancouver:

Min JH. Fused floating-point arithmetic for application specific processors. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2013. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/2152/23342.

Council of Science Editors:

Min JH. Fused floating-point arithmetic for application specific processors. [Doctoral Dissertation]. University of Texas – Austin; 2013. Available from: http://hdl.handle.net/2152/23342


Georgia Tech

19. Weinstein, Randall Kenneth. Techniques for FPGA neural modeling.

Degree: PhD, Bioengineering, 2006, Georgia Tech

 Neural simulations and general dynamical system modeling consistently push the limits of available computational horsepower. This is occurring for a number of reasons: 1) models… (more)

Subjects/Keywords: Motoneuron; Field programmable gate arrays; Neural computers; Floating Point arithmetic; Computer arithmetic

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APA (6th Edition):

Weinstein, R. K. (2006). Techniques for FPGA neural modeling. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/26685

Chicago Manual of Style (16th Edition):

Weinstein, Randall Kenneth. “Techniques for FPGA neural modeling.” 2006. Doctoral Dissertation, Georgia Tech. Accessed October 01, 2020. http://hdl.handle.net/1853/26685.

MLA Handbook (7th Edition):

Weinstein, Randall Kenneth. “Techniques for FPGA neural modeling.” 2006. Web. 01 Oct 2020.

Vancouver:

Weinstein RK. Techniques for FPGA neural modeling. [Internet] [Doctoral dissertation]. Georgia Tech; 2006. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1853/26685.

Council of Science Editors:

Weinstein RK. Techniques for FPGA neural modeling. [Doctoral Dissertation]. Georgia Tech; 2006. Available from: http://hdl.handle.net/1853/26685

20. Rosenblum, David Samuel. An Implementation of the IEEE Standard for Binary Floating-Point Arithmetic for the Motorola 6809 Microprocessor.

Degree: 1983, North Texas State University

 This thesis describes a software implementation of the IEEE Floating-Point Standard (IEEE Task P754), which is believed to be an effective system for reliable, accurate… (more)

Subjects/Keywords: floating-point standard; assembly language; computer arithmetic; Microprocessors  – Programming.; Computer arithmetic.

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APA (6th Edition):

Rosenblum, D. S. (1983). An Implementation of the IEEE Standard for Binary Floating-Point Arithmetic for the Motorola 6809 Microprocessor. (Thesis). North Texas State University. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc503940/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rosenblum, David Samuel. “An Implementation of the IEEE Standard for Binary Floating-Point Arithmetic for the Motorola 6809 Microprocessor.” 1983. Thesis, North Texas State University. Accessed October 01, 2020. https://digital.library.unt.edu/ark:/67531/metadc503940/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rosenblum, David Samuel. “An Implementation of the IEEE Standard for Binary Floating-Point Arithmetic for the Motorola 6809 Microprocessor.” 1983. Web. 01 Oct 2020.

Vancouver:

Rosenblum DS. An Implementation of the IEEE Standard for Binary Floating-Point Arithmetic for the Motorola 6809 Microprocessor. [Internet] [Thesis]. North Texas State University; 1983. [cited 2020 Oct 01]. Available from: https://digital.library.unt.edu/ark:/67531/metadc503940/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rosenblum DS. An Implementation of the IEEE Standard for Binary Floating-Point Arithmetic for the Motorola 6809 Microprocessor. [Thesis]. North Texas State University; 1983. Available from: https://digital.library.unt.edu/ark:/67531/metadc503940/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Ratan, Amrita. Hardware Modules for Safe Integer and Floating-Point Arithmetic.

Degree: MS, Engineering and Applied Science: Computer Engineering, 2013, University of Cincinnati

 Integer and floating-point data types are widely used to represent numerical data in computer arithmetic. Since the range of values representable in a computer are… (more)

Subjects/Keywords: Computer Engineering; computer arithmetic; integer overflows; floating-point overflows; arithmetic and logic unit; floating-point unit

floating-point data. We present our hardware logic design of an Arithmetic and Logic Unit (… …Floating-Point Unit (FPU) that performs basic arithmetic operations on floating-point… …floating-point arithmetic. The goals of the thesis are also presented in this chapter. 2.1… …integer or floating-point data types is limited. For this reason, arithmetic operations on… …Their limited size representation in computer arithmetic leads to inaccuracy in floating-point… 

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APA (6th Edition):

Ratan, A. (2013). Hardware Modules for Safe Integer and Floating-Point Arithmetic. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1383812316

Chicago Manual of Style (16th Edition):

Ratan, Amrita. “Hardware Modules for Safe Integer and Floating-Point Arithmetic.” 2013. Masters Thesis, University of Cincinnati. Accessed October 01, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1383812316.

MLA Handbook (7th Edition):

Ratan, Amrita. “Hardware Modules for Safe Integer and Floating-Point Arithmetic.” 2013. Web. 01 Oct 2020.

Vancouver:

Ratan A. Hardware Modules for Safe Integer and Floating-Point Arithmetic. [Internet] [Masters thesis]. University of Cincinnati; 2013. [cited 2020 Oct 01]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1383812316.

Council of Science Editors:

Ratan A. Hardware Modules for Safe Integer and Floating-Point Arithmetic. [Masters Thesis]. University of Cincinnati; 2013. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1383812316

22. Plet, Antoine. Contribution to error analysis of algorithms in floating-point arithmetic : Contribution à l'analyse d'algorithmes en arithmétique à virgule flottante.

Degree: Docteur es, Informatique, 2017, Lyon

L’arithmétique virgule flottante est une approximation de l’arithmétique réelle dans laquelle chaque opération peut introduire une erreur. La norme IEEE 754 requiert que les opérations… (more)

Subjects/Keywords: Arithmétique à virgule flottante; Arithmétique complexe en virgule flottante; Analyse d'erreur; Arrondi correct; Erreur numérique; Calcul symbolique; Bibliothèque Maple; Floating-point arithmetic; Complex floating-point arithmetic; Error analysis; Correct rounding; Numerical error; Symbolic computation; Maple library

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APA (6th Edition):

Plet, A. (2017). Contribution to error analysis of algorithms in floating-point arithmetic : Contribution à l'analyse d'algorithmes en arithmétique à virgule flottante. (Doctoral Dissertation). Lyon. Retrieved from http://www.theses.fr/2017LYSEN038

Chicago Manual of Style (16th Edition):

Plet, Antoine. “Contribution to error analysis of algorithms in floating-point arithmetic : Contribution à l'analyse d'algorithmes en arithmétique à virgule flottante.” 2017. Doctoral Dissertation, Lyon. Accessed October 01, 2020. http://www.theses.fr/2017LYSEN038.

MLA Handbook (7th Edition):

Plet, Antoine. “Contribution to error analysis of algorithms in floating-point arithmetic : Contribution à l'analyse d'algorithmes en arithmétique à virgule flottante.” 2017. Web. 01 Oct 2020.

Vancouver:

Plet A. Contribution to error analysis of algorithms in floating-point arithmetic : Contribution à l'analyse d'algorithmes en arithmétique à virgule flottante. [Internet] [Doctoral dissertation]. Lyon; 2017. [cited 2020 Oct 01]. Available from: http://www.theses.fr/2017LYSEN038.

Council of Science Editors:

Plet A. Contribution to error analysis of algorithms in floating-point arithmetic : Contribution à l'analyse d'algorithmes en arithmétique à virgule flottante. [Doctoral Dissertation]. Lyon; 2017. Available from: http://www.theses.fr/2017LYSEN038

23. Popescu, Valentina. Towards fast and certified multiple-precision librairies : Vers des bibliothèques multi-précision certifiées et performantes.

Degree: Docteur es, Informatique, 2017, Lyon

De nombreux problèmes de calcul numérique demandent parfois à effectuer des calculs très précis. L'étude desystèmes dynamiques chaotiques fournit des exemples très connus: la stabilité… (more)

Subjects/Keywords: Arithmétique flottante; Arithmétique multi-précision; Calcul GPGPU; Expansions virgule flottante; Processeurs graphiques; Systèmes dynamiques; Attracteur de Hénon; Programmation semi-définie mal-posée; Floating-point arithmetic; Multi-precision arithmetic; GPGPU computing; Floating-point expansions; Graphics process unit; Dynamical systems; Henon map; Ill-posed semidefinite programming

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APA (6th Edition):

Popescu, V. (2017). Towards fast and certified multiple-precision librairies : Vers des bibliothèques multi-précision certifiées et performantes. (Doctoral Dissertation). Lyon. Retrieved from http://www.theses.fr/2017LYSEN036

Chicago Manual of Style (16th Edition):

Popescu, Valentina. “Towards fast and certified multiple-precision librairies : Vers des bibliothèques multi-précision certifiées et performantes.” 2017. Doctoral Dissertation, Lyon. Accessed October 01, 2020. http://www.theses.fr/2017LYSEN036.

MLA Handbook (7th Edition):

Popescu, Valentina. “Towards fast and certified multiple-precision librairies : Vers des bibliothèques multi-précision certifiées et performantes.” 2017. Web. 01 Oct 2020.

Vancouver:

Popescu V. Towards fast and certified multiple-precision librairies : Vers des bibliothèques multi-précision certifiées et performantes. [Internet] [Doctoral dissertation]. Lyon; 2017. [cited 2020 Oct 01]. Available from: http://www.theses.fr/2017LYSEN036.

Council of Science Editors:

Popescu V. Towards fast and certified multiple-precision librairies : Vers des bibliothèques multi-précision certifiées et performantes. [Doctoral Dissertation]. Lyon; 2017. Available from: http://www.theses.fr/2017LYSEN036

24. Brunie, Nicolas. Contribution à l'arithmétique des ordinateurs et applications aux systèmes embarqués : Contributions to computer arithmetic and applications to embedded systems.

Degree: Docteur es, Informatique, 2014, Lyon, École normale supérieure

Au cours des dernières décennies les systèmes embarqués ont dû faire face à des demandes applicatives de plus en plus variées et de plus en… (more)

Subjects/Keywords: Arithmétique; Système; Embarqué; Virgule flottante; FMA; Fonctions élémentaires; Reconfigurable; Matériel; Logiciel; Implémentation; Architecture; Micro-architecture; Unité virgule flottante; Sous-normaux; Arithmetic; System; Embedded; Floating-point; FMA; Elementary functions; Reconfigurable; Hardware; Software; Implementation; Architecture; Micro-architecture; Floating-point unit; Subnormal; 004

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APA (6th Edition):

Brunie, N. (2014). Contribution à l'arithmétique des ordinateurs et applications aux systèmes embarqués : Contributions to computer arithmetic and applications to embedded systems. (Doctoral Dissertation). Lyon, École normale supérieure. Retrieved from http://www.theses.fr/2014ENSL0894

Chicago Manual of Style (16th Edition):

Brunie, Nicolas. “Contribution à l'arithmétique des ordinateurs et applications aux systèmes embarqués : Contributions to computer arithmetic and applications to embedded systems.” 2014. Doctoral Dissertation, Lyon, École normale supérieure. Accessed October 01, 2020. http://www.theses.fr/2014ENSL0894.

MLA Handbook (7th Edition):

Brunie, Nicolas. “Contribution à l'arithmétique des ordinateurs et applications aux systèmes embarqués : Contributions to computer arithmetic and applications to embedded systems.” 2014. Web. 01 Oct 2020.

Vancouver:

Brunie N. Contribution à l'arithmétique des ordinateurs et applications aux systèmes embarqués : Contributions to computer arithmetic and applications to embedded systems. [Internet] [Doctoral dissertation]. Lyon, École normale supérieure; 2014. [cited 2020 Oct 01]. Available from: http://www.theses.fr/2014ENSL0894.

Council of Science Editors:

Brunie N. Contribution à l'arithmétique des ordinateurs et applications aux systèmes embarqués : Contributions to computer arithmetic and applications to embedded systems. [Doctoral Dissertation]. Lyon, École normale supérieure; 2014. Available from: http://www.theses.fr/2014ENSL0894


ITESO – Universidad Jesuita de Guadalajara

25. Aguilera-Galicia, Cuauhtémoc R. Design and Implementation of Reciprocal Square Root Units on Digital ASIC Technology For Low Power Embedded Applications .

Degree: 2019, ITESO – Universidad Jesuita de Guadalajara

Subjects/Keywords: Reciprocal Square Root; Digital ASIC; Newton-Raphson; Piecewise Polynomial Approximation; Floating Point Arithmetic; Fixed Point Arithmetic

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APA (6th Edition):

Aguilera-Galicia, C. R. (2019). Design and Implementation of Reciprocal Square Root Units on Digital ASIC Technology For Low Power Embedded Applications . (Thesis). ITESO – Universidad Jesuita de Guadalajara. Retrieved from http://hdl.handle.net/11117/5844

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Aguilera-Galicia, Cuauhtémoc R. “Design and Implementation of Reciprocal Square Root Units on Digital ASIC Technology For Low Power Embedded Applications .” 2019. Thesis, ITESO – Universidad Jesuita de Guadalajara. Accessed October 01, 2020. http://hdl.handle.net/11117/5844.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Aguilera-Galicia, Cuauhtémoc R. “Design and Implementation of Reciprocal Square Root Units on Digital ASIC Technology For Low Power Embedded Applications .” 2019. Web. 01 Oct 2020.

Vancouver:

Aguilera-Galicia CR. Design and Implementation of Reciprocal Square Root Units on Digital ASIC Technology For Low Power Embedded Applications . [Internet] [Thesis]. ITESO – Universidad Jesuita de Guadalajara; 2019. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/11117/5844.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Aguilera-Galicia CR. Design and Implementation of Reciprocal Square Root Units on Digital ASIC Technology For Low Power Embedded Applications . [Thesis]. ITESO – Universidad Jesuita de Guadalajara; 2019. Available from: http://hdl.handle.net/11117/5844

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

26. Williams, Bertrand Jeffery. A bit-serial floating point multiply/add architecture for signal processing applications.

Degree: MS, electrical engineering, 2012, Texas A&M University

Subjects/Keywords: electrical engineering.; Major electrical engineering.; Signal processing.; Computer architecture.; Floating-point arithmetic.

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APA (6th Edition):

Williams, B. J. (2012). A bit-serial floating point multiply/add architecture for signal processing applications. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-1983-THESIS-W721

Chicago Manual of Style (16th Edition):

Williams, Bertrand Jeffery. “A bit-serial floating point multiply/add architecture for signal processing applications.” 2012. Masters Thesis, Texas A&M University. Accessed October 01, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-1983-THESIS-W721.

MLA Handbook (7th Edition):

Williams, Bertrand Jeffery. “A bit-serial floating point multiply/add architecture for signal processing applications.” 2012. Web. 01 Oct 2020.

Vancouver:

Williams BJ. A bit-serial floating point multiply/add architecture for signal processing applications. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1983-THESIS-W721.

Council of Science Editors:

Williams BJ. A bit-serial floating point multiply/add architecture for signal processing applications. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1983-THESIS-W721

27. Damouche, Nasrine. Improving the Numerical Accuracy of Floating-Point Programs with Automatic Code Transformation Methods : Amélioration de la précision numérique de programmes basés sur l'arithmétique flottante par les méthodes de transformation automatique.

Degree: Docteur es, Informatique, 2016, Perpignan

Les systèmes critiques basés sur l’arithmétique flottante exigent un processus rigoureux de vérification et de validation pour augmenter notre confiance en leur sureté et leur… (more)

Subjects/Keywords: Arithmétique flottante; Précision numérique; Erreur d'arrondi; Transformation automatique de programmes; Analyse statique; Interprétation abstraite; Floating-point arithmetic; Numerical accuracy; Rounding errors; Automatic transformation of programs; Static analysis; Abstract interpretation; 004

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Damouche, N. (2016). Improving the Numerical Accuracy of Floating-Point Programs with Automatic Code Transformation Methods : Amélioration de la précision numérique de programmes basés sur l'arithmétique flottante par les méthodes de transformation automatique. (Doctoral Dissertation). Perpignan. Retrieved from http://www.theses.fr/2016PERP0032

Chicago Manual of Style (16th Edition):

Damouche, Nasrine. “Improving the Numerical Accuracy of Floating-Point Programs with Automatic Code Transformation Methods : Amélioration de la précision numérique de programmes basés sur l'arithmétique flottante par les méthodes de transformation automatique.” 2016. Doctoral Dissertation, Perpignan. Accessed October 01, 2020. http://www.theses.fr/2016PERP0032.

MLA Handbook (7th Edition):

Damouche, Nasrine. “Improving the Numerical Accuracy of Floating-Point Programs with Automatic Code Transformation Methods : Amélioration de la précision numérique de programmes basés sur l'arithmétique flottante par les méthodes de transformation automatique.” 2016. Web. 01 Oct 2020.

Vancouver:

Damouche N. Improving the Numerical Accuracy of Floating-Point Programs with Automatic Code Transformation Methods : Amélioration de la précision numérique de programmes basés sur l'arithmétique flottante par les méthodes de transformation automatique. [Internet] [Doctoral dissertation]. Perpignan; 2016. [cited 2020 Oct 01]. Available from: http://www.theses.fr/2016PERP0032.

Council of Science Editors:

Damouche N. Improving the Numerical Accuracy of Floating-Point Programs with Automatic Code Transformation Methods : Amélioration de la précision numérique de programmes basés sur l'arithmétique flottante par les méthodes de transformation automatique. [Doctoral Dissertation]. Perpignan; 2016. Available from: http://www.theses.fr/2016PERP0032


Brno University of Technology

28. Válek, Vít. Moderní metody návrhu řídicích systémů s podporou MATLAB/Simulink: Novel Methods of Control Systems Design with MATLAB/Simulink.

Degree: 2019, Brno University of Technology

 The content of this thesis is to introduce the tools of MATLAB/Simulink, which allow to generate the source code in C language. It will be… (more)

Subjects/Keywords: Generování kódu; zdrojový kód; celočíselná a plovoucí aritmetika; vektorové řízení; RTCESL; Code generation; source code; fixed and floating point arithmetic; field-oriented control; RTCESL

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Válek, V. (2019). Moderní metody návrhu řídicích systémů s podporou MATLAB/Simulink: Novel Methods of Control Systems Design with MATLAB/Simulink. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/173682

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Válek, Vít. “Moderní metody návrhu řídicích systémů s podporou MATLAB/Simulink: Novel Methods of Control Systems Design with MATLAB/Simulink.” 2019. Thesis, Brno University of Technology. Accessed October 01, 2020. http://hdl.handle.net/11012/173682.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Válek, Vít. “Moderní metody návrhu řídicích systémů s podporou MATLAB/Simulink: Novel Methods of Control Systems Design with MATLAB/Simulink.” 2019. Web. 01 Oct 2020.

Vancouver:

Válek V. Moderní metody návrhu řídicích systémů s podporou MATLAB/Simulink: Novel Methods of Control Systems Design with MATLAB/Simulink. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Oct 01]. Available from: http://hdl.handle.net/11012/173682.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Válek V. Moderní metody návrhu řídicích systémů s podporou MATLAB/Simulink: Novel Methods of Control Systems Design with MATLAB/Simulink. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/173682

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Kupriianova, Olga. Towards a modern floating-point environment : Vers l'environnement flottant moderne.

Degree: Docteur es, Informatique, 2015, Université Pierre et Marie Curie – Paris VI

Cette thèse fait une étude sur deux moyens d'enrichir l'environnement flottant courant : le premier est d'obtenir plusieurs versions d'implantation pour chaque fonction mathématique, le… (more)

Subjects/Keywords: Arithmétique des ordinateurs; Virgule flottante; Fonctions élémentaires; Générateur de code; Metalibm; Arithmétique en base mixte; Computer arithmetic; Floating-point numbers; Elementary functions; 004

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kupriianova, O. (2015). Towards a modern floating-point environment : Vers l'environnement flottant moderne. (Doctoral Dissertation). Université Pierre et Marie Curie – Paris VI. Retrieved from http://www.theses.fr/2015PA066584

Chicago Manual of Style (16th Edition):

Kupriianova, Olga. “Towards a modern floating-point environment : Vers l'environnement flottant moderne.” 2015. Doctoral Dissertation, Université Pierre et Marie Curie – Paris VI. Accessed October 01, 2020. http://www.theses.fr/2015PA066584.

MLA Handbook (7th Edition):

Kupriianova, Olga. “Towards a modern floating-point environment : Vers l'environnement flottant moderne.” 2015. Web. 01 Oct 2020.

Vancouver:

Kupriianova O. Towards a modern floating-point environment : Vers l'environnement flottant moderne. [Internet] [Doctoral dissertation]. Université Pierre et Marie Curie – Paris VI; 2015. [cited 2020 Oct 01]. Available from: http://www.theses.fr/2015PA066584.

Council of Science Editors:

Kupriianova O. Towards a modern floating-point environment : Vers l'environnement flottant moderne. [Doctoral Dissertation]. Université Pierre et Marie Curie – Paris VI; 2015. Available from: http://www.theses.fr/2015PA066584

30. Nheili, Rafife. How to improve the numerical reproducibility of hydrodynamics simulations : analysis and solutions for one open-source HPC software : Galling in stainless steels : influence of materials nature, microstructure and thermochemical heat surface treatment.

Degree: Docteur es, Informatique, 2016, Perpignan

La non-reproductibilité numérique apparait dans divers domaines d'application de la simulation HPC. En effet, les différentes distributions d'un calcul parallèle peuvent mener à des résultats… (more)

Subjects/Keywords: Arithmétique flottante; Reproductibilité; Éléments finis; Décomposition de domaine; Simulation hydrodynamique; Compensation; OpenTelemac; Floating-point arithmetic; Reproducibility; Finite element; Domain decomposition; Hydrodynamics simulation; Compensation; OpenTelemac; 004

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nheili, R. (2016). How to improve the numerical reproducibility of hydrodynamics simulations : analysis and solutions for one open-source HPC software : Galling in stainless steels : influence of materials nature, microstructure and thermochemical heat surface treatment. (Doctoral Dissertation). Perpignan. Retrieved from http://www.theses.fr/2016PERP0045

Chicago Manual of Style (16th Edition):

Nheili, Rafife. “How to improve the numerical reproducibility of hydrodynamics simulations : analysis and solutions for one open-source HPC software : Galling in stainless steels : influence of materials nature, microstructure and thermochemical heat surface treatment.” 2016. Doctoral Dissertation, Perpignan. Accessed October 01, 2020. http://www.theses.fr/2016PERP0045.

MLA Handbook (7th Edition):

Nheili, Rafife. “How to improve the numerical reproducibility of hydrodynamics simulations : analysis and solutions for one open-source HPC software : Galling in stainless steels : influence of materials nature, microstructure and thermochemical heat surface treatment.” 2016. Web. 01 Oct 2020.

Vancouver:

Nheili R. How to improve the numerical reproducibility of hydrodynamics simulations : analysis and solutions for one open-source HPC software : Galling in stainless steels : influence of materials nature, microstructure and thermochemical heat surface treatment. [Internet] [Doctoral dissertation]. Perpignan; 2016. [cited 2020 Oct 01]. Available from: http://www.theses.fr/2016PERP0045.

Council of Science Editors:

Nheili R. How to improve the numerical reproducibility of hydrodynamics simulations : analysis and solutions for one open-source HPC software : Galling in stainless steels : influence of materials nature, microstructure and thermochemical heat surface treatment. [Doctoral Dissertation]. Perpignan; 2016. Available from: http://www.theses.fr/2016PERP0045

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