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You searched for subject:(Flip chip). Showing records 1 – 30 of 74 total matches.

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University of Waterloo

1. Laor, Ariel. A Novel 8x8 CMOS Sensor Array for Thermal Compression Bonding with in-situ XYZ Force and Temperature Measurement.

Degree: 2016, University of Waterloo

Flip chip is an electronic packaging technology that is becoming more popular in first level electronic packaging as the need for high density electrical interconnects… (more)

Subjects/Keywords: Flip Chip Electronic Packaging CMOS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Laor, A. (2016). A Novel 8x8 CMOS Sensor Array for Thermal Compression Bonding with in-situ XYZ Force and Temperature Measurement. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/10452

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Laor, Ariel. “A Novel 8x8 CMOS Sensor Array for Thermal Compression Bonding with in-situ XYZ Force and Temperature Measurement.” 2016. Thesis, University of Waterloo. Accessed September 23, 2019. http://hdl.handle.net/10012/10452.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Laor, Ariel. “A Novel 8x8 CMOS Sensor Array for Thermal Compression Bonding with in-situ XYZ Force and Temperature Measurement.” 2016. Web. 23 Sep 2019.

Vancouver:

Laor A. A Novel 8x8 CMOS Sensor Array for Thermal Compression Bonding with in-situ XYZ Force and Temperature Measurement. [Internet] [Thesis]. University of Waterloo; 2016. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/10012/10452.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Laor A. A Novel 8x8 CMOS Sensor Array for Thermal Compression Bonding with in-situ XYZ Force and Temperature Measurement. [Thesis]. University of Waterloo; 2016. Available from: http://hdl.handle.net/10012/10452

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

2. Huang, Chang-Chia. Short-Time Scale Dynamic Failure Modes in a Through-Silicon-Via (TSV) Flip-Chip Configuration.

Degree: 2010, Texas A&M University

 The demand for high performance microelectronic products drives the development of 3-D chip-stacking structure. By the introduction of through-silicon-via (TSV) into 3-D flip-chip packages, microelectronic… (more)

Subjects/Keywords: Flip-chip packages; Reliability; Short-time scale

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APA (6th Edition):

Huang, C. (2010). Short-Time Scale Dynamic Failure Modes in a Through-Silicon-Via (TSV) Flip-Chip Configuration. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2009-08-7037

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Chang-Chia. “Short-Time Scale Dynamic Failure Modes in a Through-Silicon-Via (TSV) Flip-Chip Configuration.” 2010. Thesis, Texas A&M University. Accessed September 23, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2009-08-7037.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Chang-Chia. “Short-Time Scale Dynamic Failure Modes in a Through-Silicon-Via (TSV) Flip-Chip Configuration.” 2010. Web. 23 Sep 2019.

Vancouver:

Huang C. Short-Time Scale Dynamic Failure Modes in a Through-Silicon-Via (TSV) Flip-Chip Configuration. [Internet] [Thesis]. Texas A&M University; 2010. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-08-7037.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang C. Short-Time Scale Dynamic Failure Modes in a Through-Silicon-Via (TSV) Flip-Chip Configuration. [Thesis]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-08-7037

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

3. Chen, Ping-Ju. Numerical Simulation on Thermal Fatigue of a Flip Chip Scale Packaging.

Degree: Master, Mechanical and Electro-Mechanical Engineering, 2002, NSYSU

 Abstract The thesis is aimed to simulate the flip chip in chip scale package (FCCSP) by finite element method incorporated with software ANSYS due to… (more)

Subjects/Keywords: Fatigue; Flip Chip

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APA (6th Edition):

Chen, P. (2002). Numerical Simulation on Thermal Fatigue of a Flip Chip Scale Packaging. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627102-185433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Ping-Ju. “Numerical Simulation on Thermal Fatigue of a Flip Chip Scale Packaging.” 2002. Thesis, NSYSU. Accessed September 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627102-185433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Ping-Ju. “Numerical Simulation on Thermal Fatigue of a Flip Chip Scale Packaging.” 2002. Web. 23 Sep 2019.

Vancouver:

Chen P. Numerical Simulation on Thermal Fatigue of a Flip Chip Scale Packaging. [Internet] [Thesis]. NSYSU; 2002. [cited 2019 Sep 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627102-185433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen P. Numerical Simulation on Thermal Fatigue of a Flip Chip Scale Packaging. [Thesis]. NSYSU; 2002. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627102-185433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

4. Lightsey, Charles Hunter. All-copper chip-to-substrate interconnections for flip-chip packages.

Degree: MS, Chemical Engineering, 2010, Georgia Tech

 Avatrel 8000P's excellent photo-definition properties and mechanical strength make it an ideal polymer collar material. Avatrel 8000P is a high contrast, I-line sensitive mixture that… (more)

Subjects/Keywords: Bonding; Flip-chip; Pillar; Electroless deposition; Copper; Flip chip technology; Microelectronic packaging; Microelectronics; Electroless plating

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APA (6th Edition):

Lightsey, C. H. (2010). All-copper chip-to-substrate interconnections for flip-chip packages. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/34729

Chicago Manual of Style (16th Edition):

Lightsey, Charles Hunter. “All-copper chip-to-substrate interconnections for flip-chip packages.” 2010. Masters Thesis, Georgia Tech. Accessed September 23, 2019. http://hdl.handle.net/1853/34729.

MLA Handbook (7th Edition):

Lightsey, Charles Hunter. “All-copper chip-to-substrate interconnections for flip-chip packages.” 2010. Web. 23 Sep 2019.

Vancouver:

Lightsey CH. All-copper chip-to-substrate interconnections for flip-chip packages. [Internet] [Masters thesis]. Georgia Tech; 2010. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/1853/34729.

Council of Science Editors:

Lightsey CH. All-copper chip-to-substrate interconnections for flip-chip packages. [Masters Thesis]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/34729


Georgia Tech

5. Lee, Sangil. Fundamental study of underfill void formation in flip chip assembly.

Degree: PhD, Mechanical Engineering, 2009, Georgia Tech

Flip Chip in Package (FCIP) has been developed to achieve the assembly process with area array interconnects. Particularly, a high I/O count coupled with finer… (more)

Subjects/Keywords: Nano; Nucleation; Void; No-flow; Flip chip; Flip chip technology; Microelectronic packaging; Solder and soldering

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APA (6th Edition):

Lee, S. (2009). Fundamental study of underfill void formation in flip chip assembly. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/29755

Chicago Manual of Style (16th Edition):

Lee, Sangil. “Fundamental study of underfill void formation in flip chip assembly.” 2009. Doctoral Dissertation, Georgia Tech. Accessed September 23, 2019. http://hdl.handle.net/1853/29755.

MLA Handbook (7th Edition):

Lee, Sangil. “Fundamental study of underfill void formation in flip chip assembly.” 2009. Web. 23 Sep 2019.

Vancouver:

Lee S. Fundamental study of underfill void formation in flip chip assembly. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/1853/29755.

Council of Science Editors:

Lee S. Fundamental study of underfill void formation in flip chip assembly. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/29755


Brno University of Technology

6. Dóczy, Robert. Izolační vlastnosti struktur typu Flip chip .

Degree: 2012, Brno University of Technology

 Tato práce se zabývá problematikou izolačních vlastností mikroelektronických struktur. Konkrétně odporem izolační mezery, jež odděluje vodivé části systému. Jsou zde nastíněny vlivy, které na izolační… (more)

Subjects/Keywords: Izolační odpor; Flip chip; čištění; substrát; Insulation resistance; Flip chip; cleaning; substrate

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APA (6th Edition):

Dóczy, R. (2012). Izolační vlastnosti struktur typu Flip chip . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/12610

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dóczy, Robert. “Izolační vlastnosti struktur typu Flip chip .” 2012. Thesis, Brno University of Technology. Accessed September 23, 2019. http://hdl.handle.net/11012/12610.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dóczy, Robert. “Izolační vlastnosti struktur typu Flip chip .” 2012. Web. 23 Sep 2019.

Vancouver:

Dóczy R. Izolační vlastnosti struktur typu Flip chip . [Internet] [Thesis]. Brno University of Technology; 2012. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/11012/12610.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dóczy R. Izolační vlastnosti struktur typu Flip chip . [Thesis]. Brno University of Technology; 2012. Available from: http://hdl.handle.net/11012/12610

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

7. Anjos, Angélica dos. Integração de blocos RF CMOS com indutores usando tecnologia Flip Chip.

Degree: PhD, Microeletrônica, 2012, University of São Paulo

 Neste trabalho foi feita uma ampla pesquisa sobre blocos de RF, VCOs e LNAs, que fazem parte de transceptores. Esses blocos foram projetados utilizando um… (more)

Subjects/Keywords: ASITIC; ASITIC; Circuitos integrados (Projeto); Flip Chip; Flip Chip; Inductors; Indutores; LNA; LNA; RF CMOS; RF CMOS; VCO; VCO

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APA (6th Edition):

Anjos, A. d. (2012). Integração de blocos RF CMOS com indutores usando tecnologia Flip Chip. (Doctoral Dissertation). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/3/3140/tde-15072013-164829/ ;

Chicago Manual of Style (16th Edition):

Anjos, Angélica dos. “Integração de blocos RF CMOS com indutores usando tecnologia Flip Chip.” 2012. Doctoral Dissertation, University of São Paulo. Accessed September 23, 2019. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-15072013-164829/ ;.

MLA Handbook (7th Edition):

Anjos, Angélica dos. “Integração de blocos RF CMOS com indutores usando tecnologia Flip Chip.” 2012. Web. 23 Sep 2019.

Vancouver:

Anjos Ad. Integração de blocos RF CMOS com indutores usando tecnologia Flip Chip. [Internet] [Doctoral dissertation]. University of São Paulo; 2012. [cited 2019 Sep 23]. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-15072013-164829/ ;.

Council of Science Editors:

Anjos Ad. Integração de blocos RF CMOS com indutores usando tecnologia Flip Chip. [Doctoral Dissertation]. University of São Paulo; 2012. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-15072013-164829/ ;

8. Jemai, Norchene. Développement de la technique de sérigraphie pour la formation de billes de connexions inférieures a 100µm pour l'assemblage 3D : optimisation et étude de fiabilité : Stencil printing of Pb-free solder paste for formation of bumps smaller than 100μm : optimization and reliability study.

Degree: Docteur es, Conception des circuits microelectroniques et microsystemes, 2010, Toulouse, INSA

L’assemblage et le conditionnement en électronique représentent un enjeu de création de nouveaux systèmes électroniques hybrides rassemblant sur un même substrat des éléments électroniques, optiques,… (more)

Subjects/Keywords: Pâte à braser sans-Plomb; Technologie Flip-Chip; Sérigraphie; Pb-free solder paste; Flip-Chip Technology; Stencil printing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jemai, N. (2010). Développement de la technique de sérigraphie pour la formation de billes de connexions inférieures a 100µm pour l'assemblage 3D : optimisation et étude de fiabilité : Stencil printing of Pb-free solder paste for formation of bumps smaller than 100μm : optimization and reliability study. (Doctoral Dissertation). Toulouse, INSA. Retrieved from http://www.theses.fr/2010ISAT0010

Chicago Manual of Style (16th Edition):

Jemai, Norchene. “Développement de la technique de sérigraphie pour la formation de billes de connexions inférieures a 100µm pour l'assemblage 3D : optimisation et étude de fiabilité : Stencil printing of Pb-free solder paste for formation of bumps smaller than 100μm : optimization and reliability study.” 2010. Doctoral Dissertation, Toulouse, INSA. Accessed September 23, 2019. http://www.theses.fr/2010ISAT0010.

MLA Handbook (7th Edition):

Jemai, Norchene. “Développement de la technique de sérigraphie pour la formation de billes de connexions inférieures a 100µm pour l'assemblage 3D : optimisation et étude de fiabilité : Stencil printing of Pb-free solder paste for formation of bumps smaller than 100μm : optimization and reliability study.” 2010. Web. 23 Sep 2019.

Vancouver:

Jemai N. Développement de la technique de sérigraphie pour la formation de billes de connexions inférieures a 100µm pour l'assemblage 3D : optimisation et étude de fiabilité : Stencil printing of Pb-free solder paste for formation of bumps smaller than 100μm : optimization and reliability study. [Internet] [Doctoral dissertation]. Toulouse, INSA; 2010. [cited 2019 Sep 23]. Available from: http://www.theses.fr/2010ISAT0010.

Council of Science Editors:

Jemai N. Développement de la technique de sérigraphie pour la formation de billes de connexions inférieures a 100µm pour l'assemblage 3D : optimisation et étude de fiabilité : Stencil printing of Pb-free solder paste for formation of bumps smaller than 100μm : optimization and reliability study. [Doctoral Dissertation]. Toulouse, INSA; 2010. Available from: http://www.theses.fr/2010ISAT0010

9. Quelennec, Aurore. Capteurs intégrés pour la fiabilisation des technologies d'encapsulation en microélectronique : Embedded sensors for microelectronics packaged module reliability.

Degree: Docteur es, Electronique, 2018, Bordeaux; Université de Sherbrooke (Québec, Canada)

L’entreprise IBM a lancé en 2014 un projet de recherche pour introduire de l’intelligence, c’est-à-dire des capteurs, dans des modules micro-électroniques. Le projet vise l’amélioration,… (more)

Subjects/Keywords: Matrice de capteurs; Découplage; Température; Humidité; Flip-chip; Fiabilité; Contrainte; Array of sensors; Separation; Temperature; Moisture; Flip-chip; Reliability; Strain

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Quelennec, A. (2018). Capteurs intégrés pour la fiabilisation des technologies d'encapsulation en microélectronique : Embedded sensors for microelectronics packaged module reliability. (Doctoral Dissertation). Bordeaux; Université de Sherbrooke (Québec, Canada). Retrieved from http://www.theses.fr/2018BORD0105

Chicago Manual of Style (16th Edition):

Quelennec, Aurore. “Capteurs intégrés pour la fiabilisation des technologies d'encapsulation en microélectronique : Embedded sensors for microelectronics packaged module reliability.” 2018. Doctoral Dissertation, Bordeaux; Université de Sherbrooke (Québec, Canada). Accessed September 23, 2019. http://www.theses.fr/2018BORD0105.

MLA Handbook (7th Edition):

Quelennec, Aurore. “Capteurs intégrés pour la fiabilisation des technologies d'encapsulation en microélectronique : Embedded sensors for microelectronics packaged module reliability.” 2018. Web. 23 Sep 2019.

Vancouver:

Quelennec A. Capteurs intégrés pour la fiabilisation des technologies d'encapsulation en microélectronique : Embedded sensors for microelectronics packaged module reliability. [Internet] [Doctoral dissertation]. Bordeaux; Université de Sherbrooke (Québec, Canada); 2018. [cited 2019 Sep 23]. Available from: http://www.theses.fr/2018BORD0105.

Council of Science Editors:

Quelennec A. Capteurs intégrés pour la fiabilisation des technologies d'encapsulation en microélectronique : Embedded sensors for microelectronics packaged module reliability. [Doctoral Dissertation]. Bordeaux; Université de Sherbrooke (Québec, Canada); 2018. Available from: http://www.theses.fr/2018BORD0105


NSYSU

10. Hsieh, Yu-han. Reliability of Cu pillar bump under cyclic thermal loading.

Degree: Master, Mechanical and Electro-Mechanical Engineering, 2014, NSYSU

 The thesis is to find out the longest fatigue life of the flip chip ball grid array (FCBGA) package by changing the geometry of copper… (more)

Subjects/Keywords: Reliability; Flip Chip; Cu Pillar Bump; taguchi method; Temperature Cyclic Test

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hsieh, Y. (2014). Reliability of Cu pillar bump under cyclic thermal loading. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0603114-171942

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsieh, Yu-han. “Reliability of Cu pillar bump under cyclic thermal loading.” 2014. Thesis, NSYSU. Accessed September 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0603114-171942.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsieh, Yu-han. “Reliability of Cu pillar bump under cyclic thermal loading.” 2014. Web. 23 Sep 2019.

Vancouver:

Hsieh Y. Reliability of Cu pillar bump under cyclic thermal loading. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Sep 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0603114-171942.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsieh Y. Reliability of Cu pillar bump under cyclic thermal loading. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0603114-171942

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

11. Guo, Yu-Lun. Thermo-Mechanical Deformation and Stress Analysis of Flip-Chip Ball Grid Array.

Degree: Master, Mechanical and Electro-Mechanical Engineering, 2003, NSYSU

 The thesis investigates the thermo-mechanical deformation and stress of a flip-chip package (FCBGA) via both experiment and simulation. First, Shadow Moiré is used to evaluate… (more)

Subjects/Keywords: ANSYS; Flip-Chip; Warpage

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APA (6th Edition):

Guo, Y. (2003). Thermo-Mechanical Deformation and Stress Analysis of Flip-Chip Ball Grid Array. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701103-144851

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Guo, Yu-Lun. “Thermo-Mechanical Deformation and Stress Analysis of Flip-Chip Ball Grid Array.” 2003. Thesis, NSYSU. Accessed September 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701103-144851.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Guo, Yu-Lun. “Thermo-Mechanical Deformation and Stress Analysis of Flip-Chip Ball Grid Array.” 2003. Web. 23 Sep 2019.

Vancouver:

Guo Y. Thermo-Mechanical Deformation and Stress Analysis of Flip-Chip Ball Grid Array. [Internet] [Thesis]. NSYSU; 2003. [cited 2019 Sep 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701103-144851.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Guo Y. Thermo-Mechanical Deformation and Stress Analysis of Flip-Chip Ball Grid Array. [Thesis]. NSYSU; 2003. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701103-144851

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

12. Chiou, Sheng-yu. Finite Element Analyses of Copper Pillar Flip-Chip Package Processes.

Degree: Master, Mechanical and Electro-Mechanical Engineering, 2015, NSYSU

 With advanced packaging technology and due to increasing demands in packaged products, packaged products have been applied in many electronic appliances in our daily life.… (more)

Subjects/Keywords: Package; Thermal compression bonding; Flip Chip; Solder ball; Copper pillar

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APA (6th Edition):

Chiou, S. (2015). Finite Element Analyses of Copper Pillar Flip-Chip Package Processes. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724115-172053

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chiou, Sheng-yu. “Finite Element Analyses of Copper Pillar Flip-Chip Package Processes.” 2015. Thesis, NSYSU. Accessed September 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724115-172053.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chiou, Sheng-yu. “Finite Element Analyses of Copper Pillar Flip-Chip Package Processes.” 2015. Web. 23 Sep 2019.

Vancouver:

Chiou S. Finite Element Analyses of Copper Pillar Flip-Chip Package Processes. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Sep 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724115-172053.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chiou S. Finite Element Analyses of Copper Pillar Flip-Chip Package Processes. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0724115-172053

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

13. Cheng, Kun-chu. A Study on the Analysis of Competitive Strategy of Flip Chip Packaging Insdustry in Taiwan -Case Study on S Company.

Degree: Master, Business Management, 2004, NSYSU

 A Study on the Analysis of Competitive Strategy of Flip Chip Packaging Industry in Taiwanâ Case Study on S Company Abstract The success of semiconductor… (more)

Subjects/Keywords: Flip Chip; Competitive Strategy

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cheng, K. (2004). A Study on the Analysis of Competitive Strategy of Flip Chip Packaging Insdustry in Taiwan -Case Study on S Company. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0129104-133737

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cheng, Kun-chu. “A Study on the Analysis of Competitive Strategy of Flip Chip Packaging Insdustry in Taiwan -Case Study on S Company.” 2004. Thesis, NSYSU. Accessed September 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0129104-133737.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cheng, Kun-chu. “A Study on the Analysis of Competitive Strategy of Flip Chip Packaging Insdustry in Taiwan -Case Study on S Company.” 2004. Web. 23 Sep 2019.

Vancouver:

Cheng K. A Study on the Analysis of Competitive Strategy of Flip Chip Packaging Insdustry in Taiwan -Case Study on S Company. [Internet] [Thesis]. NSYSU; 2004. [cited 2019 Sep 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0129104-133737.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cheng K. A Study on the Analysis of Competitive Strategy of Flip Chip Packaging Insdustry in Taiwan -Case Study on S Company. [Thesis]. NSYSU; 2004. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0129104-133737

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

14. Hung, Jhen-Siou. Reliability of Coreless substrate under thermal loading.

Degree: Master, Mechanical and Electro-Mechanical Engineering, 2015, NSYSU

 The thesis aims to enhance the reliability of the flip-chip ball grid array (FCBGA) package and coreless substrate by changing the material properties of dielectric… (more)

Subjects/Keywords: Reliability; Thermal loading; Coreless substrate; Flip-chip; Warpage

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APA (6th Edition):

Hung, J. (2015). Reliability of Coreless substrate under thermal loading. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1004115-165049

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hung, Jhen-Siou. “Reliability of Coreless substrate under thermal loading.” 2015. Thesis, NSYSU. Accessed September 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1004115-165049.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hung, Jhen-Siou. “Reliability of Coreless substrate under thermal loading.” 2015. Web. 23 Sep 2019.

Vancouver:

Hung J. Reliability of Coreless substrate under thermal loading. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Sep 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1004115-165049.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hung J. Reliability of Coreless substrate under thermal loading. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1004115-165049

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

15. Tao, Mian. Characterization and modeling of the non-uniform junction temperature and the current crowding effect in flip-chip light emitting diodes.

Degree: 2016, Hong Kong University of Science and Technology

 Light emitting diodes (LED) have been rapidly developed in the past decades. In recent years, LEDs of the flip-chip structure attracted great attention from the… (more)

Subjects/Keywords: Light emitting diodes; Flip chip technology; Electronic packaging

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APA (6th Edition):

Tao, M. (2016). Characterization and modeling of the non-uniform junction temperature and the current crowding effect in flip-chip light emitting diodes. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1627882 ; http://repository.ust.hk/ir/bitstream/1783.1-86922/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tao, Mian. “Characterization and modeling of the non-uniform junction temperature and the current crowding effect in flip-chip light emitting diodes.” 2016. Thesis, Hong Kong University of Science and Technology. Accessed September 23, 2019. https://doi.org/10.14711/thesis-b1627882 ; http://repository.ust.hk/ir/bitstream/1783.1-86922/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tao, Mian. “Characterization and modeling of the non-uniform junction temperature and the current crowding effect in flip-chip light emitting diodes.” 2016. Web. 23 Sep 2019.

Vancouver:

Tao M. Characterization and modeling of the non-uniform junction temperature and the current crowding effect in flip-chip light emitting diodes. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2016. [cited 2019 Sep 23]. Available from: https://doi.org/10.14711/thesis-b1627882 ; http://repository.ust.hk/ir/bitstream/1783.1-86922/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tao M. Characterization and modeling of the non-uniform junction temperature and the current crowding effect in flip-chip light emitting diodes. [Thesis]. Hong Kong University of Science and Technology; 2016. Available from: https://doi.org/10.14711/thesis-b1627882 ; http://repository.ust.hk/ir/bitstream/1783.1-86922/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

16. Ralston, Parrish Elaine. Design and Characterization of �Liquid Metal Flip Chip Interconnections for Heterogeneous Microwave Assemblies.

Degree: PhD, Electrical and Computer Engineering, 2013, Virginia Tech

Flip chip interconnections have superior performance for microwave applications compared to wire bond interconnections because of their reduced parasitics, more compact architecture, and flexibility in… (more)

Subjects/Keywords: liquid metal; electronics packaging; flip chip; 3D integration; MMIC integration

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ralston, P. E. (2013). Design and Characterization of �Liquid Metal Flip Chip Interconnections for Heterogeneous Microwave Assemblies. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/50641

Chicago Manual of Style (16th Edition):

Ralston, Parrish Elaine. “Design and Characterization of �Liquid Metal Flip Chip Interconnections for Heterogeneous Microwave Assemblies.” 2013. Doctoral Dissertation, Virginia Tech. Accessed September 23, 2019. http://hdl.handle.net/10919/50641.

MLA Handbook (7th Edition):

Ralston, Parrish Elaine. “Design and Characterization of �Liquid Metal Flip Chip Interconnections for Heterogeneous Microwave Assemblies.” 2013. Web. 23 Sep 2019.

Vancouver:

Ralston PE. Design and Characterization of �Liquid Metal Flip Chip Interconnections for Heterogeneous Microwave Assemblies. [Internet] [Doctoral dissertation]. Virginia Tech; 2013. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/10919/50641.

Council of Science Editors:

Ralston PE. Design and Characterization of �Liquid Metal Flip Chip Interconnections for Heterogeneous Microwave Assemblies. [Doctoral Dissertation]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/50641


Hong Kong University of Science and Technology

17. Chong, Wing Cheung ECE. Novel processes and device technologies for next generation light emitting diodes and micro-displays.

Degree: 2015, Hong Kong University of Science and Technology

 Remarkable development of light emitting diodes (LEDs) has driven its commercialization in large area displays and general lighting. The use of LEDs in micro-display is… (more)

Subjects/Keywords: Light emitting diodes; Gallium nitride; Flip chip technology

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APA (6th Edition):

Chong, W. C. E. (2015). Novel processes and device technologies for next generation light emitting diodes and micro-displays. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1552242 ; http://repository.ust.hk/ir/bitstream/1783.1-94719/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chong, Wing Cheung ECE. “Novel processes and device technologies for next generation light emitting diodes and micro-displays.” 2015. Thesis, Hong Kong University of Science and Technology. Accessed September 23, 2019. https://doi.org/10.14711/thesis-b1552242 ; http://repository.ust.hk/ir/bitstream/1783.1-94719/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chong, Wing Cheung ECE. “Novel processes and device technologies for next generation light emitting diodes and micro-displays.” 2015. Web. 23 Sep 2019.

Vancouver:

Chong WCE. Novel processes and device technologies for next generation light emitting diodes and micro-displays. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2015. [cited 2019 Sep 23]. Available from: https://doi.org/10.14711/thesis-b1552242 ; http://repository.ust.hk/ir/bitstream/1783.1-94719/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chong WCE. Novel processes and device technologies for next generation light emitting diodes and micro-displays. [Thesis]. Hong Kong University of Science and Technology; 2015. Available from: https://doi.org/10.14711/thesis-b1552242 ; http://repository.ust.hk/ir/bitstream/1783.1-94719/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

18. Shang, Andrew Weber. Bump and underfill effects on the thermal resistance of flip-chip light-emitting diodes.

Degree: 2018, Hong Kong University of Science and Technology

 In recent years, light-emitting diode (LED) technology has been rapidly gaining market share in the general lighting market around the world. To meet the demands… (more)

Subjects/Keywords: Electronic packaging; Thermal properties; Cooling; Light emitting diodes; Flip chip technology

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APA (6th Edition):

Shang, A. W. (2018). Bump and underfill effects on the thermal resistance of flip-chip light-emitting diodes. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-991012588665203412 ; http://repository.ust.hk/ir/bitstream/1783.1-92247/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shang, Andrew Weber. “Bump and underfill effects on the thermal resistance of flip-chip light-emitting diodes.” 2018. Thesis, Hong Kong University of Science and Technology. Accessed September 23, 2019. https://doi.org/10.14711/thesis-991012588665203412 ; http://repository.ust.hk/ir/bitstream/1783.1-92247/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shang, Andrew Weber. “Bump and underfill effects on the thermal resistance of flip-chip light-emitting diodes.” 2018. Web. 23 Sep 2019.

Vancouver:

Shang AW. Bump and underfill effects on the thermal resistance of flip-chip light-emitting diodes. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2018. [cited 2019 Sep 23]. Available from: https://doi.org/10.14711/thesis-991012588665203412 ; http://repository.ust.hk/ir/bitstream/1783.1-92247/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shang AW. Bump and underfill effects on the thermal resistance of flip-chip light-emitting diodes. [Thesis]. Hong Kong University of Science and Technology; 2018. Available from: https://doi.org/10.14711/thesis-991012588665203412 ; http://repository.ust.hk/ir/bitstream/1783.1-92247/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

19. Cho, Young Seek. Development of Three Dimensional Integration and Packaging Techniques for Complex Communication Systems.

Degree: PhD, Electrical Engineering, 2010, University of Minnesota

 Three dimensional packaging is considered as a promising packaging solution that can offer small form factor and high performance capability to high- speed electronics, for… (more)

Subjects/Keywords: 3D Packaging; embedded passive; flip-chip; silicon micromachining; through silicon via

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APA (6th Edition):

Cho, Y. S. (2010). Development of Three Dimensional Integration and Packaging Techniques for Complex Communication Systems. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/191382

Chicago Manual of Style (16th Edition):

Cho, Young Seek. “Development of Three Dimensional Integration and Packaging Techniques for Complex Communication Systems.” 2010. Doctoral Dissertation, University of Minnesota. Accessed September 23, 2019. http://hdl.handle.net/11299/191382.

MLA Handbook (7th Edition):

Cho, Young Seek. “Development of Three Dimensional Integration and Packaging Techniques for Complex Communication Systems.” 2010. Web. 23 Sep 2019.

Vancouver:

Cho YS. Development of Three Dimensional Integration and Packaging Techniques for Complex Communication Systems. [Internet] [Doctoral dissertation]. University of Minnesota; 2010. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/11299/191382.

Council of Science Editors:

Cho YS. Development of Three Dimensional Integration and Packaging Techniques for Complex Communication Systems. [Doctoral Dissertation]. University of Minnesota; 2010. Available from: http://hdl.handle.net/11299/191382

20. Yang, Zhening. Flexible substrate technology for millimeter wave applications : Technologie sur substrat souple pour applications en ondes millimétriques.

Degree: Docteur es, Micro et Nanosystèmes, 2016, Toulouse, INSA

Cette thèse fait partie des efforts de recherche pour étudier l’intégration hétérogène sur le substrat souple des nœuds de communicants pour les réseaux de capteurs… (more)

Subjects/Keywords: Intégration hétérogène; Flip-chip; Process technologic sur substrat souple; Antennes sur Kapton; 3D heterogeneous integration; Flip-chip; Technological process on flexible substrate; Antennas on Kapton; 621.381; 620.5

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APA (6th Edition):

Yang, Z. (2016). Flexible substrate technology for millimeter wave applications : Technologie sur substrat souple pour applications en ondes millimétriques. (Doctoral Dissertation). Toulouse, INSA. Retrieved from http://www.theses.fr/2016ISAT0023

Chicago Manual of Style (16th Edition):

Yang, Zhening. “Flexible substrate technology for millimeter wave applications : Technologie sur substrat souple pour applications en ondes millimétriques.” 2016. Doctoral Dissertation, Toulouse, INSA. Accessed September 23, 2019. http://www.theses.fr/2016ISAT0023.

MLA Handbook (7th Edition):

Yang, Zhening. “Flexible substrate technology for millimeter wave applications : Technologie sur substrat souple pour applications en ondes millimétriques.” 2016. Web. 23 Sep 2019.

Vancouver:

Yang Z. Flexible substrate technology for millimeter wave applications : Technologie sur substrat souple pour applications en ondes millimétriques. [Internet] [Doctoral dissertation]. Toulouse, INSA; 2016. [cited 2019 Sep 23]. Available from: http://www.theses.fr/2016ISAT0023.

Council of Science Editors:

Yang Z. Flexible substrate technology for millimeter wave applications : Technologie sur substrat souple pour applications en ondes millimétriques. [Doctoral Dissertation]. Toulouse, INSA; 2016. Available from: http://www.theses.fr/2016ISAT0023

21. Le Neal, Jean-François. Impact du packaging sur le comportement d'un capteur de pression piézorésistif pour application aéronautique : Impact of packaging on piezoresistive pressure sensor behaviour for aeronautical applications.

Degree: Docteur es, Matériaux, Technologie et Composants de l'Electronique, 2011, Toulouse, INSA

 La protection de nombreux capteurs de pression en milieux hostiles se résume souvent en un boitier métallique hermétique rempli d’huile enveloppant la puce. La pression… (more)

Subjects/Keywords: Microcapteur; Pression; Piézorésistivité; Wafer bonding; Wafer-level packaging; First-level packaging; Assemblage; Flip-chip; Microsensor; Pressure; Piezoresistivity; Wafer bonding; Wafer-level packaging; First-level packaging; Assembly; Flip-chip; 621.3

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APA (6th Edition):

Le Neal, J. (2011). Impact du packaging sur le comportement d'un capteur de pression piézorésistif pour application aéronautique : Impact of packaging on piezoresistive pressure sensor behaviour for aeronautical applications. (Doctoral Dissertation). Toulouse, INSA. Retrieved from http://www.theses.fr/2011ISAT0035

Chicago Manual of Style (16th Edition):

Le Neal, Jean-François. “Impact du packaging sur le comportement d'un capteur de pression piézorésistif pour application aéronautique : Impact of packaging on piezoresistive pressure sensor behaviour for aeronautical applications.” 2011. Doctoral Dissertation, Toulouse, INSA. Accessed September 23, 2019. http://www.theses.fr/2011ISAT0035.

MLA Handbook (7th Edition):

Le Neal, Jean-François. “Impact du packaging sur le comportement d'un capteur de pression piézorésistif pour application aéronautique : Impact of packaging on piezoresistive pressure sensor behaviour for aeronautical applications.” 2011. Web. 23 Sep 2019.

Vancouver:

Le Neal J. Impact du packaging sur le comportement d'un capteur de pression piézorésistif pour application aéronautique : Impact of packaging on piezoresistive pressure sensor behaviour for aeronautical applications. [Internet] [Doctoral dissertation]. Toulouse, INSA; 2011. [cited 2019 Sep 23]. Available from: http://www.theses.fr/2011ISAT0035.

Council of Science Editors:

Le Neal J. Impact du packaging sur le comportement d'un capteur de pression piézorésistif pour application aéronautique : Impact of packaging on piezoresistive pressure sensor behaviour for aeronautical applications. [Doctoral Dissertation]. Toulouse, INSA; 2011. Available from: http://www.theses.fr/2011ISAT0035


Université Paris-Sud – Paris XI

22. Bria, Toufiq. Etude de mécanismes d’hybridation pour les détecteurs d’imagerie Infrarouge : Study of hybridization mechanisms for two dimensional infrared detectors.

Degree: Docteur es, Optoélectronique, 2012, Université Paris-Sud – Paris XI

L’évolution de la microélectronique suit plusieurs axes notamment la miniaturisation des éléments actifs (réduction de taille des transistors), et l’augmentation de la densité d’interconnexion qui… (more)

Subjects/Keywords: Miniaturisation; Eléments actifs; Bille indium; Hybridation; Nano-scratch; I/O density; Nano-fils; Flip chip; Smallest; Active elements; Bumps indium; Hybridization; Nano-scratch; I/O density; Nanorod; Flip chip

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APA (6th Edition):

Bria, T. (2012). Etude de mécanismes d’hybridation pour les détecteurs d’imagerie Infrarouge : Study of hybridization mechanisms for two dimensional infrared detectors. (Doctoral Dissertation). Université Paris-Sud – Paris XI. Retrieved from http://www.theses.fr/2012PA112342

Chicago Manual of Style (16th Edition):

Bria, Toufiq. “Etude de mécanismes d’hybridation pour les détecteurs d’imagerie Infrarouge : Study of hybridization mechanisms for two dimensional infrared detectors.” 2012. Doctoral Dissertation, Université Paris-Sud – Paris XI. Accessed September 23, 2019. http://www.theses.fr/2012PA112342.

MLA Handbook (7th Edition):

Bria, Toufiq. “Etude de mécanismes d’hybridation pour les détecteurs d’imagerie Infrarouge : Study of hybridization mechanisms for two dimensional infrared detectors.” 2012. Web. 23 Sep 2019.

Vancouver:

Bria T. Etude de mécanismes d’hybridation pour les détecteurs d’imagerie Infrarouge : Study of hybridization mechanisms for two dimensional infrared detectors. [Internet] [Doctoral dissertation]. Université Paris-Sud – Paris XI; 2012. [cited 2019 Sep 23]. Available from: http://www.theses.fr/2012PA112342.

Council of Science Editors:

Bria T. Etude de mécanismes d’hybridation pour les détecteurs d’imagerie Infrarouge : Study of hybridization mechanisms for two dimensional infrared detectors. [Doctoral Dissertation]. Université Paris-Sud – Paris XI; 2012. Available from: http://www.theses.fr/2012PA112342


Brno University of Technology

23. Hřešil, Tomáš. Nové směry v pouzdření .

Degree: 2011, Brno University of Technology

 Tento projekt řeší vytvoření manuálu pro moderní elektronická pouzdra, která jsou stále častěji používána v dnešních elektronických obvodech a zařízeních. Mezi moderní pouzdra patří především… (more)

Subjects/Keywords: Pouzdření v elektronice; DIL; QFP; BGA; PGA; CSP; Flip chip; SiP; návrhová pravidla pro montáž; Packaging in electronics; DIL; QFP; BGA; PGA; CSP; Flip chip; SiP; design rules (guidelines)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hřešil, T. (2011). Nové směry v pouzdření . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/1904

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hřešil, Tomáš. “Nové směry v pouzdření .” 2011. Thesis, Brno University of Technology. Accessed September 23, 2019. http://hdl.handle.net/11012/1904.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hřešil, Tomáš. “Nové směry v pouzdření .” 2011. Web. 23 Sep 2019.

Vancouver:

Hřešil T. Nové směry v pouzdření . [Internet] [Thesis]. Brno University of Technology; 2011. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/11012/1904.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hřešil T. Nové směry v pouzdření . [Thesis]. Brno University of Technology; 2011. Available from: http://hdl.handle.net/11012/1904

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


KTH

24. Gärdin, Marcus. Characterization of Graphene-Based Anisotropic Conducting Adhesives : A study regarding x-ray sensing applications.

Degree: Electrical Engineering and Computer Science (EECS), 2019, KTH

A common method of cancer treatment is radiation therapy. In radiation therapy, a treatment planning system is made to specify the dose of X-rays… (more)

Subjects/Keywords: Anisotropic conductive adhesive; Graphene; Flip-chip; Graphene oxide; Epoxy composite; Anisotropt ledande adhesive; Grafen; Flip-chip; Grafenoxid; Epoxykomposit; Computer and Information Sciences; Data- och informationsvetenskap

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APA (6th Edition):

Gärdin, M. (2019). Characterization of Graphene-Based Anisotropic Conducting Adhesives : A study regarding x-ray sensing applications. (Thesis). KTH. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-257844

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gärdin, Marcus. “Characterization of Graphene-Based Anisotropic Conducting Adhesives : A study regarding x-ray sensing applications.” 2019. Thesis, KTH. Accessed September 23, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-257844.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gärdin, Marcus. “Characterization of Graphene-Based Anisotropic Conducting Adhesives : A study regarding x-ray sensing applications.” 2019. Web. 23 Sep 2019.

Vancouver:

Gärdin M. Characterization of Graphene-Based Anisotropic Conducting Adhesives : A study regarding x-ray sensing applications. [Internet] [Thesis]. KTH; 2019. [cited 2019 Sep 23]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-257844.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gärdin M. Characterization of Graphene-Based Anisotropic Conducting Adhesives : A study regarding x-ray sensing applications. [Thesis]. KTH; 2019. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-257844

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

25. Su, Wei-Hung. Finite Element Analyzes of Warpage Behavior of Embedded Copper Trace Substrate During Flip Chip Package Processes.

Degree: Master, Mechanical and Electro-Mechanical Engineering, 2017, NSYSU

 With the advance of the semiconductor industry and in response to the demands of ultra-thin electronic products, packaging technology has been continuously developed. Thermal bonding… (more)

Subjects/Keywords: Embedded copper trace substrate; Flip-chip package; Finite element analysis; Warpage deformation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Su, W. (2017). Finite Element Analyzes of Warpage Behavior of Embedded Copper Trace Substrate During Flip Chip Package Processes. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-111125

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Su, Wei-Hung. “Finite Element Analyzes of Warpage Behavior of Embedded Copper Trace Substrate During Flip Chip Package Processes.” 2017. Thesis, NSYSU. Accessed September 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-111125.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Su, Wei-Hung. “Finite Element Analyzes of Warpage Behavior of Embedded Copper Trace Substrate During Flip Chip Package Processes.” 2017. Web. 23 Sep 2019.

Vancouver:

Su W. Finite Element Analyzes of Warpage Behavior of Embedded Copper Trace Substrate During Flip Chip Package Processes. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Sep 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-111125.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Su W. Finite Element Analyzes of Warpage Behavior of Embedded Copper Trace Substrate During Flip Chip Package Processes. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-111125

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

26. Hsieh, Cheng-Han. The Fabrication of Laser Array Module by Flip Chip Technique.

Degree: Master, Electro-Optical Engineering, 2001, NSYSU

 We have fabricated a laser array module using a passive self-aligned flip-chip bonding technique. Silicon optical bench was used as a submount with PbSn (Tm=183â)… (more)

Subjects/Keywords: Flip Chip Technique; Laser Array Module

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hsieh, C. (2001). The Fabrication of Laser Array Module by Flip Chip Technique. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0112101-132614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsieh, Cheng-Han. “The Fabrication of Laser Array Module by Flip Chip Technique.” 2001. Thesis, NSYSU. Accessed September 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0112101-132614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsieh, Cheng-Han. “The Fabrication of Laser Array Module by Flip Chip Technique.” 2001. Web. 23 Sep 2019.

Vancouver:

Hsieh C. The Fabrication of Laser Array Module by Flip Chip Technique. [Internet] [Thesis]. NSYSU; 2001. [cited 2019 Sep 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0112101-132614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsieh C. The Fabrication of Laser Array Module by Flip Chip Technique. [Thesis]. NSYSU; 2001. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0112101-132614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Loughborough University

27. Qin, Yi. Electrodeposition and characterisation of lead-free solder alloys for electronics interconnection.

Degree: PhD, 2010, Loughborough University

 Conventional tin-lead solder alloys have been widely used in electronics interconnection owing to their properties such as low melting temperature, good ductility and excellent wettability… (more)

Subjects/Keywords: 671.7; Lead-free solder alloys; Electrodeposition; Wafer level solder bumping; Flip chip interconnection

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APA (6th Edition):

Qin, Y. (2010). Electrodeposition and characterisation of lead-free solder alloys for electronics interconnection. (Doctoral Dissertation). Loughborough University. Retrieved from https://dspace.lboro.ac.uk/2134/7788 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.634759

Chicago Manual of Style (16th Edition):

Qin, Yi. “Electrodeposition and characterisation of lead-free solder alloys for electronics interconnection.” 2010. Doctoral Dissertation, Loughborough University. Accessed September 23, 2019. https://dspace.lboro.ac.uk/2134/7788 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.634759.

MLA Handbook (7th Edition):

Qin, Yi. “Electrodeposition and characterisation of lead-free solder alloys for electronics interconnection.” 2010. Web. 23 Sep 2019.

Vancouver:

Qin Y. Electrodeposition and characterisation of lead-free solder alloys for electronics interconnection. [Internet] [Doctoral dissertation]. Loughborough University; 2010. [cited 2019 Sep 23]. Available from: https://dspace.lboro.ac.uk/2134/7788 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.634759.

Council of Science Editors:

Qin Y. Electrodeposition and characterisation of lead-free solder alloys for electronics interconnection. [Doctoral Dissertation]. Loughborough University; 2010. Available from: https://dspace.lboro.ac.uk/2134/7788 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.634759


Hong Kong University of Science and Technology

28. Liu, Zhaojun. Flip-chip mounted active matrix programmable monolithic light emitting diodes on silicon (LEDoS) displays.

Degree: 2010, Hong Kong University of Science and Technology

 Monolithic III-nitride based LED micro-arrays offer many potential applications due totheir superior characteristics such as high brightness, long lifetime and high contrast. In previously developed… (more)

Subjects/Keywords: Light emitting diodes; Multichip modules (Microelectronics); Silicon; Electric properties; Flip chip technology

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, Z. (2010). Flip-chip mounted active matrix programmable monolithic light emitting diodes on silicon (LEDoS) displays. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1129739 ; http://repository.ust.hk/ir/bitstream/1783.1-8066/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Zhaojun. “Flip-chip mounted active matrix programmable monolithic light emitting diodes on silicon (LEDoS) displays.” 2010. Thesis, Hong Kong University of Science and Technology. Accessed September 23, 2019. https://doi.org/10.14711/thesis-b1129739 ; http://repository.ust.hk/ir/bitstream/1783.1-8066/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Zhaojun. “Flip-chip mounted active matrix programmable monolithic light emitting diodes on silicon (LEDoS) displays.” 2010. Web. 23 Sep 2019.

Vancouver:

Liu Z. Flip-chip mounted active matrix programmable monolithic light emitting diodes on silicon (LEDoS) displays. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2010. [cited 2019 Sep 23]. Available from: https://doi.org/10.14711/thesis-b1129739 ; http://repository.ust.hk/ir/bitstream/1783.1-8066/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu Z. Flip-chip mounted active matrix programmable monolithic light emitting diodes on silicon (LEDoS) displays. [Thesis]. Hong Kong University of Science and Technology; 2010. Available from: https://doi.org/10.14711/thesis-b1129739 ; http://repository.ust.hk/ir/bitstream/1783.1-8066/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

29. Cai, Yuefei ECE. Integrated GaN devices for lighting and detection applications.

Degree: 2018, Hong Kong University of Science and Technology

 Optoelectronic Integrated circuits (OEICs) have found many applications in short-distance communication, intelligent displays and sensing. With the increasing demand for higher speed, more functions and… (more)

Subjects/Keywords: Optoelectronic devices; Integrated circuits; Gallium nitride; Modulation-doped field-effect transistors; Flip chip technology

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cai, Y. E. (2018). Integrated GaN devices for lighting and detection applications. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-991012588465303412 ; http://repository.ust.hk/ir/bitstream/1783.1-92254/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cai, Yuefei ECE. “Integrated GaN devices for lighting and detection applications.” 2018. Thesis, Hong Kong University of Science and Technology. Accessed September 23, 2019. https://doi.org/10.14711/thesis-991012588465303412 ; http://repository.ust.hk/ir/bitstream/1783.1-92254/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cai, Yuefei ECE. “Integrated GaN devices for lighting and detection applications.” 2018. Web. 23 Sep 2019.

Vancouver:

Cai YE. Integrated GaN devices for lighting and detection applications. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2018. [cited 2019 Sep 23]. Available from: https://doi.org/10.14711/thesis-991012588465303412 ; http://repository.ust.hk/ir/bitstream/1783.1-92254/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cai YE. Integrated GaN devices for lighting and detection applications. [Thesis]. Hong Kong University of Science and Technology; 2018. Available from: https://doi.org/10.14711/thesis-991012588465303412 ; http://repository.ust.hk/ir/bitstream/1783.1-92254/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Case Western Reserve University

30. Zhao, Peng. Analysis of Light Extraction Efficiency Enhancement for Deep Ultraviolet and Visible Light-Emitting Diodes with III-Nitride Micro-Domes.

Degree: MSs (Engineering), EECS - Electrical Engineering, 2013, Case Western Reserve University

 III-nitride (In, Al, Ga-N) semiconductors are considered as wide-bandgap materials that have promising applications in the next generation of lighting technology such as ultraviolet (UV)… (more)

Subjects/Keywords: Electrical Engineering; Optics; III-nitride light-emitting diodes; light extraction efficiency; deep ultraviolet; thin-film flip-chip; micro-domes

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APA (6th Edition):

Zhao, P. (2013). Analysis of Light Extraction Efficiency Enhancement for Deep Ultraviolet and Visible Light-Emitting Diodes with III-Nitride Micro-Domes. (Masters Thesis). Case Western Reserve University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=case1346876941

Chicago Manual of Style (16th Edition):

Zhao, Peng. “Analysis of Light Extraction Efficiency Enhancement for Deep Ultraviolet and Visible Light-Emitting Diodes with III-Nitride Micro-Domes.” 2013. Masters Thesis, Case Western Reserve University. Accessed September 23, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=case1346876941.

MLA Handbook (7th Edition):

Zhao, Peng. “Analysis of Light Extraction Efficiency Enhancement for Deep Ultraviolet and Visible Light-Emitting Diodes with III-Nitride Micro-Domes.” 2013. Web. 23 Sep 2019.

Vancouver:

Zhao P. Analysis of Light Extraction Efficiency Enhancement for Deep Ultraviolet and Visible Light-Emitting Diodes with III-Nitride Micro-Domes. [Internet] [Masters thesis]. Case Western Reserve University; 2013. [cited 2019 Sep 23]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1346876941.

Council of Science Editors:

Zhao P. Analysis of Light Extraction Efficiency Enhancement for Deep Ultraviolet and Visible Light-Emitting Diodes with III-Nitride Micro-Domes. [Masters Thesis]. Case Western Reserve University; 2013. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1346876941

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