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You searched for subject:(FinFET). Showing records 1 – 30 of 83 total matches.

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1. Rousselin, Thomas. Modélisation et interprétation des effets combinés vieillissement/SEE dans les technologies d'échelles nanométriques appliquées au domaine avionique : Modelisation and analysis of the impact of the combined effects of aging and SEE for nano-scaled technologies in avionics.

Degree: Docteur es, Génie Electrique, 2018, Toulouse, ISAE

L’électronique embarquée dans l’aéronautique, couramment appelé avionique, est chargée d’effectuer des tâches critiques et doit présenter une fiabilité élevée. La technologie Complementary Metal Oxyde Semiconductor… (more)

Subjects/Keywords: Vieillissement; NBTI; SEE; FinFET; Avionique; Aging; NBTI; SEE; FinFET; Avionics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rousselin, T. (2018). Modélisation et interprétation des effets combinés vieillissement/SEE dans les technologies d'échelles nanométriques appliquées au domaine avionique : Modelisation and analysis of the impact of the combined effects of aging and SEE for nano-scaled technologies in avionics. (Doctoral Dissertation). Toulouse, ISAE. Retrieved from http://www.theses.fr/2018ESAE0044

Chicago Manual of Style (16th Edition):

Rousselin, Thomas. “Modélisation et interprétation des effets combinés vieillissement/SEE dans les technologies d'échelles nanométriques appliquées au domaine avionique : Modelisation and analysis of the impact of the combined effects of aging and SEE for nano-scaled technologies in avionics.” 2018. Doctoral Dissertation, Toulouse, ISAE. Accessed April 09, 2020. http://www.theses.fr/2018ESAE0044.

MLA Handbook (7th Edition):

Rousselin, Thomas. “Modélisation et interprétation des effets combinés vieillissement/SEE dans les technologies d'échelles nanométriques appliquées au domaine avionique : Modelisation and analysis of the impact of the combined effects of aging and SEE for nano-scaled technologies in avionics.” 2018. Web. 09 Apr 2020.

Vancouver:

Rousselin T. Modélisation et interprétation des effets combinés vieillissement/SEE dans les technologies d'échelles nanométriques appliquées au domaine avionique : Modelisation and analysis of the impact of the combined effects of aging and SEE for nano-scaled technologies in avionics. [Internet] [Doctoral dissertation]. Toulouse, ISAE; 2018. [cited 2020 Apr 09]. Available from: http://www.theses.fr/2018ESAE0044.

Council of Science Editors:

Rousselin T. Modélisation et interprétation des effets combinés vieillissement/SEE dans les technologies d'échelles nanométriques appliquées au domaine avionique : Modelisation and analysis of the impact of the combined effects of aging and SEE for nano-scaled technologies in avionics. [Doctoral Dissertation]. Toulouse, ISAE; 2018. Available from: http://www.theses.fr/2018ESAE0044

2. Boudier, Dimitri. Etude des phénomènes de transport de porteurs et du bruit basse fréquence en fonction de la température dans les transistors FinFET et GAA NWFET sub-10 nm : Study of carrier transport phenomena and of low frequency noise as a function of the temperature in sub-10 nm FinFETs and GAA NWFETs.

Degree: Docteur es, Electronique, microelectronique, optique et lasers, optoelectronique microondes, 2018, Normandie

Les travaux menés pendant cette thèse se concentrent sur l'étude de technologies avancées de MOSFET, plus précisément de FinFET à triple-grille et de nanofils à… (more)

Subjects/Keywords: FinFET; Ransistor; MOSFET; FinFET; Nanowire; Electrical noise; Spectroscopy; Defect; Quantum transport

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APA (6th Edition):

Boudier, D. (2018). Etude des phénomènes de transport de porteurs et du bruit basse fréquence en fonction de la température dans les transistors FinFET et GAA NWFET sub-10 nm : Study of carrier transport phenomena and of low frequency noise as a function of the temperature in sub-10 nm FinFETs and GAA NWFETs. (Doctoral Dissertation). Normandie. Retrieved from http://www.theses.fr/2018NORMC220

Chicago Manual of Style (16th Edition):

Boudier, Dimitri. “Etude des phénomènes de transport de porteurs et du bruit basse fréquence en fonction de la température dans les transistors FinFET et GAA NWFET sub-10 nm : Study of carrier transport phenomena and of low frequency noise as a function of the temperature in sub-10 nm FinFETs and GAA NWFETs.” 2018. Doctoral Dissertation, Normandie. Accessed April 09, 2020. http://www.theses.fr/2018NORMC220.

MLA Handbook (7th Edition):

Boudier, Dimitri. “Etude des phénomènes de transport de porteurs et du bruit basse fréquence en fonction de la température dans les transistors FinFET et GAA NWFET sub-10 nm : Study of carrier transport phenomena and of low frequency noise as a function of the temperature in sub-10 nm FinFETs and GAA NWFETs.” 2018. Web. 09 Apr 2020.

Vancouver:

Boudier D. Etude des phénomènes de transport de porteurs et du bruit basse fréquence en fonction de la température dans les transistors FinFET et GAA NWFET sub-10 nm : Study of carrier transport phenomena and of low frequency noise as a function of the temperature in sub-10 nm FinFETs and GAA NWFETs. [Internet] [Doctoral dissertation]. Normandie; 2018. [cited 2020 Apr 09]. Available from: http://www.theses.fr/2018NORMC220.

Council of Science Editors:

Boudier D. Etude des phénomènes de transport de porteurs et du bruit basse fréquence en fonction de la température dans les transistors FinFET et GAA NWFET sub-10 nm : Study of carrier transport phenomena and of low frequency noise as a function of the temperature in sub-10 nm FinFETs and GAA NWFETs. [Doctoral Dissertation]. Normandie; 2018. Available from: http://www.theses.fr/2018NORMC220


Universidade do Rio Grande do Sul

3. Meinhardt, Cristina. Variabilidade em FinFETs.

Degree: 2014, Universidade do Rio Grande do Sul

Circuitos integrados VLSI (Very Large Scale Integration) usando nanotecnologia demandam novos materiais, estruturas, metodologias de projeto e ferramentas de CAD para lidar com os problemas… (more)

Subjects/Keywords: Microeletrônica; Microelectronics; Nanotecnologia; Nanotechnology; Variability; FinFET

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APA (6th Edition):

Meinhardt, C. (2014). Variabilidade em FinFETs. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/114799

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Meinhardt, Cristina. “Variabilidade em FinFETs.” 2014. Thesis, Universidade do Rio Grande do Sul. Accessed April 09, 2020. http://hdl.handle.net/10183/114799.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Meinhardt, Cristina. “Variabilidade em FinFETs.” 2014. Web. 09 Apr 2020.

Vancouver:

Meinhardt C. Variabilidade em FinFETs. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2014. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/10183/114799.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Meinhardt C. Variabilidade em FinFETs. [Thesis]. Universidade do Rio Grande do Sul; 2014. Available from: http://hdl.handle.net/10183/114799

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

4. Vakil, Apoorva Babu. Characterization of Multi-fin Quantum Well Structures using Photo-conductance Decay Technique.

Degree: MS, Electrical Engineering, 2012, Penn State University

 The era of traditional ‘Moore’s Law’ scaling of transistors encountered a roadblock with problems like short channel effects and sub-threshold leakage current increasingly plaguing the… (more)

Subjects/Keywords: Electrical Characterization; Photoconductance Decay; FinFET; Fin sidewalls

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APA (6th Edition):

Vakil, A. B. (2012). Characterization of Multi-fin Quantum Well Structures using Photo-conductance Decay Technique. (Masters Thesis). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/15317

Chicago Manual of Style (16th Edition):

Vakil, Apoorva Babu. “Characterization of Multi-fin Quantum Well Structures using Photo-conductance Decay Technique.” 2012. Masters Thesis, Penn State University. Accessed April 09, 2020. https://etda.libraries.psu.edu/catalog/15317.

MLA Handbook (7th Edition):

Vakil, Apoorva Babu. “Characterization of Multi-fin Quantum Well Structures using Photo-conductance Decay Technique.” 2012. Web. 09 Apr 2020.

Vancouver:

Vakil AB. Characterization of Multi-fin Quantum Well Structures using Photo-conductance Decay Technique. [Internet] [Masters thesis]. Penn State University; 2012. [cited 2020 Apr 09]. Available from: https://etda.libraries.psu.edu/catalog/15317.

Council of Science Editors:

Vakil AB. Characterization of Multi-fin Quantum Well Structures using Photo-conductance Decay Technique. [Masters Thesis]. Penn State University; 2012. Available from: https://etda.libraries.psu.edu/catalog/15317

5. 東原, 敬. 時間軸積和演算のためのSiナノディスクアレイ-FinFETニューロンデバイスの研究 : A Research of Silicon Nanodisk Array with a FinFET Neuron Device for Time-domain Weighted Calculation.

Degree: 博士(工学), 2017, Kyushu Institute of Technology / 九州工業大学

九州工業大学博士学位論文 学位記番号:生工博甲第271号 学位授与年月日:平成28年6月30日

第1章 序論|第2章 積和演算モデル|第3章 NDA-FinFET 結合型デバイスの製造技術|第4章 試作デバイスの評価|第5章 考察・課題|第6章 結論

平成28年度

Advisors/Committee Members: 森江, 隆.

Subjects/Keywords: ナノディスクアレイ; FinFET; スパイキングニューロン; Nanodisk Array; Spiking Neuron

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APA (6th Edition):

東原, . . (2017). 時間軸積和演算のためのSiナノディスクアレイ-FinFETニューロンデバイスの研究 : A Research of Silicon Nanodisk Array with a FinFET Neuron Device for Time-domain Weighted Calculation. (Thesis). Kyushu Institute of Technology / 九州工業大学. Retrieved from http://hdl.handle.net/10228/00006264

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

東原, 敬. “時間軸積和演算のためのSiナノディスクアレイ-FinFETニューロンデバイスの研究 : A Research of Silicon Nanodisk Array with a FinFET Neuron Device for Time-domain Weighted Calculation.” 2017. Thesis, Kyushu Institute of Technology / 九州工業大学. Accessed April 09, 2020. http://hdl.handle.net/10228/00006264.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

東原, 敬. “時間軸積和演算のためのSiナノディスクアレイ-FinFETニューロンデバイスの研究 : A Research of Silicon Nanodisk Array with a FinFET Neuron Device for Time-domain Weighted Calculation.” 2017. Web. 09 Apr 2020.

Vancouver:

東原 . 時間軸積和演算のためのSiナノディスクアレイ-FinFETニューロンデバイスの研究 : A Research of Silicon Nanodisk Array with a FinFET Neuron Device for Time-domain Weighted Calculation. [Internet] [Thesis]. Kyushu Institute of Technology / 九州工業大学; 2017. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/10228/00006264.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

東原 . 時間軸積和演算のためのSiナノディスクアレイ-FinFETニューロンデバイスの研究 : A Research of Silicon Nanodisk Array with a FinFET Neuron Device for Time-domain Weighted Calculation. [Thesis]. Kyushu Institute of Technology / 九州工業大学; 2017. Available from: http://hdl.handle.net/10228/00006264

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

6. Gorbenko, Viktoriia. Caractérisation par faisceaux d’ions d’hétérostructures III-V pour les applications micro et optoélectroniques : Ion beam characterisation of III-V heterostructures for micro and optoelectronic applications.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2015, Grenoble Alpes

L'intégration de composés semi-conducteurs III-V sur silicium devrait conduire au développement de nouveaux dispositifs micro- et optoélectroniques performants. Le composé InGaAs de haute mobilité électronique… (more)

Subjects/Keywords: III-V hétérostructures; SIMS; FinFET; Microélectronique; Optoélectronique; Puits quantique; III-V heterostructures; SIMS; FinFET; Microelectronics; Optoelectronics; Quantum wells; 620

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APA (6th Edition):

Gorbenko, V. (2015). Caractérisation par faisceaux d’ions d’hétérostructures III-V pour les applications micro et optoélectroniques : Ion beam characterisation of III-V heterostructures for micro and optoelectronic applications. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2015GREAT140

Chicago Manual of Style (16th Edition):

Gorbenko, Viktoriia. “Caractérisation par faisceaux d’ions d’hétérostructures III-V pour les applications micro et optoélectroniques : Ion beam characterisation of III-V heterostructures for micro and optoelectronic applications.” 2015. Doctoral Dissertation, Grenoble Alpes. Accessed April 09, 2020. http://www.theses.fr/2015GREAT140.

MLA Handbook (7th Edition):

Gorbenko, Viktoriia. “Caractérisation par faisceaux d’ions d’hétérostructures III-V pour les applications micro et optoélectroniques : Ion beam characterisation of III-V heterostructures for micro and optoelectronic applications.” 2015. Web. 09 Apr 2020.

Vancouver:

Gorbenko V. Caractérisation par faisceaux d’ions d’hétérostructures III-V pour les applications micro et optoélectroniques : Ion beam characterisation of III-V heterostructures for micro and optoelectronic applications. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2015. [cited 2020 Apr 09]. Available from: http://www.theses.fr/2015GREAT140.

Council of Science Editors:

Gorbenko V. Caractérisation par faisceaux d’ions d’hétérostructures III-V pour les applications micro et optoélectroniques : Ion beam characterisation of III-V heterostructures for micro and optoelectronic applications. [Doctoral Dissertation]. Grenoble Alpes; 2015. Available from: http://www.theses.fr/2015GREAT140

7. Karel, Amit. Comparative Study of FinFET and FDSOI Nanometric Technologies Based on Manufacturing Defect Testability : Etude comparative des technologies nanométriques FinFET et FD-SOI au regard de la testabilité des défauts de fabrication.

Degree: Docteur es, Systèmes automatiques et micro-électroniques, 2017, Montpellier

 Deux innovations en matière de procédés technologiques des semi-conducteurs sont des alternatives à la technologie traditionnelle des transistors MOS (« Metal-Oxide-Semiconductor ») « Bulk »… (more)

Subjects/Keywords: Technologie; Test orienté défauts; Testabilité; FinFET; Fd-Soi; Technology; Defect-Oriented Testing; Testability; FinFET; Fd-Soi

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APA (6th Edition):

Karel, A. (2017). Comparative Study of FinFET and FDSOI Nanometric Technologies Based on Manufacturing Defect Testability : Etude comparative des technologies nanométriques FinFET et FD-SOI au regard de la testabilité des défauts de fabrication. (Doctoral Dissertation). Montpellier. Retrieved from http://www.theses.fr/2017MONTS084

Chicago Manual of Style (16th Edition):

Karel, Amit. “Comparative Study of FinFET and FDSOI Nanometric Technologies Based on Manufacturing Defect Testability : Etude comparative des technologies nanométriques FinFET et FD-SOI au regard de la testabilité des défauts de fabrication.” 2017. Doctoral Dissertation, Montpellier. Accessed April 09, 2020. http://www.theses.fr/2017MONTS084.

MLA Handbook (7th Edition):

Karel, Amit. “Comparative Study of FinFET and FDSOI Nanometric Technologies Based on Manufacturing Defect Testability : Etude comparative des technologies nanométriques FinFET et FD-SOI au regard de la testabilité des défauts de fabrication.” 2017. Web. 09 Apr 2020.

Vancouver:

Karel A. Comparative Study of FinFET and FDSOI Nanometric Technologies Based on Manufacturing Defect Testability : Etude comparative des technologies nanométriques FinFET et FD-SOI au regard de la testabilité des défauts de fabrication. [Internet] [Doctoral dissertation]. Montpellier; 2017. [cited 2020 Apr 09]. Available from: http://www.theses.fr/2017MONTS084.

Council of Science Editors:

Karel A. Comparative Study of FinFET and FDSOI Nanometric Technologies Based on Manufacturing Defect Testability : Etude comparative des technologies nanométriques FinFET et FD-SOI au regard de la testabilité des défauts de fabrication. [Doctoral Dissertation]. Montpellier; 2017. Available from: http://www.theses.fr/2017MONTS084


NSYSU

8. Hsieh, Chen-Yen. A Study of Ultralow Sheet Resistance and Homogenous Nickel Silicide by Low Thermal Budget Carbon Dioxide Laser Spike Annealing.

Degree: Master, Electrical Engineering, 2017, NSYSU

 In this thesis, we propose low thermal budget laser technologies to form a homogenous and ultralow sheet resistance nickel silicide on the Source/Drain region of… (more)

Subjects/Keywords: FinFET; MR-CTLM; Nickel silicide; Carbon Dioxide Laser Annealing

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APA (6th Edition):

Hsieh, C. (2017). A Study of Ultralow Sheet Resistance and Homogenous Nickel Silicide by Low Thermal Budget Carbon Dioxide Laser Spike Annealing. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701117-151104

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsieh, Chen-Yen. “A Study of Ultralow Sheet Resistance and Homogenous Nickel Silicide by Low Thermal Budget Carbon Dioxide Laser Spike Annealing.” 2017. Thesis, NSYSU. Accessed April 09, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701117-151104.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsieh, Chen-Yen. “A Study of Ultralow Sheet Resistance and Homogenous Nickel Silicide by Low Thermal Budget Carbon Dioxide Laser Spike Annealing.” 2017. Web. 09 Apr 2020.

Vancouver:

Hsieh C. A Study of Ultralow Sheet Resistance and Homogenous Nickel Silicide by Low Thermal Budget Carbon Dioxide Laser Spike Annealing. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Apr 09]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701117-151104.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsieh C. A Study of Ultralow Sheet Resistance and Homogenous Nickel Silicide by Low Thermal Budget Carbon Dioxide Laser Spike Annealing. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701117-151104

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

9. Chang, Cheng-Hsien. A New Extended Body FinFET for 1T-DRAM Application.

Degree: Master, Electrical Engineering, 2014, NSYSU

 In this paper, we propose a new extended body FinFET (EB-FinFET) for one transistor dynamic random access memory (1T-DRAM) application. As the device scales down,… (more)

Subjects/Keywords: 1T-DRAM; FinFET; Extended Body Region; GIDL Mechanism; Programming Window

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, C. (2014). A New Extended Body FinFET for 1T-DRAM Application. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701114-104442

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Cheng-Hsien. “A New Extended Body FinFET for 1T-DRAM Application.” 2014. Thesis, NSYSU. Accessed April 09, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701114-104442.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Cheng-Hsien. “A New Extended Body FinFET for 1T-DRAM Application.” 2014. Web. 09 Apr 2020.

Vancouver:

Chang C. A New Extended Body FinFET for 1T-DRAM Application. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Apr 09]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701114-104442.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang C. A New Extended Body FinFET for 1T-DRAM Application. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701114-104442

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Berkeley

10. Lu, Darsen Duane. Compact Models for Future Generation CMOS.

Degree: Electrical Engineering & Computer Sciences, 2011, University of California – Berkeley

 Multiple-gate MOSFETs with superior short channel control are expected to replace planar CMOS in the near future. An accurate and computationally efficient compact transistor model… (more)

Subjects/Keywords: Electrical engineering; Compact Model; FinFET; MOSFET; SOI; SRAM; Thermal Noise

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APA (6th Edition):

Lu, D. D. (2011). Compact Models for Future Generation CMOS. (Thesis). University of California – Berkeley. Retrieved from http://www.escholarship.org/uc/item/7qn9x2jd

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lu, Darsen Duane. “Compact Models for Future Generation CMOS.” 2011. Thesis, University of California – Berkeley. Accessed April 09, 2020. http://www.escholarship.org/uc/item/7qn9x2jd.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lu, Darsen Duane. “Compact Models for Future Generation CMOS.” 2011. Web. 09 Apr 2020.

Vancouver:

Lu DD. Compact Models for Future Generation CMOS. [Internet] [Thesis]. University of California – Berkeley; 2011. [cited 2020 Apr 09]. Available from: http://www.escholarship.org/uc/item/7qn9x2jd.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lu DD. Compact Models for Future Generation CMOS. [Thesis]. University of California – Berkeley; 2011. Available from: http://www.escholarship.org/uc/item/7qn9x2jd

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

11. Leung, Gregory. Variability and Heterogeneous Integration of Emerging Device Technologies.

Degree: Electrical Engineering, 2015, UCLA

 The continued push for microelectronics scaling has driven many changes in modern transistor design, such as the adoption of non-planar, multi-gate architectures (e.g., FinFETs) starting… (more)

Subjects/Keywords: Engineering; Electrical engineering; FinFET; heterogeneous integration; modeling; semiconductor; supercapacitor; variability

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APA (6th Edition):

Leung, G. (2015). Variability and Heterogeneous Integration of Emerging Device Technologies. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/9847f1jb

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Leung, Gregory. “Variability and Heterogeneous Integration of Emerging Device Technologies.” 2015. Thesis, UCLA. Accessed April 09, 2020. http://www.escholarship.org/uc/item/9847f1jb.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Leung, Gregory. “Variability and Heterogeneous Integration of Emerging Device Technologies.” 2015. Web. 09 Apr 2020.

Vancouver:

Leung G. Variability and Heterogeneous Integration of Emerging Device Technologies. [Internet] [Thesis]. UCLA; 2015. [cited 2020 Apr 09]. Available from: http://www.escholarship.org/uc/item/9847f1jb.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Leung G. Variability and Heterogeneous Integration of Emerging Device Technologies. [Thesis]. UCLA; 2015. Available from: http://www.escholarship.org/uc/item/9847f1jb

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Berkeley

12. Guo, Zheng. Large-Scale Variability Characterization and Robust Design Techniques for Nanoscale SRAM.

Degree: Electrical Engineering & Computer Sciences, 2009, University of California – Berkeley

 Continued increase in the process variability is perceived to be a major roadblock for future technology scaling. Its impact is particularly pronounced in large memory… (more)

Subjects/Keywords: Electrical engineering; CMOS; FinFET; measurement; noise margins; SRAM; variability

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APA (6th Edition):

Guo, Z. (2009). Large-Scale Variability Characterization and Robust Design Techniques for Nanoscale SRAM. (Thesis). University of California – Berkeley. Retrieved from http://www.escholarship.org/uc/item/9jk6x3wc

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Guo, Zheng. “Large-Scale Variability Characterization and Robust Design Techniques for Nanoscale SRAM.” 2009. Thesis, University of California – Berkeley. Accessed April 09, 2020. http://www.escholarship.org/uc/item/9jk6x3wc.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Guo, Zheng. “Large-Scale Variability Characterization and Robust Design Techniques for Nanoscale SRAM.” 2009. Web. 09 Apr 2020.

Vancouver:

Guo Z. Large-Scale Variability Characterization and Robust Design Techniques for Nanoscale SRAM. [Internet] [Thesis]. University of California – Berkeley; 2009. [cited 2020 Apr 09]. Available from: http://www.escholarship.org/uc/item/9jk6x3wc.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Guo Z. Large-Scale Variability Characterization and Robust Design Techniques for Nanoscale SRAM. [Thesis]. University of California – Berkeley; 2009. Available from: http://www.escholarship.org/uc/item/9jk6x3wc

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

13. Suh, Jae Woo. Device Design Parameterization of III-V Multi-Gate FETs.

Degree: PhD, Electrical Engineering, 2016, Texas A&M University

 The use of group III-V semiconductor materials promise superior performance compared to silicon and can be considered a fundamental paradigm shift away from mature silicon… (more)

Subjects/Keywords: GaN; FinFET; III-V; semiconductor; ohmic contact; strain; 2DEG

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APA (6th Edition):

Suh, J. W. (2016). Device Design Parameterization of III-V Multi-Gate FETs. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/159072

Chicago Manual of Style (16th Edition):

Suh, Jae Woo. “Device Design Parameterization of III-V Multi-Gate FETs.” 2016. Doctoral Dissertation, Texas A&M University. Accessed April 09, 2020. http://hdl.handle.net/1969.1/159072.

MLA Handbook (7th Edition):

Suh, Jae Woo. “Device Design Parameterization of III-V Multi-Gate FETs.” 2016. Web. 09 Apr 2020.

Vancouver:

Suh JW. Device Design Parameterization of III-V Multi-Gate FETs. [Internet] [Doctoral dissertation]. Texas A&M University; 2016. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/1969.1/159072.

Council of Science Editors:

Suh JW. Device Design Parameterization of III-V Multi-Gate FETs. [Doctoral Dissertation]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/159072

14. 高橋, 啓介. 三次元構造トランジスタにおける基板バイアス効果の検討 : Study of Body Effect in Transistor with Three-Dimensional Structure.

Degree: 修士(工学), 2017, The University of Tokyo / 東京大学

将来のMOSFETの構造として有力な、三次元構造FinFETにおける基板バイアス効果の有効性を、3次元シミュレーションと試作の両面から検討した。

Subjects/Keywords: 基板バイアス; FinFET

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APA (6th Edition):

高橋, . (2017). 三次元構造トランジスタにおける基板バイアス効果の検討 : Study of Body Effect in Transistor with Three-Dimensional Structure. (Thesis). The University of Tokyo / 東京大学. Retrieved from http://hdl.handle.net/2261/29065

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

高橋, 啓介. “三次元構造トランジスタにおける基板バイアス効果の検討 : Study of Body Effect in Transistor with Three-Dimensional Structure.” 2017. Thesis, The University of Tokyo / 東京大学. Accessed April 09, 2020. http://hdl.handle.net/2261/29065.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

高橋, 啓介. “三次元構造トランジスタにおける基板バイアス効果の検討 : Study of Body Effect in Transistor with Three-Dimensional Structure.” 2017. Web. 09 Apr 2020.

Vancouver:

高橋 . 三次元構造トランジスタにおける基板バイアス効果の検討 : Study of Body Effect in Transistor with Three-Dimensional Structure. [Internet] [Thesis]. The University of Tokyo / 東京大学; 2017. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/2261/29065.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

高橋 . 三次元構造トランジスタにおける基板バイアス効果の検討 : Study of Body Effect in Transistor with Three-Dimensional Structure. [Thesis]. The University of Tokyo / 東京大学; 2017. Available from: http://hdl.handle.net/2261/29065

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

15. Seresht, Elham Pak. Numerical Modeling of Self-heating in MOSFET and FinFET Basic Logic Gates Using Effective Thermal Conductivity.

Degree: 2012, University of Toronto

Recent trend of minimization in microprocessors has introduced increasing self-heating effects in FinFET and MOSFET transistors. To study these self-heating effects, we developed self-consistent 3D… (more)

Subjects/Keywords: Self-heating; MOSFET; FinFET; Basic Logic Gates; Effective Thermal Conductivity; 0548

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APA (6th Edition):

Seresht, E. P. (2012). Numerical Modeling of Self-heating in MOSFET and FinFET Basic Logic Gates Using Effective Thermal Conductivity. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/33496

Chicago Manual of Style (16th Edition):

Seresht, Elham Pak. “Numerical Modeling of Self-heating in MOSFET and FinFET Basic Logic Gates Using Effective Thermal Conductivity.” 2012. Masters Thesis, University of Toronto. Accessed April 09, 2020. http://hdl.handle.net/1807/33496.

MLA Handbook (7th Edition):

Seresht, Elham Pak. “Numerical Modeling of Self-heating in MOSFET and FinFET Basic Logic Gates Using Effective Thermal Conductivity.” 2012. Web. 09 Apr 2020.

Vancouver:

Seresht EP. Numerical Modeling of Self-heating in MOSFET and FinFET Basic Logic Gates Using Effective Thermal Conductivity. [Internet] [Masters thesis]. University of Toronto; 2012. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/1807/33496.

Council of Science Editors:

Seresht EP. Numerical Modeling of Self-heating in MOSFET and FinFET Basic Logic Gates Using Effective Thermal Conductivity. [Masters Thesis]. University of Toronto; 2012. Available from: http://hdl.handle.net/1807/33496

16. Tang, Aoxiang. Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures .

Degree: PhD, 2015, Princeton University

 Technology scaling has been one of the most fundamental ways to improve chip performance and reduce power consumption. However, as the industry dives deeper into… (more)

Subjects/Keywords: delay modeling; FinFET; genetic algorithm; power modeling; PVT variation; SSTA

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APA (6th Edition):

Tang, A. (2015). Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01z890rw568

Chicago Manual of Style (16th Edition):

Tang, Aoxiang. “Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures .” 2015. Doctoral Dissertation, Princeton University. Accessed April 09, 2020. http://arks.princeton.edu/ark:/88435/dsp01z890rw568.

MLA Handbook (7th Edition):

Tang, Aoxiang. “Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures .” 2015. Web. 09 Apr 2020.

Vancouver:

Tang A. Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures . [Internet] [Doctoral dissertation]. Princeton University; 2015. [cited 2020 Apr 09]. Available from: http://arks.princeton.edu/ark:/88435/dsp01z890rw568.

Council of Science Editors:

Tang A. Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures . [Doctoral Dissertation]. Princeton University; 2015. Available from: http://arks.princeton.edu/ark:/88435/dsp01z890rw568


Princeton University

17. Chen, Xianmin. FinFET-based System Modeling and Low-Power System Design .

Degree: PhD, 2016, Princeton University

FinFET has begun to replace MOSFET at the 22nm technology node and beyond. Compared to planar CMOS, FinFET has higher on-current and lower leakage due… (more)

Subjects/Keywords: 3D IC; FinFET; Low-power; NoC; PVT variation; System modeling

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APA (6th Edition):

Chen, X. (2016). FinFET-based System Modeling and Low-Power System Design . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp016t053j389

Chicago Manual of Style (16th Edition):

Chen, Xianmin. “FinFET-based System Modeling and Low-Power System Design .” 2016. Doctoral Dissertation, Princeton University. Accessed April 09, 2020. http://arks.princeton.edu/ark:/88435/dsp016t053j389.

MLA Handbook (7th Edition):

Chen, Xianmin. “FinFET-based System Modeling and Low-Power System Design .” 2016. Web. 09 Apr 2020.

Vancouver:

Chen X. FinFET-based System Modeling and Low-Power System Design . [Internet] [Doctoral dissertation]. Princeton University; 2016. [cited 2020 Apr 09]. Available from: http://arks.princeton.edu/ark:/88435/dsp016t053j389.

Council of Science Editors:

Chen X. FinFET-based System Modeling and Low-Power System Design . [Doctoral Dissertation]. Princeton University; 2016. Available from: http://arks.princeton.edu/ark:/88435/dsp016t053j389


Princeton University

18. Bhattacharya, Debajit. Exploring the system hierarchy from devices to on-chip communication .

Degree: PhD, 2016, Princeton University

 FinFETs have replaced planar CMOS at and beyond the 22 nm node because of their superior short-channel behavior. Despite their significant advantages in electrostatics, FinFETs… (more)

Subjects/Keywords: 3D Monolithic integration; Capacitance extraction; FinFET; Network on chip; SRAM; TCAD

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APA (6th Edition):

Bhattacharya, D. (2016). Exploring the system hierarchy from devices to on-chip communication . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01cc08hj107

Chicago Manual of Style (16th Edition):

Bhattacharya, Debajit. “Exploring the system hierarchy from devices to on-chip communication .” 2016. Doctoral Dissertation, Princeton University. Accessed April 09, 2020. http://arks.princeton.edu/ark:/88435/dsp01cc08hj107.

MLA Handbook (7th Edition):

Bhattacharya, Debajit. “Exploring the system hierarchy from devices to on-chip communication .” 2016. Web. 09 Apr 2020.

Vancouver:

Bhattacharya D. Exploring the system hierarchy from devices to on-chip communication . [Internet] [Doctoral dissertation]. Princeton University; 2016. [cited 2020 Apr 09]. Available from: http://arks.princeton.edu/ark:/88435/dsp01cc08hj107.

Council of Science Editors:

Bhattacharya D. Exploring the system hierarchy from devices to on-chip communication . [Doctoral Dissertation]. Princeton University; 2016. Available from: http://arks.princeton.edu/ark:/88435/dsp01cc08hj107

19. -7629-8614. Design and implementation of a scribe line measurement transistor test array structure in 14nm FinFET CMOS technology.

Degree: MSin Engineering, Electrical and Computer Engineering, 2015, University of Texas – Austin

 Submicron fin-shaped field effect transistor (FinFET) process technologies pose a variety of challenges for foundries ramping designs into production due to parameter variation. Accurate and… (more)

Subjects/Keywords: FinFET; SLM; Inline testing

…57 viii List of Tables Table 2.1: FinFET DUT design of experiment… …26 Table 2.2: FinFET DUT experimental splits… …design for manufacturing (DFM) techniques, FinFET transistors emerged as a solution… …to some of the issues with sub-20nm planar CMOS transistor scaling. FinFET transistors… …several more generations beyond the 20nm node. Despite these advantages FinFET devices pose… 

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APA (6th Edition):

-7629-8614. (2015). Design and implementation of a scribe line measurement transistor test array structure in 14nm FinFET CMOS technology. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/32301

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-7629-8614. “Design and implementation of a scribe line measurement transistor test array structure in 14nm FinFET CMOS technology.” 2015. Masters Thesis, University of Texas – Austin. Accessed April 09, 2020. http://hdl.handle.net/2152/32301.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-7629-8614. “Design and implementation of a scribe line measurement transistor test array structure in 14nm FinFET CMOS technology.” 2015. Web. 09 Apr 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-7629-8614. Design and implementation of a scribe line measurement transistor test array structure in 14nm FinFET CMOS technology. [Internet] [Masters thesis]. University of Texas – Austin; 2015. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/2152/32301.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-7629-8614. Design and implementation of a scribe line measurement transistor test array structure in 14nm FinFET CMOS technology. [Masters Thesis]. University of Texas – Austin; 2015. Available from: http://hdl.handle.net/2152/32301

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


University of Toronto

20. Wang, Luke. ADC-based Receivers for Wireline Communication.

Degree: PhD, 2019, University of Toronto

 Power efficient analog to digital converter (ADC) based receivers are desired for wireline communications as the industry transitions to 4-PAM at data-rates above 50Gb/s. A… (more)

Subjects/Keywords: ADC; FinFET; Greedy Search; PAM; receiver; SERDES; 0544

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APA (6th Edition):

Wang, L. (2019). ADC-based Receivers for Wireline Communication. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/94073

Chicago Manual of Style (16th Edition):

Wang, Luke. “ADC-based Receivers for Wireline Communication.” 2019. Doctoral Dissertation, University of Toronto. Accessed April 09, 2020. http://hdl.handle.net/1807/94073.

MLA Handbook (7th Edition):

Wang, Luke. “ADC-based Receivers for Wireline Communication.” 2019. Web. 09 Apr 2020.

Vancouver:

Wang L. ADC-based Receivers for Wireline Communication. [Internet] [Doctoral dissertation]. University of Toronto; 2019. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/1807/94073.

Council of Science Editors:

Wang L. ADC-based Receivers for Wireline Communication. [Doctoral Dissertation]. University of Toronto; 2019. Available from: http://hdl.handle.net/1807/94073

21. Martino, Márcio Dalla Valle. Estudo de transistores de tunelamento controlados por efeito de campo.

Degree: Mestrado, Microeletrônica, 2012, University of São Paulo

Este trabalho apresenta o estudo de transistores de tunelamento controlados por efeito de campo, denominados TFETs. Foram realizadas análises com base em explicação teórica, simulação… (more)

Subjects/Keywords: Ambipolaridade; Ambipolarity; Band-to-band tunneling; FinFET; FinFET; Impacto da temperatura; Inclinação de sublimiar; Subthreshold slope; Temperature impact; TFET; TFET; Tunelamento de banda para banda

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APA (6th Edition):

Martino, M. D. V. (2012). Estudo de transistores de tunelamento controlados por efeito de campo. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/3/3140/tde-16112012-164339/ ;

Chicago Manual of Style (16th Edition):

Martino, Márcio Dalla Valle. “Estudo de transistores de tunelamento controlados por efeito de campo.” 2012. Masters Thesis, University of São Paulo. Accessed April 09, 2020. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-16112012-164339/ ;.

MLA Handbook (7th Edition):

Martino, Márcio Dalla Valle. “Estudo de transistores de tunelamento controlados por efeito de campo.” 2012. Web. 09 Apr 2020.

Vancouver:

Martino MDV. Estudo de transistores de tunelamento controlados por efeito de campo. [Internet] [Masters thesis]. University of São Paulo; 2012. [cited 2020 Apr 09]. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-16112012-164339/ ;.

Council of Science Editors:

Martino MDV. Estudo de transistores de tunelamento controlados por efeito de campo. [Masters Thesis]. University of São Paulo; 2012. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-16112012-164339/ ;

22. Doria, Rodrigo Trevisoli. Operação analógica de transistores de múltiplas portas em função da temperatura.

Degree: PhD, Microeletrônica, 2010, University of São Paulo

 Neste trabalho, é apresentada uma análise da operação analógica de transistores de múltiplas portas, avaliando a tensão Early, o ganho de tensão em malha aberta,… (more)

Subjects/Keywords: Canal gradual; Distorção harmônica; Double gate; FinFET; FinFET; GAA; GAA; Graded-channel; Harmonic distortion; Junctionless; Junctionless; Porta dupla; SOI; SOI; Strain; Tensão mecânica

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APA (6th Edition):

Doria, R. T. (2010). Operação analógica de transistores de múltiplas portas em função da temperatura. (Doctoral Dissertation). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/3/3140/tde-10012011-135500/ ;

Chicago Manual of Style (16th Edition):

Doria, Rodrigo Trevisoli. “Operação analógica de transistores de múltiplas portas em função da temperatura.” 2010. Doctoral Dissertation, University of São Paulo. Accessed April 09, 2020. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-10012011-135500/ ;.

MLA Handbook (7th Edition):

Doria, Rodrigo Trevisoli. “Operação analógica de transistores de múltiplas portas em função da temperatura.” 2010. Web. 09 Apr 2020.

Vancouver:

Doria RT. Operação analógica de transistores de múltiplas portas em função da temperatura. [Internet] [Doctoral dissertation]. University of São Paulo; 2010. [cited 2020 Apr 09]. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-10012011-135500/ ;.

Council of Science Editors:

Doria RT. Operação analógica de transistores de múltiplas portas em função da temperatura. [Doctoral Dissertation]. University of São Paulo; 2010. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-10012011-135500/ ;


Aristotle University Of Thessaloniki (AUTH); Αριστοτέλειο Πανεπιστήμιο Θεσσαλονίκης (ΑΠΘ)

23. Fasarakis, Nikolaos. Nano-scale multi-gate MOSFETs: compact models for the drain current and noise for development of automated design tools of nano-electronics.

Degree: 2014, Aristotle University Of Thessaloniki (AUTH); Αριστοτέλειο Πανεπιστήμιο Θεσσαλονίκης (ΑΠΘ)

 Fundamental goal of this dissertation is to develop compact models for the drain current and trans-capacitances of nano-scale multi-gate (MG) MOSFETs valid in all regions… (more)

Subjects/Keywords: FinFET πολλαπλών πυλών; Ηλεκτρικός χαρακτηρισμός; Συμπαγή μοντέλα; Τεχνική εξαγωγής παραμέτρων; Κατασκευαστική μεταβλητότητα; Multi-Gate FinFET; Electrical characterization; Compact models; Parameter extraction technique; Variability

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APA (6th Edition):

Fasarakis, N. (2014). Nano-scale multi-gate MOSFETs: compact models for the drain current and noise for development of automated design tools of nano-electronics. (Thesis). Aristotle University Of Thessaloniki (AUTH); Αριστοτέλειο Πανεπιστήμιο Θεσσαλονίκης (ΑΠΘ). Retrieved from http://hdl.handle.net/10442/hedi/35362

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fasarakis, Nikolaos. “Nano-scale multi-gate MOSFETs: compact models for the drain current and noise for development of automated design tools of nano-electronics.” 2014. Thesis, Aristotle University Of Thessaloniki (AUTH); Αριστοτέλειο Πανεπιστήμιο Θεσσαλονίκης (ΑΠΘ). Accessed April 09, 2020. http://hdl.handle.net/10442/hedi/35362.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fasarakis, Nikolaos. “Nano-scale multi-gate MOSFETs: compact models for the drain current and noise for development of automated design tools of nano-electronics.” 2014. Web. 09 Apr 2020.

Vancouver:

Fasarakis N. Nano-scale multi-gate MOSFETs: compact models for the drain current and noise for development of automated design tools of nano-electronics. [Internet] [Thesis]. Aristotle University Of Thessaloniki (AUTH); Αριστοτέλειο Πανεπιστήμιο Θεσσαλονίκης (ΑΠΘ); 2014. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/10442/hedi/35362.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fasarakis N. Nano-scale multi-gate MOSFETs: compact models for the drain current and noise for development of automated design tools of nano-electronics. [Thesis]. Aristotle University Of Thessaloniki (AUTH); Αριστοτέλειο Πανεπιστήμιο Θεσσαλονίκης (ΑΠΘ); 2014. Available from: http://hdl.handle.net/10442/hedi/35362

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. Bizouerne, Maxime. Développement de procédés de gravure plasma sans dommages pour l'intégration de l'InGaAs comme canal tridimensionnel de transistor nMOS non-planaire : Development of damage free plasma etching processes for the integration of InGaAs as non-planar nMOS transistor tridimensional channel.

Degree: Docteur es, Nano electronique et nano technologies, 2018, Grenoble Alpes

L’augmentation des performances des dispositifs de la microélectronique repose encore pour une dizaine d’années sur une miniaturisation des circuits intégrés. Cette miniaturisation s’accompagne inévitablement d’une… (more)

Subjects/Keywords: Procédés de gravure plasma; Défauts induits par plasma; InGaAs; Transistors finFET; Microélectronique; Plasma etching processes; Plasma induced damage; InGaAs; FinFET transistors; Microelectronics; 620

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APA (6th Edition):

Bizouerne, M. (2018). Développement de procédés de gravure plasma sans dommages pour l'intégration de l'InGaAs comme canal tridimensionnel de transistor nMOS non-planaire : Development of damage free plasma etching processes for the integration of InGaAs as non-planar nMOS transistor tridimensional channel. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2018GREAT030

Chicago Manual of Style (16th Edition):

Bizouerne, Maxime. “Développement de procédés de gravure plasma sans dommages pour l'intégration de l'InGaAs comme canal tridimensionnel de transistor nMOS non-planaire : Development of damage free plasma etching processes for the integration of InGaAs as non-planar nMOS transistor tridimensional channel.” 2018. Doctoral Dissertation, Grenoble Alpes. Accessed April 09, 2020. http://www.theses.fr/2018GREAT030.

MLA Handbook (7th Edition):

Bizouerne, Maxime. “Développement de procédés de gravure plasma sans dommages pour l'intégration de l'InGaAs comme canal tridimensionnel de transistor nMOS non-planaire : Development of damage free plasma etching processes for the integration of InGaAs as non-planar nMOS transistor tridimensional channel.” 2018. Web. 09 Apr 2020.

Vancouver:

Bizouerne M. Développement de procédés de gravure plasma sans dommages pour l'intégration de l'InGaAs comme canal tridimensionnel de transistor nMOS non-planaire : Development of damage free plasma etching processes for the integration of InGaAs as non-planar nMOS transistor tridimensional channel. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2018. [cited 2020 Apr 09]. Available from: http://www.theses.fr/2018GREAT030.

Council of Science Editors:

Bizouerne M. Développement de procédés de gravure plasma sans dommages pour l'intégration de l'InGaAs comme canal tridimensionnel de transistor nMOS non-planaire : Development of damage free plasma etching processes for the integration of InGaAs as non-planar nMOS transistor tridimensional channel. [Doctoral Dissertation]. Grenoble Alpes; 2018. Available from: http://www.theses.fr/2018GREAT030

25. Lackmann-Zimpeck, Alexandra. Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells : Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET.

Degree: Docteur es, Micro et Nanosystèmes, 2019, Toulouse, ISAE; Universidade Federal do Rio Grande do Sul (Porto Alegre, Brésil)

 Les contraintes imposées par la roadmap technologique nanométrique imposent aux fabricants de microélectronique une réduction de la variabilité de fabrication mais également de durcissement vis-à-vis… (more)

Subjects/Keywords: Microélectronique; Design au niveau circuit; Variabilité de fabrication; Fiabilité; Soft error; FinFET; Microelectronics; Circuit-Level design; Process variability; Reliability; Soft error; FinFET

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lackmann-Zimpeck, A. (2019). Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells : Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET. (Doctoral Dissertation). Toulouse, ISAE; Universidade Federal do Rio Grande do Sul (Porto Alegre, Brésil). Retrieved from http://www.theses.fr/2019ESAE0026

Chicago Manual of Style (16th Edition):

Lackmann-Zimpeck, Alexandra. “Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells : Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET.” 2019. Doctoral Dissertation, Toulouse, ISAE; Universidade Federal do Rio Grande do Sul (Porto Alegre, Brésil). Accessed April 09, 2020. http://www.theses.fr/2019ESAE0026.

MLA Handbook (7th Edition):

Lackmann-Zimpeck, Alexandra. “Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells : Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET.” 2019. Web. 09 Apr 2020.

Vancouver:

Lackmann-Zimpeck A. Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells : Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET. [Internet] [Doctoral dissertation]. Toulouse, ISAE; Universidade Federal do Rio Grande do Sul (Porto Alegre, Brésil); 2019. [cited 2020 Apr 09]. Available from: http://www.theses.fr/2019ESAE0026.

Council of Science Editors:

Lackmann-Zimpeck A. Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells : Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET. [Doctoral Dissertation]. Toulouse, ISAE; Universidade Federal do Rio Grande do Sul (Porto Alegre, Brésil); 2019. Available from: http://www.theses.fr/2019ESAE0026


Texas A&M University

26. Bekal, Prasanna. Analysis and Modeling of Parasitic Capacitances in Advanced Nanoscale Devices.

Degree: 2012, Texas A&M University

 In order to correctly perform circuit simulation, it is crucial that parasitic capacitances near devices are accurately extracted and are consistent with the SPICE models.… (more)

Subjects/Keywords: Parasitic Extraction; fringing capacitance; MOSFET; Vertical BJT; FinFET; 3D Fieldsolver; Calibre xACT

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APA (6th Edition):

Bekal, P. (2012). Analysis and Modeling of Parasitic Capacitances in Advanced Nanoscale Devices. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11215

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bekal, Prasanna. “Analysis and Modeling of Parasitic Capacitances in Advanced Nanoscale Devices.” 2012. Thesis, Texas A&M University. Accessed April 09, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11215.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bekal, Prasanna. “Analysis and Modeling of Parasitic Capacitances in Advanced Nanoscale Devices.” 2012. Web. 09 Apr 2020.

Vancouver:

Bekal P. Analysis and Modeling of Parasitic Capacitances in Advanced Nanoscale Devices. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Apr 09]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11215.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bekal P. Analysis and Modeling of Parasitic Capacitances in Advanced Nanoscale Devices. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-11215

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Purdue University

27. Singh, Jolene. Finfet Device Optimization at 15NM for Near-threshold Operation.

Degree: MSECE, Electrical and Computer Engineering, 2013, Purdue University

  Much of the current research in the electronic industry focuses on reducing power consumption of digital circuits. Towards the same many attempts are being… (more)

Subjects/Keywords: applied sciences; finfet; minimum energy; near-threshold; optimization; Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Singh, J. (2013). Finfet Device Optimization at 15NM for Near-threshold Operation. (Thesis). Purdue University. Retrieved from http://docs.lib.purdue.edu/open_access_theses/72

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Singh, Jolene. “Finfet Device Optimization at 15NM for Near-threshold Operation.” 2013. Thesis, Purdue University. Accessed April 09, 2020. http://docs.lib.purdue.edu/open_access_theses/72.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Singh, Jolene. “Finfet Device Optimization at 15NM for Near-threshold Operation.” 2013. Web. 09 Apr 2020.

Vancouver:

Singh J. Finfet Device Optimization at 15NM for Near-threshold Operation. [Internet] [Thesis]. Purdue University; 2013. [cited 2020 Apr 09]. Available from: http://docs.lib.purdue.edu/open_access_theses/72.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Singh J. Finfet Device Optimization at 15NM for Near-threshold Operation. [Thesis]. Purdue University; 2013. Available from: http://docs.lib.purdue.edu/open_access_theses/72

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

28. Thathachary, Arun V. Physics, Fabrication And Characterization Of Iii-v Multi-gate Fets For Low Power Electronics.

Degree: PhD, Electrical Engineering, 2015, Penn State University

 With transistor technology close to its limits for power constrained scaling and the simultaneous emergence of mobile devices as the dominant driver for new scaling,… (more)

Subjects/Keywords: III-V; low power; CMOS; FinFET; transport; MOSFET; Hall mobility; transconductance; injection velocity

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APA (6th Edition):

Thathachary, A. V. (2015). Physics, Fabrication And Characterization Of Iii-v Multi-gate Fets For Low Power Electronics. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/26417

Chicago Manual of Style (16th Edition):

Thathachary, Arun V. “Physics, Fabrication And Characterization Of Iii-v Multi-gate Fets For Low Power Electronics.” 2015. Doctoral Dissertation, Penn State University. Accessed April 09, 2020. https://etda.libraries.psu.edu/catalog/26417.

MLA Handbook (7th Edition):

Thathachary, Arun V. “Physics, Fabrication And Characterization Of Iii-v Multi-gate Fets For Low Power Electronics.” 2015. Web. 09 Apr 2020.

Vancouver:

Thathachary AV. Physics, Fabrication And Characterization Of Iii-v Multi-gate Fets For Low Power Electronics. [Internet] [Doctoral dissertation]. Penn State University; 2015. [cited 2020 Apr 09]. Available from: https://etda.libraries.psu.edu/catalog/26417.

Council of Science Editors:

Thathachary AV. Physics, Fabrication And Characterization Of Iii-v Multi-gate Fets For Low Power Electronics. [Doctoral Dissertation]. Penn State University; 2015. Available from: https://etda.libraries.psu.edu/catalog/26417


Penn State University

29. Mushtaq, Muhammad Umar. Reliability and Power Analysis of FinFET-based FPGAs.

Degree: MS, Computer Science and Engineering, 2008, Penn State University

 This thesis presents the results of exploring hitherto unchartered territory for the emerging FinFET device: FPGAs. As the inexorable descent to lower technology nodes continues… (more)

Subjects/Keywords: FPGA; FinFET; Soft-Error; Process Variations; Sub-Threshold Leakage; Independent Gate Control

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mushtaq, M. U. (2008). Reliability and Power Analysis of FinFET-based FPGAs. (Masters Thesis). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/8699

Chicago Manual of Style (16th Edition):

Mushtaq, Muhammad Umar. “Reliability and Power Analysis of FinFET-based FPGAs.” 2008. Masters Thesis, Penn State University. Accessed April 09, 2020. https://etda.libraries.psu.edu/catalog/8699.

MLA Handbook (7th Edition):

Mushtaq, Muhammad Umar. “Reliability and Power Analysis of FinFET-based FPGAs.” 2008. Web. 09 Apr 2020.

Vancouver:

Mushtaq MU. Reliability and Power Analysis of FinFET-based FPGAs. [Internet] [Masters thesis]. Penn State University; 2008. [cited 2020 Apr 09]. Available from: https://etda.libraries.psu.edu/catalog/8699.

Council of Science Editors:

Mushtaq MU. Reliability and Power Analysis of FinFET-based FPGAs. [Masters Thesis]. Penn State University; 2008. Available from: https://etda.libraries.psu.edu/catalog/8699


University of California – Berkeley

30. Venugopalan, Sriramkumar. From Poisson to Silicon - Advancing Compact SPICE Models for IC Design.

Degree: Electrical Engineering & Computer Sciences, 2013, University of California – Berkeley

 The semiconductor industry has relied on accurate device models for analyzing, predicting and innovating integrated circuit design. Multi-gate MOSFET device architectures like FinFETs are beginning… (more)

Subjects/Keywords: Electrical engineering; BSIM; Compact SPICE Modeling; FinFET; MOSFET; Multi-Gate FET; Semiconductor Device

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Venugopalan, S. (2013). From Poisson to Silicon - Advancing Compact SPICE Models for IC Design. (Thesis). University of California – Berkeley. Retrieved from http://www.escholarship.org/uc/item/0qq3h6fg

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Venugopalan, Sriramkumar. “From Poisson to Silicon - Advancing Compact SPICE Models for IC Design.” 2013. Thesis, University of California – Berkeley. Accessed April 09, 2020. http://www.escholarship.org/uc/item/0qq3h6fg.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Venugopalan, Sriramkumar. “From Poisson to Silicon - Advancing Compact SPICE Models for IC Design.” 2013. Web. 09 Apr 2020.

Vancouver:

Venugopalan S. From Poisson to Silicon - Advancing Compact SPICE Models for IC Design. [Internet] [Thesis]. University of California – Berkeley; 2013. [cited 2020 Apr 09]. Available from: http://www.escholarship.org/uc/item/0qq3h6fg.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Venugopalan S. From Poisson to Silicon - Advancing Compact SPICE Models for IC Design. [Thesis]. University of California – Berkeley; 2013. Available from: http://www.escholarship.org/uc/item/0qq3h6fg

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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