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You searched for subject:(Field programmable gate array). Showing records 1 – 30 of 19216 total matches.

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Brunel University

1. Afandi, Ahmad. Efficient reconfigurable architectures for 3D medical image compression.

Degree: PhD, 2010, Brunel University

 Recently, the more widespread use of three-dimensional (3-D) imaging modalities, such as magnetic resonance imaging (MRI), computed tomography (CT), positron emission tomography (PET), and ultrasound… (more)

Subjects/Keywords: 621.39; Field programmable gate array; Reconfigurable computing

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APA (6th Edition):

Afandi, A. (2010). Efficient reconfigurable architectures for 3D medical image compression. (Doctoral Dissertation). Brunel University. Retrieved from http://bura.brunel.ac.uk/handle/2438/7677 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.582880

Chicago Manual of Style (16th Edition):

Afandi, Ahmad. “Efficient reconfigurable architectures for 3D medical image compression.” 2010. Doctoral Dissertation, Brunel University. Accessed October 16, 2019. http://bura.brunel.ac.uk/handle/2438/7677 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.582880.

MLA Handbook (7th Edition):

Afandi, Ahmad. “Efficient reconfigurable architectures for 3D medical image compression.” 2010. Web. 16 Oct 2019.

Vancouver:

Afandi A. Efficient reconfigurable architectures for 3D medical image compression. [Internet] [Doctoral dissertation]. Brunel University; 2010. [cited 2019 Oct 16]. Available from: http://bura.brunel.ac.uk/handle/2438/7677 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.582880.

Council of Science Editors:

Afandi A. Efficient reconfigurable architectures for 3D medical image compression. [Doctoral Dissertation]. Brunel University; 2010. Available from: http://bura.brunel.ac.uk/handle/2438/7677 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.582880


University of New Mexico

2. Hoffman, John. High-speed dynamic partial reconfiguration for field programmable gate arrays.

Degree: Electrical and Computer Engineering, 2009, University of New Mexico

 With dynamically and partially reconfigurable designs, it is necessary that the speed of the reconfiguration be accomplished in a time that is sufficiently small such… (more)

Subjects/Keywords: Field programmable gate arrays; Adaptive computing systems; Programmable array logic.

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APA (6th Edition):

Hoffman, J. (2009). High-speed dynamic partial reconfiguration for field programmable gate arrays. (Masters Thesis). University of New Mexico. Retrieved from http://hdl.handle.net/1928/9783

Chicago Manual of Style (16th Edition):

Hoffman, John. “High-speed dynamic partial reconfiguration for field programmable gate arrays.” 2009. Masters Thesis, University of New Mexico. Accessed October 16, 2019. http://hdl.handle.net/1928/9783.

MLA Handbook (7th Edition):

Hoffman, John. “High-speed dynamic partial reconfiguration for field programmable gate arrays.” 2009. Web. 16 Oct 2019.

Vancouver:

Hoffman J. High-speed dynamic partial reconfiguration for field programmable gate arrays. [Internet] [Masters thesis]. University of New Mexico; 2009. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/1928/9783.

Council of Science Editors:

Hoffman J. High-speed dynamic partial reconfiguration for field programmable gate arrays. [Masters Thesis]. University of New Mexico; 2009. Available from: http://hdl.handle.net/1928/9783


Cape Peninsula University of Technology

3. Han, Yi. Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology .

Degree: 2008, Cape Peninsula University of Technology

 As one of the biggest developing country in the world, South Africa is developing very fast resent years. The country’s industrialization process is rapidly evolved.… (more)

Subjects/Keywords: Field programmable gate arrays; Array processors; Programmable array logic; Crane operations; MTech

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APA (6th Edition):

Han, Y. (2008). Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology . (Thesis). Cape Peninsula University of Technology. Retrieved from http://etd.cput.ac.za/handle/20.500.11838/1069

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Han, Yi. “Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology .” 2008. Thesis, Cape Peninsula University of Technology. Accessed October 16, 2019. http://etd.cput.ac.za/handle/20.500.11838/1069.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Han, Yi. “Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology .” 2008. Web. 16 Oct 2019.

Vancouver:

Han Y. Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology . [Internet] [Thesis]. Cape Peninsula University of Technology; 2008. [cited 2019 Oct 16]. Available from: http://etd.cput.ac.za/handle/20.500.11838/1069.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Han Y. Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology . [Thesis]. Cape Peninsula University of Technology; 2008. Available from: http://etd.cput.ac.za/handle/20.500.11838/1069

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. Turki, Mariem. Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform.

Degree: Docteur es, Informatique et Micro-Electronique, 2014, Université Pierre et Marie Curie – Paris VI

De nos jours, la complexité de la conception des circuits intégrés et du logiciel croit régulièrement, faisant croître le besoin de la vérification dans chaque… (more)

Subjects/Keywords: FPGA (Field Programmable Gate Array); Prototypage; Routage; Pathfinder; Itératif; Multiplexage; FPGA (Field Programmable Gate Array); Prototyping; 005.18

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APA (6th Edition):

Turki, M. (2014). Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform. (Doctoral Dissertation). Université Pierre et Marie Curie – Paris VI. Retrieved from http://www.theses.fr/2014PA066698

Chicago Manual of Style (16th Edition):

Turki, Mariem. “Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform.” 2014. Doctoral Dissertation, Université Pierre et Marie Curie – Paris VI. Accessed October 16, 2019. http://www.theses.fr/2014PA066698.

MLA Handbook (7th Edition):

Turki, Mariem. “Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform.” 2014. Web. 16 Oct 2019.

Vancouver:

Turki M. Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform. [Internet] [Doctoral dissertation]. Université Pierre et Marie Curie – Paris VI; 2014. [cited 2019 Oct 16]. Available from: http://www.theses.fr/2014PA066698.

Council of Science Editors:

Turki M. Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform. [Doctoral Dissertation]. Université Pierre et Marie Curie – Paris VI; 2014. Available from: http://www.theses.fr/2014PA066698


Universidade Estadual de Campinas

5. Monte, Luis Renato. Especificação do nucleo de processamento para rede de chaveamento de rajadas opticas .

Degree: 2009, Universidade Estadual de Campinas

 Resumo: Este trabalho apresenta as especificações arquitetônicas e funcionais de uma rede ótica avançada, fundamentada na comutação óptica de rajadas e que objetiva um melhor… (more)

Subjects/Keywords: Fibras óticas; Comunicações óticas; Chaveamento ótico; FPGA (Field Programmable Gate Array)

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APA (6th Edition):

Monte, L. R. (2009). Especificação do nucleo de processamento para rede de chaveamento de rajadas opticas . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/259738

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Monte, Luis Renato. “Especificação do nucleo de processamento para rede de chaveamento de rajadas opticas .” 2009. Thesis, Universidade Estadual de Campinas. Accessed October 16, 2019. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259738.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Monte, Luis Renato. “Especificação do nucleo de processamento para rede de chaveamento de rajadas opticas .” 2009. Web. 16 Oct 2019.

Vancouver:

Monte LR. Especificação do nucleo de processamento para rede de chaveamento de rajadas opticas . [Internet] [Thesis]. Universidade Estadual de Campinas; 2009. [cited 2019 Oct 16]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/259738.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Monte LR. Especificação do nucleo de processamento para rede de chaveamento de rajadas opticas . [Thesis]. Universidade Estadual de Campinas; 2009. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/259738

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Victoria University of Wellington

6. Ang, Andrew. Development of an Open PXIe System based on FPGA Modules.

Degree: 2018, Victoria University of Wellington

 PXIe is a instrumentation platform that is used as the basis for developing test equipment, modular electronic instruments and automated test systems. A typical PXIe… (more)

Subjects/Keywords: FPGA; PXIe; Electronics; PCI eXtensions for Instrumentation; Field Programmable Gate Array

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APA (6th Edition):

Ang, A. (2018). Development of an Open PXIe System based on FPGA Modules. (Masters Thesis). Victoria University of Wellington. Retrieved from http://hdl.handle.net/10063/7653

Chicago Manual of Style (16th Edition):

Ang, Andrew. “Development of an Open PXIe System based on FPGA Modules.” 2018. Masters Thesis, Victoria University of Wellington. Accessed October 16, 2019. http://hdl.handle.net/10063/7653.

MLA Handbook (7th Edition):

Ang, Andrew. “Development of an Open PXIe System based on FPGA Modules.” 2018. Web. 16 Oct 2019.

Vancouver:

Ang A. Development of an Open PXIe System based on FPGA Modules. [Internet] [Masters thesis]. Victoria University of Wellington; 2018. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/10063/7653.

Council of Science Editors:

Ang A. Development of an Open PXIe System based on FPGA Modules. [Masters Thesis]. Victoria University of Wellington; 2018. Available from: http://hdl.handle.net/10063/7653


Anna University

7. Rajeswari P. An FPGA based architecture for real Time network traffic analysis;.

Degree: An FPGA based architecture for real Time network traffic analysis, 2015, Anna University

The Internet is persistently expanding in all dimensions and evolving newlineinto a global communications medium consisting of heterogeneously interconnected newlinesystems and carrying an increasing mix… (more)

Subjects/Keywords: Field Programmable Gate Array; Network monitoring and traffic

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APA (6th Edition):

P, R. (2015). An FPGA based architecture for real Time network traffic analysis;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/39198

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

P, Rajeswari. “An FPGA based architecture for real Time network traffic analysis;.” 2015. Thesis, Anna University. Accessed October 16, 2019. http://shodhganga.inflibnet.ac.in/handle/10603/39198.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

P, Rajeswari. “An FPGA based architecture for real Time network traffic analysis;.” 2015. Web. 16 Oct 2019.

Vancouver:

P R. An FPGA based architecture for real Time network traffic analysis;. [Internet] [Thesis]. Anna University; 2015. [cited 2019 Oct 16]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/39198.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

P R. An FPGA based architecture for real Time network traffic analysis;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/39198

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

8. Jayanthi, V E. Design and implementation of vlsi Architecture algorithms for digital Image watermarking; -.

Degree: Information and Communication Engineering, 2014, Anna University

Nowadays digital documents can be distributed through the World newlineWide Web to a large number of people in a cost efficient way The increasing newlineimportance… (more)

Subjects/Keywords: Digital Image watermarking; Field Programmable Gate Array; Information hiding Watermarking technology

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APA (6th Edition):

Jayanthi, V. E. (2014). Design and implementation of vlsi Architecture algorithms for digital Image watermarking; -. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/24741

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jayanthi, V E. “Design and implementation of vlsi Architecture algorithms for digital Image watermarking; -.” 2014. Thesis, Anna University. Accessed October 16, 2019. http://shodhganga.inflibnet.ac.in/handle/10603/24741.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jayanthi, V E. “Design and implementation of vlsi Architecture algorithms for digital Image watermarking; -.” 2014. Web. 16 Oct 2019.

Vancouver:

Jayanthi VE. Design and implementation of vlsi Architecture algorithms for digital Image watermarking; -. [Internet] [Thesis]. Anna University; 2014. [cited 2019 Oct 16]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/24741.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jayanthi VE. Design and implementation of vlsi Architecture algorithms for digital Image watermarking; -. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/24741

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Addis Ababa University

9. Misiker, Tadesse. HIGH PERFORMANCE AUTOMATIC TARGET RECOGNITION .

Degree: 2013, Addis Ababa University

 Designing a vision system, which was motivated by that of the human eye, has been done since the introduction of digital computing devices. Due to… (more)

Subjects/Keywords: AUTOMATIC TARGET RECOGNITION; Field Programmable Gate Array; Graphics Processing Unit

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APA (6th Edition):

Misiker, T. (2013). HIGH PERFORMANCE AUTOMATIC TARGET RECOGNITION . (Thesis). Addis Ababa University. Retrieved from http://etd.aau.edu.et/dspace/handle/123456789/4503

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Misiker, Tadesse. “HIGH PERFORMANCE AUTOMATIC TARGET RECOGNITION .” 2013. Thesis, Addis Ababa University. Accessed October 16, 2019. http://etd.aau.edu.et/dspace/handle/123456789/4503.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Misiker, Tadesse. “HIGH PERFORMANCE AUTOMATIC TARGET RECOGNITION .” 2013. Web. 16 Oct 2019.

Vancouver:

Misiker T. HIGH PERFORMANCE AUTOMATIC TARGET RECOGNITION . [Internet] [Thesis]. Addis Ababa University; 2013. [cited 2019 Oct 16]. Available from: http://etd.aau.edu.et/dspace/handle/123456789/4503.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Misiker T. HIGH PERFORMANCE AUTOMATIC TARGET RECOGNITION . [Thesis]. Addis Ababa University; 2013. Available from: http://etd.aau.edu.et/dspace/handle/123456789/4503

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


California State University – Sacramento

10. Patel, Maunank V. Integrated equipment operation and central control system of power plants.

Degree: MS, Electrical and Electronic Engineering, 2010, California State University – Sacramento

 As we know our each day to day activity requires electricity, starting from waking up by alarm to using cell phone and computer at work… (more)

Subjects/Keywords: FPGA; Field programmable gate array; Power plant optimization

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APA (6th Edition):

Patel, M. V. (2010). Integrated equipment operation and central control system of power plants. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.9/241

Chicago Manual of Style (16th Edition):

Patel, Maunank V. “Integrated equipment operation and central control system of power plants.” 2010. Masters Thesis, California State University – Sacramento. Accessed October 16, 2019. http://hdl.handle.net/10211.9/241.

MLA Handbook (7th Edition):

Patel, Maunank V. “Integrated equipment operation and central control system of power plants.” 2010. Web. 16 Oct 2019.

Vancouver:

Patel MV. Integrated equipment operation and central control system of power plants. [Internet] [Masters thesis]. California State University – Sacramento; 2010. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/10211.9/241.

Council of Science Editors:

Patel MV. Integrated equipment operation and central control system of power plants. [Masters Thesis]. California State University – Sacramento; 2010. Available from: http://hdl.handle.net/10211.9/241

11. Heyse, Stefan. Post quantum cryptography : implementing alternative public key schemes of embedded devices ; preparing for the rise of quantum computers.

Degree: 2013, Ruhr Universität Bochum

 In dieser Arbeit diskutieren wir neue Primitiven für Public-Key-Kryptographie, die sich als Alternativen zu den derzeit verwendeten RSA und ECC Kryptosystemen etablieren könnten. Die Analyse… (more)

Subjects/Keywords: Integrierte Software; Public-Key-Kryptosystem; Codierung; Field programmable gate array; Mikrokontroller

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APA (6th Edition):

Heyse, S. (2013). Post quantum cryptography : implementing alternative public key schemes of embedded devices ; preparing for the rise of quantum computers. (Thesis). Ruhr Universität Bochum. Retrieved from http://nbn-resolving.de/urn/resolver.pl?urn=urn:nbn:de:hbz:294-40373

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Heyse, Stefan. “Post quantum cryptography : implementing alternative public key schemes of embedded devices ; preparing for the rise of quantum computers.” 2013. Thesis, Ruhr Universität Bochum. Accessed October 16, 2019. http://nbn-resolving.de/urn/resolver.pl?urn=urn:nbn:de:hbz:294-40373.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Heyse, Stefan. “Post quantum cryptography : implementing alternative public key schemes of embedded devices ; preparing for the rise of quantum computers.” 2013. Web. 16 Oct 2019.

Vancouver:

Heyse S. Post quantum cryptography : implementing alternative public key schemes of embedded devices ; preparing for the rise of quantum computers. [Internet] [Thesis]. Ruhr Universität Bochum; 2013. [cited 2019 Oct 16]. Available from: http://nbn-resolving.de/urn/resolver.pl?urn=urn:nbn:de:hbz:294-40373.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Heyse S. Post quantum cryptography : implementing alternative public key schemes of embedded devices ; preparing for the rise of quantum computers. [Thesis]. Ruhr Universität Bochum; 2013. Available from: http://nbn-resolving.de/urn/resolver.pl?urn=urn:nbn:de:hbz:294-40373

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Estadual de Campinas

12. Almeida, Carlos Caetano de, 1976-. Arquitetura do módulo de convolução para visão computacional baseada em FPGA .

Degree: 2015, Universidade Estadual de Campinas

 Resumo: Esta dissertação apresenta o estudo de uma arquitetura para o processamento digital de imagens, desenvolvido através de dispositivos de hardware programável, no caso FPGA,… (more)

Subjects/Keywords: Processamento de imagens; Visão por computador; FPGA (Field Programmable Gate Array)

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APA (6th Edition):

Almeida, Carlos Caetano de, 1. (2015). Arquitetura do módulo de convolução para visão computacional baseada em FPGA . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/265780

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Almeida, Carlos Caetano de, 1976-. “Arquitetura do módulo de convolução para visão computacional baseada em FPGA .” 2015. Thesis, Universidade Estadual de Campinas. Accessed October 16, 2019. http://repositorio.unicamp.br/jspui/handle/REPOSIP/265780.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Almeida, Carlos Caetano de, 1976-. “Arquitetura do módulo de convolução para visão computacional baseada em FPGA .” 2015. Web. 16 Oct 2019.

Vancouver:

Almeida, Carlos Caetano de 1. Arquitetura do módulo de convolução para visão computacional baseada em FPGA . [Internet] [Thesis]. Universidade Estadual de Campinas; 2015. [cited 2019 Oct 16]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/265780.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Almeida, Carlos Caetano de 1. Arquitetura do módulo de convolução para visão computacional baseada em FPGA . [Thesis]. Universidade Estadual de Campinas; 2015. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/265780

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Estadual de Campinas

13. Américo Filho, Júlio Cesar Soares, 1987-. Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128 .

Degree: 2016, Universidade Estadual de Campinas

 Resumo: Neste trabalho, propõe-se uma arquitetura de hardware para um co-processador capaz de realizar encriptação e decriptação segundo o padrão AES-128 com suporte aos modos… (more)

Subjects/Keywords: Algoritmos; Hardware - Arquitetura; Computadores canalizados; Criptografia; FPGA (Field Programmable Gate Array)

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APA (6th Edition):

Américo Filho, Júlio Cesar Soares, 1. (2016). Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128 . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/321942

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Américo Filho, Júlio Cesar Soares, 1987-. “Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128 .” 2016. Thesis, Universidade Estadual de Campinas. Accessed October 16, 2019. http://repositorio.unicamp.br/jspui/handle/REPOSIP/321942.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Américo Filho, Júlio Cesar Soares, 1987-. “Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128 .” 2016. Web. 16 Oct 2019.

Vancouver:

Américo Filho, Júlio Cesar Soares 1. Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128 . [Internet] [Thesis]. Universidade Estadual de Campinas; 2016. [cited 2019 Oct 16]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/321942.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Américo Filho, Júlio Cesar Soares 1. Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128 . [Thesis]. Universidade Estadual de Campinas; 2016. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/321942

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Estadual de Campinas

14. Moreira, Veruska Rodrigues. Plataforma em hardware reconfiguravel para o ensino e pesquisa em laboratorio de sistemas digitais a distancia .

Degree: 2009, Universidade Estadual de Campinas

 Resumo: Esta dissertação apresenta a concepção e o desenvolvimento de uma plataforma em hardware reconfigurável denominada REDLART - REconfigurable Digital Laboratory for Advanced Research and… (more)

Subjects/Keywords: Ensino a distância; FPGA (Field Programmable Gate Array); Serviços na Web

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Moreira, V. R. (2009). Plataforma em hardware reconfiguravel para o ensino e pesquisa em laboratorio de sistemas digitais a distancia . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/258897

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Moreira, Veruska Rodrigues. “Plataforma em hardware reconfiguravel para o ensino e pesquisa em laboratorio de sistemas digitais a distancia .” 2009. Thesis, Universidade Estadual de Campinas. Accessed October 16, 2019. http://repositorio.unicamp.br/jspui/handle/REPOSIP/258897.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Moreira, Veruska Rodrigues. “Plataforma em hardware reconfiguravel para o ensino e pesquisa em laboratorio de sistemas digitais a distancia .” 2009. Web. 16 Oct 2019.

Vancouver:

Moreira VR. Plataforma em hardware reconfiguravel para o ensino e pesquisa em laboratorio de sistemas digitais a distancia . [Internet] [Thesis]. Universidade Estadual de Campinas; 2009. [cited 2019 Oct 16]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/258897.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Moreira VR. Plataforma em hardware reconfiguravel para o ensino e pesquisa em laboratorio de sistemas digitais a distancia . [Thesis]. Universidade Estadual de Campinas; 2009. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/258897

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Chicago

15. Mastinu, Matteo. Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures.

Degree: 2013, University of Illinois – Chicago

 This work addresses the Maxeler Technologies Ltd. platforms, and the principal goal of this work is to design a new methodology to support Partial Reconfiguration… (more)

Subjects/Keywords: Maxeler; Field-Programmable Gate Array (FPGA); Partial Reconfiguration

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mastinu, M. (2013). Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/10018

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mastinu, Matteo. “Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures.” 2013. Thesis, University of Illinois – Chicago. Accessed October 16, 2019. http://hdl.handle.net/10027/10018.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mastinu, Matteo. “Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures.” 2013. Web. 16 Oct 2019.

Vancouver:

Mastinu M. Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures. [Internet] [Thesis]. University of Illinois – Chicago; 2013. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/10027/10018.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mastinu M. Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures. [Thesis]. University of Illinois – Chicago; 2013. Available from: http://hdl.handle.net/10027/10018

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Bucknell University

16. Su, Juliana. Design and Development of an FPGA-based Distributed Computing Processing Platform.

Degree: 2011, Bucknell University

 This thesis presents two frameworks- a software framework and a hardware core manager framework- which, together, can be used to develop a processing platform using… (more)

Subjects/Keywords: field-programmable gate array; FPGA; distributed computing; reconfigurable computing; processing platform

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Su, J. (2011). Design and Development of an FPGA-based Distributed Computing Processing Platform. (Thesis). Bucknell University. Retrieved from https://digitalcommons.bucknell.edu/masters_theses/38

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Su, Juliana. “Design and Development of an FPGA-based Distributed Computing Processing Platform.” 2011. Thesis, Bucknell University. Accessed October 16, 2019. https://digitalcommons.bucknell.edu/masters_theses/38.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Su, Juliana. “Design and Development of an FPGA-based Distributed Computing Processing Platform.” 2011. Web. 16 Oct 2019.

Vancouver:

Su J. Design and Development of an FPGA-based Distributed Computing Processing Platform. [Internet] [Thesis]. Bucknell University; 2011. [cited 2019 Oct 16]. Available from: https://digitalcommons.bucknell.edu/masters_theses/38.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Su J. Design and Development of an FPGA-based Distributed Computing Processing Platform. [Thesis]. Bucknell University; 2011. Available from: https://digitalcommons.bucknell.edu/masters_theses/38

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Leiva Cochachin, Andrés Mijail. Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA.

Degree: 2012, Universidad Nacional de Ingeniería

 En la presente tesis se explica la metodología utilizada en el diseño e implementación de una solución integral (un módulo de captura de paquetes IP… (more)

Subjects/Keywords: Red Ethernet; Módulo de captura; FPGA (Field Programmable Gate Array)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Leiva Cochachin, A. M. (2012). Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA. (Thesis). Universidad Nacional de Ingeniería. Retrieved from http://cybertesis.uni.edu.pe/handle/uni/1325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Leiva Cochachin, Andrés Mijail. “Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA.” 2012. Thesis, Universidad Nacional de Ingeniería. Accessed October 16, 2019. http://cybertesis.uni.edu.pe/handle/uni/1325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Leiva Cochachin, Andrés Mijail. “Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA.” 2012. Web. 16 Oct 2019.

Vancouver:

Leiva Cochachin AM. Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA. [Internet] [Thesis]. Universidad Nacional de Ingeniería; 2012. [cited 2019 Oct 16]. Available from: http://cybertesis.uni.edu.pe/handle/uni/1325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Leiva Cochachin AM. Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA. [Thesis]. Universidad Nacional de Ingeniería; 2012. Available from: http://cybertesis.uni.edu.pe/handle/uni/1325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


McMaster University

18. Zuzarte, Marvin. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.

Degree: MASc, 2014, McMaster University

Safety and mission critical systems are currently deployed in many different fields where there is a greater presence of high energy particles (e.g. aerospace). The… (more)

Subjects/Keywords: FPGA; Fault injection; Field programmable gate array; runtime; soft error

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zuzarte, M. (2014). A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. (Masters Thesis). McMaster University. Retrieved from http://hdl.handle.net/11375/16500

Chicago Manual of Style (16th Edition):

Zuzarte, Marvin. “A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.” 2014. Masters Thesis, McMaster University. Accessed October 16, 2019. http://hdl.handle.net/11375/16500.

MLA Handbook (7th Edition):

Zuzarte, Marvin. “A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.” 2014. Web. 16 Oct 2019.

Vancouver:

Zuzarte M. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. [Internet] [Masters thesis]. McMaster University; 2014. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/11375/16500.

Council of Science Editors:

Zuzarte M. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. [Masters Thesis]. McMaster University; 2014. Available from: http://hdl.handle.net/11375/16500


Georgia Tech

19. Kim, Sihwan. Low power mixed signal system design environment using floating-gate FPAAs.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The objective of this research is to create a low-power mixed-signal system design environment using FG FPAAs. To achieve this, my research focused on implementing… (more)

Subjects/Keywords: Floating-gate; FG; Field programmable analog array (FPAA)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, S. (2018). Low power mixed signal system design environment using floating-gate FPAAs. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59923

Chicago Manual of Style (16th Edition):

Kim, Sihwan. “Low power mixed signal system design environment using floating-gate FPAAs.” 2018. Doctoral Dissertation, Georgia Tech. Accessed October 16, 2019. http://hdl.handle.net/1853/59923.

MLA Handbook (7th Edition):

Kim, Sihwan. “Low power mixed signal system design environment using floating-gate FPAAs.” 2018. Web. 16 Oct 2019.

Vancouver:

Kim S. Low power mixed signal system design environment using floating-gate FPAAs. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/1853/59923.

Council of Science Editors:

Kim S. Low power mixed signal system design environment using floating-gate FPAAs. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59923


University of Toronto

20. Tai, Justin Isaiah. High-level Synthesis of Datacenter Services.

Degree: 2017, University of Toronto

Field programmable gate arrays have become of great interest for implementing datacenter applications due to high performance gains over traditional compute hardware at a fraction… (more)

Subjects/Keywords: Datacenter; Field Programmable Gate Array; High-Level Synthesis; 0464

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APA (6th Edition):

Tai, J. I. (2017). High-level Synthesis of Datacenter Services. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/76671

Chicago Manual of Style (16th Edition):

Tai, Justin Isaiah. “High-level Synthesis of Datacenter Services.” 2017. Masters Thesis, University of Toronto. Accessed October 16, 2019. http://hdl.handle.net/1807/76671.

MLA Handbook (7th Edition):

Tai, Justin Isaiah. “High-level Synthesis of Datacenter Services.” 2017. Web. 16 Oct 2019.

Vancouver:

Tai JI. High-level Synthesis of Datacenter Services. [Internet] [Masters thesis]. University of Toronto; 2017. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/1807/76671.

Council of Science Editors:

Tai JI. High-level Synthesis of Datacenter Services. [Masters Thesis]. University of Toronto; 2017. Available from: http://hdl.handle.net/1807/76671


University of Illinois – Urbana-Champaign

21. Li, Shuo. Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA).

Degree: MS, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 Direct digital synthesis is a technique for using digital data processing blocks as a means to generate a frequency and phase tunable output signal referenced… (more)

Subjects/Keywords: direct digital synthesizer (DDS); Field-Programmable Gate Array (FPGA); digital design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, S. (2015). Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA). (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78598

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Shuo. “Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA).” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed October 16, 2019. http://hdl.handle.net/2142/78598.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Shuo. “Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA).” 2015. Web. 16 Oct 2019.

Vancouver:

Li S. Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA). [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/2142/78598.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li S. Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA). [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78598

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

22. Xia, Tian. FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition.

Degree: MS, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 Despite the recent success of neural network in the research eld, the num- ber of resulting applications for non-academic settings is very limited. One setback… (more)

Subjects/Keywords: Field-Programmable Gate Array (FPGA); Restricted Boltzmann Machine (RBM)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xia, T. (2015). FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78800

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xia, Tian. “FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed October 16, 2019. http://hdl.handle.net/2142/78800.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xia, Tian. “FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition.” 2015. Web. 16 Oct 2019.

Vancouver:

Xia T. FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/2142/78800.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xia T. FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78800

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

23. Tolar, Jacob. A directory enhanced network on chip for FPGA.

Degree: MS, 1200, 2013, University of Illinois – Urbana-Champaign

 This thesis presents and evaluates a directory enhanced network on chip for FPGA, with the goal of improving the performance of cores generated by FCUDA,… (more)

Subjects/Keywords: Network on Chip; Field-Programmable Gate Array (FPGA); FCUDA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tolar, J. (2013). A directory enhanced network on chip for FPGA. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/44439

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tolar, Jacob. “A directory enhanced network on chip for FPGA.” 2013. Thesis, University of Illinois – Urbana-Champaign. Accessed October 16, 2019. http://hdl.handle.net/2142/44439.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tolar, Jacob. “A directory enhanced network on chip for FPGA.” 2013. Web. 16 Oct 2019.

Vancouver:

Tolar J. A directory enhanced network on chip for FPGA. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2013. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/2142/44439.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tolar J. A directory enhanced network on chip for FPGA. [Thesis]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/44439

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. Jadeglans, Tim. FPGA-implementation av ett neuralt nätverk .

Degree: Chalmers tekniska högskola / Institutionen för data och informationsvetenskap, 2019, Chalmers University of Technology

 Image recognition is a quickly growing field where convolutional neural networks, CNN, are in the bleeding edge. Today fast GPUs are used which consume a… (more)

Subjects/Keywords: Convolutional Neural Network; CNN; Field Programmable Gate Array; FPGA; Image Recognition

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jadeglans, T. (2019). FPGA-implementation av ett neuralt nätverk . (Thesis). Chalmers University of Technology. Retrieved from http://hdl.handle.net/20.500.12380/300036

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jadeglans, Tim. “FPGA-implementation av ett neuralt nätverk .” 2019. Thesis, Chalmers University of Technology. Accessed October 16, 2019. http://hdl.handle.net/20.500.12380/300036.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jadeglans, Tim. “FPGA-implementation av ett neuralt nätverk .” 2019. Web. 16 Oct 2019.

Vancouver:

Jadeglans T. FPGA-implementation av ett neuralt nätverk . [Internet] [Thesis]. Chalmers University of Technology; 2019. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/20.500.12380/300036.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jadeglans T. FPGA-implementation av ett neuralt nätverk . [Thesis]. Chalmers University of Technology; 2019. Available from: http://hdl.handle.net/20.500.12380/300036

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

25. Mayekar, Pallavi Avinash. Design and Verification of a DFI-AXI DDR4 Memory PHY Bridge Suitable for FPGA Based RTL Emulation and Prototyping.

Degree: MS, Electrical Engineering, 2019, Rochester Institute of Technology

  System on chip (SoC) designers today are emphasizing on a process which can ensure robust silicon at the first tape-out. Given the complexity of… (more)

Subjects/Keywords: DDR; Emulation; Field programmable gate array; Hardware design languages; Prototypes; SDRAM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mayekar, P. A. (2019). Design and Verification of a DFI-AXI DDR4 Memory PHY Bridge Suitable for FPGA Based RTL Emulation and Prototyping. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10157

Chicago Manual of Style (16th Edition):

Mayekar, Pallavi Avinash. “Design and Verification of a DFI-AXI DDR4 Memory PHY Bridge Suitable for FPGA Based RTL Emulation and Prototyping.” 2019. Masters Thesis, Rochester Institute of Technology. Accessed October 16, 2019. https://scholarworks.rit.edu/theses/10157.

MLA Handbook (7th Edition):

Mayekar, Pallavi Avinash. “Design and Verification of a DFI-AXI DDR4 Memory PHY Bridge Suitable for FPGA Based RTL Emulation and Prototyping.” 2019. Web. 16 Oct 2019.

Vancouver:

Mayekar PA. Design and Verification of a DFI-AXI DDR4 Memory PHY Bridge Suitable for FPGA Based RTL Emulation and Prototyping. [Internet] [Masters thesis]. Rochester Institute of Technology; 2019. [cited 2019 Oct 16]. Available from: https://scholarworks.rit.edu/theses/10157.

Council of Science Editors:

Mayekar PA. Design and Verification of a DFI-AXI DDR4 Memory PHY Bridge Suitable for FPGA Based RTL Emulation and Prototyping. [Masters Thesis]. Rochester Institute of Technology; 2019. Available from: https://scholarworks.rit.edu/theses/10157


Ryerson University

26. Oviedo, Alejandro Emerio Alfonso. Autonomous stereo vision system for depth computation of moving object.

Degree: 2017, Ryerson University

 This work targets one real world application of stereo vision technology: the computation of the depth information of a moving object in a scene. It… (more)

Subjects/Keywords: Field programmable gate arrays; Artificial satellites  – Control systems; Programmable array logic; Computer algorithms

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Oviedo, A. E. A. (2017). Autonomous stereo vision system for depth computation of moving object. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A6669

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Oviedo, Alejandro Emerio Alfonso. “Autonomous stereo vision system for depth computation of moving object.” 2017. Thesis, Ryerson University. Accessed October 16, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A6669.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Oviedo, Alejandro Emerio Alfonso. “Autonomous stereo vision system for depth computation of moving object.” 2017. Web. 16 Oct 2019.

Vancouver:

Oviedo AEA. Autonomous stereo vision system for depth computation of moving object. [Internet] [Thesis]. Ryerson University; 2017. [cited 2019 Oct 16]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6669.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Oviedo AEA. Autonomous stereo vision system for depth computation of moving object. [Thesis]. Ryerson University; 2017. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6669

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

27. Tan, Zhou. Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing.

Degree: MS, Electrical and Computer Engineering, 2011, North Dakota State University

 This paper presents the design of a reconfigurable asynchronous unit, called the pulsed quad-cell (PQ-cell), for conformal computing. The conformal computing vision is to create… (more)

Subjects/Keywords: Cellular automata.; Asynchronous circuits.; Pulse circuits.; Field programmable gate arrays.; Gate array circuits.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tan, Z. (2011). Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing. (Masters Thesis). North Dakota State University. Retrieved from http://hdl.handle.net/10365/29176

Chicago Manual of Style (16th Edition):

Tan, Zhou. “Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing.” 2011. Masters Thesis, North Dakota State University. Accessed October 16, 2019. http://hdl.handle.net/10365/29176.

MLA Handbook (7th Edition):

Tan, Zhou. “Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing.” 2011. Web. 16 Oct 2019.

Vancouver:

Tan Z. Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing. [Internet] [Masters thesis]. North Dakota State University; 2011. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/10365/29176.

Council of Science Editors:

Tan Z. Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing. [Masters Thesis]. North Dakota State University; 2011. Available from: http://hdl.handle.net/10365/29176

28. Guilherme Seelaender. Emulação e co-simulação do sistema de controle de atitude da PMM e do sistema eletro-hidráulico de uma aeronave usando FPGAs.

Degree: 2009, Instituto Nacional de Pesquisas Espaciais

This work addresses the different development processes that leads to the implementation of simulation and control algorithms into a FPGA. As case study two applications… (more)

Subjects/Keywords: Field programmable gate array (FPGA); fluxo de desenvolvimento; co-simulação-emulação; sistemas aeroespaciais; field programmable gate array (FPGA); development flow; co-simulation-emulation; aerospace systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Seelaender, G. (2009). Emulação e co-simulação do sistema de controle de atitude da PMM e do sistema eletro-hidráulico de uma aeronave usando FPGAs. (Thesis). Instituto Nacional de Pesquisas Espaciais. Retrieved from http://urlib.net/sid.inpe.br/[email protected]/2009/04.09.15.46

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Seelaender, Guilherme. “Emulação e co-simulação do sistema de controle de atitude da PMM e do sistema eletro-hidráulico de uma aeronave usando FPGAs.” 2009. Thesis, Instituto Nacional de Pesquisas Espaciais. Accessed October 16, 2019. http://urlib.net/sid.inpe.br/[email protected]/2009/04.09.15.46.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Seelaender, Guilherme. “Emulação e co-simulação do sistema de controle de atitude da PMM e do sistema eletro-hidráulico de uma aeronave usando FPGAs.” 2009. Web. 16 Oct 2019.

Vancouver:

Seelaender G. Emulação e co-simulação do sistema de controle de atitude da PMM e do sistema eletro-hidráulico de uma aeronave usando FPGAs. [Internet] [Thesis]. Instituto Nacional de Pesquisas Espaciais; 2009. [cited 2019 Oct 16]. Available from: http://urlib.net/sid.inpe.br/[email protected]/2009/04.09.15.46.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Seelaender G. Emulação e co-simulação do sistema de controle de atitude da PMM e do sistema eletro-hidráulico de uma aeronave usando FPGAs. [Thesis]. Instituto Nacional de Pesquisas Espaciais; 2009. Available from: http://urlib.net/sid.inpe.br/[email protected]/2009/04.09.15.46

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade de Brasília

29. Daniel Mauricio Muñoz Arboleda. Implementação e simulação de algoritmos de escalonamento para sistemas de elevadores usando arquiteturas reconfiguráveis.

Degree: 2006, Universidade de Brasília

Este trabalho propõe um sistema de elevadores que permite o transporte vertical de passageiros de uma forma eficiente. A abordagem é baseada na implementação de… (more)

Subjects/Keywords: elevator system; sistemas inteligentes de controle; lógica nebulosa; FPGAs (Field Programmable Gate Array); sistema de Elevadores; ENGENHARIA MECANICA; FPGAs (Field Programmable Gate Array)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Arboleda, D. M. M. (2006). Implementação e simulação de algoritmos de escalonamento para sistemas de elevadores usando arquiteturas reconfiguráveis. (Thesis). Universidade de Brasília. Retrieved from http://bdtd.bce.unb.br/tedesimplificado/tde_busca/arquivo.php?codArquivo=882

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Arboleda, Daniel Mauricio Muñoz. “Implementação e simulação de algoritmos de escalonamento para sistemas de elevadores usando arquiteturas reconfiguráveis.” 2006. Thesis, Universidade de Brasília. Accessed October 16, 2019. http://bdtd.bce.unb.br/tedesimplificado/tde_busca/arquivo.php?codArquivo=882.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Arboleda, Daniel Mauricio Muñoz. “Implementação e simulação de algoritmos de escalonamento para sistemas de elevadores usando arquiteturas reconfiguráveis.” 2006. Web. 16 Oct 2019.

Vancouver:

Arboleda DMM. Implementação e simulação de algoritmos de escalonamento para sistemas de elevadores usando arquiteturas reconfiguráveis. [Internet] [Thesis]. Universidade de Brasília; 2006. [cited 2019 Oct 16]. Available from: http://bdtd.bce.unb.br/tedesimplificado/tde_busca/arquivo.php?codArquivo=882.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Arboleda DMM. Implementação e simulação de algoritmos de escalonamento para sistemas de elevadores usando arquiteturas reconfiguráveis. [Thesis]. Universidade de Brasília; 2006. Available from: http://bdtd.bce.unb.br/tedesimplificado/tde_busca/arquivo.php?codArquivo=882

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université de Lorraine

30. Becker, Florent. Contribution à la continuité de service des convertisseurs statiques multiniveaux : Contribution to the continuity of service of multilevel converters.

Degree: Docteur es, Génie électrique, 2017, Université de Lorraine

Ce mémoire s’inscrit dans le contexte général de la continuité de service des convertisseurs multiniveaux, lors de la défaillance d’un de leurs composants de puissance.… (more)

Subjects/Keywords: Continuité de service; Tolérance de pannes; Convertisseurs multiniveaux; Field Programmable Gate Array; Continuity of service; Fault tolerant operation; Multilevel converter; Field Programmable Gate Array; 621.313

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Becker, F. (2017). Contribution à la continuité de service des convertisseurs statiques multiniveaux : Contribution to the continuity of service of multilevel converters. (Doctoral Dissertation). Université de Lorraine. Retrieved from http://www.theses.fr/2017LORR0202

Chicago Manual of Style (16th Edition):

Becker, Florent. “Contribution à la continuité de service des convertisseurs statiques multiniveaux : Contribution to the continuity of service of multilevel converters.” 2017. Doctoral Dissertation, Université de Lorraine. Accessed October 16, 2019. http://www.theses.fr/2017LORR0202.

MLA Handbook (7th Edition):

Becker, Florent. “Contribution à la continuité de service des convertisseurs statiques multiniveaux : Contribution to the continuity of service of multilevel converters.” 2017. Web. 16 Oct 2019.

Vancouver:

Becker F. Contribution à la continuité de service des convertisseurs statiques multiniveaux : Contribution to the continuity of service of multilevel converters. [Internet] [Doctoral dissertation]. Université de Lorraine; 2017. [cited 2019 Oct 16]. Available from: http://www.theses.fr/2017LORR0202.

Council of Science Editors:

Becker F. Contribution à la continuité de service des convertisseurs statiques multiniveaux : Contribution to the continuity of service of multilevel converters. [Doctoral Dissertation]. Université de Lorraine; 2017. Available from: http://www.theses.fr/2017LORR0202

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