subject:(Field programmable gate array FPGA )

1. Turki, Mariem. Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform.

Degree: Docteur es, Informatique et Micro-Electronique, 2014, Université Pierre et Marie Curie – Paris VI

URL: http://www.theses.fr/2014PA066698

►

De nos jours, la complexité de la conception des circuits intégrés et du logiciel croit régulièrement, faisant croître le besoin de la vérification dans chaque… (more)

▼

De nos jours, la complexité de la conception des circuits intégrés et du logiciel croit régulièrement, faisant croître le besoin de la vérification dans chaque étape du cycle de conception. Le prototypage matériel sur une plateforme multi-FPGA présente le meilleur compromis entre le temps de conception d'un circuit et le temps d'exécution d'une application par ce circuit. Pour l'implémenter sur cette plateforme, une opération de partitionnement est effectuée avant de créer des partitions capables de s'intégrer dans chaque FPGAPar conséquent, des signaux coupés à l'interface des partitions doivent passer d'un FPGA à un autre. Cependant, le nombre de traces physiques inter-FPGA est limité ce qui crée des problèmes de routabilité du circuit prototypé. Cette thèse touche surtout la partie post-partitionnement et s'intéresse au problème deroutage inter-FPGA. Ainsi, les principaux travaux de cette thèse sont les suivants :Dans un premier temps, nous nous intéressons au développement d'un générateur debenchmarks qui permet, à l'aide d'une description architecturale simple du benchmark, de générer un circuit modélisé avec le langage de description matérielle VHDL. Le générateur utilise un ensemble de composants ce qui donne aux benchmarks un aspect réel semblable à celui des circuits industriels. Ces circuits de tests nous serviront pour évalue rles performances des techniques développées dans cette thèse. Dans un deuxième temps, nous proposons de développer un outil spécifique qui intervient après le partitionnement pour prendre en compte la contrainte liée à la limitation du nombre d'interconnexion entre les FPGAs. Cet outil est basé sur une approcheitérative visant à réduire le taux de multiplexage (nombre de signaux qui partagent un seul _l physique). Le routage en lui même est assuré par l'algorithme de routage Pathfinder adapté. Cet algorithme servira comme point de départ pour les techniques de routage développées durant cette thèse. Des adaptations adéquates seront faites pour cibler un ré-seau de routage inter-FPGA. Dans une deuxième partie, nous essayons de déterminer la meilleure forme du signal à router (bi-points ou multi-points) ainsi que le graphe de routage utilisé. Pour cela, nous proposons des scénarios de test a_n de sélectionner les critères qui donnent la fréquence de fonctionnement la plus performante. Par la suite, nous présentons une description détaillée des IPs de multiplexage utilisés.Ces IPs sont insérés dans les parties émettrices et réceptrices d'un canal de communication. Ces IPs incluent des composants spécifiques appelés SERDES pour assurer la sérialisation/déserialisation des données à transmettre. L'insertion de ces composants peut créer des problèmes de routabilité intra-FPGA. Ainsi, dans une deuxième partie, nous proposons un algorithme de placement basé sur l'estimation de la congestion afin d'améliorer la routabilité du circuit.

This thesis mainly deals with the post-partitioning task and addresses the problem of inter-FPGA routing. Thus, the main contributions of this thesis are:…

Advisors/Committee Members: Abid, Mohamed (thesis director), Mehrez, Habib (thesis director).

Subjects/Keywords: FPGA (Field Programmable Gate Array); Prototypage; Routage; Pathfinder; Itératif; Multiplexage; FPGA (Field Programmable Gate Array); Prototyping; 005.18

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Turki, M. (2014). Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform. (Doctoral Dissertation). Université Pierre et Marie Curie – Paris VI. Retrieved from http://www.theses.fr/2014PA066698

Chicago Manual of Style (16^th Edition):

Turki, Mariem. “Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform.” 2014. Doctoral Dissertation, Université Pierre et Marie Curie – Paris VI. Accessed March 02, 2021. http://www.theses.fr/2014PA066698.

MLA Handbook (7^th Edition):

Turki, Mariem. “Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform.” 2014. Web. 02 Mar 2021.

Vancouver:

Turki M. Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform. [Internet] [Doctoral dissertation]. Université Pierre et Marie Curie – Paris VI; 2014. [cited 2021 Mar 02]. Available from: http://www.theses.fr/2014PA066698.

Council of Science Editors:

Turki M. Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform. [Doctoral Dissertation]. Université Pierre et Marie Curie – Paris VI; 2014. Available from: http://www.theses.fr/2014PA066698

McMaster University

2. Zuzarte, Marvin. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.

Degree: MASc, 2014, McMaster University

URL: http://hdl.handle.net/11375/16500

►

Safety and mission critical systems are currently deployed in many different fields where there is a greater presence of high energy particles (e.g. aerospace). The… (more)

▼

Safety and mission critical systems are currently deployed in many different fields where there is a greater presence of high energy particles (e.g. aerospace). The use of field programmable gate arrays (FPGAs) within safety critical systems is becoming more prevalent due to the design and cost benefits their use provides. The effects of externally caused faults on these safety critical systems cannot be neglected. In particular, high energy particle striking a circuit can cause a voltage change in the circuit known as a soft error. The effects these soft errors will have on the circuit needs to be understood in order to ensure that the systems will function properly in the event soft errors do occur. In this thesis a tool is designed to facilitate the run-time injection of soft errors into a hardware circuit running on a FPGA. The tool allows for the control over the number of injections that can be performed and control over the rate that the injections will occur at. Additionally the tool records time stamps of when injections occur and time stamps of when errors are detected. This recorded data allows for the analysis of designs in conditions prone to soft errors. The implemented tool allows for design time parametrization and run time configuration, allowing a multitude of tests to be run for a single compiled design. The tool also eliminates the need for a host computer after configuration by generating the injection locations and times on the FPGA. Eliminating the host computer allows for faster testing when compared to other methods as data transfer times are greatly reduced. The implemented tool was run on classical examples of redundant structures, such as duplication with comparison and triple modular redundancy as well as a non-redundant structure to establish a baseline. The results of multiple tests run on each structure are analyzed to illustrate the uses of the tool and how the tool may be used to test other designs.

Thesis

Master of Applied Science (MASc)

Advisors/Committee Members: Lawford, Mark, Nicolici, Nicola, Software Engineering.

Subjects/Keywords: FPGA; Fault injection; Field programmable gate array; runtime; soft error

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Zuzarte, M. (2014). A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. (Masters Thesis). McMaster University. Retrieved from http://hdl.handle.net/11375/16500

Chicago Manual of Style (16^th Edition):

Zuzarte, Marvin. “A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.” 2014. Masters Thesis, McMaster University. Accessed March 02, 2021. http://hdl.handle.net/11375/16500.

MLA Handbook (7^th Edition):

Zuzarte, Marvin. “A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.” 2014. Web. 02 Mar 2021.

Vancouver:

Zuzarte M. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. [Internet] [Masters thesis]. McMaster University; 2014. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/11375/16500.

Council of Science Editors:

Zuzarte M. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. [Masters Thesis]. McMaster University; 2014. Available from: http://hdl.handle.net/11375/16500

Victoria University of Wellington

3. Ang, Andrew. Development of an Open PXIe System based on FPGA Modules.

Degree: 2018, Victoria University of Wellington

URL: http://hdl.handle.net/10063/7653

► PXIe is a instrumentation platform that is used as the basis for developing test equipment, modular electronic instruments and automated test systems. A typical PXIe… (more)

Subjects/Keywords: FPGA; PXIe; Electronics; PCI eXtensions for Instrumentation; Field Programmable Gate Array

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Ang, A. (2018). Development of an Open PXIe System based on FPGA Modules. (Masters Thesis). Victoria University of Wellington. Retrieved from http://hdl.handle.net/10063/7653

Chicago Manual of Style (16^th Edition):

Ang, Andrew. “Development of an Open PXIe System based on FPGA Modules.” 2018. Masters Thesis, Victoria University of Wellington. Accessed March 02, 2021. http://hdl.handle.net/10063/7653.

MLA Handbook (7^th Edition):

Ang, Andrew. “Development of an Open PXIe System based on FPGA Modules.” 2018. Web. 02 Mar 2021.

Vancouver:

Ang A. Development of an Open PXIe System based on FPGA Modules. [Internet] [Masters thesis]. Victoria University of Wellington; 2018. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/10063/7653.

Council of Science Editors:

Ang A. Development of an Open PXIe System based on FPGA Modules. [Masters Thesis]. Victoria University of Wellington; 2018. Available from: http://hdl.handle.net/10063/7653

Bucknell University

4. Su, Juliana. Design and Development of an FPGA-based Distributed Computing Processing Platform.

Degree: 2011, Bucknell University

URL: https://digitalcommons.bucknell.edu/masters_theses/38

► This thesis presents two frameworks- a software framework and a hardware core manager framework- which, together, can be used to develop a processing platform using… (more)

Subjects/Keywords: field-programmable gate array; FPGA; distributed computing; reconfigurable computing; processing platform

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Su, J. (2011). Design and Development of an FPGA-based Distributed Computing Processing Platform. (Thesis). Bucknell University. Retrieved from https://digitalcommons.bucknell.edu/masters_theses/38

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Su, Juliana. “Design and Development of an FPGA-based Distributed Computing Processing Platform.” 2011. Thesis, Bucknell University. Accessed March 02, 2021. https://digitalcommons.bucknell.edu/masters_theses/38.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Su, Juliana. “Design and Development of an FPGA-based Distributed Computing Processing Platform.” 2011. Web. 02 Mar 2021.

Vancouver:

Su J. Design and Development of an FPGA-based Distributed Computing Processing Platform. [Internet] [Thesis]. Bucknell University; 2011. [cited 2021 Mar 02]. Available from: https://digitalcommons.bucknell.edu/masters_theses/38.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Su J. Design and Development of an FPGA-based Distributed Computing Processing Platform. [Thesis]. Bucknell University; 2011. Available from: https://digitalcommons.bucknell.edu/masters_theses/38

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Illinois – Chicago

5. Mastinu, Matteo. Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures.

Degree: 2013, University of Illinois – Chicago

URL: http://hdl.handle.net/10027/10018

► This work addresses the Maxeler Technologies Ltd. platforms, and the principal goal of this work is to design a new methodology to support Partial Reconfiguration… (more)

Subjects/Keywords: Maxeler; Field-Programmable Gate Array (FPGA); Partial Reconfiguration

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Mastinu, M. (2013). Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/10018

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Mastinu, Matteo. “Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures.” 2013. Thesis, University of Illinois – Chicago. Accessed March 02, 2021. http://hdl.handle.net/10027/10018.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Mastinu, Matteo. “Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures.” 2013. Web. 02 Mar 2021.

Vancouver:

Mastinu M. Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures. [Internet] [Thesis]. University of Illinois – Chicago; 2013. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/10027/10018.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mastinu M. Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures. [Thesis]. University of Illinois – Chicago; 2013. Available from: http://hdl.handle.net/10027/10018

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Toronto

6. Yazdanshenas, Sadegh. Datacenter-optimized FPGAs.

Degree: PhD, 2019, University of Toronto

URL: http://hdl.handle.net/1807/97003

► Large-scale deployment of field-programmable gate arrays (FPGAs) into datacenters has introduced new use cases that utilize the FPGA as a multi-user compute platform, require more… (more)

Subjects/Keywords: Datacenter; Field-programmable Gate Array; FPGA Architecture; 0464

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Yazdanshenas, S. (2019). Datacenter-optimized FPGAs. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/97003

Chicago Manual of Style (16^th Edition):

Yazdanshenas, Sadegh. “Datacenter-optimized FPGAs.” 2019. Doctoral Dissertation, University of Toronto. Accessed March 02, 2021. http://hdl.handle.net/1807/97003.

MLA Handbook (7^th Edition):

Yazdanshenas, Sadegh. “Datacenter-optimized FPGAs.” 2019. Web. 02 Mar 2021.

Vancouver:

Yazdanshenas S. Datacenter-optimized FPGAs. [Internet] [Doctoral dissertation]. University of Toronto; 2019. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/1807/97003.

Council of Science Editors:

Yazdanshenas S. Datacenter-optimized FPGAs. [Doctoral Dissertation]. University of Toronto; 2019. Available from: http://hdl.handle.net/1807/97003

University of Illinois – Urbana-Champaign

7. Tolar, Jacob. A directory enhanced network on chip for FPGA.

Degree: MS, 1200, 2013, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/44439

► This thesis presents and evaluates a directory enhanced network on chip for FPGA, with the goal of improving the performance of cores generated by FCUDA,… (more)

Subjects/Keywords: Network on Chip; Field-Programmable Gate Array (FPGA); FCUDA

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Tolar, J. (2013). A directory enhanced network on chip for FPGA. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/44439

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Tolar, Jacob. “A directory enhanced network on chip for FPGA.” 2013. Thesis, University of Illinois – Urbana-Champaign. Accessed March 02, 2021. http://hdl.handle.net/2142/44439.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Tolar, Jacob. “A directory enhanced network on chip for FPGA.” 2013. Web. 02 Mar 2021.

Vancouver:

Tolar J. A directory enhanced network on chip for FPGA. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2013. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/2142/44439.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tolar J. A directory enhanced network on chip for FPGA. [Thesis]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/44439

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Illinois – Urbana-Champaign

8. Li, Shuo. Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA).

Degree: MS, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/78598

► Direct digital synthesis is a technique for using digital data processing blocks as a means to generate a frequency and phase tunable output signal referenced… (more)

Subjects/Keywords: direct digital synthesizer (DDS); Field-Programmable Gate Array (FPGA); digital design

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Li, S. (2015). Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA). (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78598

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Li, Shuo. “Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA).” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed March 02, 2021. http://hdl.handle.net/2142/78598.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Li, Shuo. “Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA).” 2015. Web. 02 Mar 2021.

Vancouver:

Li S. Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA). [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/2142/78598.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li S. Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA). [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78598

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Illinois – Urbana-Champaign

9. Xia, Tian. FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition.

Degree: MS, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/78800

► Despite the recent success of neural network in the research eld, the num- ber of resulting applications for non-academic settings is very limited. One setback… (more)

Subjects/Keywords: Field-Programmable Gate Array (FPGA); Restricted Boltzmann Machine (RBM)

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Xia, T. (2015). FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78800

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Xia, Tian. “FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed March 02, 2021. http://hdl.handle.net/2142/78800.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Xia, Tian. “FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition.” 2015. Web. 02 Mar 2021.

Vancouver:

Xia T. FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/2142/78800.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xia T. FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78800

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

10. Jadeglans, Tim. FPGA-implementation av ett neuralt nätverk .

Degree: Chalmers tekniska högskola / Institutionen för data och informationsteknik, 2019, Chalmers University of Technology

URL: http://hdl.handle.net/20.500.12380/300036

► Image recognition is a quickly growing field where convolutional neural networks, CNN, are in the bleeding edge. Today fast GPUs are used which consume a… (more)

Subjects/Keywords: Convolutional Neural Network; CNN; Field Programmable Gate Array; FPGA; Image Recognition

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Jadeglans, T. (2019). FPGA-implementation av ett neuralt nätverk . (Thesis). Chalmers University of Technology. Retrieved from http://hdl.handle.net/20.500.12380/300036

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Jadeglans, Tim. “FPGA-implementation av ett neuralt nätverk .” 2019. Thesis, Chalmers University of Technology. Accessed March 02, 2021. http://hdl.handle.net/20.500.12380/300036.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Jadeglans, Tim. “FPGA-implementation av ett neuralt nätverk .” 2019. Web. 02 Mar 2021.

Vancouver:

Jadeglans T. FPGA-implementation av ett neuralt nätverk . [Internet] [Thesis]. Chalmers University of Technology; 2019. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/20.500.12380/300036.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jadeglans T. FPGA-implementation av ett neuralt nätverk . [Thesis]. Chalmers University of Technology; 2019. Available from: http://hdl.handle.net/20.500.12380/300036

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Leiva Cochachin, Andrés Mijail. Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA.

Degree: 2012, Universidad Nacional de Ingeniería

URL: http://cybertesis.uni.edu.pe/handle/uni/1325

► En la presente tesis se explica la metodología utilizada en el diseño e implementación de una solución integral (un módulo de captura de paquetes IP… (more)

▼ En la presente tesis se explica la metodología utilizada en el diseño e implementación de una solución integral (un módulo de captura de paquetes IP y una aplicación de software ejecutada en un servidor) que tiene el propósito de determinar los indicadores de la producción y utilización de servicios de una red Ethernet. La solución es capaz de realizar la recopilación, evaluación y supervisión del contenido del tráfico IP para determinar las diferentes fuentes y destinos de cada servicio IP tanto dentro de la red como fuera de la misma, así como el nivel de tráfico significativo generado por cada servicio, para posteriormente generar reportes con los que una entidad, poseedora de una red privada, puede evaluar el interés y uso de los usuarios de sus diferentes servicios disponibles, determinar los principales servicios externos accedidos por usuarios internos, así como si tales servicios están siendo brindados adecuadamente. Con tal información la entidad puede determinar el nivel de utilización de sus servicios así como evaluar el comportamiento en el tiempo de sus usuarios buscando alcanzar sus objetivos o corregir comportamientos mediante la aplicación de mejores prácticas para mejorar sus prestaciones y conseguir el mayor beneficio para su entidad. La solución integral consta de dos diseños - El “Módulo de Captura”.- El cual es la solución de hardware basada en FPGA (Field Programmable Gate Array), encargada de capturar paquetes IP, realizar un preprocesamiento de la información capturada y enviar los resultados del preprocesamiento hacia un ordenador. - La “Aplicación para Modelamiento y Reportes”.- La cual es una solución de software que utiliza el método desarrollado por Kuai Xu, Zhi-Li Zhang y Supratik Battacharyya y resumido en el documento “Profiling Internet Backbone Traffic: Behavior Models and Applications". Esta aplicación procesa la información proveniente del módulo de captura, y genera reportes estadísticos de indicadores de la producción de servicios.

Subjects/Keywords: Red Ethernet; Módulo de captura; FPGA (Field Programmable Gate Array)

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Leiva Cochachin, A. M. (2012). Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA. (Thesis). Universidad Nacional de Ingeniería. Retrieved from http://cybertesis.uni.edu.pe/handle/uni/1325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Leiva Cochachin, Andrés Mijail. “Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA.” 2012. Thesis, Universidad Nacional de Ingeniería. Accessed March 02, 2021. http://cybertesis.uni.edu.pe/handle/uni/1325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Leiva Cochachin, Andrés Mijail. “Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA.” 2012. Web. 02 Mar 2021.

Vancouver:

Leiva Cochachin AM. Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA. [Internet] [Thesis]. Universidad Nacional de Ingeniería; 2012. [cited 2021 Mar 02]. Available from: http://cybertesis.uni.edu.pe/handle/uni/1325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Leiva Cochachin AM. Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA. [Thesis]. Universidad Nacional de Ingeniería; 2012. Available from: http://cybertesis.uni.edu.pe/handle/uni/1325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

12. Guilherme Seelaender. Emulação e co-simulação do sistema de controle de atitude da PMM e do sistema eletro-hidráulico de uma aeronave usando FPGAs.

Degree: 2009, Instituto Nacional de Pesquisas Espaciais

URL: http://urlib.net/sid.inpe.br/[email protected]/2009/04.09.15.46

►

This work addresses the different development processes that leads to the implementation of simulation and control algorithms into a FPGA. As case study two applications… (more)

Subjects/Keywords: Field programmable gate array (FPGA); fluxo de desenvolvimento; co-simulação-emulação; sistemas aeroespaciais; field programmable gate array (FPGA); development flow; co-simulation-emulation; aerospace systems

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Seelaender, G. (2009). Emulação e co-simulação do sistema de controle de atitude da PMM e do sistema eletro-hidráulico de uma aeronave usando FPGAs. (Thesis). Instituto Nacional de Pesquisas Espaciais. Retrieved from http://urlib.net/sid.inpe.br/[email protected]/2009/04.09.15.46

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Seelaender, Guilherme. “Emulação e co-simulação do sistema de controle de atitude da PMM e do sistema eletro-hidráulico de uma aeronave usando FPGAs.” 2009. Thesis, Instituto Nacional de Pesquisas Espaciais. Accessed March 02, 2021. http://urlib.net/sid.inpe.br/[email protected]/2009/04.09.15.46.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Seelaender, Guilherme. “Emulação e co-simulação do sistema de controle de atitude da PMM e do sistema eletro-hidráulico de uma aeronave usando FPGAs.” 2009. Web. 02 Mar 2021.

Vancouver:

Seelaender G. Emulação e co-simulação do sistema de controle de atitude da PMM e do sistema eletro-hidráulico de uma aeronave usando FPGAs. [Internet] [Thesis]. Instituto Nacional de Pesquisas Espaciais; 2009. [cited 2021 Mar 02]. Available from: http://urlib.net/sid.inpe.br/[email protected]/2009/04.09.15.46.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Seelaender G. Emulação e co-simulação do sistema de controle de atitude da PMM e do sistema eletro-hidráulico de uma aeronave usando FPGAs. [Thesis]. Instituto Nacional de Pesquisas Espaciais; 2009. Available from: http://urlib.net/sid.inpe.br/[email protected]/2009/04.09.15.46

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Universidade do Porto

13. Alves, Miguel Antenor Anjos Soares. Deteção coerente de sinais acústicos para localização robusta de veículos subaquáticos.

Degree: 2013, Universidade do Porto

URL: http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/72629

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores - Major Telecomunicações. Faculdade de Engenharia. Universidade do Porto. 2013 Advisors/Committee Members: Alves, José Carlos dos Santos, Universidade do Porto. Faculdade de Engenharia.

Subjects/Keywords: Veículos subaquáticos; Deteção robusta e precisa de sinais acústicos; Tecnologia FPGA (Field Programmable Gate Array)

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Alves, M. A. A. S. (2013). Deteção coerente de sinais acústicos para localização robusta de veículos subaquáticos. (Thesis). Universidade do Porto. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/72629

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Alves, Miguel Antenor Anjos Soares. “Deteção coerente de sinais acústicos para localização robusta de veículos subaquáticos.” 2013. Thesis, Universidade do Porto. Accessed March 02, 2021. http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/72629.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Alves, Miguel Antenor Anjos Soares. “Deteção coerente de sinais acústicos para localização robusta de veículos subaquáticos.” 2013. Web. 02 Mar 2021.

Vancouver:

Alves MAAS. Deteção coerente de sinais acústicos para localização robusta de veículos subaquáticos. [Internet] [Thesis]. Universidade do Porto; 2013. [cited 2021 Mar 02]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/72629.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Alves MAAS. Deteção coerente de sinais acústicos para localização robusta de veículos subaquáticos. [Thesis]. Universidade do Porto; 2013. Available from: http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/72629

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

14. SILVA JÚNIOR, Luis Carlos da. SynMaker: uma ferramenta de síntese de alto nível para processamento digital de imagem .

Degree: 2013, Universidade Federal de Pernambuco

URL: http://repositorio.ufpe.br/handle/123456789/12404

► Nesta dissertação de mestrado é introduzida uma nova ferramenta de síntese de alto nível chamada SynMaker que recebe como entrada um código de alto nível… (more)

Subjects/Keywords: Síntese de alto nível; Field Programmable Gate Array; FPGA; Processamento digital de imagem

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

SILVA JÚNIOR, L. C. d. (2013). SynMaker: uma ferramenta de síntese de alto nível para processamento digital de imagem . (Thesis). Universidade Federal de Pernambuco. Retrieved from http://repositorio.ufpe.br/handle/123456789/12404

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

SILVA JÚNIOR, Luis Carlos da. “SynMaker: uma ferramenta de síntese de alto nível para processamento digital de imagem .” 2013. Thesis, Universidade Federal de Pernambuco. Accessed March 02, 2021. http://repositorio.ufpe.br/handle/123456789/12404.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

SILVA JÚNIOR, Luis Carlos da. “SynMaker: uma ferramenta de síntese de alto nível para processamento digital de imagem .” 2013. Web. 02 Mar 2021.

Vancouver:

SILVA JÚNIOR LCd. SynMaker: uma ferramenta de síntese de alto nível para processamento digital de imagem . [Internet] [Thesis]. Universidade Federal de Pernambuco; 2013. [cited 2021 Mar 02]. Available from: http://repositorio.ufpe.br/handle/123456789/12404.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

SILVA JÚNIOR LCd. SynMaker: uma ferramenta de síntese de alto nível para processamento digital de imagem . [Thesis]. Universidade Federal de Pernambuco; 2013. Available from: http://repositorio.ufpe.br/handle/123456789/12404

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

UCLA

15. Bergeron, Matthew Ryan. An Improved Quadrature Direct Digital Frequency Synthesizer in an FPGA.

Degree: Electrical Engineering, 2013, UCLA

URL: http://www.escholarship.org/uc/item/9nd0h13k

► The architecture and design of a high-speed quadrature direct digital frequency synthesizer (DDFS) is presented. The architecture is based on a novel multiplier-based angle-rotation algorithm… (more)

Subjects/Keywords: Electrical engineering; angle rotation; Direct Digital Frequency Synthesizer (DDFS); Field Programmable Gate Array (FPGA)

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Bergeron, M. R. (2013). An Improved Quadrature Direct Digital Frequency Synthesizer in an FPGA. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/9nd0h13k

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Bergeron, Matthew Ryan. “An Improved Quadrature Direct Digital Frequency Synthesizer in an FPGA.” 2013. Thesis, UCLA. Accessed March 02, 2021. http://www.escholarship.org/uc/item/9nd0h13k.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Bergeron, Matthew Ryan. “An Improved Quadrature Direct Digital Frequency Synthesizer in an FPGA.” 2013. Web. 02 Mar 2021.

Vancouver:

Bergeron MR. An Improved Quadrature Direct Digital Frequency Synthesizer in an FPGA. [Internet] [Thesis]. UCLA; 2013. [cited 2021 Mar 02]. Available from: http://www.escholarship.org/uc/item/9nd0h13k.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bergeron MR. An Improved Quadrature Direct Digital Frequency Synthesizer in an FPGA. [Thesis]. UCLA; 2013. Available from: http://www.escholarship.org/uc/item/9nd0h13k

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Michigan

16. Hashem, Amjad Qusay. ALU and Dependency Manager Using FPGA.

Degree: MSin Engineering, Computer Engineering, College of Engineering & Computer Science, 2020, University of Michigan

URL: http://hdl.handle.net/2027.42/155349

► In this project, we have researched the design of high-speed processing units through parallel processing scheme. Our design will be used for Real – Time… (more)

Subjects/Keywords: ALU; Arithmetic logic unit; Dependency manager; FPGA; Field Programmable Gate Array; Parallel processing

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Hashem, A. Q. (2020). ALU and Dependency Manager Using FPGA. (Masters Thesis). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/155349

Chicago Manual of Style (16^th Edition):

Hashem, Amjad Qusay. “ALU and Dependency Manager Using FPGA.” 2020. Masters Thesis, University of Michigan. Accessed March 02, 2021. http://hdl.handle.net/2027.42/155349.

MLA Handbook (7^th Edition):

Hashem, Amjad Qusay. “ALU and Dependency Manager Using FPGA.” 2020. Web. 02 Mar 2021.

Vancouver:

Hashem AQ. ALU and Dependency Manager Using FPGA. [Internet] [Masters thesis]. University of Michigan; 2020. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/2027.42/155349.

Council of Science Editors:

Hashem AQ. ALU and Dependency Manager Using FPGA. [Masters Thesis]. University of Michigan; 2020. Available from: http://hdl.handle.net/2027.42/155349

University of Newcastle

17. Dalton, John. A reconfigurable prototyping system for multiple-input multiple-output communications.

Degree: MIMO) communications over-the-air. It covers the entire process, from concept to design and construction, culminating in transmitting space-time coded data packets and producing bit error rate (BER) performance curves. A flexible modular architecture is designed, able to test current MIMO systems and to be upgraded as the field develops. Printed circuit boards for a field-programmable gate array (FPGA) based mainboard, 2.4 GHz transceivers and antennas are then designed, embodying the aforementioned architecture. The mainboard uses a Xilinx XC2S600E FPGA, with ∼600,000 logic gates. Hardware is assembled and tested, forming a foundation for further layers of firmware and software. An abstraction layer, with associated test benches, is written in a hardware description language (VHDL), allowing the core logic of the FPGA to be written and simulated in a device-independent manner. Further VHDL is written and the testbed configured to transmit and receive bursts of data. A device driver is implemented, and abstract data types are layered on top of the driver, enabling high-level control of the testbed. Single antenna and MIMO data links are implemented using 1x1 binary phase-shift keying (BPSK, transmitting space-time coded data packets and producing bit error rate (BER) performance curves. A flexible modular architecture is designed, able to test current MIMO systems and to be upgraded as the field develops. Printed circuit boards for a field-programmable gate array (FPGA) based mainboard, 2.4 GHz transceivers and antennas are then designed, embodying the aforementioned architecture. The mainboard uses a Xilinx XC2S600E FPGA, with ∼600,000 logic gates. Hardware is assembled and tested, forming a foundation for further layers of firmware and software. An abstraction layer, with associated test benches, is written in a hardware description language (VHDL), allowing the core logic of the FPGA to be written and simulated in a device-independent manner. Further VHDL is written and the testbed configured to transmit and receive bursts of data. A device driver is implemented, and abstract data types are layered on top of the driver, enabling high-level control of the testbed. Single antenna and MIMO data links are implemented using 1x1 binary phase-shift keying (BPSK, 2009, University of Newcastle

URL: http://hdl.handle.net/1959.13/41758

►

Masters Research - Master of Engineering

This thesis demonstrates the process of building a system to test multiple-input multiple-output (MIMO) communications over-the-air. It covers the… (more)

▼

Masters Research - Master of Engineering

This thesis demonstrates the process of building a system to test multiple-input multiple-output (MIMO) communications over-the-air. It covers the entire process, from concept to design and construction, culminating in transmitting space-time coded data packets and producing bit error rate (BER) performance curves. A flexible modular architecture is designed, able to test current MIMO systems and to be upgraded as the field develops. Printed circuit boards for a field-programmable gate array (FPGA) based mainboard, 2.4 GHz transceivers and antennas are then designed, embodying the aforementioned architecture. The mainboard uses a Xilinx XC2S600E FPGA, with ∼600,000 logic gates. Hardware is assembled and tested, forming a foundation for further layers of firmware and software. An abstraction layer, with associated test benches, is written in a hardware description language (VHDL), allowing the core logic of the FPGA to be written and simulated in a device-independent manner. Further VHDL is written and the testbed configured to transmit and receive bursts of data. A device driver is implemented, and abstract data types are layered on top of the driver, enabling high-level control of the testbed. Single antenna and MIMO data links are implemented using 1x1 binary phase-shift keying (BPSK) and 2x2 Alamouti encoded BPSK modulation respectively. Finally, data packets are transmitted and measured BER performance curves constructed. Channel estimation is proved to work on a 2x2 MIMO channel over-the-air, the introduced loss of Eb/N0 shown to be approximately 0.5 dB compared to perfect channel information. The analogue limitations of the hardware are investigated and bit error rate performance measured as a function of operating point. Finally single antenna communications and a 2x2 Alamouti MIMO scheme are compared over-the-air, the Alamouti scheme delivering a 3 dB improvement in Eb/N0 performance. Satisfyingly the MIMO scheme also exceeds the best case theoretical performance bound of the single antenna case by a margin of 2 dB in Eb/N0.

Advisors/Committee Members: University of Newcastle. Faculty of Engineering and Built Environment, School of Electrical Engineering and Computer Science.

Subjects/Keywords: FPGA; field programmable gate array; smart antenna communications; MIMO; multiple-input mulitiple-output

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Dalton, J. (2009). A reconfigurable prototyping system for multiple-input multiple-output communications. (Masters Thesis). University of Newcastle. Retrieved from http://hdl.handle.net/1959.13/41758

Chicago Manual of Style (16^th Edition):

Dalton, John. “A reconfigurable prototyping system for multiple-input multiple-output communications.” 2009. Masters Thesis, University of Newcastle. Accessed March 02, 2021. http://hdl.handle.net/1959.13/41758.

MLA Handbook (7^th Edition):

Dalton, John. “A reconfigurable prototyping system for multiple-input multiple-output communications.” 2009. Web. 02 Mar 2021.

Vancouver:

Dalton J. A reconfigurable prototyping system for multiple-input multiple-output communications. [Internet] [Masters thesis]. University of Newcastle; 2009. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/1959.13/41758.

Council of Science Editors:

Dalton J. A reconfigurable prototyping system for multiple-input multiple-output communications. [Masters Thesis]. University of Newcastle; 2009. Available from: http://hdl.handle.net/1959.13/41758

18. Swientek, Stefan. A data processing firmware for an upgrade of the Outer Tracker detector at the LHCb experiment.

Degree: 2015, Technische Universität Dortmund

URL: http://dx.doi.org/10.17877/DE290R-7448

► This thesis describes the data processing software for an Outer Tracker upgrade at the LHCb experiment. The 2018/19 intended upgrade for the LHCb detector will… (more)

Subjects/Keywords: LHC; LHCb; FPGA; Outer Tracker; Upgrade; Firmware; 530; LHC; Detektor; Field programmable gate array

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Swientek, S. (2015). A data processing firmware for an upgrade of the Outer Tracker detector at the LHCb experiment. (Doctoral Dissertation). Technische Universität Dortmund. Retrieved from http://dx.doi.org/10.17877/DE290R-7448

Chicago Manual of Style (16^th Edition):

Swientek, Stefan. “A data processing firmware for an upgrade of the Outer Tracker detector at the LHCb experiment.” 2015. Doctoral Dissertation, Technische Universität Dortmund. Accessed March 02, 2021. http://dx.doi.org/10.17877/DE290R-7448.

MLA Handbook (7^th Edition):

Swientek, Stefan. “A data processing firmware for an upgrade of the Outer Tracker detector at the LHCb experiment.” 2015. Web. 02 Mar 2021.

Vancouver:

Swientek S. A data processing firmware for an upgrade of the Outer Tracker detector at the LHCb experiment. [Internet] [Doctoral dissertation]. Technische Universität Dortmund; 2015. [cited 2021 Mar 02]. Available from: http://dx.doi.org/10.17877/DE290R-7448.

Council of Science Editors:

Swientek S. A data processing firmware for an upgrade of the Outer Tracker detector at the LHCb experiment. [Doctoral Dissertation]. Technische Universität Dortmund; 2015. Available from: http://dx.doi.org/10.17877/DE290R-7448

Vilnius Gediminas Technical University

19. Arminas, Vytautas. MicroBlaze programinio procesoriaus įgyvendinimo tyrimas.

Degree: Master, Informatics Engineering, 2010, Vilnius Gediminas Technical University

URL: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100619_142408-89771 ;

►

Magistro studijų baigiamajame darbe pateikiamas atliktas lauku programuojamų loginių matricų gamintojos Xilinx kompanijos MicroBlaze programinio procesoriaus tyrimas. Tyrimas vykdytas sėkmingai baigtuose 2008 ir 2009 metais… (more)

▼

Magistro studijų baigiamajame darbe pateikiamas atliktas lauku programuojamų loginių matricų gamintojos Xilinx kompanijos MicroBlaze programinio procesoriaus tyrimas. Tyrimas vykdytas sėkmingai baigtuose 2008 ir 2009 metais Lietuvos Valstybinio mokslo ir studijų fondo remtuose mokslininkų grupių projektuose. Baigiamajame darbe aprašytos MicroBlaze programinio procesoriaus pagrindu sukurtos dvi originalios įterptinės sistemos. Pirmoji įterptinė sistema įgyvendina optimizavimą skruzdžių kolonijomis ir yra skirta vaizdams apdoroti. Antroji įterptinė sistema atlieka lietuvių kalbos pavienių žodžių atpažinimą, todėl gali būti sėkmingai taikoma įvairios paskirties prietaisams valdyti. Atlikti eksperimentai su įgyvendintais algoritmais, ištirtas jų našumas, aparatinių išteklių poreikis, įvertinta skirtingų lustų įtaka spartai. Įterptinių sistemų tyrimų rezultatai paskelbti dviejuose moksliniuose straipsniuose žurnale, cituojamame ISI WEB of Science duomenų bazėje, dviejuose moksliniuose straipsniuose tarptautinių konferencijų medžiagose. Rezultatai viešinti vienoje respublikinėje ir dviejose tarptautinėse konferencijose.

Master thesis presents completed investigation of soft-core processor MicroBlaze, available from Xilinx company–one of main producers of Field Programmable Gate Arrays. The scientific investigation was done in a framework of two successfully completed projects that in years 2008 and 2009 were supported by Lithuanian State Science and Studies Foundation. Development of two original embedded systems based on soft-core processor MicroBlaze is described in Master thesis. Ant colony optimization technique is implemented in the first embedded system that is devoted for image processing. Lithuanian isolated word recognition is implemented in the second embedded system that can be used for remote voice control of various devices. All implemented algorithms are experimentally evaluated on the subject of performance, resource utilization and influence of different FPGA boards upon execution speed of embedded systems. Investigation results of embedded systems are publicized in two scientific articles published in journals that are indexed in ISI WEB of Science database and in two articles published in international conference proceedings. Results are also announced in one national and two international conferences.

Advisors/Committee Members: Navakauskas, Dalius (Master’s thesis supervisor), Babickienė, Zofija (Master’s thesis advisor), Martavičius, Romanas (Master’s thesis reviewer), Filipovič, Mark (Master’s degree committee chair), Skudutis, Julius (Master’s degree committee member), Usovaitė, Ana (Master’s degree committee member).

Subjects/Keywords: MicroBlaze; LPLM; Lauku programuojama loginė matrica; MicroBlaze; FPGA; Field Programmable Gate Array

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Arminas, Vytautas. (2010). MicroBlaze programinio procesoriaus įgyvendinimo tyrimas. (Masters Thesis). Vilnius Gediminas Technical University. Retrieved from http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100619_142408-89771 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16^th Edition):

Arminas, Vytautas. “MicroBlaze programinio procesoriaus įgyvendinimo tyrimas.” 2010. Masters Thesis, Vilnius Gediminas Technical University. Accessed March 02, 2021. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100619_142408-89771 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7^th Edition):

Arminas, Vytautas. “MicroBlaze programinio procesoriaus įgyvendinimo tyrimas.” 2010. Web. 02 Mar 2021.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

Arminas, Vytautas. MicroBlaze programinio procesoriaus įgyvendinimo tyrimas. [Internet] [Masters thesis]. Vilnius Gediminas Technical University; 2010. [cited 2021 Mar 02]. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100619_142408-89771 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

Arminas, Vytautas. MicroBlaze programinio procesoriaus įgyvendinimo tyrimas. [Masters Thesis]. Vilnius Gediminas Technical University; 2010. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100619_142408-89771 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

20. Kimmitt, Jonathan R. R. A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance.

Degree: PhD, 2015, Anglia Ruskin University

URL: http://arro.anglia.ac.uk/id/eprint/581958/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.675601

► The increasing commoditization of computers in modern society has exceeded the pace of associated developments in reliability. Although theoretical computer science has advanced greatly in… (more)

▼ The increasing commoditization of computers in modern society has exceeded the pace of associated developments in reliability. Although theoretical computer science has advanced greatly in the last thirty years, many of the best techniques have yet to find their way into embedded computers, and their failure can have a great potential for disrupting society. This dissertation presents some approaches to improve computer reliability using software and hardware techniques, and makes the following claims for novelty: innovative development of a toolchain and libraries to support extraction from dependent type checking in a theorem prover; conceptual design and deployment in reconfigurable hardware; an extension of static type-safety to hardware description language and FPGA level; elimination of legacy C code from the target and toolchain; a novel hardware error detection scheme is described and compared with conventional triple modular redundancy. The elimination of any user control of memory management promotes robustness against buffer overruns, and consequently prevents vulnerability to common Trojan techniques. The methodology identifies type punning as a key weakness of commonly encountered embedded languages such as C, in particular the extreme difficulty of determining if an array access is in bounds, or if dynamic memory has been properly allocated and released. A method of eliminating dependence on type-unsafe libraries is presented, in conjunction with code that has optionally been proved correct according to user-defined criteria. An appropriately defined subset of OCaml is chosen with support for the Coq theorem prover in mind, and then evaluated with a custom backend that supports behavioural Verilog, as well as a fixed execution unit and associated control store. Results are presented for this alternative platform for reliable embedded systems development that may be used in future industrial flows. To provide assurance of correct operation, the proven software needs to be executed in an environment where errors are checked and corrected in conjunction with appropriate exception processing in the event of an uncorrectable error. Therefore, the present author’s previously published error detection scheme based on dual-rail logic and self-checking checkers is further developed and compared with traditional N-modular redundancy.

Subjects/Keywords: 004.2; FPGA; type-safety; fault-tolerance; self-checking; OCaml; field programmable gate array; type-preservation

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Kimmitt, J. R. R. (2015). A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance. (Doctoral Dissertation). Anglia Ruskin University. Retrieved from http://arro.anglia.ac.uk/id/eprint/581958/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.675601

Chicago Manual of Style (16^th Edition):

Kimmitt, Jonathan R R. “A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance.” 2015. Doctoral Dissertation, Anglia Ruskin University. Accessed March 02, 2021. http://arro.anglia.ac.uk/id/eprint/581958/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.675601.

MLA Handbook (7^th Edition):

Kimmitt, Jonathan R R. “A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance.” 2015. Web. 02 Mar 2021.

Vancouver:

Kimmitt JRR. A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance. [Internet] [Doctoral dissertation]. Anglia Ruskin University; 2015. [cited 2021 Mar 02]. Available from: http://arro.anglia.ac.uk/id/eprint/581958/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.675601.

Council of Science Editors:

Kimmitt JRR. A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance. [Doctoral Dissertation]. Anglia Ruskin University; 2015. Available from: http://arro.anglia.ac.uk/id/eprint/581958/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.675601

University of Illinois – Urbana-Champaign

21. Papakonstantinou, Alexandros. High-level automation of custom hardware design for high-performance computing.

Degree: PhD, 1200, 2013, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/42137

► This dissertation focuses on efficient generation of custom processors from high-level language descriptions. Our work exploits compiler-based optimizations and transformations in tandem with high-level synthesis… (more)

▼ This dissertation focuses on efficient generation of custom processors from high-level language descriptions. Our work exploits compiler-based optimizations and transformations in tandem with high-level synthesis (HLS) to build high-performance custom processors. The goal is to offer a common multiplatform high-abstraction programming interface for heterogeneous compute systems where the benefits of custom reconfigurable (or fixed) processors can be exploited by the application developers. The research presented in this dissertation supports the following thesis: In an increasingly heterogeneous compute environment it is important to leverage the compute capabilities of each heterogeneous processor efficiently. In the case of FPGA and ASIC accelerators this can be achieved through HLS-based flows that (i) extract parallelism at coarser than basic block granularities, (ii) leverage common high-level parallel programming languages, and (iii) employ high-level source-to-source transformations to generate high-throughput custom processors. First, we propose a novel HLS flow that extracts instruction level parallelism beyond the boundary of basic blocks from C code. Subsequently, we describe FCUDA, an HLS-based framework for mapping fine-grained and coarse-grained parallelism from parallel CUDA kernels onto spatial parallelism. FCUDA provides a common programming model for acceleration on heterogeneous devices (i.e. GPUs and FPGAs). Moreover, the FCUDA framework balances multilevel granularity parallelism synthesis using efficient techniques that leverage fast and accurate estimation models (i.e. do not rely on lengthy physical implementation tools). Finally, we describe an advanced source-to-source transformation framework for throughput-driven parallelism synthesis (TDPS), which appropriately restructures CUDA kernel code to maximize throughput on FPGA devices. We have integrated the TDPS framework into the FCUDA flow to enable automatic performance porting of CUDA kernels designed for the GPU architecture onto the FPGA architecture. Advisors/Committee Members: Chen, Deming (advisor), Chen, Deming (Committee Chair), Cong, Jason (committee member), Hwu, Wen-Mei W. (committee member), Wong, Martin D.F. (committee member).

Subjects/Keywords: High-level synthesis; Field-Programmable Gate Array (FPGA); CUDA; parallel programming; High Performance Computing (HPC)

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Papakonstantinou, A. (2013). High-level automation of custom hardware design for high-performance computing. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/42137

Chicago Manual of Style (16^th Edition):

Papakonstantinou, Alexandros. “High-level automation of custom hardware design for high-performance computing.” 2013. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 02, 2021. http://hdl.handle.net/2142/42137.

MLA Handbook (7^th Edition):

Papakonstantinou, Alexandros. “High-level automation of custom hardware design for high-performance computing.” 2013. Web. 02 Mar 2021.

Vancouver:

Papakonstantinou A. High-level automation of custom hardware design for high-performance computing. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2013. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/2142/42137.

Council of Science Editors:

Papakonstantinou A. High-level automation of custom hardware design for high-performance computing. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/42137

University of Illinois – Urbana-Champaign

22. Dong, Chen. Architecture and CAD for nanoscale and 3d FPGA.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/18492

► FPGAs (field programmable gate arrays) are attractive alternatives compared to ASICs (application-specific integrated circuits) for significantly lowering amortized manufacturing costs and dramatically improving design productivity.… (more)

▼ FPGAs (field programmable gate arrays) are attractive alternatives compared to ASICs (application-specific integrated circuits) for significantly lowering amortized manufacturing costs and dramatically improving design productivity. The architecture of an FPGA is very regular. It is relatively easy to design a highly optimized tile, with consideration of various manufacturing related issues, and then to replicate it many times across the chip. The configurability of FPGAs also enables yield improvement and defect tolerance. However, FPGAs are still facing serious challenges in terms of delay, power consumption, and logic density compared to ASICs. FPGA is estimated to be over twenty times less efficient in logic density, over three times worse in delay, and over ten times higher in power consumption compared to a functionally equivalent ASIC. One promising way to improve FPGA performance is to incorporate three-dimensional (3D) integration, which increases the number of active layers and optimizes the interconnect network vertically. Another solution is to apply novel nanoelectronic materials (nanomaterials) and devices. This dissertation introduces three novel reconfigurable architectures, named 3D nFPGA, FPCNA (field programmable carbon nanotube array), and NEM FPGA (nanoelectromechanical FPGA), which utilize 3D integration techniques and new nanoscale materials synergistically. Customized CAD flows that consider process variation have been developed for different architectures to evaluate their potential performances. Also described is a 3D variation aware routing flow, which is an essential tool for future 3D FPGA architecture exploration. 3D nFPGA is based on CMOS (complementary metal-oxide-semiconductor) and nano hybrid techniques that incorporate nanomaterials such as nanowire crossbars and carbon nanotube bundles into the CMOS fabrication process. Using unique features of FPGAs and a novel 3D stacking method enabled by the application of nanomaterials, 3D nFPGA obtains a 4× footprint reduction comparing to the traditional CMOS-based 2D FPGAs. The performance and power of 3D nFPGA driven by the 20 largest MCNC (microelectronics center of North Carolina) benchmarks have been evaluated. Results demonstrate that 3D nFPGA is able to provide a performance gain of 2.6× with a small power overhead compared to the traditional 2D FPGA. FPCNA includes lookup tables created entirely from continuous carbon nanotube (CNT) ribbons. To determine the performance of the building blocks, variation aware physical design tools are used, with statistical static timing analysis (SSTA) that can handle both Gaussian and non-Gaussian random variables. A 2.75× performance improvement is seen over an equivalent CMOS FPGA at a 95% yield. In addition, FPCNA offers a 5× footprint reduction compared to a baseline FPGA. 3D NEM FPGA is the architecture that utilizes nanoelectromechanical (NEM) relays and 3D integration techniques synergistically. This proposed architecture has unique features including a… Advisors/Committee Members: Chen, Deming (advisor), Chen, Deming (Committee Chair), Pop, Eric (committee member), Shanbhag, Naresh R. (committee member), Wong, Martin D.F. (committee member).

Subjects/Keywords: Field-Programmable Gate Array (FPGA); Carbon Nanotube; 3D Integration; Computer-aided design (CAD); Physical Design

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Dong, C. (2011). Architecture and CAD for nanoscale and 3d FPGA. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18492

Chicago Manual of Style (16^th Edition):

Dong, Chen. “Architecture and CAD for nanoscale and 3d FPGA.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 02, 2021. http://hdl.handle.net/2142/18492.

MLA Handbook (7^th Edition):

Dong, Chen. “Architecture and CAD for nanoscale and 3d FPGA.” 2011. Web. 02 Mar 2021.

Vancouver:

Dong C. Architecture and CAD for nanoscale and 3d FPGA. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/2142/18492.

Council of Science Editors:

Dong C. Architecture and CAD for nanoscale and 3d FPGA. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18492

University of Illinois – Urbana-Champaign

23. Johnson, Matthew Robert. Fast, accurate power measurement and optimization for microprocessor platforms.

Degree: PhD, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/78785

► Power and energy consumption have become important for all computers, but the tools used to measure and optimize power on physical hardware lag far behind… (more)

Subjects/Keywords: Power measurement; Current measurement; Energy efficiency; Software optimization; Field-Programmable Gate Array (FPGA); Power optimization

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Johnson, M. R. (2015). Fast, accurate power measurement and optimization for microprocessor platforms. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78785

Chicago Manual of Style (16^th Edition):

Johnson, Matthew Robert. “Fast, accurate power measurement and optimization for microprocessor platforms.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 02, 2021. http://hdl.handle.net/2142/78785.

MLA Handbook (7^th Edition):

Johnson, Matthew Robert. “Fast, accurate power measurement and optimization for microprocessor platforms.” 2015. Web. 02 Mar 2021.

Vancouver:

Johnson MR. Fast, accurate power measurement and optimization for microprocessor platforms. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/2142/78785.

Council of Science Editors:

Johnson MR. Fast, accurate power measurement and optimization for microprocessor platforms. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78785

University of Illinois – Urbana-Champaign

24. Wei, Chunan. New PCM based FPGA architecture and graphene memory cell design.

Degree: MS, 1200, 2014, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/49715

► In this work, we introduce a new look-up table (LUT) implementation using phase change memory (PCM) cells. Utilizing the fact that PCM cells store data… (more)

▼ In this work, we introduce a new look-up table (LUT) implementation using phase change memory (PCM) cells. Utilizing the fact that PCM cells store data using resistance values, unlike traditional memory cells, the memory cell we propose can store up to 2 bits per cell. This is achieved by controlling the 1T2R PCM cell resistances between the on resistance and the off resistance. Taking advantage of this property, a new LUT is designed that can either store two functions or a single function with an additional input. Thus the new design greatly improves FPGA logic density and reduces the area and timing cost. In order to access this new type of memory cell, a sense circuit is designed. We also propose a new hybrid architecture that uses LUTs with single and independent twin-outputs. The architecture is evaluated over delay and area with different LUT configurations. Experimental results show that on average 50 percent area reduction and 10 percent delay reduction can be achieved with the use of the new PCM based LUTs over SRAM based designs. Also, further savings can be achieved by incorporating hybrid architecture. Also, we introduce a new device design based on the SYMFET. This new type of device can be implemented to a memory cell utilizing the graphene sheet-to-sheet tunneling effect to store data. The SYMFET sheet-to-sheet tunneling can generate high current density when the Dirac points of graphene sheets are aligned; low current density is generated when Dirac points are not aligned. This new SYMFET memory has a GIGIG (graphene-insulator-graphene-insulator-graphene) structure. With this new type of device structure, a new mechanism for controlling data stored in the memory cell is introduced. Based on self-limiting tunneling, a third piece of graphene sheet is inserted in-between the source and drain graphene sheets serving as the tunneling current control mechanism. We also developed methods to calculate the on/off currents and gate potentials for this device. Advisors/Committee Members: Chen, Deming (advisor).

Subjects/Keywords: Phase change memory (PCM); Graphene; Field-Programmable Gate Array (FPGA); Memory; Lookup table (LUT)

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Wei, C. (2014). New PCM based FPGA architecture and graphene memory cell design. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/49715

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wei, Chunan. “New PCM based FPGA architecture and graphene memory cell design.” 2014. Thesis, University of Illinois – Urbana-Champaign. Accessed March 02, 2021. http://hdl.handle.net/2142/49715.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wei, Chunan. “New PCM based FPGA architecture and graphene memory cell design.” 2014. Web. 02 Mar 2021.

Vancouver:

Wei C. New PCM based FPGA architecture and graphene memory cell design. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2014. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/2142/49715.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wei C. New PCM based FPGA architecture and graphene memory cell design. [Thesis]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/49715

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Illinois – Urbana-Champaign

25. Chen, Daniel E. FPGA acceleration of short read alignment with high-level synthesis.

Degree: MS, Electrical and Computer Engineering, 2017, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/97641

► With the introduction of next-generation sequencing (NGS) technologies, DNA sequencing is becoming an increasingly widespread process. When performed on human patients, it can allow for… (more)

Subjects/Keywords: Field-programmable gate array (FPGA); Hardware acceleration; High-level synthesis; OpenCL; Short read alignment

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chen, D. E. (2017). FPGA acceleration of short read alignment with high-level synthesis. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97641

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chen, Daniel E. “FPGA acceleration of short read alignment with high-level synthesis.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed March 02, 2021. http://hdl.handle.net/2142/97641.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chen, Daniel E. “FPGA acceleration of short read alignment with high-level synthesis.” 2017. Web. 02 Mar 2021.

Vancouver:

Chen DE. FPGA acceleration of short read alignment with high-level synthesis. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/2142/97641.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen DE. FPGA acceleration of short read alignment with high-level synthesis. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97641

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Illinois – Urbana-Champaign

26. Xu, Zhangqi. FCUDA: Efficient high-level automation CUDA-to-FPGA compilation.

Degree: MS, Electrical and Computer Engineering, 2017, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/99536

► The demand for high-performance computing has been growing significantly in the past decade. The bottleneck of Moore's law and the increasing power consumption in the… (more)

Subjects/Keywords: Field programmable gate array (FPGA); High-level synthesis (HLS); Compute unified device architecture (CUDA)

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Xu, Z. (2017). FCUDA: Efficient high-level automation CUDA-to-FPGA compilation. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99536

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Xu, Zhangqi. “FCUDA: Efficient high-level automation CUDA-to-FPGA compilation.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed March 02, 2021. http://hdl.handle.net/2142/99536.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Xu, Zhangqi. “FCUDA: Efficient high-level automation CUDA-to-FPGA compilation.” 2017. Web. 02 Mar 2021.

Vancouver:

Xu Z. FCUDA: Efficient high-level automation CUDA-to-FPGA compilation. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/2142/99536.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xu Z. FCUDA: Efficient high-level automation CUDA-to-FPGA compilation. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99536

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Arizona

27. Josiah, Jeff G. The CCAP: A New Physical Unclonable Function (PUF) for Protecting Internet of Things (IoT) and Other FPGA-Based Embedded Systems .

Degree: 2020, University of Arizona

URL: http://hdl.handle.net/10150/636691

► The importance of cybersecurity has grown exponentially over the years due to our highly interconnected world and the evolution of computer threats. These threats –… (more)

▼ The importance of cybersecurity has grown exponentially over the years due to our highly interconnected world and the evolution of computer threats. These threats – once as simple as annoying computer viruses – are now destructive malware, ransomware, and advanced persistent threats (APT) sponsored by nation states used to steal military secrets, wage industrial espionage, and weaponize the Cyberspace into the 5th domain of future military conflict right behind Land, Sea, Air, and Space. Every device that interfaces with the Internet is a potential target. For instance, the attack surface for Internet of Things (IoT) is expected to expand with an estimated 14.2 billion connected “things” projected to be in use this year alone. These “things” are diverse and include rugged-industrial sensors, personal wearables, in-home appliances, and even some of the vehicles on the road today. Many IoT devices are beginning to utilize Field Programmable Gate Arrays (FPGAs) for their processing subsystem due to design flexibility and because FPGAs, as a design element, enable product lifecycle support through aftermarket upgradability of both the computer software (CSCI) and firmware/hardware (FWCI) configuration items. This allows manufacturers to enhance product functionality through over-the-Internet (OTI) or over-the-air (OTA) upgrades. Unfortunately, the increasing use of FPGAs has also brought a major concern of intellectual property (IP) theft and product counterfeiting. To help thwart IP theft, FPGA vendors such as Xilinx and Intel PSG (formerly Altera) provide end-users with the ability to encrypt design bitstreams at rest with a cryptographic key. This encryption key is typically stored in EEPROM, Battery-Backed RAM, or within dedicated Anti-Fuses within the device; however, numerous non-invasive, semi-invasive, and invasive attacks exist that can retrieve the encryption key and compromise the design bitstream. Physical (sometimes referred to as physically) unclonable functions (PUFs) have been proposed as a countermeasure to eliminate the need for cryptographic key storage. PUFs have been widely researched for nearly two decades. An efficient implementation for FPGAs has remained elusive and is an area of much needed research focus. The goal of this research was to deliver a new, innovative PUF design targeted specifically for FPGA implementation. We propose the CCAP which is an efficient, scalable hardware security primitive supporting today’s most advanced FPGAs. It requires no hard macros or interactive design floorplanning and is portable to any UltraScale+-based FPGA. Experimental results on several Avnet Ultra96 boards have shown excellent PUF performance in terms of PUF inter-device uniqueness, acceptable performance for PUF intra-device uniqueness, and good overall PUF output stability at the targeted operating temperatures. Additionally, the randomness of several CCAP “raw” signatures at various FPGA die locations have been tested and deemed random according to the NIST Randomness Test Suite, and chi-square… Advisors/Committee Members: Hariri, Salim (advisor), Akoglu, Ali (committeemember), Bruyere, Donald (committeemember), Li, Ming (committeemember).

Subjects/Keywords: Embedded Systems; Field Programmable Gate Array; FPGA Security; IoT; Physical Unclonable Functions; PUFs

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Josiah, J. G. (2020). The CCAP: A New Physical Unclonable Function (PUF) for Protecting Internet of Things (IoT) and Other FPGA-Based Embedded Systems . (Doctoral Dissertation). University of Arizona. Retrieved from http://hdl.handle.net/10150/636691

Chicago Manual of Style (16^th Edition):

Josiah, Jeff G. “The CCAP: A New Physical Unclonable Function (PUF) for Protecting Internet of Things (IoT) and Other FPGA-Based Embedded Systems .” 2020. Doctoral Dissertation, University of Arizona. Accessed March 02, 2021. http://hdl.handle.net/10150/636691.

MLA Handbook (7^th Edition):

Josiah, Jeff G. “The CCAP: A New Physical Unclonable Function (PUF) for Protecting Internet of Things (IoT) and Other FPGA-Based Embedded Systems .” 2020. Web. 02 Mar 2021.

Vancouver:

Josiah JG. The CCAP: A New Physical Unclonable Function (PUF) for Protecting Internet of Things (IoT) and Other FPGA-Based Embedded Systems . [Internet] [Doctoral dissertation]. University of Arizona; 2020. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/10150/636691.

Council of Science Editors:

Josiah JG. The CCAP: A New Physical Unclonable Function (PUF) for Protecting Internet of Things (IoT) and Other FPGA-Based Embedded Systems . [Doctoral Dissertation]. University of Arizona; 2020. Available from: http://hdl.handle.net/10150/636691

University of Saskatchewan

28. Loi, Kung Chi Cinnati 1985-. Hardware Implementations of Scalable and Unified Elliptic Curve Cryptosystem Processors.

Degree: 2015, University of Saskatchewan

URL: http://hdl.handle.net/10388/12649

► As the amount of information exchanged through the network grows, so does the demand for increased security over the transmission of this information. As the… (more)

▼ As the amount of information exchanged through the network grows, so does the demand for increased security over the transmission of this information. As the growth of computers increased in the past few decades, more sophisticated methods of cryptography have been developed. One method of transmitting data securely over the network is by using symmetric-key cryptography. However, a drawback of symmetric-key cryptography is the need to exchange the shared key securely. One of the solutions is to use public-key cryptography. One of the modern public-key cryptography algorithms is called Elliptic Curve Cryptography (ECC). The advantage of ECC over some older algorithms is the smaller number of key sizes to provide a similar level of security. As a result, implementations of ECC are much faster and consume fewer resources. In order to achieve better performance, ECC operations are often offloaded onto hardware to alleviate the workload from the servers' processors. The most important and complex operation in ECC schemes is the elliptic curve point multiplication (ECPM). This thesis explores the implementation of hardware accelerators that offload the ECPM operation to hardware. These processors are referred to as ECC processors, or simply ECPs. This thesis targets the efficient hardware implementation of ECPs specifically for the 15 elliptic curves recommended by the National Institute of Standards and Technology (NIST). The main contribution of this thesis is the implementation of highly efficient hardware for scalable and unified finite field arithmetic units that are used in the design of ECPs. In this thesis, scalability refers to the processor's ability to support multiple key sizes without the need to reconfigure the hardware. By doing so, the hardware does not need to be redesigned for the server to handle different levels of security. Unified refers to the ability of the ECP to handle both prime and binary fields. The resultant designs are valuable to the research community and industry, as a single hardware device is able to handle a wide range of ECC operations efficiently and at high speeds. Thus, improving the ability of network servers to handle secure transaction more quickly and improve productivity at lower costs. Advisors/Committee Members: Ko, Seok-Bum, Teng, Daniel, Bui, Francis, Spiteri, Raymond, Dimitrov, Vassil.

Subjects/Keywords: elliptic curve cryptography(ECC); finite field arithmetic, field programmable gate array (FPGA); hardware architecture; security; computer arithmetic; parallelization

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Loi, K. C. C. 1. (2015). Hardware Implementations of Scalable and Unified Elliptic Curve Cryptosystem Processors. (Thesis). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/12649

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Loi, Kung Chi Cinnati 1985-. “Hardware Implementations of Scalable and Unified Elliptic Curve Cryptosystem Processors.” 2015. Thesis, University of Saskatchewan. Accessed March 02, 2021. http://hdl.handle.net/10388/12649.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Loi, Kung Chi Cinnati 1985-. “Hardware Implementations of Scalable and Unified Elliptic Curve Cryptosystem Processors.” 2015. Web. 02 Mar 2021.

Vancouver:

Loi KCC1. Hardware Implementations of Scalable and Unified Elliptic Curve Cryptosystem Processors. [Internet] [Thesis]. University of Saskatchewan; 2015. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/10388/12649.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Loi KCC1. Hardware Implementations of Scalable and Unified Elliptic Curve Cryptosystem Processors. [Thesis]. University of Saskatchewan; 2015. Available from: http://hdl.handle.net/10388/12649

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Harahap, Charles Ronald. Fully FPGA-Based Permanent Magnet Synchronous Motor Speed Control System Using Two-Degrees-of- Freedom Method Designed by Fictitious Reference Iterative Tuning : 擬似参照信号反復調整法で設計した2自由度制御手法を用いた全FPGA永久磁石同期電動機速度制御系に関する研究.

Degree: 博士（工学）, 2017, Kyushu Institute of Technology / 九州工業大学

URL: http://hdl.handle.net/10228/00006320

►

This dissertation proposes proportional-integral/proportional (PI-P) gain controller parameter tuning in a two-degrees-of-freedom (2DOF) control system using the fictitious reference iterative tuning (FRIT) method for permanent… (more)

▼

This dissertation proposes proportional-integral/proportional (PI-P) gain controller parameter tuning in a two-degrees-of-freedom (2DOF) control system using the fictitious reference iterative tuning (FRIT) method for permanent magnet synchronous motor (PMSM) speed control using a field-programmable gate array (FPGA) for a high-frequency SiC MOSFET inverter. The PI-P controller parameters can be tuned using the FRIT method from one-shot experimental data without using a mathematical model of the plant. FRIT method is used to tune PI-P controller parameters for both step response and disturbance response. A virtual disturbance reference method is proposed in FRIT method where the position of disturbance can be moved virtually to the position of reference so that PI-P controller parameters are designed for both step response and disturbance response at the same time and PI-P controller parameters are not designed separately. Particle swarm optimization is used for FRIT optimization. An inverter that uses a SiC MOSFET is presented to achieve high-frequency operation at up to 100 kHz using a switching pulse-width modulation (PWM) technique. As a result, a high responsivity and high stability PMSM control system is achieved, where the speed response follows the desired response characteristic for both the step response and the disturbance response. High responsivity and disturbance rejection can be achieved using the 2DOF control system. FPGA-based digital hardware control is used to maximize the switching frequency of the SiC MOSFET inverter. Finally, an experimental system is set up and experimental results are presented to prove the viability of the proposed method.

九州工業大学博士学位論文学位記番号:生工博甲第285号学位授与年月日:平成29年3月24日

1 Introduction|2 Permanent Magnet Synchronous Motor Speed Control|3 Controller Design using Fictitious Reference Iterative Tuning for PMSM Speed Control|4 Design 2DOF PI-P Controller using Fictitious Reference Iterative Tuning- Particle Swarm Optimization Method (FRIT-PSO Method)|5 Experimental and Results|6 Conclusions

平成28年度

Advisors/Committee Members: 花本, 剛士.

Subjects/Keywords: Fictitious Reference Iterative Tuning; Field-Programmable Gate Array (FPGA); Two-Degrees-of-Freedom (2DOF); Permanent Magnet Synchronous Motor; SiC MOSFET Inverter

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Harahap, . C. R. (2017). Fully FPGA-Based Permanent Magnet Synchronous Motor Speed Control System Using Two-Degrees-of- Freedom Method Designed by Fictitious Reference Iterative Tuning : 擬似参照信号反復調整法で設計した2自由度制御手法を用いた全FPGA永久磁石同期電動機速度制御系に関する研究. (Thesis). Kyushu Institute of Technology / 九州工業大学. Retrieved from http://hdl.handle.net/10228/00006320

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Harahap, Charles Ronald. “Fully FPGA-Based Permanent Magnet Synchronous Motor Speed Control System Using Two-Degrees-of- Freedom Method Designed by Fictitious Reference Iterative Tuning : 擬似参照信号反復調整法で設計した2自由度制御手法を用いた全FPGA永久磁石同期電動機速度制御系に関する研究.” 2017. Thesis, Kyushu Institute of Technology / 九州工業大学. Accessed March 02, 2021. http://hdl.handle.net/10228/00006320.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Harahap, Charles Ronald. “Fully FPGA-Based Permanent Magnet Synchronous Motor Speed Control System Using Two-Degrees-of- Freedom Method Designed by Fictitious Reference Iterative Tuning : 擬似参照信号反復調整法で設計した2自由度制御手法を用いた全FPGA永久磁石同期電動機速度制御系に関する研究.” 2017. Web. 02 Mar 2021.

Vancouver:

Harahap CR. Fully FPGA-Based Permanent Magnet Synchronous Motor Speed Control System Using Two-Degrees-of- Freedom Method Designed by Fictitious Reference Iterative Tuning : 擬似参照信号反復調整法で設計した2自由度制御手法を用いた全FPGA永久磁石同期電動機速度制御系に関する研究. [Internet] [Thesis]. Kyushu Institute of Technology / 九州工業大学; 2017. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/10228/00006320.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Harahap CR. Fully FPGA-Based Permanent Magnet Synchronous Motor Speed Control System Using Two-Degrees-of- Freedom Method Designed by Fictitious Reference Iterative Tuning : 擬似参照信号反復調整法で設計した2自由度制御手法を用いた全FPGA永久磁石同期電動機速度制御系に関する研究. [Thesis]. Kyushu Institute of Technology / 九州工業大学; 2017. Available from: http://hdl.handle.net/10228/00006320

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Universidade do Rio Grande do Sul

30. Leipnitz, Marcos Tomazzoli. Resilient regular expression matching on FPGAs with fast error repair.

Degree: 2017, Universidade do Rio Grande do Sul

URL: http://hdl.handle.net/10183/168788

►

The Network Function Virtualization (NFV) paradigm promises to make computer networks more scalable and flexible by decoupling the network functions (NFs) from dedicated and vendor-specific… (more)

▼

The Network Function Virtualization (NFV) paradigm promises to make computer networks more scalable and flexible by decoupling the network functions (NFs) from dedicated and vendor-specific hardware. However, network and compute intensive NFs may be difficult to virtualize without performance degradation. In this context, Field-Programmable Gate Arrays (FPGAs) have been shown to be a good option for hardware acceleration of virtual NFs that require high throughput, without deviating from the concept of an NFV infrastructure which aims at high flexibility. Regular expression matching is an important and compute intensive mechanism used to perform Deep Packet Inspection, which can be FPGA-accelerated to meet performance constraints. This solution, however, introduces new challenges regarding dependability requirements. Particularly for SRAM-based FPGAs, soft errors on the configuration memory are a significant dependability threat. In this work we present a comprehensive fault tolerance mechanism to deal with configuration faults on the functionality of FPGA-based regular expression matching engines. Moreover, a placement-aware scrubbing mechanism is introduced to reduce the system repair time, improving the system reliability and availability. Experimental results show that the overall failure rate and the system mean time to repair can be reduced in 95% and 90%, respectively, with manageable area and performance costs.

O paradigma Network Function Virtualization (NFV) promete tornar as redes de computadores mais escaláveis e flexíveis, através do desacoplamento das funções de rede de hardware dedicado e fornecedor específico. No entanto, funções de rede computacionalmente intensivas podem ser difíceis de virtualizar sem degradação de desempenho. Neste contexto, Field-Programmable Gate Arrays (FPGAs) têm se mostrado uma boa opção para aceleração por hardware de funções de rede virtuais que requerem alta vazão, sem se desviar do conceito de uma infraestrutura NFV que visa alta flexibilidade. A avaliação de expressões regulares é um mecanismo importante e computacionalmente intensivo, usado para realizar Deep Packet Inpection, que pode ser acelerado por FPGA para atender aos requisitos de desempenho. Esta solução, no entanto, apresenta novos desafios em relação aos requisitos de confiabilidade. Particularmente para FPGAs baseados em SRAM, soft errors na memória de configuração são uma ameaça de confiabilidade significativa. Neste trabalho, apresentamos um mecanismo de tolerância a falhas abrangente para lidar com falhas de configuração na funcionalidade de módulos de avaliação de expressões regulares baseados em FPGA. Além disso, é introduzido um mecanismo de correção de erros que considera o posicionamento desses módulos no FPGA para reduzir o tempo de reparo do sistema, melhorando a confiabilidade e a disponibilidade. Os resultados experimentais mostram que a taxa de falha geral e o tempo de reparo do sistema podem ser reduzidos em 95% e 90%, respectivamente, com custos de área e performance admissíveis.

Advisors/Committee Members: Nazar, Gabriel Luca.

Subjects/Keywords: Microeletrônica; Field-Programmable Gate Array; Repair Time; Tolerancia : Falhas; Fpga; Fault-Tolerance; Regular Expression Matching; Network Function Virtualization

Record Details Similar Records Cite « Share

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Leipnitz, M. T. (2017). Resilient regular expression matching on FPGAs with fast error repair. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/168788

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Leipnitz, Marcos Tomazzoli. “Resilient regular expression matching on FPGAs with fast error repair.” 2017. Thesis, Universidade do Rio Grande do Sul. Accessed March 02, 2021. http://hdl.handle.net/10183/168788.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Leipnitz, Marcos Tomazzoli. “Resilient regular expression matching on FPGAs with fast error repair.” 2017. Web. 02 Mar 2021.

Vancouver:

Leipnitz MT. Resilient regular expression matching on FPGAs with fast error repair. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2017. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/10183/168788.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Leipnitz MT. Resilient regular expression matching on FPGAs with fast error repair. [Thesis]. Universidade do Rio Grande do Sul; 2017. Available from: http://hdl.handle.net/10183/168788

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

		in
And / Or
		in
And / Or
		in
And / Or
		in

Open Access Theses and Dissertations