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You searched for subject:(Field programmable carbon nanotube array FPCNA ). Showing records 1 – 30 of 29133 total matches.

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University of Illinois – Urbana-Champaign

1. Chilstedt, Scott E. Architecture and CAD for carbon nanomaterial integrated circuits.

Degree: MS, 1200, 2010, University of Illinois – Urbana-Champaign

 The ITRS (International Technology Roadmap for Semiconductors) has recommended that carbon-based transistors be given further study as a potential ???Beyond CMOS??? technology. Unlike traditional devices… (more)

Subjects/Keywords: Carbon Nanotubes; Graphene Nanoribbons; Carbon Nanomaterial Transistors; Nanoelectronic Architectures; Field programmable carbon nanotube array (FPCNA); Variation-Aware CAD; Discretized statistical static timing analysis (SSTA)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chilstedt, S. E. (2010). Architecture and CAD for carbon nanomaterial integrated circuits. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/15969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chilstedt, Scott E. “Architecture and CAD for carbon nanomaterial integrated circuits.” 2010. Thesis, University of Illinois – Urbana-Champaign. Accessed April 01, 2020. http://hdl.handle.net/2142/15969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chilstedt, Scott E. “Architecture and CAD for carbon nanomaterial integrated circuits.” 2010. Web. 01 Apr 2020.

Vancouver:

Chilstedt SE. Architecture and CAD for carbon nanomaterial integrated circuits. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2010. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/2142/15969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chilstedt SE. Architecture and CAD for carbon nanomaterial integrated circuits. [Thesis]. University of Illinois – Urbana-Champaign; 2010. Available from: http://hdl.handle.net/2142/15969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

2. Dong, Chen. Architecture and CAD for nanoscale and 3d FPGA.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

 FPGAs (field programmable gate arrays) are attractive alternatives compared to ASICs (application-specific integrated circuits) for significantly lowering amortized manufacturing costs and dramatically improving design productivity.… (more)

Subjects/Keywords: Field-Programmable Gate Array (FPGA); Carbon Nanotube; 3D Integration; Computer-aided design (CAD); Physical Design

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APA (6th Edition):

Dong, C. (2011). Architecture and CAD for nanoscale and 3d FPGA. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18492

Chicago Manual of Style (16th Edition):

Dong, Chen. “Architecture and CAD for nanoscale and 3d FPGA.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 01, 2020. http://hdl.handle.net/2142/18492.

MLA Handbook (7th Edition):

Dong, Chen. “Architecture and CAD for nanoscale and 3d FPGA.” 2011. Web. 01 Apr 2020.

Vancouver:

Dong C. Architecture and CAD for nanoscale and 3d FPGA. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/2142/18492.

Council of Science Editors:

Dong C. Architecture and CAD for nanoscale and 3d FPGA. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18492


Delft University of Technology

3. Buter, J. Synthesis of a Long Vertically Aligned Carbon Nanotube Array by Chemical Vapour Deposition:.

Degree: 2015, Delft University of Technology

 Although a lot of research has been devoted to the growth of a long Vertically Aligned Carbon Nanotube Array (VANTA), it remains difficult to find… (more)

Subjects/Keywords: CNT; array; forest; carbon; nanotube

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APA (6th Edition):

Buter, J. (2015). Synthesis of a Long Vertically Aligned Carbon Nanotube Array by Chemical Vapour Deposition:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:7d84920d-e0d7-425e-885b-10af7208e9d6

Chicago Manual of Style (16th Edition):

Buter, J. “Synthesis of a Long Vertically Aligned Carbon Nanotube Array by Chemical Vapour Deposition:.” 2015. Masters Thesis, Delft University of Technology. Accessed April 01, 2020. http://resolver.tudelft.nl/uuid:7d84920d-e0d7-425e-885b-10af7208e9d6.

MLA Handbook (7th Edition):

Buter, J. “Synthesis of a Long Vertically Aligned Carbon Nanotube Array by Chemical Vapour Deposition:.” 2015. Web. 01 Apr 2020.

Vancouver:

Buter J. Synthesis of a Long Vertically Aligned Carbon Nanotube Array by Chemical Vapour Deposition:. [Internet] [Masters thesis]. Delft University of Technology; 2015. [cited 2020 Apr 01]. Available from: http://resolver.tudelft.nl/uuid:7d84920d-e0d7-425e-885b-10af7208e9d6.

Council of Science Editors:

Buter J. Synthesis of a Long Vertically Aligned Carbon Nanotube Array by Chemical Vapour Deposition:. [Masters Thesis]. Delft University of Technology; 2015. Available from: http://resolver.tudelft.nl/uuid:7d84920d-e0d7-425e-885b-10af7208e9d6


University of Illinois – Urbana-Champaign

4. Kim, Ji Hun. Optimization of purely semiconducting carbon nanotube complementary field effect transistors.

Degree: MS, 1200, 2013, University of Illinois – Urbana-Champaign

 Among the remarkable variety of semiconducting nanomaterials that have been discovered, single walled carbon nanotubes (SWNTs) have properties that make them uniquely well suited for… (more)

Subjects/Keywords: carbon nanotube; carbon nanotube field-effect transistors

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APA (6th Edition):

Kim, J. H. (2013). Optimization of purely semiconducting carbon nanotube complementary field effect transistors. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/42442

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kim, Ji Hun. “Optimization of purely semiconducting carbon nanotube complementary field effect transistors.” 2013. Thesis, University of Illinois – Urbana-Champaign. Accessed April 01, 2020. http://hdl.handle.net/2142/42442.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kim, Ji Hun. “Optimization of purely semiconducting carbon nanotube complementary field effect transistors.” 2013. Web. 01 Apr 2020.

Vancouver:

Kim JH. Optimization of purely semiconducting carbon nanotube complementary field effect transistors. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2013. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/2142/42442.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim JH. Optimization of purely semiconducting carbon nanotube complementary field effect transistors. [Thesis]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/42442

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brunel University

5. Afandi, Ahmad. Efficient reconfigurable architectures for 3D medical image compression.

Degree: PhD, 2010, Brunel University

 Recently, the more widespread use of three-dimensional (3-D) imaging modalities, such as magnetic resonance imaging (MRI), computed tomography (CT), positron emission tomography (PET), and ultrasound… (more)

Subjects/Keywords: 621.39; Field programmable gate array; Reconfigurable computing

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APA (6th Edition):

Afandi, A. (2010). Efficient reconfigurable architectures for 3D medical image compression. (Doctoral Dissertation). Brunel University. Retrieved from http://bura.brunel.ac.uk/handle/2438/7677 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.582880

Chicago Manual of Style (16th Edition):

Afandi, Ahmad. “Efficient reconfigurable architectures for 3D medical image compression.” 2010. Doctoral Dissertation, Brunel University. Accessed April 01, 2020. http://bura.brunel.ac.uk/handle/2438/7677 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.582880.

MLA Handbook (7th Edition):

Afandi, Ahmad. “Efficient reconfigurable architectures for 3D medical image compression.” 2010. Web. 01 Apr 2020.

Vancouver:

Afandi A. Efficient reconfigurable architectures for 3D medical image compression. [Internet] [Doctoral dissertation]. Brunel University; 2010. [cited 2020 Apr 01]. Available from: http://bura.brunel.ac.uk/handle/2438/7677 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.582880.

Council of Science Editors:

Afandi A. Efficient reconfigurable architectures for 3D medical image compression. [Doctoral Dissertation]. Brunel University; 2010. Available from: http://bura.brunel.ac.uk/handle/2438/7677 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.582880


Cape Peninsula University of Technology

6. Han, Yi. Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology .

Degree: 2008, Cape Peninsula University of Technology

 As one of the biggest developing country in the world, South Africa is developing very fast resent years. The country’s industrialization process is rapidly evolved.… (more)

Subjects/Keywords: Field programmable gate arrays; Array processors; Programmable array logic; Crane operations; MTech

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APA (6th Edition):

Han, Y. (2008). Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology . (Thesis). Cape Peninsula University of Technology. Retrieved from http://etd.cput.ac.za/handle/20.500.11838/1069

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Han, Yi. “Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology .” 2008. Thesis, Cape Peninsula University of Technology. Accessed April 01, 2020. http://etd.cput.ac.za/handle/20.500.11838/1069.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Han, Yi. “Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology .” 2008. Web. 01 Apr 2020.

Vancouver:

Han Y. Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology . [Internet] [Thesis]. Cape Peninsula University of Technology; 2008. [cited 2020 Apr 01]. Available from: http://etd.cput.ac.za/handle/20.500.11838/1069.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Han Y. Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology . [Thesis]. Cape Peninsula University of Technology; 2008. Available from: http://etd.cput.ac.za/handle/20.500.11838/1069

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Wright State University

7. Patel, Jay. GROWTH AND CHARACTERIZATION OF CARBON NANOMATERIALS.

Degree: MS, Physics, 2011, Wright State University

 In this thesis, single and multi-layered graphene films were epitaxially grown on either Si-face or C-face of SiC single crystal substrates. The film growth conditions,… (more)

Subjects/Keywords: Physics; carbon nanotube; field emission; cathode; graphene

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Patel, J. (2011). GROWTH AND CHARACTERIZATION OF CARBON NANOMATERIALS. (Masters Thesis). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1310148312

Chicago Manual of Style (16th Edition):

Patel, Jay. “GROWTH AND CHARACTERIZATION OF CARBON NANOMATERIALS.” 2011. Masters Thesis, Wright State University. Accessed April 01, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=wright1310148312.

MLA Handbook (7th Edition):

Patel, Jay. “GROWTH AND CHARACTERIZATION OF CARBON NANOMATERIALS.” 2011. Web. 01 Apr 2020.

Vancouver:

Patel J. GROWTH AND CHARACTERIZATION OF CARBON NANOMATERIALS. [Internet] [Masters thesis]. Wright State University; 2011. [cited 2020 Apr 01]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1310148312.

Council of Science Editors:

Patel J. GROWTH AND CHARACTERIZATION OF CARBON NANOMATERIALS. [Masters Thesis]. Wright State University; 2011. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1310148312

8. Turki, Mariem. Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform.

Degree: Docteur es, Informatique et Micro-Electronique, 2014, Université Pierre et Marie Curie – Paris VI

De nos jours, la complexité de la conception des circuits intégrés et du logiciel croit régulièrement, faisant croître le besoin de la vérification dans chaque… (more)

Subjects/Keywords: FPGA (Field Programmable Gate Array); Prototypage; Routage; Pathfinder; Itératif; Multiplexage; FPGA (Field Programmable Gate Array); Prototyping; 005.18

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Turki, M. (2014). Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform. (Doctoral Dissertation). Université Pierre et Marie Curie – Paris VI. Retrieved from http://www.theses.fr/2014PA066698

Chicago Manual of Style (16th Edition):

Turki, Mariem. “Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform.” 2014. Doctoral Dissertation, Université Pierre et Marie Curie – Paris VI. Accessed April 01, 2020. http://www.theses.fr/2014PA066698.

MLA Handbook (7th Edition):

Turki, Mariem. “Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform.” 2014. Web. 01 Apr 2020.

Vancouver:

Turki M. Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform. [Internet] [Doctoral dissertation]. Université Pierre et Marie Curie – Paris VI; 2014. [cited 2020 Apr 01]. Available from: http://www.theses.fr/2014PA066698.

Council of Science Editors:

Turki M. Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform. [Doctoral Dissertation]. Université Pierre et Marie Curie – Paris VI; 2014. Available from: http://www.theses.fr/2014PA066698


Ryerson University

9. Oviedo, Alejandro Emerio Alfonso. Autonomous stereo vision system for depth computation of moving object.

Degree: 2017, Ryerson University

 This work targets one real world application of stereo vision technology: the computation of the depth information of a moving object in a scene. It… (more)

Subjects/Keywords: Field programmable gate arrays; Artificial satellites  – Control systems; Programmable array logic; Computer algorithms

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APA (6th Edition):

Oviedo, A. E. A. (2017). Autonomous stereo vision system for depth computation of moving object. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A6669

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Oviedo, Alejandro Emerio Alfonso. “Autonomous stereo vision system for depth computation of moving object.” 2017. Thesis, Ryerson University. Accessed April 01, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A6669.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Oviedo, Alejandro Emerio Alfonso. “Autonomous stereo vision system for depth computation of moving object.” 2017. Web. 01 Apr 2020.

Vancouver:

Oviedo AEA. Autonomous stereo vision system for depth computation of moving object. [Internet] [Thesis]. Ryerson University; 2017. [cited 2020 Apr 01]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6669.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Oviedo AEA. Autonomous stereo vision system for depth computation of moving object. [Thesis]. Ryerson University; 2017. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6669

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Central Florida

10. Kang, Narae. The Effect Of Carbon Nanotube/organic Semiconductor Interfacial Area On The Performance Of Organic Transistors.

Degree: 2012, University of Central Florida

 Organic field-effect transistors (OFETs) have attracted tremendous attention due to their flexibility, transparency, easy processiblity and low cost of fabrication. High-performance OFETs are required for… (more)

Subjects/Keywords: Organic field effect transistors; carbon nanotube electrode; pentacene; aligned array; solution processed; dielectrophoresis; interfacial area; interfacial barrier; Physics; Dissertations, Academic  – Sciences, Sciences  – Dissertations, Academic

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APA (6th Edition):

Kang, N. (2012). The Effect Of Carbon Nanotube/organic Semiconductor Interfacial Area On The Performance Of Organic Transistors. (Masters Thesis). University of Central Florida. Retrieved from https://stars.library.ucf.edu/etd/2497

Chicago Manual of Style (16th Edition):

Kang, Narae. “The Effect Of Carbon Nanotube/organic Semiconductor Interfacial Area On The Performance Of Organic Transistors.” 2012. Masters Thesis, University of Central Florida. Accessed April 01, 2020. https://stars.library.ucf.edu/etd/2497.

MLA Handbook (7th Edition):

Kang, Narae. “The Effect Of Carbon Nanotube/organic Semiconductor Interfacial Area On The Performance Of Organic Transistors.” 2012. Web. 01 Apr 2020.

Vancouver:

Kang N. The Effect Of Carbon Nanotube/organic Semiconductor Interfacial Area On The Performance Of Organic Transistors. [Internet] [Masters thesis]. University of Central Florida; 2012. [cited 2020 Apr 01]. Available from: https://stars.library.ucf.edu/etd/2497.

Council of Science Editors:

Kang N. The Effect Of Carbon Nanotube/organic Semiconductor Interfacial Area On The Performance Of Organic Transistors. [Masters Thesis]. University of Central Florida; 2012. Available from: https://stars.library.ucf.edu/etd/2497


Universidade Estadual de Campinas

11. Monte, Luis Renato. Especificação do nucleo de processamento para rede de chaveamento de rajadas opticas .

Degree: 2009, Universidade Estadual de Campinas

 Resumo: Este trabalho apresenta as especificações arquitetônicas e funcionais de uma rede ótica avançada, fundamentada na comutação óptica de rajadas e que objetiva um melhor… (more)

Subjects/Keywords: Fibras óticas; Comunicações óticas; Chaveamento ótico; FPGA (Field Programmable Gate Array)

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APA (6th Edition):

Monte, L. R. (2009). Especificação do nucleo de processamento para rede de chaveamento de rajadas opticas . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/259738

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Monte, Luis Renato. “Especificação do nucleo de processamento para rede de chaveamento de rajadas opticas .” 2009. Thesis, Universidade Estadual de Campinas. Accessed April 01, 2020. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259738.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Monte, Luis Renato. “Especificação do nucleo de processamento para rede de chaveamento de rajadas opticas .” 2009. Web. 01 Apr 2020.

Vancouver:

Monte LR. Especificação do nucleo de processamento para rede de chaveamento de rajadas opticas . [Internet] [Thesis]. Universidade Estadual de Campinas; 2009. [cited 2020 Apr 01]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/259738.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Monte LR. Especificação do nucleo de processamento para rede de chaveamento de rajadas opticas . [Thesis]. Universidade Estadual de Campinas; 2009. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/259738

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Victoria University of Wellington

12. Ang, Andrew. Development of an Open PXIe System based on FPGA Modules.

Degree: 2018, Victoria University of Wellington

 PXIe is a instrumentation platform that is used as the basis for developing test equipment, modular electronic instruments and automated test systems. A typical PXIe… (more)

Subjects/Keywords: FPGA; PXIe; Electronics; PCI eXtensions for Instrumentation; Field Programmable Gate Array

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APA (6th Edition):

Ang, A. (2018). Development of an Open PXIe System based on FPGA Modules. (Masters Thesis). Victoria University of Wellington. Retrieved from http://hdl.handle.net/10063/7653

Chicago Manual of Style (16th Edition):

Ang, Andrew. “Development of an Open PXIe System based on FPGA Modules.” 2018. Masters Thesis, Victoria University of Wellington. Accessed April 01, 2020. http://hdl.handle.net/10063/7653.

MLA Handbook (7th Edition):

Ang, Andrew. “Development of an Open PXIe System based on FPGA Modules.” 2018. Web. 01 Apr 2020.

Vancouver:

Ang A. Development of an Open PXIe System based on FPGA Modules. [Internet] [Masters thesis]. Victoria University of Wellington; 2018. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10063/7653.

Council of Science Editors:

Ang A. Development of an Open PXIe System based on FPGA Modules. [Masters Thesis]. Victoria University of Wellington; 2018. Available from: http://hdl.handle.net/10063/7653


Universidade Estadual de Campinas

13. Almeida, Carlos Caetano de, 1976-. Arquitetura do módulo de convolução para visão computacional baseada em FPGA .

Degree: 2015, Universidade Estadual de Campinas

 Resumo: Esta dissertação apresenta o estudo de uma arquitetura para o processamento digital de imagens, desenvolvido através de dispositivos de hardware programável, no caso FPGA,… (more)

Subjects/Keywords: Processamento de imagens; Visão por computador; FPGA (Field Programmable Gate Array)

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APA (6th Edition):

Almeida, Carlos Caetano de, 1. (2015). Arquitetura do módulo de convolução para visão computacional baseada em FPGA . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/265780

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Almeida, Carlos Caetano de, 1976-. “Arquitetura do módulo de convolução para visão computacional baseada em FPGA .” 2015. Thesis, Universidade Estadual de Campinas. Accessed April 01, 2020. http://repositorio.unicamp.br/jspui/handle/REPOSIP/265780.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Almeida, Carlos Caetano de, 1976-. “Arquitetura do módulo de convolução para visão computacional baseada em FPGA .” 2015. Web. 01 Apr 2020.

Vancouver:

Almeida, Carlos Caetano de 1. Arquitetura do módulo de convolução para visão computacional baseada em FPGA . [Internet] [Thesis]. Universidade Estadual de Campinas; 2015. [cited 2020 Apr 01]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/265780.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Almeida, Carlos Caetano de 1. Arquitetura do módulo de convolução para visão computacional baseada em FPGA . [Thesis]. Universidade Estadual de Campinas; 2015. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/265780

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Estadual de Campinas

14. Américo Filho, Júlio Cesar Soares, 1987-. Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128 .

Degree: 2016, Universidade Estadual de Campinas

 Resumo: Neste trabalho, propõe-se uma arquitetura de hardware para um co-processador capaz de realizar encriptação e decriptação segundo o padrão AES-128 com suporte aos modos… (more)

Subjects/Keywords: Algoritmos; Hardware - Arquitetura; Computadores canalizados; Criptografia; FPGA (Field Programmable Gate Array)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Américo Filho, Júlio Cesar Soares, 1. (2016). Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128 . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/321942

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Américo Filho, Júlio Cesar Soares, 1987-. “Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128 .” 2016. Thesis, Universidade Estadual de Campinas. Accessed April 01, 2020. http://repositorio.unicamp.br/jspui/handle/REPOSIP/321942.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Américo Filho, Júlio Cesar Soares, 1987-. “Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128 .” 2016. Web. 01 Apr 2020.

Vancouver:

Américo Filho, Júlio Cesar Soares 1. Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128 . [Internet] [Thesis]. Universidade Estadual de Campinas; 2016. [cited 2020 Apr 01]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/321942.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Américo Filho, Júlio Cesar Soares 1. Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128 . [Thesis]. Universidade Estadual de Campinas; 2016. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/321942

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Estadual de Campinas

15. Moreira, Veruska Rodrigues. Plataforma em hardware reconfiguravel para o ensino e pesquisa em laboratorio de sistemas digitais a distancia .

Degree: 2009, Universidade Estadual de Campinas

 Resumo: Esta dissertação apresenta a concepção e o desenvolvimento de uma plataforma em hardware reconfigurável denominada REDLART - REconfigurable Digital Laboratory for Advanced Research and… (more)

Subjects/Keywords: Ensino a distância; FPGA (Field Programmable Gate Array); Serviços na Web

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Moreira, V. R. (2009). Plataforma em hardware reconfiguravel para o ensino e pesquisa em laboratorio de sistemas digitais a distancia . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/258897

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Moreira, Veruska Rodrigues. “Plataforma em hardware reconfiguravel para o ensino e pesquisa em laboratorio de sistemas digitais a distancia .” 2009. Thesis, Universidade Estadual de Campinas. Accessed April 01, 2020. http://repositorio.unicamp.br/jspui/handle/REPOSIP/258897.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Moreira, Veruska Rodrigues. “Plataforma em hardware reconfiguravel para o ensino e pesquisa em laboratorio de sistemas digitais a distancia .” 2009. Web. 01 Apr 2020.

Vancouver:

Moreira VR. Plataforma em hardware reconfiguravel para o ensino e pesquisa em laboratorio de sistemas digitais a distancia . [Internet] [Thesis]. Universidade Estadual de Campinas; 2009. [cited 2020 Apr 01]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/258897.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Moreira VR. Plataforma em hardware reconfiguravel para o ensino e pesquisa em laboratorio de sistemas digitais a distancia . [Thesis]. Universidade Estadual de Campinas; 2009. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/258897

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

16. Rajeswari P. An FPGA based architecture for real Time network traffic analysis;.

Degree: An FPGA based architecture for real Time network traffic analysis, 2015, Anna University

The Internet is persistently expanding in all dimensions and evolving newlineinto a global communications medium consisting of heterogeneously interconnected newlinesystems and carrying an increasing mix… (more)

Subjects/Keywords: Field Programmable Gate Array; Network monitoring and traffic

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

P, R. (2015). An FPGA based architecture for real Time network traffic analysis;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/39198

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

P, Rajeswari. “An FPGA based architecture for real Time network traffic analysis;.” 2015. Thesis, Anna University. Accessed April 01, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/39198.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

P, Rajeswari. “An FPGA based architecture for real Time network traffic analysis;.” 2015. Web. 01 Apr 2020.

Vancouver:

P R. An FPGA based architecture for real Time network traffic analysis;. [Internet] [Thesis]. Anna University; 2015. [cited 2020 Apr 01]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/39198.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

P R. An FPGA based architecture for real Time network traffic analysis;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/39198

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

17. Jayanthi, V E. Design and implementation of vlsi Architecture algorithms for digital Image watermarking; -.

Degree: Information and Communication Engineering, 2014, Anna University

Nowadays digital documents can be distributed through the World newlineWide Web to a large number of people in a cost efficient way The increasing newlineimportance… (more)

Subjects/Keywords: Digital Image watermarking; Field Programmable Gate Array; Information hiding Watermarking technology

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jayanthi, V. E. (2014). Design and implementation of vlsi Architecture algorithms for digital Image watermarking; -. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/24741

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jayanthi, V E. “Design and implementation of vlsi Architecture algorithms for digital Image watermarking; -.” 2014. Thesis, Anna University. Accessed April 01, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/24741.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jayanthi, V E. “Design and implementation of vlsi Architecture algorithms for digital Image watermarking; -.” 2014. Web. 01 Apr 2020.

Vancouver:

Jayanthi VE. Design and implementation of vlsi Architecture algorithms for digital Image watermarking; -. [Internet] [Thesis]. Anna University; 2014. [cited 2020 Apr 01]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/24741.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jayanthi VE. Design and implementation of vlsi Architecture algorithms for digital Image watermarking; -. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/24741

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Addis Ababa University

18. Misiker, Tadesse. HIGH PERFORMANCE AUTOMATIC TARGET RECOGNITION .

Degree: 2013, Addis Ababa University

 Designing a vision system, which was motivated by that of the human eye, has been done since the introduction of digital computing devices. Due to… (more)

Subjects/Keywords: AUTOMATIC TARGET RECOGNITION; Field Programmable Gate Array; Graphics Processing Unit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Misiker, T. (2013). HIGH PERFORMANCE AUTOMATIC TARGET RECOGNITION . (Thesis). Addis Ababa University. Retrieved from http://etd.aau.edu.et/dspace/handle/123456789/4503

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Misiker, Tadesse. “HIGH PERFORMANCE AUTOMATIC TARGET RECOGNITION .” 2013. Thesis, Addis Ababa University. Accessed April 01, 2020. http://etd.aau.edu.et/dspace/handle/123456789/4503.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Misiker, Tadesse. “HIGH PERFORMANCE AUTOMATIC TARGET RECOGNITION .” 2013. Web. 01 Apr 2020.

Vancouver:

Misiker T. HIGH PERFORMANCE AUTOMATIC TARGET RECOGNITION . [Internet] [Thesis]. Addis Ababa University; 2013. [cited 2020 Apr 01]. Available from: http://etd.aau.edu.et/dspace/handle/123456789/4503.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Misiker T. HIGH PERFORMANCE AUTOMATIC TARGET RECOGNITION . [Thesis]. Addis Ababa University; 2013. Available from: http://etd.aau.edu.et/dspace/handle/123456789/4503

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Heyse, Stefan. Post quantum cryptography : implementing alternative public key schemes of embedded devices ; preparing for the rise of quantum computers.

Degree: 2013, Ruhr Universität Bochum

 In dieser Arbeit diskutieren wir neue Primitiven für Public-Key-Kryptographie, die sich als Alternativen zu den derzeit verwendeten RSA und ECC Kryptosystemen etablieren könnten. Die Analyse… (more)

Subjects/Keywords: Integrierte Software; Public-Key-Kryptosystem; Codierung; Field programmable gate array; Mikrokontroller

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APA (6th Edition):

Heyse, S. (2013). Post quantum cryptography : implementing alternative public key schemes of embedded devices ; preparing for the rise of quantum computers. (Thesis). Ruhr Universität Bochum. Retrieved from http://nbn-resolving.de/urn/resolver.pl?urn=urn:nbn:de:hbz:294-40373

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Heyse, Stefan. “Post quantum cryptography : implementing alternative public key schemes of embedded devices ; preparing for the rise of quantum computers.” 2013. Thesis, Ruhr Universität Bochum. Accessed April 01, 2020. http://nbn-resolving.de/urn/resolver.pl?urn=urn:nbn:de:hbz:294-40373.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Heyse, Stefan. “Post quantum cryptography : implementing alternative public key schemes of embedded devices ; preparing for the rise of quantum computers.” 2013. Web. 01 Apr 2020.

Vancouver:

Heyse S. Post quantum cryptography : implementing alternative public key schemes of embedded devices ; preparing for the rise of quantum computers. [Internet] [Thesis]. Ruhr Universität Bochum; 2013. [cited 2020 Apr 01]. Available from: http://nbn-resolving.de/urn/resolver.pl?urn=urn:nbn:de:hbz:294-40373.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Heyse S. Post quantum cryptography : implementing alternative public key schemes of embedded devices ; preparing for the rise of quantum computers. [Thesis]. Ruhr Universität Bochum; 2013. Available from: http://nbn-resolving.de/urn/resolver.pl?urn=urn:nbn:de:hbz:294-40373

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

20. Leiva Cochachin, Andrés Mijail. Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA.

Degree: 2012, Universidad Nacional de Ingeniería

 En la presente tesis se explica la metodología utilizada en el diseño e implementación de una solución integral (un módulo de captura de paquetes IP… (more)

Subjects/Keywords: Red Ethernet; Módulo de captura; FPGA (Field Programmable Gate Array)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Leiva Cochachin, A. M. (2012). Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA. (Thesis). Universidad Nacional de Ingeniería. Retrieved from http://cybertesis.uni.edu.pe/handle/uni/1325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Leiva Cochachin, Andrés Mijail. “Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA.” 2012. Thesis, Universidad Nacional de Ingeniería. Accessed April 01, 2020. http://cybertesis.uni.edu.pe/handle/uni/1325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Leiva Cochachin, Andrés Mijail. “Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA.” 2012. Web. 01 Apr 2020.

Vancouver:

Leiva Cochachin AM. Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA. [Internet] [Thesis]. Universidad Nacional de Ingeniería; 2012. [cited 2020 Apr 01]. Available from: http://cybertesis.uni.edu.pe/handle/uni/1325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Leiva Cochachin AM. Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA. [Thesis]. Universidad Nacional de Ingeniería; 2012. Available from: http://cybertesis.uni.edu.pe/handle/uni/1325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


McMaster University

21. Zuzarte, Marvin. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.

Degree: MASc, 2014, McMaster University

Safety and mission critical systems are currently deployed in many different fields where there is a greater presence of high energy particles (e.g. aerospace). The… (more)

Subjects/Keywords: FPGA; Fault injection; Field programmable gate array; runtime; soft error

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zuzarte, M. (2014). A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. (Masters Thesis). McMaster University. Retrieved from http://hdl.handle.net/11375/16500

Chicago Manual of Style (16th Edition):

Zuzarte, Marvin. “A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.” 2014. Masters Thesis, McMaster University. Accessed April 01, 2020. http://hdl.handle.net/11375/16500.

MLA Handbook (7th Edition):

Zuzarte, Marvin. “A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.” 2014. Web. 01 Apr 2020.

Vancouver:

Zuzarte M. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. [Internet] [Masters thesis]. McMaster University; 2014. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/11375/16500.

Council of Science Editors:

Zuzarte M. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. [Masters Thesis]. McMaster University; 2014. Available from: http://hdl.handle.net/11375/16500


Bucknell University

22. Su, Juliana. Design and Development of an FPGA-based Distributed Computing Processing Platform.

Degree: 2011, Bucknell University

 This thesis presents two frameworks- a software framework and a hardware core manager framework- which, together, can be used to develop a processing platform using… (more)

Subjects/Keywords: field-programmable gate array; FPGA; distributed computing; reconfigurable computing; processing platform

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APA (6th Edition):

Su, J. (2011). Design and Development of an FPGA-based Distributed Computing Processing Platform. (Thesis). Bucknell University. Retrieved from https://digitalcommons.bucknell.edu/masters_theses/38

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Su, Juliana. “Design and Development of an FPGA-based Distributed Computing Processing Platform.” 2011. Thesis, Bucknell University. Accessed April 01, 2020. https://digitalcommons.bucknell.edu/masters_theses/38.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Su, Juliana. “Design and Development of an FPGA-based Distributed Computing Processing Platform.” 2011. Web. 01 Apr 2020.

Vancouver:

Su J. Design and Development of an FPGA-based Distributed Computing Processing Platform. [Internet] [Thesis]. Bucknell University; 2011. [cited 2020 Apr 01]. Available from: https://digitalcommons.bucknell.edu/masters_theses/38.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Su J. Design and Development of an FPGA-based Distributed Computing Processing Platform. [Thesis]. Bucknell University; 2011. Available from: https://digitalcommons.bucknell.edu/masters_theses/38

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

23. Tai, Justin Isaiah. High-level Synthesis of Datacenter Services.

Degree: 2017, University of Toronto

Field programmable gate arrays have become of great interest for implementing datacenter applications due to high performance gains over traditional compute hardware at a fraction… (more)

Subjects/Keywords: Datacenter; Field Programmable Gate Array; High-Level Synthesis; 0464

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APA (6th Edition):

Tai, J. I. (2017). High-level Synthesis of Datacenter Services. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/76671

Chicago Manual of Style (16th Edition):

Tai, Justin Isaiah. “High-level Synthesis of Datacenter Services.” 2017. Masters Thesis, University of Toronto. Accessed April 01, 2020. http://hdl.handle.net/1807/76671.

MLA Handbook (7th Edition):

Tai, Justin Isaiah. “High-level Synthesis of Datacenter Services.” 2017. Web. 01 Apr 2020.

Vancouver:

Tai JI. High-level Synthesis of Datacenter Services. [Internet] [Masters thesis]. University of Toronto; 2017. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1807/76671.

Council of Science Editors:

Tai JI. High-level Synthesis of Datacenter Services. [Masters Thesis]. University of Toronto; 2017. Available from: http://hdl.handle.net/1807/76671


University of Illinois – Chicago

24. Mastinu, Matteo. Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures.

Degree: 2013, University of Illinois – Chicago

 This work addresses the Maxeler Technologies Ltd. platforms, and the principal goal of this work is to design a new methodology to support Partial Reconfiguration… (more)

Subjects/Keywords: Maxeler; Field-Programmable Gate Array (FPGA); Partial Reconfiguration

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APA (6th Edition):

Mastinu, M. (2013). Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/10018

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mastinu, Matteo. “Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures.” 2013. Thesis, University of Illinois – Chicago. Accessed April 01, 2020. http://hdl.handle.net/10027/10018.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mastinu, Matteo. “Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures.” 2013. Web. 01 Apr 2020.

Vancouver:

Mastinu M. Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures. [Internet] [Thesis]. University of Illinois – Chicago; 2013. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10027/10018.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mastinu M. Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures. [Thesis]. University of Illinois – Chicago; 2013. Available from: http://hdl.handle.net/10027/10018

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

25. Mayekar, Pallavi Avinash. Design and Verification of a DFI-AXI DDR4 Memory PHY Bridge Suitable for FPGA Based RTL Emulation and Prototyping.

Degree: MS, Electrical Engineering, 2019, Rochester Institute of Technology

  System on chip (SoC) designers today are emphasizing on a process which can ensure robust silicon at the first tape-out. Given the complexity of… (more)

Subjects/Keywords: DDR; Emulation; Field programmable gate array; Hardware design languages; Prototypes; SDRAM

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APA (6th Edition):

Mayekar, P. A. (2019). Design and Verification of a DFI-AXI DDR4 Memory PHY Bridge Suitable for FPGA Based RTL Emulation and Prototyping. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10157

Chicago Manual of Style (16th Edition):

Mayekar, Pallavi Avinash. “Design and Verification of a DFI-AXI DDR4 Memory PHY Bridge Suitable for FPGA Based RTL Emulation and Prototyping.” 2019. Masters Thesis, Rochester Institute of Technology. Accessed April 01, 2020. https://scholarworks.rit.edu/theses/10157.

MLA Handbook (7th Edition):

Mayekar, Pallavi Avinash. “Design and Verification of a DFI-AXI DDR4 Memory PHY Bridge Suitable for FPGA Based RTL Emulation and Prototyping.” 2019. Web. 01 Apr 2020.

Vancouver:

Mayekar PA. Design and Verification of a DFI-AXI DDR4 Memory PHY Bridge Suitable for FPGA Based RTL Emulation and Prototyping. [Internet] [Masters thesis]. Rochester Institute of Technology; 2019. [cited 2020 Apr 01]. Available from: https://scholarworks.rit.edu/theses/10157.

Council of Science Editors:

Mayekar PA. Design and Verification of a DFI-AXI DDR4 Memory PHY Bridge Suitable for FPGA Based RTL Emulation and Prototyping. [Masters Thesis]. Rochester Institute of Technology; 2019. Available from: https://scholarworks.rit.edu/theses/10157

26. Jadeglans, Tim. FPGA-implementation av ett neuralt nätverk .

Degree: Chalmers tekniska högskola / Institutionen för data och informationsvetenskap, 2019, Chalmers University of Technology

 Image recognition is a quickly growing field where convolutional neural networks, CNN, are in the bleeding edge. Today fast GPUs are used which consume a… (more)

Subjects/Keywords: Convolutional Neural Network; CNN; Field Programmable Gate Array; FPGA; Image Recognition

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jadeglans, T. (2019). FPGA-implementation av ett neuralt nätverk . (Thesis). Chalmers University of Technology. Retrieved from http://hdl.handle.net/20.500.12380/300036

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jadeglans, Tim. “FPGA-implementation av ett neuralt nätverk .” 2019. Thesis, Chalmers University of Technology. Accessed April 01, 2020. http://hdl.handle.net/20.500.12380/300036.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jadeglans, Tim. “FPGA-implementation av ett neuralt nätverk .” 2019. Web. 01 Apr 2020.

Vancouver:

Jadeglans T. FPGA-implementation av ett neuralt nätverk . [Internet] [Thesis]. Chalmers University of Technology; 2019. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/20.500.12380/300036.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jadeglans T. FPGA-implementation av ett neuralt nätverk . [Thesis]. Chalmers University of Technology; 2019. Available from: http://hdl.handle.net/20.500.12380/300036

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

27. Nease, Stephen H. Neural and analog computation on reconfigurable mixed-signal platforms.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 This work addresses neural and analog computation on reconfigurable mixed-signal platforms. Many engineered systems could gain tremendous benefits by emulating neural systems. For example, neural… (more)

Subjects/Keywords: Neuromorphic; Field programmable analog array; Analog signal processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nease, S. H. (2014). Neural and analog computation on reconfigurable mixed-signal platforms. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53999

Chicago Manual of Style (16th Edition):

Nease, Stephen H. “Neural and analog computation on reconfigurable mixed-signal platforms.” 2014. Doctoral Dissertation, Georgia Tech. Accessed April 01, 2020. http://hdl.handle.net/1853/53999.

MLA Handbook (7th Edition):

Nease, Stephen H. “Neural and analog computation on reconfigurable mixed-signal platforms.” 2014. Web. 01 Apr 2020.

Vancouver:

Nease SH. Neural and analog computation on reconfigurable mixed-signal platforms. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1853/53999.

Council of Science Editors:

Nease SH. Neural and analog computation on reconfigurable mixed-signal platforms. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/53999


Georgia Tech

28. Kim, Sihwan. Low power mixed signal system design environment using floating-gate FPAAs.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The objective of this research is to create a low-power mixed-signal system design environment using FG FPAAs. To achieve this, my research focused on implementing… (more)

Subjects/Keywords: Floating-gate; FG; Field programmable analog array (FPAA)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, S. (2018). Low power mixed signal system design environment using floating-gate FPAAs. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59923

Chicago Manual of Style (16th Edition):

Kim, Sihwan. “Low power mixed signal system design environment using floating-gate FPAAs.” 2018. Doctoral Dissertation, Georgia Tech. Accessed April 01, 2020. http://hdl.handle.net/1853/59923.

MLA Handbook (7th Edition):

Kim, Sihwan. “Low power mixed signal system design environment using floating-gate FPAAs.” 2018. Web. 01 Apr 2020.

Vancouver:

Kim S. Low power mixed signal system design environment using floating-gate FPAAs. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1853/59923.

Council of Science Editors:

Kim S. Low power mixed signal system design environment using floating-gate FPAAs. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59923


University of Toronto

29. Yazdanshenas, Sadegh. Datacenter-optimized FPGAs.

Degree: PhD, 2019, University of Toronto

 Large-scale deployment of field-programmable gate arrays (FPGAs) into datacenters has introduced new use cases that utilize the FPGA as a multi-user compute platform, require more… (more)

Subjects/Keywords: Datacenter; Field-programmable Gate Array; FPGA Architecture; 0464

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yazdanshenas, S. (2019). Datacenter-optimized FPGAs. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/97003

Chicago Manual of Style (16th Edition):

Yazdanshenas, Sadegh. “Datacenter-optimized FPGAs.” 2019. Doctoral Dissertation, University of Toronto. Accessed April 01, 2020. http://hdl.handle.net/1807/97003.

MLA Handbook (7th Edition):

Yazdanshenas, Sadegh. “Datacenter-optimized FPGAs.” 2019. Web. 01 Apr 2020.

Vancouver:

Yazdanshenas S. Datacenter-optimized FPGAs. [Internet] [Doctoral dissertation]. University of Toronto; 2019. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1807/97003.

Council of Science Editors:

Yazdanshenas S. Datacenter-optimized FPGAs. [Doctoral Dissertation]. University of Toronto; 2019. Available from: http://hdl.handle.net/1807/97003


University of Illinois – Urbana-Champaign

30. Tolar, Jacob. A directory enhanced network on chip for FPGA.

Degree: MS, 1200, 2013, University of Illinois – Urbana-Champaign

 This thesis presents and evaluates a directory enhanced network on chip for FPGA, with the goal of improving the performance of cores generated by FCUDA,… (more)

Subjects/Keywords: Network on Chip; Field-Programmable Gate Array (FPGA); FCUDA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tolar, J. (2013). A directory enhanced network on chip for FPGA. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/44439

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tolar, Jacob. “A directory enhanced network on chip for FPGA.” 2013. Thesis, University of Illinois – Urbana-Champaign. Accessed April 01, 2020. http://hdl.handle.net/2142/44439.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tolar, Jacob. “A directory enhanced network on chip for FPGA.” 2013. Web. 01 Apr 2020.

Vancouver:

Tolar J. A directory enhanced network on chip for FPGA. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2013. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/2142/44439.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tolar J. A directory enhanced network on chip for FPGA. [Thesis]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/44439

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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