Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(Field Programmable Gate Arrays). Showing records 1 – 30 of 13872 total matches.

[1] [2] [3] [4] [5] … [463]

Search Limiters

Last 2 Years | English Only

Degrees

Languages

Country

▼ Search Limiters


University of Hong Kong

1. Liu, Cheng. QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay.

Degree: PhD, 2015, University of Hong Kong

The use of FPGAs as accelerators for compute-intensive loops has been demonstrated by numerous researchers as an effective solution to meet both the performance and… (more)

Subjects/Keywords: Field programmable gate arrays

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, C. (2015). QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay. (Doctoral Dissertation). University of Hong Kong. Retrieved from Liu, C. [刘成]. (2015). QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5760939 ; http://hdl.handle.net/10722/226764

Chicago Manual of Style (16th Edition):

Liu, Cheng. “QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay.” 2015. Doctoral Dissertation, University of Hong Kong. Accessed February 21, 2020. Liu, C. [刘成]. (2015). QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5760939 ; http://hdl.handle.net/10722/226764.

MLA Handbook (7th Edition):

Liu, Cheng. “QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay.” 2015. Web. 21 Feb 2020.

Vancouver:

Liu C. QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay. [Internet] [Doctoral dissertation]. University of Hong Kong; 2015. [cited 2020 Feb 21]. Available from: Liu, C. [刘成]. (2015). QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5760939 ; http://hdl.handle.net/10722/226764.

Council of Science Editors:

Liu C. QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay. [Doctoral Dissertation]. University of Hong Kong; 2015. Available from: Liu, C. [刘成]. (2015). QuickDough : a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5760939 ; http://hdl.handle.net/10722/226764


University of Hong Kong

2. Ng, Ho-cheung. A soft processor overlay with tightly-coupled FPGA accelerator.

Degree: M. Phil., 2015, University of Hong Kong

FPGA overlays have shown the potential to improve designers’ productivity through balancing flexibility and ease of configuration of the underlying fabric while maintaining considerable overall… (more)

Subjects/Keywords: Field programmable gate arrays

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ng, H. (2015). A soft processor overlay with tightly-coupled FPGA accelerator. (Masters Thesis). University of Hong Kong. Retrieved from Ng, H. [吳浩彰]. (2015). A soft processor overlay with tightly-coupled FPGA accelerator. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5760970 ; http://hdl.handle.net/10722/226791

Chicago Manual of Style (16th Edition):

Ng, Ho-cheung. “A soft processor overlay with tightly-coupled FPGA accelerator.” 2015. Masters Thesis, University of Hong Kong. Accessed February 21, 2020. Ng, H. [吳浩彰]. (2015). A soft processor overlay with tightly-coupled FPGA accelerator. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5760970 ; http://hdl.handle.net/10722/226791.

MLA Handbook (7th Edition):

Ng, Ho-cheung. “A soft processor overlay with tightly-coupled FPGA accelerator.” 2015. Web. 21 Feb 2020.

Vancouver:

Ng H. A soft processor overlay with tightly-coupled FPGA accelerator. [Internet] [Masters thesis]. University of Hong Kong; 2015. [cited 2020 Feb 21]. Available from: Ng, H. [吳浩彰]. (2015). A soft processor overlay with tightly-coupled FPGA accelerator. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5760970 ; http://hdl.handle.net/10722/226791.

Council of Science Editors:

Ng H. A soft processor overlay with tightly-coupled FPGA accelerator. [Masters Thesis]. University of Hong Kong; 2015. Available from: Ng, H. [吳浩彰]. (2015). A soft processor overlay with tightly-coupled FPGA accelerator. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5760970 ; http://hdl.handle.net/10722/226791


University of Hong Kong

3. 林郁.; Lin, Yu, Colin. ArchSyn: an energy-efficient FPGA high-level synthesizer.

Degree: PhD, 2012, University of Hong Kong

 Due to their high potential performance and reduced energy and power consumption, field-programmable gate arrays (FPGAs) are widely used as accelerators for today’s computationally intensive… (more)

Subjects/Keywords: Field programmable gate arrays.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

林郁.; Lin, Yu, C. (2012). ArchSyn: an energy-efficient FPGA high-level synthesizer. (Doctoral Dissertation). University of Hong Kong. Retrieved from Lin, Y. C. [林郁]. (2012). ArchSyn : an energy-efficient FPGA high-level synthesizer. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4979959 ; http://dx.doi.org/10.5353/th_b4979959 ; http://hdl.handle.net/10722/181525

Chicago Manual of Style (16th Edition):

林郁.; Lin, Yu, Colin. “ArchSyn: an energy-efficient FPGA high-level synthesizer.” 2012. Doctoral Dissertation, University of Hong Kong. Accessed February 21, 2020. Lin, Y. C. [林郁]. (2012). ArchSyn : an energy-efficient FPGA high-level synthesizer. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4979959 ; http://dx.doi.org/10.5353/th_b4979959 ; http://hdl.handle.net/10722/181525.

MLA Handbook (7th Edition):

林郁.; Lin, Yu, Colin. “ArchSyn: an energy-efficient FPGA high-level synthesizer.” 2012. Web. 21 Feb 2020.

Vancouver:

林郁.; Lin, Yu C. ArchSyn: an energy-efficient FPGA high-level synthesizer. [Internet] [Doctoral dissertation]. University of Hong Kong; 2012. [cited 2020 Feb 21]. Available from: Lin, Y. C. [林郁]. (2012). ArchSyn : an energy-efficient FPGA high-level synthesizer. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4979959 ; http://dx.doi.org/10.5353/th_b4979959 ; http://hdl.handle.net/10722/181525.

Council of Science Editors:

林郁.; Lin, Yu C. ArchSyn: an energy-efficient FPGA high-level synthesizer. [Doctoral Dissertation]. University of Hong Kong; 2012. Available from: Lin, Y. C. [林郁]. (2012). ArchSyn : an energy-efficient FPGA high-level synthesizer. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4979959 ; http://dx.doi.org/10.5353/th_b4979959 ; http://hdl.handle.net/10722/181525


Oregon State University

4. Zhao, Yichen. Design and FPGA implementation of digital transmission over severe ISI channels.

Degree: MS, Electrical and Computer Engineering, 2013, Oregon State University

 Inter-symbol interference is one of the major factors that make the realization of high-data-rate digital communications system complex. Current designs face two main challenges: how… (more)

Subjects/Keywords: ISI; Field programmable gate arrays

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhao, Y. (2013). Design and FPGA implementation of digital transmission over severe ISI channels. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/39400

Chicago Manual of Style (16th Edition):

Zhao, Yichen. “Design and FPGA implementation of digital transmission over severe ISI channels.” 2013. Masters Thesis, Oregon State University. Accessed February 21, 2020. http://hdl.handle.net/1957/39400.

MLA Handbook (7th Edition):

Zhao, Yichen. “Design and FPGA implementation of digital transmission over severe ISI channels.” 2013. Web. 21 Feb 2020.

Vancouver:

Zhao Y. Design and FPGA implementation of digital transmission over severe ISI channels. [Internet] [Masters thesis]. Oregon State University; 2013. [cited 2020 Feb 21]. Available from: http://hdl.handle.net/1957/39400.

Council of Science Editors:

Zhao Y. Design and FPGA implementation of digital transmission over severe ISI channels. [Masters Thesis]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/39400


Nelson Mandela Metropolitan University

5. Potgieter, Juan-Pierre. Single event upset testing of flash based field programmable gate arrays.

Degree: Faculty of Engineering, the Built Environment and Information Technology, 2015, Nelson Mandela Metropolitan University

 In the last 50 years microelectronics have advanced at an exponential rate, causing microelectronic devices to shrink, have very low operating voltages and increased complexities;… (more)

Subjects/Keywords: Field programmable gate arrays

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Potgieter, J. (2015). Single event upset testing of flash based field programmable gate arrays. (Thesis). Nelson Mandela Metropolitan University. Retrieved from http://hdl.handle.net/10948/12520

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Potgieter, Juan-Pierre. “Single event upset testing of flash based field programmable gate arrays.” 2015. Thesis, Nelson Mandela Metropolitan University. Accessed February 21, 2020. http://hdl.handle.net/10948/12520.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Potgieter, Juan-Pierre. “Single event upset testing of flash based field programmable gate arrays.” 2015. Web. 21 Feb 2020.

Vancouver:

Potgieter J. Single event upset testing of flash based field programmable gate arrays. [Internet] [Thesis]. Nelson Mandela Metropolitan University; 2015. [cited 2020 Feb 21]. Available from: http://hdl.handle.net/10948/12520.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Potgieter J. Single event upset testing of flash based field programmable gate arrays. [Thesis]. Nelson Mandela Metropolitan University; 2015. Available from: http://hdl.handle.net/10948/12520

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Hong Kong

6. 蔡育明; Choi, Yuk-ming. A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster.

Degree: M. Phil., 2013, University of Hong Kong

The era of big data has led to problems of unprecedented scale and complexity that are challenging the computing capability of conventional computer systems. One… (more)

Subjects/Keywords: Field programmable gate arrays; High performance computing

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

蔡育明; Choi, Y. (2013). A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster. (Masters Thesis). University of Hong Kong. Retrieved from Choi, Y. [蔡育明]. (2013). A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5270558 ; http://dx.doi.org/10.5353/th_b5270558 ; http://hdl.handle.net/10722/206679

Chicago Manual of Style (16th Edition):

蔡育明; Choi, Yuk-ming. “A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster.” 2013. Masters Thesis, University of Hong Kong. Accessed February 21, 2020. Choi, Y. [蔡育明]. (2013). A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5270558 ; http://dx.doi.org/10.5353/th_b5270558 ; http://hdl.handle.net/10722/206679.

MLA Handbook (7th Edition):

蔡育明; Choi, Yuk-ming. “A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster.” 2013. Web. 21 Feb 2020.

Vancouver:

蔡育明; Choi Y. A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster. [Internet] [Masters thesis]. University of Hong Kong; 2013. [cited 2020 Feb 21]. Available from: Choi, Y. [蔡育明]. (2013). A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5270558 ; http://dx.doi.org/10.5353/th_b5270558 ; http://hdl.handle.net/10722/206679.

Council of Science Editors:

蔡育明; Choi Y. A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster. [Masters Thesis]. University of Hong Kong; 2013. Available from: Choi, Y. [蔡育明]. (2013). A run-time hardware task execution framework for FPGA-accelerated heterogeneous cluster. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b5270558 ; http://dx.doi.org/10.5353/th_b5270558 ; http://hdl.handle.net/10722/206679


Montana State University

7. Turner, David Lee Douglas. Implementation of a radiation-tolerant computer based on a LEON3 architecture.

Degree: College of Engineering, 2015, Montana State University

 It is desired to create an inexpensive, open-source, radiation-tolerant computer for space applications using commercial, off-the-shelf parts and a proven space-grade processor. Building upon previous… (more)

Subjects/Keywords: Field programmable gate arrays.; Radiation.; Computer software.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Turner, D. L. D. (2015). Implementation of a radiation-tolerant computer based on a LEON3 architecture. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/10163

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Turner, David Lee Douglas. “Implementation of a radiation-tolerant computer based on a LEON3 architecture.” 2015. Thesis, Montana State University. Accessed February 21, 2020. https://scholarworks.montana.edu/xmlui/handle/1/10163.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Turner, David Lee Douglas. “Implementation of a radiation-tolerant computer based on a LEON3 architecture.” 2015. Web. 21 Feb 2020.

Vancouver:

Turner DLD. Implementation of a radiation-tolerant computer based on a LEON3 architecture. [Internet] [Thesis]. Montana State University; 2015. [cited 2020 Feb 21]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/10163.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Turner DLD. Implementation of a radiation-tolerant computer based on a LEON3 architecture. [Thesis]. Montana State University; 2015. Available from: https://scholarworks.montana.edu/xmlui/handle/1/10163

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

8. Mutukuda, Omesh. Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits.

Degree: 2010, Ryerson University

Field Programmable Gate Arrays (FPGAs) are increasingly being used to implement large datapath-oriented application that are designed to process multiple-bit wide data. Studies have shown… (more)

Subjects/Keywords: Field programmable gate arrays; Integrated circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mutukuda, O. (2010). Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A1868

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mutukuda, Omesh. “Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits.” 2010. Thesis, Ryerson University. Accessed February 21, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A1868.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mutukuda, Omesh. “Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits.” 2010. Web. 21 Feb 2020.

Vancouver:

Mutukuda O. Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits. [Internet] [Thesis]. Ryerson University; 2010. [cited 2020 Feb 21]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1868.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mutukuda O. Unidirectional Multi-Bit FPGA Architecture For Area Efficient Implementation of Datapath Circuits. [Thesis]. Ryerson University; 2010. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1868

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Montana State University

9. Buerkle, Todd Michael. Ionizing radiation detector for environmental awareness in FPGA-based flight computers.

Degree: College of Engineering, 2012, Montana State University

 Ionizing radiation has a detrimental effect on digital electronics that operate in extraterrestrial environments. When electronics are struck by these high energy particles, the effect… (more)

Subjects/Keywords: Ionizing radiation.; Field programmable gate arrays.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Buerkle, T. M. (2012). Ionizing radiation detector for environmental awareness in FPGA-based flight computers. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/1007

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Buerkle, Todd Michael. “Ionizing radiation detector for environmental awareness in FPGA-based flight computers.” 2012. Thesis, Montana State University. Accessed February 21, 2020. https://scholarworks.montana.edu/xmlui/handle/1/1007.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Buerkle, Todd Michael. “Ionizing radiation detector for environmental awareness in FPGA-based flight computers.” 2012. Web. 21 Feb 2020.

Vancouver:

Buerkle TM. Ionizing radiation detector for environmental awareness in FPGA-based flight computers. [Internet] [Thesis]. Montana State University; 2012. [cited 2020 Feb 21]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/1007.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Buerkle TM. Ionizing radiation detector for environmental awareness in FPGA-based flight computers. [Thesis]. Montana State University; 2012. Available from: https://scholarworks.montana.edu/xmlui/handle/1/1007

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Montana State University

10. Casebeer, Christopher Ness. A system to eavesdrop on marmosets.

Degree: College of Engineering, 2015, Montana State University

 This masters thesis describes developing a custom digital recording system to record the vocalizations and behavior of marmosets, which are small primates native to the… (more)

Subjects/Keywords: Field programmable gate arrays.; Animal behavior.; Monkeys.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Casebeer, C. N. (2015). A system to eavesdrop on marmosets. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/12731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Casebeer, Christopher Ness. “A system to eavesdrop on marmosets.” 2015. Thesis, Montana State University. Accessed February 21, 2020. https://scholarworks.montana.edu/xmlui/handle/1/12731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Casebeer, Christopher Ness. “A system to eavesdrop on marmosets.” 2015. Web. 21 Feb 2020.

Vancouver:

Casebeer CN. A system to eavesdrop on marmosets. [Internet] [Thesis]. Montana State University; 2015. [cited 2020 Feb 21]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/12731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Casebeer CN. A system to eavesdrop on marmosets. [Thesis]. Montana State University; 2015. Available from: https://scholarworks.montana.edu/xmlui/handle/1/12731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Montana State University

11. Weber, Raymond Joseph. Reconfigurable hardware accelerators for high performance radiation tolerant computers.

Degree: College of Engineering, 2014, Montana State University

 Computers play an important role in spaceflight and with ever more complex mission goals and sensors, current devices are not sufficient to meet the requirements… (more)

Subjects/Keywords: Field programmable gate arrays.; Radiation tolerance.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Weber, R. J. (2014). Reconfigurable hardware accelerators for high performance radiation tolerant computers. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/8695

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Weber, Raymond Joseph. “Reconfigurable hardware accelerators for high performance radiation tolerant computers.” 2014. Thesis, Montana State University. Accessed February 21, 2020. https://scholarworks.montana.edu/xmlui/handle/1/8695.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Weber, Raymond Joseph. “Reconfigurable hardware accelerators for high performance radiation tolerant computers.” 2014. Web. 21 Feb 2020.

Vancouver:

Weber RJ. Reconfigurable hardware accelerators for high performance radiation tolerant computers. [Internet] [Thesis]. Montana State University; 2014. [cited 2020 Feb 21]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/8695.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Weber RJ. Reconfigurable hardware accelerators for high performance radiation tolerant computers. [Thesis]. Montana State University; 2014. Available from: https://scholarworks.montana.edu/xmlui/handle/1/8695

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

12. Hyder, Nafiul. Minimizing the layout area of 2-input look up tables.

Degree: 2017, Ryerson University

 This work investigates the minimum layout area of multiplexers, a fundamental building block of Field-Programmable Gate Arrays (FPGAs). In particular, we investigate the minimum layout… (more)

Subjects/Keywords: Field programmable gate arrays  – Computer-aided design.; Field programmable gate arrays  – Design and construction.; Multiplexing.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hyder, N. (2017). Minimizing the layout area of 2-input look up tables. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A6861

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hyder, Nafiul. “Minimizing the layout area of 2-input look up tables.” 2017. Thesis, Ryerson University. Accessed February 21, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A6861.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hyder, Nafiul. “Minimizing the layout area of 2-input look up tables.” 2017. Web. 21 Feb 2020.

Vancouver:

Hyder N. Minimizing the layout area of 2-input look up tables. [Internet] [Thesis]. Ryerson University; 2017. [cited 2020 Feb 21]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6861.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hyder N. Minimizing the layout area of 2-input look up tables. [Thesis]. Ryerson University; 2017. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6861

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

13. Zafar, Muhammad Umair. Measuring the dynamic energy efficiency of FPGAs over processors.

Degree: 2016, Ryerson University

 This work investigates the dynamic energy efficiency of the parallel execution model of an FPGA and the sequential execution model of a processor, for latency-insensitive… (more)

Subjects/Keywords: Field programmable gate arrays  – Energy consumption  – Measurement; Field programmable gate arrays  – Energy consumption  – Mathematical models

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zafar, M. U. (2016). Measuring the dynamic energy efficiency of FPGAs over processors. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A5816

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zafar, Muhammad Umair. “Measuring the dynamic energy efficiency of FPGAs over processors.” 2016. Thesis, Ryerson University. Accessed February 21, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A5816.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zafar, Muhammad Umair. “Measuring the dynamic energy efficiency of FPGAs over processors.” 2016. Web. 21 Feb 2020.

Vancouver:

Zafar MU. Measuring the dynamic energy efficiency of FPGAs over processors. [Internet] [Thesis]. Ryerson University; 2016. [cited 2020 Feb 21]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5816.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zafar MU. Measuring the dynamic energy efficiency of FPGAs over processors. [Thesis]. Ryerson University; 2016. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5816

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of New Mexico

14. Hoffman, John. High-speed dynamic partial reconfiguration for field programmable gate arrays.

Degree: Electrical and Computer Engineering, 2009, University of New Mexico

 With dynamically and partially reconfigurable designs, it is necessary that the speed of the reconfiguration be accomplished in a time that is sufficiently small such… (more)

Subjects/Keywords: Field programmable gate arrays; Adaptive computing systems; Programmable array logic.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hoffman, J. (2009). High-speed dynamic partial reconfiguration for field programmable gate arrays. (Masters Thesis). University of New Mexico. Retrieved from http://hdl.handle.net/1928/9783

Chicago Manual of Style (16th Edition):

Hoffman, John. “High-speed dynamic partial reconfiguration for field programmable gate arrays.” 2009. Masters Thesis, University of New Mexico. Accessed February 21, 2020. http://hdl.handle.net/1928/9783.

MLA Handbook (7th Edition):

Hoffman, John. “High-speed dynamic partial reconfiguration for field programmable gate arrays.” 2009. Web. 21 Feb 2020.

Vancouver:

Hoffman J. High-speed dynamic partial reconfiguration for field programmable gate arrays. [Internet] [Masters thesis]. University of New Mexico; 2009. [cited 2020 Feb 21]. Available from: http://hdl.handle.net/1928/9783.

Council of Science Editors:

Hoffman J. High-speed dynamic partial reconfiguration for field programmable gate arrays. [Masters Thesis]. University of New Mexico; 2009. Available from: http://hdl.handle.net/1928/9783


Georgia Tech

15. Wunderlich, Richard Bryan. Floating-gate-programmable and reconfigurable, digital and mixed-signal systems.

Degree: PhD, Electrical and Computer Engineering, 2014, Georgia Tech

 This body of work as whole has the theme of using floating-gates and reconfigurable systems to explore and implement non-traditional computing solutions to difficult problems.… (more)

Subjects/Keywords: Floating-gate; Reconfigurable; Digital; Analog processing; Field programmable gate arrays

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wunderlich, R. B. (2014). Floating-gate-programmable and reconfigurable, digital and mixed-signal systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51815

Chicago Manual of Style (16th Edition):

Wunderlich, Richard Bryan. “Floating-gate-programmable and reconfigurable, digital and mixed-signal systems.” 2014. Doctoral Dissertation, Georgia Tech. Accessed February 21, 2020. http://hdl.handle.net/1853/51815.

MLA Handbook (7th Edition):

Wunderlich, Richard Bryan. “Floating-gate-programmable and reconfigurable, digital and mixed-signal systems.” 2014. Web. 21 Feb 2020.

Vancouver:

Wunderlich RB. Floating-gate-programmable and reconfigurable, digital and mixed-signal systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2014. [cited 2020 Feb 21]. Available from: http://hdl.handle.net/1853/51815.

Council of Science Editors:

Wunderlich RB. Floating-gate-programmable and reconfigurable, digital and mixed-signal systems. [Doctoral Dissertation]. Georgia Tech; 2014. Available from: http://hdl.handle.net/1853/51815


University of Florida

16. Nezvadovitz, Brian. Reliable FPGA Overclocking through Cycle Time Borrowing.

Degree: 2013, University of Florida

Field programmable gate arrays (FPGAs) are reconfigurable devices that are commonly used to accelerate many high performance computing applications, including those in signal processing, numerical… (more)

Subjects/Keywords: Design optimization; Electric potential; Field programmable gate arrays; Microprocessors; Phase shift; Pipelines; Propagation delay; Recycling; Signals; Timber; Field programmable gate arrays

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nezvadovitz, B. (2013). Reliable FPGA Overclocking through Cycle Time Borrowing. (Thesis). University of Florida. Retrieved from http://ufdc.ufl.edu/AA00059588

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nezvadovitz, Brian. “Reliable FPGA Overclocking through Cycle Time Borrowing.” 2013. Thesis, University of Florida. Accessed February 21, 2020. http://ufdc.ufl.edu/AA00059588.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nezvadovitz, Brian. “Reliable FPGA Overclocking through Cycle Time Borrowing.” 2013. Web. 21 Feb 2020.

Vancouver:

Nezvadovitz B. Reliable FPGA Overclocking through Cycle Time Borrowing. [Internet] [Thesis]. University of Florida; 2013. [cited 2020 Feb 21]. Available from: http://ufdc.ufl.edu/AA00059588.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nezvadovitz B. Reliable FPGA Overclocking through Cycle Time Borrowing. [Thesis]. University of Florida; 2013. Available from: http://ufdc.ufl.edu/AA00059588

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Federal de Mato Grosso do Sul

17. Corbelino, Luis Henrique Guimarães. Ferramenta para Sincronismo de Gerador Síncrono com a Rede Elétrica Empregando PLL Monofásico Embarcado em FPGA .

Degree: 2012, Universidade Federal de Mato Grosso do Sul

 Este trabalho aborda o desenvolvimento, a simulação e a implementação de um sistema automático para realizar o paralelismo entre gerador e a rede elétrica, além… (more)

Subjects/Keywords: Arranjos de Lógica Programável em Campo; Field Programmable Gate Arrays; Circuitos Gate Arrays; Gate Arrays Circuits; Energia Elétrica; Electric Power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Corbelino, L. H. G. (2012). Ferramenta para Sincronismo de Gerador Síncrono com a Rede Elétrica Empregando PLL Monofásico Embarcado em FPGA . (Thesis). Universidade Federal de Mato Grosso do Sul. Retrieved from http://repositorio.cbc.ufms.br:8080/jspui/handle/123456789/1924

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Corbelino, Luis Henrique Guimarães. “Ferramenta para Sincronismo de Gerador Síncrono com a Rede Elétrica Empregando PLL Monofásico Embarcado em FPGA .” 2012. Thesis, Universidade Federal de Mato Grosso do Sul. Accessed February 21, 2020. http://repositorio.cbc.ufms.br:8080/jspui/handle/123456789/1924.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Corbelino, Luis Henrique Guimarães. “Ferramenta para Sincronismo de Gerador Síncrono com a Rede Elétrica Empregando PLL Monofásico Embarcado em FPGA .” 2012. Web. 21 Feb 2020.

Vancouver:

Corbelino LHG. Ferramenta para Sincronismo de Gerador Síncrono com a Rede Elétrica Empregando PLL Monofásico Embarcado em FPGA . [Internet] [Thesis]. Universidade Federal de Mato Grosso do Sul; 2012. [cited 2020 Feb 21]. Available from: http://repositorio.cbc.ufms.br:8080/jspui/handle/123456789/1924.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Corbelino LHG. Ferramenta para Sincronismo de Gerador Síncrono com a Rede Elétrica Empregando PLL Monofásico Embarcado em FPGA . [Thesis]. Universidade Federal de Mato Grosso do Sul; 2012. Available from: http://repositorio.cbc.ufms.br:8080/jspui/handle/123456789/1924

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

18. Mhaidat, Khaldoon. Prototyping a scalable Montgomery multiplier using field programmable gate arrays (FPGAs).

Degree: MS, Electrical and Computer Engineering, 2002, Oregon State University

 Modular Multiplication is a time-consuming arithmetic operation because it involves multiplication as well as division. Modular exponentiation can be performed as a sequence of modular… (more)

Subjects/Keywords: Field programmable gate arrays

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mhaidat, K. (2002). Prototyping a scalable Montgomery multiplier using field programmable gate arrays (FPGAs). (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/28832

Chicago Manual of Style (16th Edition):

Mhaidat, Khaldoon. “Prototyping a scalable Montgomery multiplier using field programmable gate arrays (FPGAs).” 2002. Masters Thesis, Oregon State University. Accessed February 21, 2020. http://hdl.handle.net/1957/28832.

MLA Handbook (7th Edition):

Mhaidat, Khaldoon. “Prototyping a scalable Montgomery multiplier using field programmable gate arrays (FPGAs).” 2002. Web. 21 Feb 2020.

Vancouver:

Mhaidat K. Prototyping a scalable Montgomery multiplier using field programmable gate arrays (FPGAs). [Internet] [Masters thesis]. Oregon State University; 2002. [cited 2020 Feb 21]. Available from: http://hdl.handle.net/1957/28832.

Council of Science Editors:

Mhaidat K. Prototyping a scalable Montgomery multiplier using field programmable gate arrays (FPGAs). [Masters Thesis]. Oregon State University; 2002. Available from: http://hdl.handle.net/1957/28832


Nelson Mandela Metropolitan University

19. Van den Berg, Allan Edward. Hardware evolution of a digital circuit using a custom VLSI architecture.

Degree: Faculty of Engineering, the Built Environment and Information Technology, 2013, Nelson Mandela Metropolitan University

 This research investigates three solutions to overcoming portability and scalability concerns in the Evolutionary Hardware (EHW) field. Firstly, the study explores if the V-FPGA—a new,… (more)

Subjects/Keywords: Digital electronics; Field programmable gate arrays; Sequential machine theory

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Van den Berg, A. E. (2013). Hardware evolution of a digital circuit using a custom VLSI architecture. (Thesis). Nelson Mandela Metropolitan University. Retrieved from http://hdl.handle.net/10948/d1020984

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Van den Berg, Allan Edward. “Hardware evolution of a digital circuit using a custom VLSI architecture.” 2013. Thesis, Nelson Mandela Metropolitan University. Accessed February 21, 2020. http://hdl.handle.net/10948/d1020984.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Van den Berg, Allan Edward. “Hardware evolution of a digital circuit using a custom VLSI architecture.” 2013. Web. 21 Feb 2020.

Vancouver:

Van den Berg AE. Hardware evolution of a digital circuit using a custom VLSI architecture. [Internet] [Thesis]. Nelson Mandela Metropolitan University; 2013. [cited 2020 Feb 21]. Available from: http://hdl.handle.net/10948/d1020984.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Van den Berg AE. Hardware evolution of a digital circuit using a custom VLSI architecture. [Thesis]. Nelson Mandela Metropolitan University; 2013. Available from: http://hdl.handle.net/10948/d1020984

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Hawaii – Manoa

20. Halverson, Richard Peyton. The functional memory approach to the design of custom computing machines.

Degree: PhD, 2009, University of Hawaii – Manoa

Microfiche.

xviii, 186 leaves, bound ill. 29 cm

Subjects/Keywords: Field programmable gate arrays

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Halverson, R. P. (2009). The functional memory approach to the design of custom computing machines. (Doctoral Dissertation). University of Hawaii – Manoa. Retrieved from http://hdl.handle.net/10125/9542

Chicago Manual of Style (16th Edition):

Halverson, Richard Peyton. “The functional memory approach to the design of custom computing machines.” 2009. Doctoral Dissertation, University of Hawaii – Manoa. Accessed February 21, 2020. http://hdl.handle.net/10125/9542.

MLA Handbook (7th Edition):

Halverson, Richard Peyton. “The functional memory approach to the design of custom computing machines.” 2009. Web. 21 Feb 2020.

Vancouver:

Halverson RP. The functional memory approach to the design of custom computing machines. [Internet] [Doctoral dissertation]. University of Hawaii – Manoa; 2009. [cited 2020 Feb 21]. Available from: http://hdl.handle.net/10125/9542.

Council of Science Editors:

Halverson RP. The functional memory approach to the design of custom computing machines. [Doctoral Dissertation]. University of Hawaii – Manoa; 2009. Available from: http://hdl.handle.net/10125/9542


University of New Mexico

21. Costantine, Joseph. Design, optimization and analysis of reconfigurable antennas.

Degree: Electrical and Computer Engineering, 2010, University of New Mexico

 The ability of reconfigurable antennas to tune resonances, change polarization and modify their radiation patterns, made their development imperative in modern telecommunication systems. Their agility… (more)

Subjects/Keywords: Adaptive antennas.; Adaptive antennas – Mathematical models.; Field programmable gate arrays.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Costantine, J. (2010). Design, optimization and analysis of reconfigurable antennas. (Doctoral Dissertation). University of New Mexico. Retrieved from http://hdl.handle.net/1928/10266

Chicago Manual of Style (16th Edition):

Costantine, Joseph. “Design, optimization and analysis of reconfigurable antennas.” 2010. Doctoral Dissertation, University of New Mexico. Accessed February 21, 2020. http://hdl.handle.net/1928/10266.

MLA Handbook (7th Edition):

Costantine, Joseph. “Design, optimization and analysis of reconfigurable antennas.” 2010. Web. 21 Feb 2020.

Vancouver:

Costantine J. Design, optimization and analysis of reconfigurable antennas. [Internet] [Doctoral dissertation]. University of New Mexico; 2010. [cited 2020 Feb 21]. Available from: http://hdl.handle.net/1928/10266.

Council of Science Editors:

Costantine J. Design, optimization and analysis of reconfigurable antennas. [Doctoral Dissertation]. University of New Mexico; 2010. Available from: http://hdl.handle.net/1928/10266

22. Lorandel, Jordane. Etude de la consommation énergétique de systèmes de communications numériques sans fil implantés sur cible FPGA : Power consumption analysis of FPGA-based wireless communication systems.

Degree: Docteur es, Electronique et Télécommunications, 2015, Rennes, INSA

Les systèmes de communications sans fil n'ont cessé d'évoluer ces dernières années, poussés par de fortes demandes du marché en systèmes toujours plus autonomes et… (more)

Subjects/Keywords: FPGA; Modélisation haut-niveau; Field programmable gate arrays; 621.3

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lorandel, J. (2015). Etude de la consommation énergétique de systèmes de communications numériques sans fil implantés sur cible FPGA : Power consumption analysis of FPGA-based wireless communication systems. (Doctoral Dissertation). Rennes, INSA. Retrieved from http://www.theses.fr/2015ISAR0036

Chicago Manual of Style (16th Edition):

Lorandel, Jordane. “Etude de la consommation énergétique de systèmes de communications numériques sans fil implantés sur cible FPGA : Power consumption analysis of FPGA-based wireless communication systems.” 2015. Doctoral Dissertation, Rennes, INSA. Accessed February 21, 2020. http://www.theses.fr/2015ISAR0036.

MLA Handbook (7th Edition):

Lorandel, Jordane. “Etude de la consommation énergétique de systèmes de communications numériques sans fil implantés sur cible FPGA : Power consumption analysis of FPGA-based wireless communication systems.” 2015. Web. 21 Feb 2020.

Vancouver:

Lorandel J. Etude de la consommation énergétique de systèmes de communications numériques sans fil implantés sur cible FPGA : Power consumption analysis of FPGA-based wireless communication systems. [Internet] [Doctoral dissertation]. Rennes, INSA; 2015. [cited 2020 Feb 21]. Available from: http://www.theses.fr/2015ISAR0036.

Council of Science Editors:

Lorandel J. Etude de la consommation énergétique de systèmes de communications numériques sans fil implantés sur cible FPGA : Power consumption analysis of FPGA-based wireless communication systems. [Doctoral Dissertation]. Rennes, INSA; 2015. Available from: http://www.theses.fr/2015ISAR0036


Ryerson University

23. Khan, Farheen Fatima. Towards accurate FPGA area models for FPGA architecture evaluation.

Degree: 2017, Ryerson University

Field Programmable Gate Array (FPGA) devices are integrated circuit chips which can be configured by the end user. FPGA architectures have evolved into heterogeneous System-on-Chips… (more)

Subjects/Keywords: Systems on a chip.; Field programmable gate arrays.; Integrated circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Khan, F. F. (2017). Towards accurate FPGA area models for FPGA architecture evaluation. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A6865

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Khan, Farheen Fatima. “Towards accurate FPGA area models for FPGA architecture evaluation.” 2017. Thesis, Ryerson University. Accessed February 21, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A6865.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Khan, Farheen Fatima. “Towards accurate FPGA area models for FPGA architecture evaluation.” 2017. Web. 21 Feb 2020.

Vancouver:

Khan FF. Towards accurate FPGA area models for FPGA architecture evaluation. [Internet] [Thesis]. Ryerson University; 2017. [cited 2020 Feb 21]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6865.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Khan FF. Towards accurate FPGA area models for FPGA architecture evaluation. [Thesis]. Ryerson University; 2017. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6865

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

24. Kirischian, Valeri. The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources.

Degree: 2010, Ryerson University

 The main motivation factors for the proposed research were the increase of cost-efficiency of FPGA based systems and the simplification of the design process. The… (more)

Subjects/Keywords: Adaptive computing systems; Computer architecture; Field programmable gate arrays

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kirischian, V. (2010). The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A6386

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kirischian, Valeri. “The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources.” 2010. Thesis, Ryerson University. Accessed February 21, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A6386.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kirischian, Valeri. “The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources.” 2010. Web. 21 Feb 2020.

Vancouver:

Kirischian V. The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources. [Internet] [Thesis]. Ryerson University; 2010. [cited 2020 Feb 21]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6386.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kirischian V. The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources. [Thesis]. Ryerson University; 2010. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6386

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

25. Siddique, Sheraz Raza. Complexity analysis and hardware implementation of extensible modulo addition for lightweight block cipher in Internet of Things (IOT).

Degree: 2017, Ryerson University

 This project presents complexity analysis and hardware implementation of extensible modulo addition [15] encryption algorithm on a 32-bit lightweight FPGA based block cipher called INFLEX,… (more)

Subjects/Keywords: Cryptography.; Field programmable gate arrays  – Programming.; Data encryption (Computer science)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Siddique, S. R. (2017). Complexity analysis and hardware implementation of extensible modulo addition for lightweight block cipher in Internet of Things (IOT). (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A6903

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Siddique, Sheraz Raza. “Complexity analysis and hardware implementation of extensible modulo addition for lightweight block cipher in Internet of Things (IOT).” 2017. Thesis, Ryerson University. Accessed February 21, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A6903.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Siddique, Sheraz Raza. “Complexity analysis and hardware implementation of extensible modulo addition for lightweight block cipher in Internet of Things (IOT).” 2017. Web. 21 Feb 2020.

Vancouver:

Siddique SR. Complexity analysis and hardware implementation of extensible modulo addition for lightweight block cipher in Internet of Things (IOT). [Internet] [Thesis]. Ryerson University; 2017. [cited 2020 Feb 21]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6903.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Siddique SR. Complexity analysis and hardware implementation of extensible modulo addition for lightweight block cipher in Internet of Things (IOT). [Thesis]. Ryerson University; 2017. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6903

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Montana State University

26. Dack, Connor Aquila. Development of a smart camera system using a system on module FPGA.

Degree: College of Engineering, 2017, Montana State University

 Imaging systems can now produce more data than conventional PCs with frame grabbers can process in real-time. Moving real-time custom computation as close as possible… (more)

Subjects/Keywords: Field programmable gate arrays.; Cameras.; Optical spectroscopy.; Electronic data processing.; Algorithms.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dack, C. A. (2017). Development of a smart camera system using a system on module FPGA. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/14902

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dack, Connor Aquila. “Development of a smart camera system using a system on module FPGA.” 2017. Thesis, Montana State University. Accessed February 21, 2020. https://scholarworks.montana.edu/xmlui/handle/1/14902.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dack, Connor Aquila. “Development of a smart camera system using a system on module FPGA.” 2017. Web. 21 Feb 2020.

Vancouver:

Dack CA. Development of a smart camera system using a system on module FPGA. [Internet] [Thesis]. Montana State University; 2017. [cited 2020 Feb 21]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/14902.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dack CA. Development of a smart camera system using a system on module FPGA. [Thesis]. Montana State University; 2017. Available from: https://scholarworks.montana.edu/xmlui/handle/1/14902

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Montana State University

27. Hane, Jennifer Susan. A fault-tolerant computer architecture for space vehicle applications.

Degree: College of Engineering, 2012, Montana State University

 The discovery of new methods to protect electronics from harsh radiation environments outside earth's atmosphere is important to the future of space exploration. Reconfigurable, SRAM-based… (more)

Subjects/Keywords: Computer architecture.; Fault-tolerant computing.; Field programmable gate arrays.; Aerospace engineering.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hane, J. S. (2012). A fault-tolerant computer architecture for space vehicle applications. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/1423

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hane, Jennifer Susan. “A fault-tolerant computer architecture for space vehicle applications.” 2012. Thesis, Montana State University. Accessed February 21, 2020. https://scholarworks.montana.edu/xmlui/handle/1/1423.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hane, Jennifer Susan. “A fault-tolerant computer architecture for space vehicle applications.” 2012. Web. 21 Feb 2020.

Vancouver:

Hane JS. A fault-tolerant computer architecture for space vehicle applications. [Internet] [Thesis]. Montana State University; 2012. [cited 2020 Feb 21]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/1423.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hane JS. A fault-tolerant computer architecture for space vehicle applications. [Thesis]. Montana State University; 2012. Available from: https://scholarworks.montana.edu/xmlui/handle/1/1423

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Montana State University

28. Whitaker, Monica Jane. Development of a smart camera system on an FPGA.

Degree: College of Engineering, 2016, Montana State University

 In recent years, hyperspectral cameras have been appearing in many applications that need more information than what conventional color cameras can provide. A hyperspectral camera… (more)

Subjects/Keywords: Field programmable gate arrays.; Spectrum analysis.; Remote sensing.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Whitaker, M. J. (2016). Development of a smart camera system on an FPGA. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/12387

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Whitaker, Monica Jane. “Development of a smart camera system on an FPGA.” 2016. Thesis, Montana State University. Accessed February 21, 2020. https://scholarworks.montana.edu/xmlui/handle/1/12387.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Whitaker, Monica Jane. “Development of a smart camera system on an FPGA.” 2016. Web. 21 Feb 2020.

Vancouver:

Whitaker MJ. Development of a smart camera system on an FPGA. [Internet] [Thesis]. Montana State University; 2016. [cited 2020 Feb 21]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/12387.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Whitaker MJ. Development of a smart camera system on an FPGA. [Thesis]. Montana State University; 2016. Available from: https://scholarworks.montana.edu/xmlui/handle/1/12387

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Montana State University

29. Julien, Connor Russell. A radiation tolerant computer mission to the International Space Station.

Degree: College of Engineering, 2017, Montana State University

 The harmful effects of radiation on electronics used in space poses a difficult problem for the aerospace industry. Memory corruption and other faults caused by… (more)

Subjects/Keywords: Radiation.; Field programmable gate arrays.; Reliability (Engineering).; Montana State University Bozeman.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Julien, C. R. (2017). A radiation tolerant computer mission to the International Space Station. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/12791

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Julien, Connor Russell. “A radiation tolerant computer mission to the International Space Station.” 2017. Thesis, Montana State University. Accessed February 21, 2020. https://scholarworks.montana.edu/xmlui/handle/1/12791.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Julien, Connor Russell. “A radiation tolerant computer mission to the International Space Station.” 2017. Web. 21 Feb 2020.

Vancouver:

Julien CR. A radiation tolerant computer mission to the International Space Station. [Internet] [Thesis]. Montana State University; 2017. [cited 2020 Feb 21]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/12791.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Julien CR. A radiation tolerant computer mission to the International Space Station. [Thesis]. Montana State University; 2017. Available from: https://scholarworks.montana.edu/xmlui/handle/1/12791

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Montana State University

30. Gauer, Clinton Francis. Radiation tolerant many-core computing system for aerospace applications.

Degree: College of Engineering, 2010, Montana State University

 When integrated circuits are exposed to ionizing radiation, a variety of fault conditions can occur. This draws concern to the aerospace community as they look… (more)

Subjects/Keywords: Radiation tolerance.; Adaptive computing systems.; Field programmable gate arrays.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gauer, C. F. (2010). Radiation tolerant many-core computing system for aerospace applications. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/1313

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gauer, Clinton Francis. “Radiation tolerant many-core computing system for aerospace applications.” 2010. Thesis, Montana State University. Accessed February 21, 2020. https://scholarworks.montana.edu/xmlui/handle/1/1313.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gauer, Clinton Francis. “Radiation tolerant many-core computing system for aerospace applications.” 2010. Web. 21 Feb 2020.

Vancouver:

Gauer CF. Radiation tolerant many-core computing system for aerospace applications. [Internet] [Thesis]. Montana State University; 2010. [cited 2020 Feb 21]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/1313.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gauer CF. Radiation tolerant many-core computing system for aerospace applications. [Thesis]. Montana State University; 2010. Available from: https://scholarworks.montana.edu/xmlui/handle/1/1313

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2] [3] [4] [5] … [463]

.