Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(Field Programmable Gate Array FPGA ). Showing records 1 – 30 of 21761 total matches.

[1] [2] [3] [4] [5] … [726]

Search Limiters

Last 2 Years | English Only

Degrees

Languages

Country

▼ Search Limiters

1. Turki, Mariem. Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform.

Degree: Docteur es, Informatique et Micro-Electronique, 2014, Université Pierre et Marie Curie – Paris VI

De nos jours, la complexité de la conception des circuits intégrés et du logiciel croit régulièrement, faisant croître le besoin de la vérification dans chaque… (more)

Subjects/Keywords: FPGA (Field Programmable Gate Array); Prototypage; Routage; Pathfinder; Itératif; Multiplexage; FPGA (Field Programmable Gate Array); Prototyping; 005.18

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Turki, M. (2014). Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform. (Doctoral Dissertation). Université Pierre et Marie Curie – Paris VI. Retrieved from http://www.theses.fr/2014PA066698

Chicago Manual of Style (16th Edition):

Turki, Mariem. “Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform.” 2014. Doctoral Dissertation, Université Pierre et Marie Curie – Paris VI. Accessed December 09, 2019. http://www.theses.fr/2014PA066698.

MLA Handbook (7th Edition):

Turki, Mariem. “Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform.” 2014. Web. 09 Dec 2019.

Vancouver:

Turki M. Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform. [Internet] [Doctoral dissertation]. Université Pierre et Marie Curie – Paris VI; 2014. [cited 2019 Dec 09]. Available from: http://www.theses.fr/2014PA066698.

Council of Science Editors:

Turki M. Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform. [Doctoral Dissertation]. Université Pierre et Marie Curie – Paris VI; 2014. Available from: http://www.theses.fr/2014PA066698


Universidade Estadual de Campinas

2. Monte, Luis Renato. Especificação do nucleo de processamento para rede de chaveamento de rajadas opticas .

Degree: 2009, Universidade Estadual de Campinas

 Resumo: Este trabalho apresenta as especificações arquitetônicas e funcionais de uma rede ótica avançada, fundamentada na comutação óptica de rajadas e que objetiva um melhor… (more)

Subjects/Keywords: Fibras óticas; Comunicações óticas; Chaveamento ótico; FPGA (Field Programmable Gate Array)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Monte, L. R. (2009). Especificação do nucleo de processamento para rede de chaveamento de rajadas opticas . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/259738

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Monte, Luis Renato. “Especificação do nucleo de processamento para rede de chaveamento de rajadas opticas .” 2009. Thesis, Universidade Estadual de Campinas. Accessed December 09, 2019. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259738.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Monte, Luis Renato. “Especificação do nucleo de processamento para rede de chaveamento de rajadas opticas .” 2009. Web. 09 Dec 2019.

Vancouver:

Monte LR. Especificação do nucleo de processamento para rede de chaveamento de rajadas opticas . [Internet] [Thesis]. Universidade Estadual de Campinas; 2009. [cited 2019 Dec 09]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/259738.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Monte LR. Especificação do nucleo de processamento para rede de chaveamento de rajadas opticas . [Thesis]. Universidade Estadual de Campinas; 2009. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/259738

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Victoria University of Wellington

3. Ang, Andrew. Development of an Open PXIe System based on FPGA Modules.

Degree: 2018, Victoria University of Wellington

 PXIe is a instrumentation platform that is used as the basis for developing test equipment, modular electronic instruments and automated test systems. A typical PXIe… (more)

Subjects/Keywords: FPGA; PXIe; Electronics; PCI eXtensions for Instrumentation; Field Programmable Gate Array

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ang, A. (2018). Development of an Open PXIe System based on FPGA Modules. (Masters Thesis). Victoria University of Wellington. Retrieved from http://hdl.handle.net/10063/7653

Chicago Manual of Style (16th Edition):

Ang, Andrew. “Development of an Open PXIe System based on FPGA Modules.” 2018. Masters Thesis, Victoria University of Wellington. Accessed December 09, 2019. http://hdl.handle.net/10063/7653.

MLA Handbook (7th Edition):

Ang, Andrew. “Development of an Open PXIe System based on FPGA Modules.” 2018. Web. 09 Dec 2019.

Vancouver:

Ang A. Development of an Open PXIe System based on FPGA Modules. [Internet] [Masters thesis]. Victoria University of Wellington; 2018. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/10063/7653.

Council of Science Editors:

Ang A. Development of an Open PXIe System based on FPGA Modules. [Masters Thesis]. Victoria University of Wellington; 2018. Available from: http://hdl.handle.net/10063/7653


California State University – Sacramento

4. Patel, Maunank V. Integrated equipment operation and central control system of power plants.

Degree: MS, Electrical and Electronic Engineering, 2010, California State University – Sacramento

 As we know our each day to day activity requires electricity, starting from waking up by alarm to using cell phone and computer at work… (more)

Subjects/Keywords: FPGA; Field programmable gate array; Power plant optimization

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Patel, M. V. (2010). Integrated equipment operation and central control system of power plants. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.9/241

Chicago Manual of Style (16th Edition):

Patel, Maunank V. “Integrated equipment operation and central control system of power plants.” 2010. Masters Thesis, California State University – Sacramento. Accessed December 09, 2019. http://hdl.handle.net/10211.9/241.

MLA Handbook (7th Edition):

Patel, Maunank V. “Integrated equipment operation and central control system of power plants.” 2010. Web. 09 Dec 2019.

Vancouver:

Patel MV. Integrated equipment operation and central control system of power plants. [Internet] [Masters thesis]. California State University – Sacramento; 2010. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/10211.9/241.

Council of Science Editors:

Patel MV. Integrated equipment operation and central control system of power plants. [Masters Thesis]. California State University – Sacramento; 2010. Available from: http://hdl.handle.net/10211.9/241


Universidade Estadual de Campinas

5. Almeida, Carlos Caetano de, 1976-. Arquitetura do módulo de convolução para visão computacional baseada em FPGA .

Degree: 2015, Universidade Estadual de Campinas

 Resumo: Esta dissertação apresenta o estudo de uma arquitetura para o processamento digital de imagens, desenvolvido através de dispositivos de hardware programável, no caso FPGA,… (more)

Subjects/Keywords: Processamento de imagens; Visão por computador; FPGA (Field Programmable Gate Array)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Almeida, Carlos Caetano de, 1. (2015). Arquitetura do módulo de convolução para visão computacional baseada em FPGA . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/265780

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Almeida, Carlos Caetano de, 1976-. “Arquitetura do módulo de convolução para visão computacional baseada em FPGA .” 2015. Thesis, Universidade Estadual de Campinas. Accessed December 09, 2019. http://repositorio.unicamp.br/jspui/handle/REPOSIP/265780.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Almeida, Carlos Caetano de, 1976-. “Arquitetura do módulo de convolução para visão computacional baseada em FPGA .” 2015. Web. 09 Dec 2019.

Vancouver:

Almeida, Carlos Caetano de 1. Arquitetura do módulo de convolução para visão computacional baseada em FPGA . [Internet] [Thesis]. Universidade Estadual de Campinas; 2015. [cited 2019 Dec 09]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/265780.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Almeida, Carlos Caetano de 1. Arquitetura do módulo de convolução para visão computacional baseada em FPGA . [Thesis]. Universidade Estadual de Campinas; 2015. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/265780

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Estadual de Campinas

6. Américo Filho, Júlio Cesar Soares, 1987-. Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128 .

Degree: 2016, Universidade Estadual de Campinas

 Resumo: Neste trabalho, propõe-se uma arquitetura de hardware para um co-processador capaz de realizar encriptação e decriptação segundo o padrão AES-128 com suporte aos modos… (more)

Subjects/Keywords: Algoritmos; Hardware - Arquitetura; Computadores canalizados; Criptografia; FPGA (Field Programmable Gate Array)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Américo Filho, Júlio Cesar Soares, 1. (2016). Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128 . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/321942

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Américo Filho, Júlio Cesar Soares, 1987-. “Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128 .” 2016. Thesis, Universidade Estadual de Campinas. Accessed December 09, 2019. http://repositorio.unicamp.br/jspui/handle/REPOSIP/321942.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Américo Filho, Júlio Cesar Soares, 1987-. “Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128 .” 2016. Web. 09 Dec 2019.

Vancouver:

Américo Filho, Júlio Cesar Soares 1. Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128 . [Internet] [Thesis]. Universidade Estadual de Campinas; 2016. [cited 2019 Dec 09]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/321942.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Américo Filho, Júlio Cesar Soares 1. Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128 . [Thesis]. Universidade Estadual de Campinas; 2016. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/321942

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Estadual de Campinas

7. Moreira, Veruska Rodrigues. Plataforma em hardware reconfiguravel para o ensino e pesquisa em laboratorio de sistemas digitais a distancia .

Degree: 2009, Universidade Estadual de Campinas

 Resumo: Esta dissertação apresenta a concepção e o desenvolvimento de uma plataforma em hardware reconfigurável denominada REDLART - REconfigurable Digital Laboratory for Advanced Research and… (more)

Subjects/Keywords: Ensino a distância; FPGA (Field Programmable Gate Array); Serviços na Web

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Moreira, V. R. (2009). Plataforma em hardware reconfiguravel para o ensino e pesquisa em laboratorio de sistemas digitais a distancia . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/258897

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Moreira, Veruska Rodrigues. “Plataforma em hardware reconfiguravel para o ensino e pesquisa em laboratorio de sistemas digitais a distancia .” 2009. Thesis, Universidade Estadual de Campinas. Accessed December 09, 2019. http://repositorio.unicamp.br/jspui/handle/REPOSIP/258897.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Moreira, Veruska Rodrigues. “Plataforma em hardware reconfiguravel para o ensino e pesquisa em laboratorio de sistemas digitais a distancia .” 2009. Web. 09 Dec 2019.

Vancouver:

Moreira VR. Plataforma em hardware reconfiguravel para o ensino e pesquisa em laboratorio de sistemas digitais a distancia . [Internet] [Thesis]. Universidade Estadual de Campinas; 2009. [cited 2019 Dec 09]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/258897.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Moreira VR. Plataforma em hardware reconfiguravel para o ensino e pesquisa em laboratorio de sistemas digitais a distancia . [Thesis]. Universidade Estadual de Campinas; 2009. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/258897

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Chicago

8. Mastinu, Matteo. Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures.

Degree: 2013, University of Illinois – Chicago

 This work addresses the Maxeler Technologies Ltd. platforms, and the principal goal of this work is to design a new methodology to support Partial Reconfiguration… (more)

Subjects/Keywords: Maxeler; Field-Programmable Gate Array (FPGA); Partial Reconfiguration

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mastinu, M. (2013). Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/10018

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mastinu, Matteo. “Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures.” 2013. Thesis, University of Illinois – Chicago. Accessed December 09, 2019. http://hdl.handle.net/10027/10018.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mastinu, Matteo. “Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures.” 2013. Web. 09 Dec 2019.

Vancouver:

Mastinu M. Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures. [Internet] [Thesis]. University of Illinois – Chicago; 2013. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/10027/10018.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mastinu M. Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures. [Thesis]. University of Illinois – Chicago; 2013. Available from: http://hdl.handle.net/10027/10018

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Bucknell University

9. Su, Juliana. Design and Development of an FPGA-based Distributed Computing Processing Platform.

Degree: 2011, Bucknell University

 This thesis presents two frameworks- a software framework and a hardware core manager framework- which, together, can be used to develop a processing platform using… (more)

Subjects/Keywords: field-programmable gate array; FPGA; distributed computing; reconfigurable computing; processing platform

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Su, J. (2011). Design and Development of an FPGA-based Distributed Computing Processing Platform. (Thesis). Bucknell University. Retrieved from https://digitalcommons.bucknell.edu/masters_theses/38

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Su, Juliana. “Design and Development of an FPGA-based Distributed Computing Processing Platform.” 2011. Thesis, Bucknell University. Accessed December 09, 2019. https://digitalcommons.bucknell.edu/masters_theses/38.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Su, Juliana. “Design and Development of an FPGA-based Distributed Computing Processing Platform.” 2011. Web. 09 Dec 2019.

Vancouver:

Su J. Design and Development of an FPGA-based Distributed Computing Processing Platform. [Internet] [Thesis]. Bucknell University; 2011. [cited 2019 Dec 09]. Available from: https://digitalcommons.bucknell.edu/masters_theses/38.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Su J. Design and Development of an FPGA-based Distributed Computing Processing Platform. [Thesis]. Bucknell University; 2011. Available from: https://digitalcommons.bucknell.edu/masters_theses/38

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

10. Leiva Cochachin, Andrés Mijail. Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA.

Degree: 2012, Universidad Nacional de Ingeniería

 En la presente tesis se explica la metodología utilizada en el diseño e implementación de una solución integral (un módulo de captura de paquetes IP… (more)

Subjects/Keywords: Red Ethernet; Módulo de captura; FPGA (Field Programmable Gate Array)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Leiva Cochachin, A. M. (2012). Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA. (Thesis). Universidad Nacional de Ingeniería. Retrieved from http://cybertesis.uni.edu.pe/handle/uni/1325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Leiva Cochachin, Andrés Mijail. “Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA.” 2012. Thesis, Universidad Nacional de Ingeniería. Accessed December 09, 2019. http://cybertesis.uni.edu.pe/handle/uni/1325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Leiva Cochachin, Andrés Mijail. “Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA.” 2012. Web. 09 Dec 2019.

Vancouver:

Leiva Cochachin AM. Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA. [Internet] [Thesis]. Universidad Nacional de Ingeniería; 2012. [cited 2019 Dec 09]. Available from: http://cybertesis.uni.edu.pe/handle/uni/1325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Leiva Cochachin AM. Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA. [Thesis]. Universidad Nacional de Ingeniería; 2012. Available from: http://cybertesis.uni.edu.pe/handle/uni/1325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


McMaster University

11. Zuzarte, Marvin. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.

Degree: MASc, 2014, McMaster University

Safety and mission critical systems are currently deployed in many different fields where there is a greater presence of high energy particles (e.g. aerospace). The… (more)

Subjects/Keywords: FPGA; Fault injection; Field programmable gate array; runtime; soft error

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zuzarte, M. (2014). A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. (Masters Thesis). McMaster University. Retrieved from http://hdl.handle.net/11375/16500

Chicago Manual of Style (16th Edition):

Zuzarte, Marvin. “A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.” 2014. Masters Thesis, McMaster University. Accessed December 09, 2019. http://hdl.handle.net/11375/16500.

MLA Handbook (7th Edition):

Zuzarte, Marvin. “A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.” 2014. Web. 09 Dec 2019.

Vancouver:

Zuzarte M. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. [Internet] [Masters thesis]. McMaster University; 2014. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/11375/16500.

Council of Science Editors:

Zuzarte M. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. [Masters Thesis]. McMaster University; 2014. Available from: http://hdl.handle.net/11375/16500


University of Illinois – Urbana-Champaign

12. Li, Shuo. Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA).

Degree: MS, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 Direct digital synthesis is a technique for using digital data processing blocks as a means to generate a frequency and phase tunable output signal referenced… (more)

Subjects/Keywords: direct digital synthesizer (DDS); Field-Programmable Gate Array (FPGA); digital design

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, S. (2015). Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA). (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78598

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Shuo. “Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA).” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed December 09, 2019. http://hdl.handle.net/2142/78598.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Shuo. “Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA).” 2015. Web. 09 Dec 2019.

Vancouver:

Li S. Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA). [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/2142/78598.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li S. Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA). [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78598

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

13. Xia, Tian. FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition.

Degree: MS, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 Despite the recent success of neural network in the research eld, the num- ber of resulting applications for non-academic settings is very limited. One setback… (more)

Subjects/Keywords: Field-Programmable Gate Array (FPGA); Restricted Boltzmann Machine (RBM)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xia, T. (2015). FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78800

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xia, Tian. “FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed December 09, 2019. http://hdl.handle.net/2142/78800.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xia, Tian. “FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition.” 2015. Web. 09 Dec 2019.

Vancouver:

Xia T. FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/2142/78800.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xia T. FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78800

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

14. Tolar, Jacob. A directory enhanced network on chip for FPGA.

Degree: MS, 1200, 2013, University of Illinois – Urbana-Champaign

 This thesis presents and evaluates a directory enhanced network on chip for FPGA, with the goal of improving the performance of cores generated by FCUDA,… (more)

Subjects/Keywords: Network on Chip; Field-Programmable Gate Array (FPGA); FCUDA

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tolar, J. (2013). A directory enhanced network on chip for FPGA. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/44439

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tolar, Jacob. “A directory enhanced network on chip for FPGA.” 2013. Thesis, University of Illinois – Urbana-Champaign. Accessed December 09, 2019. http://hdl.handle.net/2142/44439.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tolar, Jacob. “A directory enhanced network on chip for FPGA.” 2013. Web. 09 Dec 2019.

Vancouver:

Tolar J. A directory enhanced network on chip for FPGA. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2013. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/2142/44439.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tolar J. A directory enhanced network on chip for FPGA. [Thesis]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/44439

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

15. Jadeglans, Tim. FPGA-implementation av ett neuralt nätverk .

Degree: Chalmers tekniska högskola / Institutionen för data och informationsvetenskap, 2019, Chalmers University of Technology

 Image recognition is a quickly growing field where convolutional neural networks, CNN, are in the bleeding edge. Today fast GPUs are used which consume a… (more)

Subjects/Keywords: Convolutional Neural Network; CNN; Field Programmable Gate Array; FPGA; Image Recognition

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jadeglans, T. (2019). FPGA-implementation av ett neuralt nätverk . (Thesis). Chalmers University of Technology. Retrieved from http://hdl.handle.net/20.500.12380/300036

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jadeglans, Tim. “FPGA-implementation av ett neuralt nätverk .” 2019. Thesis, Chalmers University of Technology. Accessed December 09, 2019. http://hdl.handle.net/20.500.12380/300036.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jadeglans, Tim. “FPGA-implementation av ett neuralt nätverk .” 2019. Web. 09 Dec 2019.

Vancouver:

Jadeglans T. FPGA-implementation av ett neuralt nätverk . [Internet] [Thesis]. Chalmers University of Technology; 2019. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/20.500.12380/300036.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jadeglans T. FPGA-implementation av ett neuralt nätverk . [Thesis]. Chalmers University of Technology; 2019. Available from: http://hdl.handle.net/20.500.12380/300036

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

16. Yazdanshenas, Sadegh. Datacenter-optimized FPGAs.

Degree: PhD, 2019, University of Toronto

 Large-scale deployment of field-programmable gate arrays (FPGAs) into datacenters has introduced new use cases that utilize the FPGA as a multi-user compute platform, require more… (more)

Subjects/Keywords: Datacenter; Field-programmable Gate Array; FPGA Architecture; 0464

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yazdanshenas, S. (2019). Datacenter-optimized FPGAs. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/97003

Chicago Manual of Style (16th Edition):

Yazdanshenas, Sadegh. “Datacenter-optimized FPGAs.” 2019. Doctoral Dissertation, University of Toronto. Accessed December 09, 2019. http://hdl.handle.net/1807/97003.

MLA Handbook (7th Edition):

Yazdanshenas, Sadegh. “Datacenter-optimized FPGAs.” 2019. Web. 09 Dec 2019.

Vancouver:

Yazdanshenas S. Datacenter-optimized FPGAs. [Internet] [Doctoral dissertation]. University of Toronto; 2019. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/1807/97003.

Council of Science Editors:

Yazdanshenas S. Datacenter-optimized FPGAs. [Doctoral Dissertation]. University of Toronto; 2019. Available from: http://hdl.handle.net/1807/97003

17. Guilherme Seelaender. Emulação e co-simulação do sistema de controle de atitude da PMM e do sistema eletro-hidráulico de uma aeronave usando FPGAs.

Degree: 2009, Instituto Nacional de Pesquisas Espaciais

This work addresses the different development processes that leads to the implementation of simulation and control algorithms into a FPGA. As case study two applications… (more)

Subjects/Keywords: Field programmable gate array (FPGA); fluxo de desenvolvimento; co-simulação-emulação; sistemas aeroespaciais; field programmable gate array (FPGA); development flow; co-simulation-emulation; aerospace systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Seelaender, G. (2009). Emulação e co-simulação do sistema de controle de atitude da PMM e do sistema eletro-hidráulico de uma aeronave usando FPGAs. (Thesis). Instituto Nacional de Pesquisas Espaciais. Retrieved from http://urlib.net/sid.inpe.br/[email protected]/2009/04.09.15.46

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Seelaender, Guilherme. “Emulação e co-simulação do sistema de controle de atitude da PMM e do sistema eletro-hidráulico de uma aeronave usando FPGAs.” 2009. Thesis, Instituto Nacional de Pesquisas Espaciais. Accessed December 09, 2019. http://urlib.net/sid.inpe.br/[email protected]/2009/04.09.15.46.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Seelaender, Guilherme. “Emulação e co-simulação do sistema de controle de atitude da PMM e do sistema eletro-hidráulico de uma aeronave usando FPGAs.” 2009. Web. 09 Dec 2019.

Vancouver:

Seelaender G. Emulação e co-simulação do sistema de controle de atitude da PMM e do sistema eletro-hidráulico de uma aeronave usando FPGAs. [Internet] [Thesis]. Instituto Nacional de Pesquisas Espaciais; 2009. [cited 2019 Dec 09]. Available from: http://urlib.net/sid.inpe.br/[email protected]/2009/04.09.15.46.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Seelaender G. Emulação e co-simulação do sistema de controle de atitude da PMM e do sistema eletro-hidráulico de uma aeronave usando FPGAs. [Thesis]. Instituto Nacional de Pesquisas Espaciais; 2009. Available from: http://urlib.net/sid.inpe.br/[email protected]/2009/04.09.15.46

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. Kimmitt, Jonathan R. R. A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance.

Degree: PhD, 2015, Anglia Ruskin University

 The increasing commoditization of computers in modern society has exceeded the pace of associated developments in reliability. Although theoretical computer science has advanced greatly in… (more)

Subjects/Keywords: FPGA; type-safety; fault-tolerance; self-checking; OCaml; field programmable gate array; type-preservation

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kimmitt, J. R. R. (2015). A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance. (Doctoral Dissertation). Anglia Ruskin University. Retrieved from http://hdl.handle.net/10540/581958

Chicago Manual of Style (16th Edition):

Kimmitt, Jonathan R R. “A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance.” 2015. Doctoral Dissertation, Anglia Ruskin University. Accessed December 09, 2019. http://hdl.handle.net/10540/581958.

MLA Handbook (7th Edition):

Kimmitt, Jonathan R R. “A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance.” 2015. Web. 09 Dec 2019.

Vancouver:

Kimmitt JRR. A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance. [Internet] [Doctoral dissertation]. Anglia Ruskin University; 2015. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/10540/581958.

Council of Science Editors:

Kimmitt JRR. A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance. [Doctoral Dissertation]. Anglia Ruskin University; 2015. Available from: http://hdl.handle.net/10540/581958


Universidade Estadual de Campinas

19. Chinatto Júnior, Adilson Walter. Processamento largamente linear em arranjo de antenas = proposta, avaliação e implementação prática de algoritmos .

Degree: 2011, Universidade Estadual de Campinas

 Resumo: O Processamento Largamente Linear, desenvolvido durante a década de 1990, tem levado a uma melhoria no desempenho de algoritmos adaptativos para determinadas situações que… (more)

Subjects/Keywords: Antenas ajustáveis; Processamento de sinais - Técnicas digitais; Filtros adaptativos; FPGA (Field Programmable Gate Array)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chinatto Júnior, A. W. (2011). Processamento largamente linear em arranjo de antenas = proposta, avaliação e implementação prática de algoritmos . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/259282

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chinatto Júnior, Adilson Walter. “Processamento largamente linear em arranjo de antenas = proposta, avaliação e implementação prática de algoritmos .” 2011. Thesis, Universidade Estadual de Campinas. Accessed December 09, 2019. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259282.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chinatto Júnior, Adilson Walter. “Processamento largamente linear em arranjo de antenas = proposta, avaliação e implementação prática de algoritmos .” 2011. Web. 09 Dec 2019.

Vancouver:

Chinatto Júnior AW. Processamento largamente linear em arranjo de antenas = proposta, avaliação e implementação prática de algoritmos . [Internet] [Thesis]. Universidade Estadual de Campinas; 2011. [cited 2019 Dec 09]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/259282.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chinatto Júnior AW. Processamento largamente linear em arranjo de antenas = proposta, avaliação e implementação prática de algoritmos . [Thesis]. Universidade Estadual de Campinas; 2011. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/259282

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Estadual de Campinas

20. Bernardo, Rodrigo. Desenvolvimento e prototipagem de um no de acesso para redes de chaveamento de pacotes opticos .

Degree: 2009, Universidade Estadual de Campinas

 Resumo: Este trabalho apresenta o desenvolvimento e a prototipagem de um nó de acesso utilizado como prova de conceito de redes de chaveamento de pacotes… (more)

Subjects/Keywords: Prototipagem; Hardware; Comutação de pacotes (Transmissão de dados); FPGA (Field Programmable Gate Array)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bernardo, R. (2009). Desenvolvimento e prototipagem de um no de acesso para redes de chaveamento de pacotes opticos . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/259105

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bernardo, Rodrigo. “Desenvolvimento e prototipagem de um no de acesso para redes de chaveamento de pacotes opticos .” 2009. Thesis, Universidade Estadual de Campinas. Accessed December 09, 2019. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259105.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bernardo, Rodrigo. “Desenvolvimento e prototipagem de um no de acesso para redes de chaveamento de pacotes opticos .” 2009. Web. 09 Dec 2019.

Vancouver:

Bernardo R. Desenvolvimento e prototipagem de um no de acesso para redes de chaveamento de pacotes opticos . [Internet] [Thesis]. Universidade Estadual de Campinas; 2009. [cited 2019 Dec 09]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/259105.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bernardo R. Desenvolvimento e prototipagem de um no de acesso para redes de chaveamento de pacotes opticos . [Thesis]. Universidade Estadual de Campinas; 2009. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/259105

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Estadual de Campinas

21. Okajima, Henri Shinichi de Souza. Desenvolvimento de um demodulador digital e de um ambiente de simulaçao para sistema de telemedidas .

Degree: 2010, Universidade Estadual de Campinas

 Resumo: Esta dissertação apresenta os resultados obtidos com a pesquisa e implementação de um sistema de demodulação para o receptor de rastreio de um radar… (more)

Subjects/Keywords: FPGA (Field Programmable Gate Array); Radar; Processamento de sinais - Técnicas digitais; Filtros digitais; Eletrônica digital

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Okajima, H. S. d. S. (2010). Desenvolvimento de um demodulador digital e de um ambiente de simulaçao para sistema de telemedidas . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/259487

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Okajima, Henri Shinichi de Souza. “Desenvolvimento de um demodulador digital e de um ambiente de simulaçao para sistema de telemedidas .” 2010. Thesis, Universidade Estadual de Campinas. Accessed December 09, 2019. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259487.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Okajima, Henri Shinichi de Souza. “Desenvolvimento de um demodulador digital e de um ambiente de simulaçao para sistema de telemedidas .” 2010. Web. 09 Dec 2019.

Vancouver:

Okajima HSdS. Desenvolvimento de um demodulador digital e de um ambiente de simulaçao para sistema de telemedidas . [Internet] [Thesis]. Universidade Estadual de Campinas; 2010. [cited 2019 Dec 09]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/259487.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Okajima HSdS. Desenvolvimento de um demodulador digital e de um ambiente de simulaçao para sistema de telemedidas . [Thesis]. Universidade Estadual de Campinas; 2010. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/259487

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Porto

22. Alves, Miguel Antenor Anjos Soares. Deteção coerente de sinais acústicos para localização robusta de veículos subaquáticos.

Degree: 2013, Universidade do Porto

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores - Major Telecomunicações. Faculdade de Engenharia. Universidade do Porto. 2013 Advisors/Committee Members: Alves, José Carlos dos Santos, Universidade do Porto. Faculdade de Engenharia.

Subjects/Keywords: Veículos subaquáticos; Deteção robusta e precisa de sinais acústicos; Tecnologia FPGA (Field Programmable Gate Array)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Alves, M. A. A. S. (2013). Deteção coerente de sinais acústicos para localização robusta de veículos subaquáticos. (Thesis). Universidade do Porto. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/72629

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Alves, Miguel Antenor Anjos Soares. “Deteção coerente de sinais acústicos para localização robusta de veículos subaquáticos.” 2013. Thesis, Universidade do Porto. Accessed December 09, 2019. http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/72629.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Alves, Miguel Antenor Anjos Soares. “Deteção coerente de sinais acústicos para localização robusta de veículos subaquáticos.” 2013. Web. 09 Dec 2019.

Vancouver:

Alves MAAS. Deteção coerente de sinais acústicos para localização robusta de veículos subaquáticos. [Internet] [Thesis]. Universidade do Porto; 2013. [cited 2019 Dec 09]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/72629.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Alves MAAS. Deteção coerente de sinais acústicos para localização robusta de veículos subaquáticos. [Thesis]. Universidade do Porto; 2013. Available from: http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/72629

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

23. SILVA JÚNIOR, Luis Carlos da. SynMaker: uma ferramenta de síntese de alto nível para processamento digital de imagem .

Degree: 2013, Universidade Federal de Pernambuco

 Nesta dissertação de mestrado é introduzida uma nova ferramenta de síntese de alto nível chamada SynMaker que recebe como entrada um código de alto nível… (more)

Subjects/Keywords: Síntese de alto nível; Field Programmable Gate Array; FPGA; Processamento digital de imagem

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

SILVA JÚNIOR, L. C. d. (2013). SynMaker: uma ferramenta de síntese de alto nível para processamento digital de imagem . (Thesis). Universidade Federal de Pernambuco. Retrieved from http://repositorio.ufpe.br/handle/123456789/12404

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

SILVA JÚNIOR, Luis Carlos da. “SynMaker: uma ferramenta de síntese de alto nível para processamento digital de imagem .” 2013. Thesis, Universidade Federal de Pernambuco. Accessed December 09, 2019. http://repositorio.ufpe.br/handle/123456789/12404.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

SILVA JÚNIOR, Luis Carlos da. “SynMaker: uma ferramenta de síntese de alto nível para processamento digital de imagem .” 2013. Web. 09 Dec 2019.

Vancouver:

SILVA JÚNIOR LCd. SynMaker: uma ferramenta de síntese de alto nível para processamento digital de imagem . [Internet] [Thesis]. Universidade Federal de Pernambuco; 2013. [cited 2019 Dec 09]. Available from: http://repositorio.ufpe.br/handle/123456789/12404.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

SILVA JÚNIOR LCd. SynMaker: uma ferramenta de síntese de alto nível para processamento digital de imagem . [Thesis]. Universidade Federal de Pernambuco; 2013. Available from: http://repositorio.ufpe.br/handle/123456789/12404

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Estadual de Campinas

24. Santos, Luciano Antonio Frezzatto. Planejamento de trajetórias e implementação de técnicas de posicionamento de eixos para dispositivo CNC com arquitetura de controle aberta .

Degree: 2011, Universidade Estadual de Campinas

 Resumo: Máquinas-ferramenta CNC são dispositivos complexos que executam movimentos automáticos, precisos e consistentes. Com o propósito de aprimorar o desempenho destes dispositivos face às mudanças… (more)

Subjects/Keywords: Maquinas-ferramenta; Controle em tempo real; FPGA (Field Programmable Gate Array); Robótica

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Santos, L. A. F. (2011). Planejamento de trajetórias e implementação de técnicas de posicionamento de eixos para dispositivo CNC com arquitetura de controle aberta . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/265316

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Santos, Luciano Antonio Frezzatto. “Planejamento de trajetórias e implementação de técnicas de posicionamento de eixos para dispositivo CNC com arquitetura de controle aberta .” 2011. Thesis, Universidade Estadual de Campinas. Accessed December 09, 2019. http://repositorio.unicamp.br/jspui/handle/REPOSIP/265316.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Santos, Luciano Antonio Frezzatto. “Planejamento de trajetórias e implementação de técnicas de posicionamento de eixos para dispositivo CNC com arquitetura de controle aberta .” 2011. Web. 09 Dec 2019.

Vancouver:

Santos LAF. Planejamento de trajetórias e implementação de técnicas de posicionamento de eixos para dispositivo CNC com arquitetura de controle aberta . [Internet] [Thesis]. Universidade Estadual de Campinas; 2011. [cited 2019 Dec 09]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/265316.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Santos LAF. Planejamento de trajetórias e implementação de técnicas de posicionamento de eixos para dispositivo CNC com arquitetura de controle aberta . [Thesis]. Universidade Estadual de Campinas; 2011. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/265316

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Estadual de Campinas

25. Pagano, Danilo Morais. Proposta de uma arquitetura de processamento de sinais utilizando FPGA .

Degree: 2012, Universidade Estadual de Campinas

 Resumo: Esta dissertação apresenta um sistema para processamento digital de sinais através de dispositivos de hardware reconfigurável. Uma implementação do algoritmo FFT foi adotada como… (more)

Subjects/Keywords: Processamento de sinais - Técnicas digitais; Fourier, Transformadas de; FPGA (Field Programmable Gate Array)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pagano, D. M. (2012). Proposta de uma arquitetura de processamento de sinais utilizando FPGA . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/264121

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pagano, Danilo Morais. “Proposta de uma arquitetura de processamento de sinais utilizando FPGA .” 2012. Thesis, Universidade Estadual de Campinas. Accessed December 09, 2019. http://repositorio.unicamp.br/jspui/handle/REPOSIP/264121.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pagano, Danilo Morais. “Proposta de uma arquitetura de processamento de sinais utilizando FPGA .” 2012. Web. 09 Dec 2019.

Vancouver:

Pagano DM. Proposta de uma arquitetura de processamento de sinais utilizando FPGA . [Internet] [Thesis]. Universidade Estadual de Campinas; 2012. [cited 2019 Dec 09]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/264121.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pagano DM. Proposta de uma arquitetura de processamento de sinais utilizando FPGA . [Thesis]. Universidade Estadual de Campinas; 2012. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/264121

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Estadual de Campinas

26. Sousa, Éricles Rodrigues. Arquitetura computacional híbrida baseada em DSP e FPGA para processamento digital de sinais .

Degree: 2011, Universidade Estadual de Campinas

 Resumo: Atualmente, aplicações multimídias exigem grande esforço computacional para manipular dados com elevadas taxas de precisão. Visando otimizar a capacidade de processamento sem elevar demasiadamente… (more)

Subjects/Keywords: Processamento digital de sinais; FPGA (Field Programmable Gate Array); Modelos matemáticos; Sinergia

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sousa, . R. (2011). Arquitetura computacional híbrida baseada em DSP e FPGA para processamento digital de sinais . (Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/259485

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sousa, Éricles Rodrigues. “Arquitetura computacional híbrida baseada em DSP e FPGA para processamento digital de sinais .” 2011. Thesis, Universidade Estadual de Campinas. Accessed December 09, 2019. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259485.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sousa, Éricles Rodrigues. “Arquitetura computacional híbrida baseada em DSP e FPGA para processamento digital de sinais .” 2011. Web. 09 Dec 2019.

Vancouver:

Sousa R. Arquitetura computacional híbrida baseada em DSP e FPGA para processamento digital de sinais . [Internet] [Thesis]. Universidade Estadual de Campinas; 2011. [cited 2019 Dec 09]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/259485.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sousa R. Arquitetura computacional híbrida baseada em DSP e FPGA para processamento digital de sinais . [Thesis]. Universidade Estadual de Campinas; 2011. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/259485

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

27. Bergeron, Matthew Ryan. An Improved Quadrature Direct Digital Frequency Synthesizer in an FPGA.

Degree: Electrical Engineering, 2013, UCLA

 The architecture and design of a high-speed quadrature direct digital frequency synthesizer (DDFS) is presented. The architecture is based on a novel multiplier-based angle-rotation algorithm… (more)

Subjects/Keywords: Electrical engineering; angle rotation; Direct Digital Frequency Synthesizer (DDFS); Field Programmable Gate Array (FPGA)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bergeron, M. R. (2013). An Improved Quadrature Direct Digital Frequency Synthesizer in an FPGA. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/9nd0h13k

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bergeron, Matthew Ryan. “An Improved Quadrature Direct Digital Frequency Synthesizer in an FPGA.” 2013. Thesis, UCLA. Accessed December 09, 2019. http://www.escholarship.org/uc/item/9nd0h13k.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bergeron, Matthew Ryan. “An Improved Quadrature Direct Digital Frequency Synthesizer in an FPGA.” 2013. Web. 09 Dec 2019.

Vancouver:

Bergeron MR. An Improved Quadrature Direct Digital Frequency Synthesizer in an FPGA. [Internet] [Thesis]. UCLA; 2013. [cited 2019 Dec 09]. Available from: http://www.escholarship.org/uc/item/9nd0h13k.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bergeron MR. An Improved Quadrature Direct Digital Frequency Synthesizer in an FPGA. [Thesis]. UCLA; 2013. Available from: http://www.escholarship.org/uc/item/9nd0h13k

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

28. Kimmitt, Jonathan R. R. A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance.

Degree: PhD, 2015, Anglia Ruskin University

 The increasing commoditization of computers in modern society has exceeded the pace of associated developments in reliability. Although theoretical computer science has advanced greatly in… (more)

Subjects/Keywords: 004.2; FPGA; type-safety; fault-tolerance; self-checking; OCaml; field programmable gate array; type-preservation

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kimmitt, J. R. R. (2015). A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance. (Doctoral Dissertation). Anglia Ruskin University. Retrieved from http://arro.anglia.ac.uk/581958/ ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.675601

Chicago Manual of Style (16th Edition):

Kimmitt, Jonathan R R. “A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance.” 2015. Doctoral Dissertation, Anglia Ruskin University. Accessed December 09, 2019. http://arro.anglia.ac.uk/581958/ ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.675601.

MLA Handbook (7th Edition):

Kimmitt, Jonathan R R. “A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance.” 2015. Web. 09 Dec 2019.

Vancouver:

Kimmitt JRR. A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance. [Internet] [Doctoral dissertation]. Anglia Ruskin University; 2015. [cited 2019 Dec 09]. Available from: http://arro.anglia.ac.uk/581958/ ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.675601.

Council of Science Editors:

Kimmitt JRR. A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance. [Doctoral Dissertation]. Anglia Ruskin University; 2015. Available from: http://arro.anglia.ac.uk/581958/ ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.675601


Vilnius Gediminas Technical University

29. Arminas, Vytautas. MicroBlaze programinio procesoriaus įgyvendinimo tyrimas.

Degree: Master, Informatics Engineering, 2010, Vilnius Gediminas Technical University

Magistro studijų baigiamajame darbe pateikiamas atliktas lauku programuojamų loginių matricų gamintojos Xilinx kompanijos MicroBlaze programinio procesoriaus tyrimas. Tyrimas vykdytas sėkmingai baigtuose 2008 ir 2009 metais… (more)

Subjects/Keywords: MicroBlaze; LPLM; Lauku programuojama loginė matrica; MicroBlaze; FPGA; Field Programmable Gate Array

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Arminas, Vytautas. (2010). MicroBlaze programinio procesoriaus įgyvendinimo tyrimas. (Masters Thesis). Vilnius Gediminas Technical University. Retrieved from http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100619_142408-89771 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

Arminas, Vytautas. “MicroBlaze programinio procesoriaus įgyvendinimo tyrimas.” 2010. Masters Thesis, Vilnius Gediminas Technical University. Accessed December 09, 2019. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100619_142408-89771 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

Arminas, Vytautas. “MicroBlaze programinio procesoriaus įgyvendinimo tyrimas.” 2010. Web. 09 Dec 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

Arminas, Vytautas. MicroBlaze programinio procesoriaus įgyvendinimo tyrimas. [Internet] [Masters thesis]. Vilnius Gediminas Technical University; 2010. [cited 2019 Dec 09]. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100619_142408-89771 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

Arminas, Vytautas. MicroBlaze programinio procesoriaus įgyvendinimo tyrimas. [Masters Thesis]. Vilnius Gediminas Technical University; 2010. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100619_142408-89771 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


Delft University of Technology

30. Kranenburg, T. Design of a Portable and Customizable Microprocessor for Rapid System Prototyping:.

Degree: 2009, Delft University of Technology

 Due to the increasing number of processors which are integrated in System On Chips (SOCs) the need for robust, highly configurable processors emerged. Preliminary research… (more)

Subjects/Keywords: microprocessor; system on chip; Field Programmable Gate Array (FPGA); microblaze; MB-lite; VHDL

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kranenburg, T. (2009). Design of a Portable and Customizable Microprocessor for Rapid System Prototyping:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:6f6b3972-c290-45eb-8b77-617129cacdac

Chicago Manual of Style (16th Edition):

Kranenburg, T. “Design of a Portable and Customizable Microprocessor for Rapid System Prototyping:.” 2009. Masters Thesis, Delft University of Technology. Accessed December 09, 2019. http://resolver.tudelft.nl/uuid:6f6b3972-c290-45eb-8b77-617129cacdac.

MLA Handbook (7th Edition):

Kranenburg, T. “Design of a Portable and Customizable Microprocessor for Rapid System Prototyping:.” 2009. Web. 09 Dec 2019.

Vancouver:

Kranenburg T. Design of a Portable and Customizable Microprocessor for Rapid System Prototyping:. [Internet] [Masters thesis]. Delft University of Technology; 2009. [cited 2019 Dec 09]. Available from: http://resolver.tudelft.nl/uuid:6f6b3972-c290-45eb-8b77-617129cacdac.

Council of Science Editors:

Kranenburg T. Design of a Portable and Customizable Microprocessor for Rapid System Prototyping:. [Masters Thesis]. Delft University of Technology; 2009. Available from: http://resolver.tudelft.nl/uuid:6f6b3972-c290-45eb-8b77-617129cacdac

[1] [2] [3] [4] [5] … [726]

.