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You searched for subject:(Field Programmable Gate Array FPGA ). Showing records 1 – 30 of 23641 total matches.

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Universidade Estadual de Campinas

1. Garcia Urdaneta, Daniel, 1982-. Fast Fourier transform implementation and integer carrier frequency offset estimation for the IEEE802.15.4g Standard : Implementação da transformada rápida de Fourier e estimador de error de frequência para a norma IEEE802.15.4g.

Degree: Faculdade de Engenharia Elétrica e de Computação; Programa de Pós-Graduação em Engenharia Elétrica, 2019, Universidade Estadual de Campinas

Orientadores: Luis Geraldo Pedroso Meloni, Eduardo Rodrigues de Lima

Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação

Made available… (more)

Subjects/Keywords: FPGA (Field Programmable Gate Array); Fourier, Transformadas de; FPGA (Field Programmable Gate Array); Fourier transform

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Garcia Urdaneta, Daniel, 1. (2019). Fast Fourier transform implementation and integer carrier frequency offset estimation for the IEEE802.15.4g Standard : Implementação da transformada rápida de Fourier e estimador de error de frequência para a norma IEEE802.15.4g. (Masters Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/334773

Chicago Manual of Style (16th Edition):

Garcia Urdaneta, Daniel, 1982-. “Fast Fourier transform implementation and integer carrier frequency offset estimation for the IEEE802.15.4g Standard : Implementação da transformada rápida de Fourier e estimador de error de frequência para a norma IEEE802.15.4g.” 2019. Masters Thesis, Universidade Estadual de Campinas. Accessed April 11, 2021. http://repositorio.unicamp.br/jspui/handle/REPOSIP/334773.

MLA Handbook (7th Edition):

Garcia Urdaneta, Daniel, 1982-. “Fast Fourier transform implementation and integer carrier frequency offset estimation for the IEEE802.15.4g Standard : Implementação da transformada rápida de Fourier e estimador de error de frequência para a norma IEEE802.15.4g.” 2019. Web. 11 Apr 2021.

Vancouver:

Garcia Urdaneta, Daniel 1. Fast Fourier transform implementation and integer carrier frequency offset estimation for the IEEE802.15.4g Standard : Implementação da transformada rápida de Fourier e estimador de error de frequência para a norma IEEE802.15.4g. [Internet] [Masters thesis]. Universidade Estadual de Campinas; 2019. [cited 2021 Apr 11]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/334773.

Council of Science Editors:

Garcia Urdaneta, Daniel 1. Fast Fourier transform implementation and integer carrier frequency offset estimation for the IEEE802.15.4g Standard : Implementação da transformada rápida de Fourier e estimador de error de frequência para a norma IEEE802.15.4g. [Masters Thesis]. Universidade Estadual de Campinas; 2019. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/334773

2. Turki, Mariem. Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform.

Degree: Docteur es, Informatique et Micro-Electronique, 2014, Université Pierre et Marie Curie – Paris VI

De nos jours, la complexité de la conception des circuits intégrés et du logiciel croit régulièrement, faisant croître le besoin de la vérification dans chaque… (more)

Subjects/Keywords: FPGA (Field Programmable Gate Array); Prototypage; Routage; Pathfinder; Itératif; Multiplexage; FPGA (Field Programmable Gate Array); Prototyping; 005.18

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APA (6th Edition):

Turki, M. (2014). Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform. (Doctoral Dissertation). Université Pierre et Marie Curie – Paris VI. Retrieved from http://www.theses.fr/2014PA066698

Chicago Manual of Style (16th Edition):

Turki, Mariem. “Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform.” 2014. Doctoral Dissertation, Université Pierre et Marie Curie – Paris VI. Accessed April 11, 2021. http://www.theses.fr/2014PA066698.

MLA Handbook (7th Edition):

Turki, Mariem. “Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform.” 2014. Web. 11 Apr 2021.

Vancouver:

Turki M. Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform. [Internet] [Doctoral dissertation]. Université Pierre et Marie Curie – Paris VI; 2014. [cited 2021 Apr 11]. Available from: http://www.theses.fr/2014PA066698.

Council of Science Editors:

Turki M. Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA : Multiplexing techniques for FPGA-based emulation and prototyping platform. [Doctoral Dissertation]. Université Pierre et Marie Curie – Paris VI; 2014. Available from: http://www.theses.fr/2014PA066698


McMaster University

3. Zuzarte, Marvin. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.

Degree: MASc, 2014, McMaster University

Safety and mission critical systems are currently deployed in many different fields where there is a greater presence of high energy particles (e.g. aerospace). The… (more)

Subjects/Keywords: FPGA; Fault injection; Field programmable gate array; runtime; soft error

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APA (6th Edition):

Zuzarte, M. (2014). A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. (Masters Thesis). McMaster University. Retrieved from http://hdl.handle.net/11375/16500

Chicago Manual of Style (16th Edition):

Zuzarte, Marvin. “A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.” 2014. Masters Thesis, McMaster University. Accessed April 11, 2021. http://hdl.handle.net/11375/16500.

MLA Handbook (7th Edition):

Zuzarte, Marvin. “A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.” 2014. Web. 11 Apr 2021.

Vancouver:

Zuzarte M. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. [Internet] [Masters thesis]. McMaster University; 2014. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/11375/16500.

Council of Science Editors:

Zuzarte M. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. [Masters Thesis]. McMaster University; 2014. Available from: http://hdl.handle.net/11375/16500


Victoria University of Wellington

4. Ang, Andrew. Development of an Open PXIe System based on FPGA Modules.

Degree: 2018, Victoria University of Wellington

 PXIe is a instrumentation platform that is used as the basis for developing test equipment, modular electronic instruments and automated test systems. A typical PXIe… (more)

Subjects/Keywords: FPGA; PXIe; Electronics; PCI eXtensions for Instrumentation; Field Programmable Gate Array

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ang, A. (2018). Development of an Open PXIe System based on FPGA Modules. (Masters Thesis). Victoria University of Wellington. Retrieved from http://hdl.handle.net/10063/7653

Chicago Manual of Style (16th Edition):

Ang, Andrew. “Development of an Open PXIe System based on FPGA Modules.” 2018. Masters Thesis, Victoria University of Wellington. Accessed April 11, 2021. http://hdl.handle.net/10063/7653.

MLA Handbook (7th Edition):

Ang, Andrew. “Development of an Open PXIe System based on FPGA Modules.” 2018. Web. 11 Apr 2021.

Vancouver:

Ang A. Development of an Open PXIe System based on FPGA Modules. [Internet] [Masters thesis]. Victoria University of Wellington; 2018. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10063/7653.

Council of Science Editors:

Ang A. Development of an Open PXIe System based on FPGA Modules. [Masters Thesis]. Victoria University of Wellington; 2018. Available from: http://hdl.handle.net/10063/7653


Bucknell University

5. Su, Juliana. Design and Development of an FPGA-based Distributed Computing Processing Platform.

Degree: 2011, Bucknell University

 This thesis presents two frameworks- a software framework and a hardware core manager framework- which, together, can be used to develop a processing platform using… (more)

Subjects/Keywords: field-programmable gate array; FPGA; distributed computing; reconfigurable computing; processing platform

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APA (6th Edition):

Su, J. (2011). Design and Development of an FPGA-based Distributed Computing Processing Platform. (Thesis). Bucknell University. Retrieved from https://digitalcommons.bucknell.edu/masters_theses/38

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Su, Juliana. “Design and Development of an FPGA-based Distributed Computing Processing Platform.” 2011. Thesis, Bucknell University. Accessed April 11, 2021. https://digitalcommons.bucknell.edu/masters_theses/38.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Su, Juliana. “Design and Development of an FPGA-based Distributed Computing Processing Platform.” 2011. Web. 11 Apr 2021.

Vancouver:

Su J. Design and Development of an FPGA-based Distributed Computing Processing Platform. [Internet] [Thesis]. Bucknell University; 2011. [cited 2021 Apr 11]. Available from: https://digitalcommons.bucknell.edu/masters_theses/38.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Su J. Design and Development of an FPGA-based Distributed Computing Processing Platform. [Thesis]. Bucknell University; 2011. Available from: https://digitalcommons.bucknell.edu/masters_theses/38

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Chicago

6. Mastinu, Matteo. Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures.

Degree: 2013, University of Illinois – Chicago

 This work addresses the Maxeler Technologies Ltd. platforms, and the principal goal of this work is to design a new methodology to support Partial Reconfiguration… (more)

Subjects/Keywords: Maxeler; Field-Programmable Gate Array (FPGA); Partial Reconfiguration

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APA (6th Edition):

Mastinu, M. (2013). Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/10018

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mastinu, Matteo. “Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures.” 2013. Thesis, University of Illinois – Chicago. Accessed April 11, 2021. http://hdl.handle.net/10027/10018.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mastinu, Matteo. “Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures.” 2013. Web. 11 Apr 2021.

Vancouver:

Mastinu M. Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures. [Internet] [Thesis]. University of Illinois – Chicago; 2013. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10027/10018.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mastinu M. Design Flow to Support Dynamic Partial Reconfiguration on Maxeler Architectures. [Thesis]. University of Illinois – Chicago; 2013. Available from: http://hdl.handle.net/10027/10018

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

7. Yazdanshenas, Sadegh. Datacenter-optimized FPGAs.

Degree: PhD, 2019, University of Toronto

 Large-scale deployment of field-programmable gate arrays (FPGAs) into datacenters has introduced new use cases that utilize the FPGA as a multi-user compute platform, require more… (more)

Subjects/Keywords: Datacenter; Field-programmable Gate Array; FPGA Architecture; 0464

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APA (6th Edition):

Yazdanshenas, S. (2019). Datacenter-optimized FPGAs. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/97003

Chicago Manual of Style (16th Edition):

Yazdanshenas, Sadegh. “Datacenter-optimized FPGAs.” 2019. Doctoral Dissertation, University of Toronto. Accessed April 11, 2021. http://hdl.handle.net/1807/97003.

MLA Handbook (7th Edition):

Yazdanshenas, Sadegh. “Datacenter-optimized FPGAs.” 2019. Web. 11 Apr 2021.

Vancouver:

Yazdanshenas S. Datacenter-optimized FPGAs. [Internet] [Doctoral dissertation]. University of Toronto; 2019. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1807/97003.

Council of Science Editors:

Yazdanshenas S. Datacenter-optimized FPGAs. [Doctoral Dissertation]. University of Toronto; 2019. Available from: http://hdl.handle.net/1807/97003


University of Illinois – Urbana-Champaign

8. Tolar, Jacob. A directory enhanced network on chip for FPGA.

Degree: MS, 1200, 2013, University of Illinois – Urbana-Champaign

 This thesis presents and evaluates a directory enhanced network on chip for FPGA, with the goal of improving the performance of cores generated by FCUDA,… (more)

Subjects/Keywords: Network on Chip; Field-Programmable Gate Array (FPGA); FCUDA

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APA (6th Edition):

Tolar, J. (2013). A directory enhanced network on chip for FPGA. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/44439

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tolar, Jacob. “A directory enhanced network on chip for FPGA.” 2013. Thesis, University of Illinois – Urbana-Champaign. Accessed April 11, 2021. http://hdl.handle.net/2142/44439.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tolar, Jacob. “A directory enhanced network on chip for FPGA.” 2013. Web. 11 Apr 2021.

Vancouver:

Tolar J. A directory enhanced network on chip for FPGA. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2013. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2142/44439.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tolar J. A directory enhanced network on chip for FPGA. [Thesis]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/44439

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

9. Li, Shuo. Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA).

Degree: MS, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 Direct digital synthesis is a technique for using digital data processing blocks as a means to generate a frequency and phase tunable output signal referenced… (more)

Subjects/Keywords: direct digital synthesizer (DDS); Field-Programmable Gate Array (FPGA); digital design

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APA (6th Edition):

Li, S. (2015). Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA). (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78598

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Shuo. “Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA).” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed April 11, 2021. http://hdl.handle.net/2142/78598.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Shuo. “Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA).” 2015. Web. 11 Apr 2021.

Vancouver:

Li S. Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA). [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2142/78598.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li S. Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA). [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78598

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

10. Xia, Tian. FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition.

Degree: MS, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 Despite the recent success of neural network in the research eld, the num- ber of resulting applications for non-academic settings is very limited. One setback… (more)

Subjects/Keywords: Field-Programmable Gate Array (FPGA); Restricted Boltzmann Machine (RBM)

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APA (6th Edition):

Xia, T. (2015). FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78800

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xia, Tian. “FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed April 11, 2021. http://hdl.handle.net/2142/78800.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xia, Tian. “FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition.” 2015. Web. 11 Apr 2021.

Vancouver:

Xia T. FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2142/78800.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xia T. FPGA implementation of a Restricted Boltzmann Machine for handwriting recognition. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78800

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Jadeglans, Tim. FPGA-implementation av ett neuralt nätverk .

Degree: Chalmers tekniska högskola / Institutionen för data och informationsteknik, 2019, Chalmers University of Technology

 Image recognition is a quickly growing field where convolutional neural networks, CNN, are in the bleeding edge. Today fast GPUs are used which consume a… (more)

Subjects/Keywords: Convolutional Neural Network; CNN; Field Programmable Gate Array; FPGA; Image Recognition

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APA (6th Edition):

Jadeglans, T. (2019). FPGA-implementation av ett neuralt nätverk . (Thesis). Chalmers University of Technology. Retrieved from http://hdl.handle.net/20.500.12380/300036

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jadeglans, Tim. “FPGA-implementation av ett neuralt nätverk .” 2019. Thesis, Chalmers University of Technology. Accessed April 11, 2021. http://hdl.handle.net/20.500.12380/300036.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jadeglans, Tim. “FPGA-implementation av ett neuralt nätverk .” 2019. Web. 11 Apr 2021.

Vancouver:

Jadeglans T. FPGA-implementation av ett neuralt nätverk . [Internet] [Thesis]. Chalmers University of Technology; 2019. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/20.500.12380/300036.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jadeglans T. FPGA-implementation av ett neuralt nätverk . [Thesis]. Chalmers University of Technology; 2019. Available from: http://hdl.handle.net/20.500.12380/300036

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

12. Leiva Cochachin, Andrés Mijail. Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA.

Degree: 2012, Universidad Nacional de Ingeniería

 En la presente tesis se explica la metodología utilizada en el diseño e implementación de una solución integral (un módulo de captura de paquetes IP… (more)

Subjects/Keywords: Red Ethernet; Módulo de captura; FPGA (Field Programmable Gate Array)

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APA (6th Edition):

Leiva Cochachin, A. M. (2012). Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA. (Thesis). Universidad Nacional de Ingeniería. Retrieved from http://cybertesis.uni.edu.pe/handle/uni/1325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Leiva Cochachin, Andrés Mijail. “Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA.” 2012. Thesis, Universidad Nacional de Ingeniería. Accessed April 11, 2021. http://cybertesis.uni.edu.pe/handle/uni/1325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Leiva Cochachin, Andrés Mijail. “Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA.” 2012. Web. 11 Apr 2021.

Vancouver:

Leiva Cochachin AM. Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA. [Internet] [Thesis]. Universidad Nacional de Ingeniería; 2012. [cited 2021 Apr 11]. Available from: http://cybertesis.uni.edu.pe/handle/uni/1325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Leiva Cochachin AM. Determinación de indicadores de la producción de servicios de una Red Ethernet utilizando un módulo de captura de paquetes IP basado en FPGA. [Thesis]. Universidad Nacional de Ingeniería; 2012. Available from: http://cybertesis.uni.edu.pe/handle/uni/1325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Estadual de Campinas

13. Queiroz, Augusto Fernandes Ribas, 1989-. Implementation of a secure code execution architecture using PUFs : Implementação de uma arquitetura para execução segura de código utilizando PUFs.

Degree: Instituto de Computação; Programa de Pós-Graduação em Ciência da Computação, 2019, Universidade Estadual de Campinas

Orientador: Guido Costa Souza de Araújo

Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação

Made available in DSpace on 2019-09-18T20:13:54Z (GMT). No. of… (more)

Subjects/Keywords: FPGA (Field Programmable Gate Array); Computadores - Medidas de segurança; Hardware - Arquitetura; Field Programmable Gate Array; Computer security; Hardware - Architecture

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APA (6th Edition):

Queiroz, Augusto Fernandes Ribas, 1. (2019). Implementation of a secure code execution architecture using PUFs : Implementação de uma arquitetura para execução segura de código utilizando PUFs. (Masters Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/335016

Chicago Manual of Style (16th Edition):

Queiroz, Augusto Fernandes Ribas, 1989-. “Implementation of a secure code execution architecture using PUFs : Implementação de uma arquitetura para execução segura de código utilizando PUFs.” 2019. Masters Thesis, Universidade Estadual de Campinas. Accessed April 11, 2021. http://repositorio.unicamp.br/jspui/handle/REPOSIP/335016.

MLA Handbook (7th Edition):

Queiroz, Augusto Fernandes Ribas, 1989-. “Implementation of a secure code execution architecture using PUFs : Implementação de uma arquitetura para execução segura de código utilizando PUFs.” 2019. Web. 11 Apr 2021.

Vancouver:

Queiroz, Augusto Fernandes Ribas 1. Implementation of a secure code execution architecture using PUFs : Implementação de uma arquitetura para execução segura de código utilizando PUFs. [Internet] [Masters thesis]. Universidade Estadual de Campinas; 2019. [cited 2021 Apr 11]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/335016.

Council of Science Editors:

Queiroz, Augusto Fernandes Ribas 1. Implementation of a secure code execution architecture using PUFs : Implementação de uma arquitetura para execução segura de código utilizando PUFs. [Masters Thesis]. Universidade Estadual de Campinas; 2019. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/335016


Universidade Estadual de Campinas

14. Américo Filho, Júlio Cesar Soares, 1987-. Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128.

Degree: Faculdade de Engenharia Elétrica e de Computação; Programa de Pós-Graduação em Engenharia Elétrica, 2016, Universidade Estadual de Campinas

Orientador: Luís Geraldo Pedroso Meloni

Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação

Made available in DSpace on 2018-09-01T05:13:48Z… (more)

Subjects/Keywords: Algoritmos; Hardware - Arquitetura; Computadores canalizados; Criptografia; FPGA (Field Programmable Gate Array); Algorithms; Hardware - Architecture; Channeled computers; Encryption; FPGA (Field Programmable Gate Array)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Américo Filho, Júlio Cesar Soares, 1. (2016). Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128. (Masters Thesis). Universidade Estadual de Campinas. Retrieved from AMÉRICO FILHO, Júlio Cesar Soares. Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128. 2016. 1 recurso online (92 p.). Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação, Campinas, SP. Disponível em: <http://www.repositorio.unicamp.br/handle/REPOSIP/321942>. Acesso em: 1 set. 2018. ; http://repositorio.unicamp.br/jspui/handle/REPOSIP/321942

Chicago Manual of Style (16th Edition):

Américo Filho, Júlio Cesar Soares, 1987-. “Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128.” 2016. Masters Thesis, Universidade Estadual de Campinas. Accessed April 11, 2021. AMÉRICO FILHO, Júlio Cesar Soares. Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128. 2016. 1 recurso online (92 p.). Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação, Campinas, SP. Disponível em: <http://www.repositorio.unicamp.br/handle/REPOSIP/321942>. Acesso em: 1 set. 2018. ; http://repositorio.unicamp.br/jspui/handle/REPOSIP/321942.

MLA Handbook (7th Edition):

Américo Filho, Júlio Cesar Soares, 1987-. “Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128.” 2016. Web. 11 Apr 2021.

Vancouver:

Américo Filho, Júlio Cesar Soares 1. Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128. [Internet] [Masters thesis]. Universidade Estadual de Campinas; 2016. [cited 2021 Apr 11]. Available from: AMÉRICO FILHO, Júlio Cesar Soares. Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128. 2016. 1 recurso online (92 p.). Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação, Campinas, SP. Disponível em: <http://www.repositorio.unicamp.br/handle/REPOSIP/321942>. Acesso em: 1 set. 2018. ; http://repositorio.unicamp.br/jspui/handle/REPOSIP/321942.

Council of Science Editors:

Américo Filho, Júlio Cesar Soares 1. Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128. [Masters Thesis]. Universidade Estadual de Campinas; 2016. Available from: AMÉRICO FILHO, Júlio Cesar Soares. Análise e implementação de uma arquitetura iterativa com "sub-pipelining" de estágios e "datapath" de 32 bits para um co-processador AES-128. 2016. 1 recurso online (92 p.). Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação, Campinas, SP. Disponível em: <http://www.repositorio.unicamp.br/handle/REPOSIP/321942>. Acesso em: 1 set. 2018. ; http://repositorio.unicamp.br/jspui/handle/REPOSIP/321942


Universidade do Porto

15. Alves, Miguel Antenor Anjos Soares. Deteção coerente de sinais acústicos para localização robusta de veículos subaquáticos.

Degree: 2013, Universidade do Porto

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores - Major Telecomunicações. Faculdade de Engenharia. Universidade do Porto. 2013 Advisors/Committee Members: Alves, José Carlos dos Santos, Universidade do Porto. Faculdade de Engenharia.

Subjects/Keywords: Veículos subaquáticos; Deteção robusta e precisa de sinais acústicos; Tecnologia FPGA (Field Programmable Gate Array)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Alves, M. A. A. S. (2013). Deteção coerente de sinais acústicos para localização robusta de veículos subaquáticos. (Thesis). Universidade do Porto. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/72629

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Alves, Miguel Antenor Anjos Soares. “Deteção coerente de sinais acústicos para localização robusta de veículos subaquáticos.” 2013. Thesis, Universidade do Porto. Accessed April 11, 2021. http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/72629.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Alves, Miguel Antenor Anjos Soares. “Deteção coerente de sinais acústicos para localização robusta de veículos subaquáticos.” 2013. Web. 11 Apr 2021.

Vancouver:

Alves MAAS. Deteção coerente de sinais acústicos para localização robusta de veículos subaquáticos. [Internet] [Thesis]. Universidade do Porto; 2013. [cited 2021 Apr 11]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/72629.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Alves MAAS. Deteção coerente de sinais acústicos para localização robusta de veículos subaquáticos. [Thesis]. Universidade do Porto; 2013. Available from: http://www.rcaap.pt/detail.jsp?id=oai:repositorio-aberto.up.pt:10216/72629

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

16. Bergeron, Matthew Ryan. An Improved Quadrature Direct Digital Frequency Synthesizer in an FPGA.

Degree: Electrical Engineering, 2013, UCLA

 The architecture and design of a high-speed quadrature direct digital frequency synthesizer (DDFS) is presented. The architecture is based on a novel multiplier-based angle-rotation algorithm… (more)

Subjects/Keywords: Electrical engineering; angle rotation; Direct Digital Frequency Synthesizer (DDFS); Field Programmable Gate Array (FPGA)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bergeron, M. R. (2013). An Improved Quadrature Direct Digital Frequency Synthesizer in an FPGA. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/9nd0h13k

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bergeron, Matthew Ryan. “An Improved Quadrature Direct Digital Frequency Synthesizer in an FPGA.” 2013. Thesis, UCLA. Accessed April 11, 2021. http://www.escholarship.org/uc/item/9nd0h13k.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bergeron, Matthew Ryan. “An Improved Quadrature Direct Digital Frequency Synthesizer in an FPGA.” 2013. Web. 11 Apr 2021.

Vancouver:

Bergeron MR. An Improved Quadrature Direct Digital Frequency Synthesizer in an FPGA. [Internet] [Thesis]. UCLA; 2013. [cited 2021 Apr 11]. Available from: http://www.escholarship.org/uc/item/9nd0h13k.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bergeron MR. An Improved Quadrature Direct Digital Frequency Synthesizer in an FPGA. [Thesis]. UCLA; 2013. Available from: http://www.escholarship.org/uc/item/9nd0h13k

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

17. Hashem, Amjad Qusay. ALU and Dependency Manager Using FPGA.

Degree: MSin Engineering, Computer Engineering, College of Engineering & Computer Science, 2020, University of Michigan

 In this project, we have researched the design of high-speed processing units through parallel processing scheme. Our design will be used for Real – Time… (more)

Subjects/Keywords: ALU; Arithmetic logic unit; Dependency manager; FPGA; Field Programmable Gate Array; Parallel processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hashem, A. Q. (2020). ALU and Dependency Manager Using FPGA. (Masters Thesis). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/155349

Chicago Manual of Style (16th Edition):

Hashem, Amjad Qusay. “ALU and Dependency Manager Using FPGA.” 2020. Masters Thesis, University of Michigan. Accessed April 11, 2021. http://hdl.handle.net/2027.42/155349.

MLA Handbook (7th Edition):

Hashem, Amjad Qusay. “ALU and Dependency Manager Using FPGA.” 2020. Web. 11 Apr 2021.

Vancouver:

Hashem AQ. ALU and Dependency Manager Using FPGA. [Internet] [Masters thesis]. University of Michigan; 2020. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2027.42/155349.

Council of Science Editors:

Hashem AQ. ALU and Dependency Manager Using FPGA. [Masters Thesis]. University of Michigan; 2020. Available from: http://hdl.handle.net/2027.42/155349


University of Newcastle

18. Dalton, John. A reconfigurable prototyping system for multiple-input multiple-output communications.

Degree: MIMO) communications over-the-air. It covers the entire process, from concept to design and construction, culminating in transmitting space-time coded data packets and producing bit error rate (BER) performance curves. A flexible modular architecture is designed, able to test current MIMO systems and to be upgraded as the field develops. Printed circuit boards for a field-programmable gate array (FPGA) based mainboard, 2.4 GHz transceivers and antennas are then designed, embodying the aforementioned architecture. The mainboard uses a Xilinx XC2S600E FPGA, with ∼600,000 logic gates. Hardware is assembled and tested, forming a foundation for further layers of firmware and software. An abstraction layer, with associated test benches, is written in a hardware description language (VHDL), allowing the core logic of the FPGA to be written and simulated in a device-independent manner. Further VHDL is written and the testbed configured to transmit and receive bursts of data. A device driver is implemented, and abstract data types are layered on top of the driver, enabling high-level control of the testbed. Single antenna and MIMO data links are implemented using 1x1 binary phase-shift keying (BPSK, transmitting space-time coded data packets and producing bit error rate (BER) performance curves. A flexible modular architecture is designed, able to test current MIMO systems and to be upgraded as the field develops. Printed circuit boards for a field-programmable gate array (FPGA) based mainboard, 2.4 GHz transceivers and antennas are then designed, embodying the aforementioned architecture. The mainboard uses a Xilinx XC2S600E FPGA, with ∼600,000 logic gates. Hardware is assembled and tested, forming a foundation for further layers of firmware and software. An abstraction layer, with associated test benches, is written in a hardware description language (VHDL), allowing the core logic of the FPGA to be written and simulated in a device-independent manner. Further VHDL is written and the testbed configured to transmit and receive bursts of data. A device driver is implemented, and abstract data types are layered on top of the driver, enabling high-level control of the testbed. Single antenna and MIMO data links are implemented using 1x1 binary phase-shift keying (BPSK, 2009, University of Newcastle

Masters Research - Master of Engineering

This thesis demonstrates the process of building a system to test multiple-input multiple-output (MIMO) communications over-the-air. It covers the… (more)

Subjects/Keywords: FPGA; field programmable gate array; smart antenna communications; MIMO; multiple-input mulitiple-output

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APA (6th Edition):

Dalton, J. (2009). A reconfigurable prototyping system for multiple-input multiple-output communications. (Masters Thesis). University of Newcastle. Retrieved from http://hdl.handle.net/1959.13/41758

Chicago Manual of Style (16th Edition):

Dalton, John. “A reconfigurable prototyping system for multiple-input multiple-output communications.” 2009. Masters Thesis, University of Newcastle. Accessed April 11, 2021. http://hdl.handle.net/1959.13/41758.

MLA Handbook (7th Edition):

Dalton, John. “A reconfigurable prototyping system for multiple-input multiple-output communications.” 2009. Web. 11 Apr 2021.

Vancouver:

Dalton J. A reconfigurable prototyping system for multiple-input multiple-output communications. [Internet] [Masters thesis]. University of Newcastle; 2009. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1959.13/41758.

Council of Science Editors:

Dalton J. A reconfigurable prototyping system for multiple-input multiple-output communications. [Masters Thesis]. University of Newcastle; 2009. Available from: http://hdl.handle.net/1959.13/41758

19. Swientek, Stefan. A data processing firmware for an upgrade of the Outer Tracker detector at the LHCb experiment.

Degree: 2015, Technische Universität Dortmund

 This thesis describes the data processing software for an Outer Tracker upgrade at the LHCb experiment. The 2018/19 intended upgrade for the LHCb detector will… (more)

Subjects/Keywords: LHC; LHCb; FPGA; Outer Tracker; Upgrade; Firmware; 530; LHC; Detektor; Field programmable gate array

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APA (6th Edition):

Swientek, S. (2015). A data processing firmware for an upgrade of the Outer Tracker detector at the LHCb experiment. (Doctoral Dissertation). Technische Universität Dortmund. Retrieved from http://dx.doi.org/10.17877/DE290R-7448

Chicago Manual of Style (16th Edition):

Swientek, Stefan. “A data processing firmware for an upgrade of the Outer Tracker detector at the LHCb experiment.” 2015. Doctoral Dissertation, Technische Universität Dortmund. Accessed April 11, 2021. http://dx.doi.org/10.17877/DE290R-7448.

MLA Handbook (7th Edition):

Swientek, Stefan. “A data processing firmware for an upgrade of the Outer Tracker detector at the LHCb experiment.” 2015. Web. 11 Apr 2021.

Vancouver:

Swientek S. A data processing firmware for an upgrade of the Outer Tracker detector at the LHCb experiment. [Internet] [Doctoral dissertation]. Technische Universität Dortmund; 2015. [cited 2021 Apr 11]. Available from: http://dx.doi.org/10.17877/DE290R-7448.

Council of Science Editors:

Swientek S. A data processing firmware for an upgrade of the Outer Tracker detector at the LHCb experiment. [Doctoral Dissertation]. Technische Universität Dortmund; 2015. Available from: http://dx.doi.org/10.17877/DE290R-7448


Vilnius Gediminas Technical University

20. Arminas, Vytautas. MicroBlaze programinio procesoriaus įgyvendinimo tyrimas.

Degree: Master, Informatics Engineering, 2010, Vilnius Gediminas Technical University

Magistro studijų baigiamajame darbe pateikiamas atliktas lauku programuojamų loginių matricų gamintojos Xilinx kompanijos MicroBlaze programinio procesoriaus tyrimas. Tyrimas vykdytas sėkmingai baigtuose 2008 ir 2009 metais… (more)

Subjects/Keywords: MicroBlaze; LPLM; Lauku programuojama loginė matrica; MicroBlaze; FPGA; Field Programmable Gate Array

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APA (6th Edition):

Arminas, Vytautas. (2010). MicroBlaze programinio procesoriaus įgyvendinimo tyrimas. (Masters Thesis). Vilnius Gediminas Technical University. Retrieved from http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100619_142408-89771 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

Arminas, Vytautas. “MicroBlaze programinio procesoriaus įgyvendinimo tyrimas.” 2010. Masters Thesis, Vilnius Gediminas Technical University. Accessed April 11, 2021. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100619_142408-89771 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

Arminas, Vytautas. “MicroBlaze programinio procesoriaus įgyvendinimo tyrimas.” 2010. Web. 11 Apr 2021.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

Arminas, Vytautas. MicroBlaze programinio procesoriaus įgyvendinimo tyrimas. [Internet] [Masters thesis]. Vilnius Gediminas Technical University; 2010. [cited 2021 Apr 11]. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100619_142408-89771 ;.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

Arminas, Vytautas. MicroBlaze programinio procesoriaus įgyvendinimo tyrimas. [Masters Thesis]. Vilnius Gediminas Technical University; 2010. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100619_142408-89771 ;

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

21. Kimmitt, Jonathan R. R. A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance.

Degree: PhD, 2015, Anglia Ruskin University

 The increasing commoditization of computers in modern society has exceeded the pace of associated developments in reliability. Although theoretical computer science has advanced greatly in… (more)

Subjects/Keywords: 004.2; FPGA; type-safety; fault-tolerance; self-checking; OCaml; field programmable gate array; type-preservation

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APA (6th Edition):

Kimmitt, J. R. R. (2015). A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance. (Doctoral Dissertation). Anglia Ruskin University. Retrieved from http://arro.anglia.ac.uk/id/eprint/581958/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.675601

Chicago Manual of Style (16th Edition):

Kimmitt, Jonathan R R. “A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance.” 2015. Doctoral Dissertation, Anglia Ruskin University. Accessed April 11, 2021. http://arro.anglia.ac.uk/id/eprint/581958/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.675601.

MLA Handbook (7th Edition):

Kimmitt, Jonathan R R. “A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance.” 2015. Web. 11 Apr 2021.

Vancouver:

Kimmitt JRR. A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance. [Internet] [Doctoral dissertation]. Anglia Ruskin University; 2015. [cited 2021 Apr 11]. Available from: http://arro.anglia.ac.uk/id/eprint/581958/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.675601.

Council of Science Editors:

Kimmitt JRR. A type-safe apparatus executing higher order functions in conjunction with hardware error tolerance. [Doctoral Dissertation]. Anglia Ruskin University; 2015. Available from: http://arro.anglia.ac.uk/id/eprint/581958/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.675601


University of Illinois – Urbana-Champaign

22. Papakonstantinou, Alexandros. High-level automation of custom hardware design for high-performance computing.

Degree: PhD, 1200, 2013, University of Illinois – Urbana-Champaign

 This dissertation focuses on efficient generation of custom processors from high-level language descriptions. Our work exploits compiler-based optimizations and transformations in tandem with high-level synthesis… (more)

Subjects/Keywords: High-level synthesis; Field-Programmable Gate Array (FPGA); CUDA; parallel programming; High Performance Computing (HPC)

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APA (6th Edition):

Papakonstantinou, A. (2013). High-level automation of custom hardware design for high-performance computing. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/42137

Chicago Manual of Style (16th Edition):

Papakonstantinou, Alexandros. “High-level automation of custom hardware design for high-performance computing.” 2013. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 11, 2021. http://hdl.handle.net/2142/42137.

MLA Handbook (7th Edition):

Papakonstantinou, Alexandros. “High-level automation of custom hardware design for high-performance computing.” 2013. Web. 11 Apr 2021.

Vancouver:

Papakonstantinou A. High-level automation of custom hardware design for high-performance computing. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2013. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2142/42137.

Council of Science Editors:

Papakonstantinou A. High-level automation of custom hardware design for high-performance computing. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/42137


University of Illinois – Urbana-Champaign

23. Dong, Chen. Architecture and CAD for nanoscale and 3d FPGA.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

 FPGAs (field programmable gate arrays) are attractive alternatives compared to ASICs (application-specific integrated circuits) for significantly lowering amortized manufacturing costs and dramatically improving design productivity.… (more)

Subjects/Keywords: Field-Programmable Gate Array (FPGA); Carbon Nanotube; 3D Integration; Computer-aided design (CAD); Physical Design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dong, C. (2011). Architecture and CAD for nanoscale and 3d FPGA. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18492

Chicago Manual of Style (16th Edition):

Dong, Chen. “Architecture and CAD for nanoscale and 3d FPGA.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 11, 2021. http://hdl.handle.net/2142/18492.

MLA Handbook (7th Edition):

Dong, Chen. “Architecture and CAD for nanoscale and 3d FPGA.” 2011. Web. 11 Apr 2021.

Vancouver:

Dong C. Architecture and CAD for nanoscale and 3d FPGA. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2142/18492.

Council of Science Editors:

Dong C. Architecture and CAD for nanoscale and 3d FPGA. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18492


University of Illinois – Urbana-Champaign

24. Johnson, Matthew Robert. Fast, accurate power measurement and optimization for microprocessor platforms.

Degree: PhD, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 Power and energy consumption have become important for all computers, but the tools used to measure and optimize power on physical hardware lag far behind… (more)

Subjects/Keywords: Power measurement; Current measurement; Energy efficiency; Software optimization; Field-Programmable Gate Array (FPGA); Power optimization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Johnson, M. R. (2015). Fast, accurate power measurement and optimization for microprocessor platforms. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78785

Chicago Manual of Style (16th Edition):

Johnson, Matthew Robert. “Fast, accurate power measurement and optimization for microprocessor platforms.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 11, 2021. http://hdl.handle.net/2142/78785.

MLA Handbook (7th Edition):

Johnson, Matthew Robert. “Fast, accurate power measurement and optimization for microprocessor platforms.” 2015. Web. 11 Apr 2021.

Vancouver:

Johnson MR. Fast, accurate power measurement and optimization for microprocessor platforms. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2142/78785.

Council of Science Editors:

Johnson MR. Fast, accurate power measurement and optimization for microprocessor platforms. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78785


University of Illinois – Urbana-Champaign

25. Wei, Chunan. New PCM based FPGA architecture and graphene memory cell design.

Degree: MS, 1200, 2014, University of Illinois – Urbana-Champaign

 In this work, we introduce a new look-up table (LUT) implementation using phase change memory (PCM) cells. Utilizing the fact that PCM cells store data… (more)

Subjects/Keywords: Phase change memory (PCM); Graphene; Field-Programmable Gate Array (FPGA); Memory; Lookup table (LUT)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wei, C. (2014). New PCM based FPGA architecture and graphene memory cell design. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/49715

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wei, Chunan. “New PCM based FPGA architecture and graphene memory cell design.” 2014. Thesis, University of Illinois – Urbana-Champaign. Accessed April 11, 2021. http://hdl.handle.net/2142/49715.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wei, Chunan. “New PCM based FPGA architecture and graphene memory cell design.” 2014. Web. 11 Apr 2021.

Vancouver:

Wei C. New PCM based FPGA architecture and graphene memory cell design. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2014. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2142/49715.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wei C. New PCM based FPGA architecture and graphene memory cell design. [Thesis]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/49715

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

26. Chen, Daniel E. FPGA acceleration of short read alignment with high-level synthesis.

Degree: MS, Electrical and Computer Engineering, 2017, University of Illinois – Urbana-Champaign

 With the introduction of next-generation sequencing (NGS) technologies, DNA sequencing is becoming an increasingly widespread process. When performed on human patients, it can allow for… (more)

Subjects/Keywords: Field-programmable gate array (FPGA); Hardware acceleration; High-level synthesis; OpenCL; Short read alignment

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, D. E. (2017). FPGA acceleration of short read alignment with high-level synthesis. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97641

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Daniel E. “FPGA acceleration of short read alignment with high-level synthesis.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed April 11, 2021. http://hdl.handle.net/2142/97641.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Daniel E. “FPGA acceleration of short read alignment with high-level synthesis.” 2017. Web. 11 Apr 2021.

Vancouver:

Chen DE. FPGA acceleration of short read alignment with high-level synthesis. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2142/97641.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen DE. FPGA acceleration of short read alignment with high-level synthesis. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97641

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

27. Xu, Zhangqi. FCUDA: Efficient high-level automation CUDA-to-FPGA compilation.

Degree: MS, Electrical and Computer Engineering, 2017, University of Illinois – Urbana-Champaign

 The demand for high-performance computing has been growing significantly in the past decade. The bottleneck of Moore's law and the increasing power consumption in the… (more)

Subjects/Keywords: Field programmable gate array (FPGA); High-level synthesis (HLS); Compute unified device architecture (CUDA)

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APA (6th Edition):

Xu, Z. (2017). FCUDA: Efficient high-level automation CUDA-to-FPGA compilation. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99536

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xu, Zhangqi. “FCUDA: Efficient high-level automation CUDA-to-FPGA compilation.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed April 11, 2021. http://hdl.handle.net/2142/99536.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xu, Zhangqi. “FCUDA: Efficient high-level automation CUDA-to-FPGA compilation.” 2017. Web. 11 Apr 2021.

Vancouver:

Xu Z. FCUDA: Efficient high-level automation CUDA-to-FPGA compilation. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2142/99536.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xu Z. FCUDA: Efficient high-level automation CUDA-to-FPGA compilation. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99536

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arizona

28. Josiah, Jeff G. The CCAP: A New Physical Unclonable Function (PUF) for Protecting Internet of Things (IoT) and Other FPGA-Based Embedded Systems .

Degree: 2020, University of Arizona

 The importance of cybersecurity has grown exponentially over the years due to our highly interconnected world and the evolution of computer threats. These threats –… (more)

Subjects/Keywords: Embedded Systems; Field Programmable Gate Array; FPGA Security; IoT; Physical Unclonable Functions; PUFs

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Josiah, J. G. (2020). The CCAP: A New Physical Unclonable Function (PUF) for Protecting Internet of Things (IoT) and Other FPGA-Based Embedded Systems . (Doctoral Dissertation). University of Arizona. Retrieved from http://hdl.handle.net/10150/636691

Chicago Manual of Style (16th Edition):

Josiah, Jeff G. “The CCAP: A New Physical Unclonable Function (PUF) for Protecting Internet of Things (IoT) and Other FPGA-Based Embedded Systems .” 2020. Doctoral Dissertation, University of Arizona. Accessed April 11, 2021. http://hdl.handle.net/10150/636691.

MLA Handbook (7th Edition):

Josiah, Jeff G. “The CCAP: A New Physical Unclonable Function (PUF) for Protecting Internet of Things (IoT) and Other FPGA-Based Embedded Systems .” 2020. Web. 11 Apr 2021.

Vancouver:

Josiah JG. The CCAP: A New Physical Unclonable Function (PUF) for Protecting Internet of Things (IoT) and Other FPGA-Based Embedded Systems . [Internet] [Doctoral dissertation]. University of Arizona; 2020. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10150/636691.

Council of Science Editors:

Josiah JG. The CCAP: A New Physical Unclonable Function (PUF) for Protecting Internet of Things (IoT) and Other FPGA-Based Embedded Systems . [Doctoral Dissertation]. University of Arizona; 2020. Available from: http://hdl.handle.net/10150/636691

29. SILVA JÚNIOR, Luis Carlos da. SynMaker: uma ferramenta de síntese de alto nível para processamento digital de imagem.

Degree: 2013, Universidade Federal de Pernambuco

 Nesta dissertação de mestrado é introduzida uma nova ferramenta de síntese de alto nível chamada SynMaker que recebe como entrada um código de alto nível… (more)

Subjects/Keywords: Síntese de alto nível; Field Programmable Gate Array; FPGA; Processamento digital de imagem

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APA (6th Edition):

SILVA JÚNIOR, L. C. d. (2013). SynMaker: uma ferramenta de síntese de alto nível para processamento digital de imagem. (Masters Thesis). Universidade Federal de Pernambuco. Retrieved from https://repositorio.ufpe.br/handle/123456789/12404

Chicago Manual of Style (16th Edition):

SILVA JÚNIOR, Luis Carlos da. “SynMaker: uma ferramenta de síntese de alto nível para processamento digital de imagem.” 2013. Masters Thesis, Universidade Federal de Pernambuco. Accessed April 11, 2021. https://repositorio.ufpe.br/handle/123456789/12404.

MLA Handbook (7th Edition):

SILVA JÚNIOR, Luis Carlos da. “SynMaker: uma ferramenta de síntese de alto nível para processamento digital de imagem.” 2013. Web. 11 Apr 2021.

Vancouver:

SILVA JÚNIOR LCd. SynMaker: uma ferramenta de síntese de alto nível para processamento digital de imagem. [Internet] [Masters thesis]. Universidade Federal de Pernambuco; 2013. [cited 2021 Apr 11]. Available from: https://repositorio.ufpe.br/handle/123456789/12404.

Council of Science Editors:

SILVA JÚNIOR LCd. SynMaker: uma ferramenta de síntese de alto nível para processamento digital de imagem. [Masters Thesis]. Universidade Federal de Pernambuco; 2013. Available from: https://repositorio.ufpe.br/handle/123456789/12404


Universidade Estadual de Campinas

30. Ceissler, Ciro Luiz Araujo, 1986-. Automatic offloading to FPGA accelerators : Transferência automática para aceleradores FPGA.

Degree: Instituto de Computação; Programa de Pós-Graduação em Ciência da Computação, 2018, Universidade Estadual de Campinas

Orientador: Guido Costa Souza de Araújo

Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação

Made available in DSpace on 2019-02-05T18:09:45Z (GMT). No. of… (more)

Subjects/Keywords: OpenMP (Programação paralela); Compiladores (Computadores); FPGA (Field Programmable Gate Array); Intel HARP (Microprocessadores); OpenMP (Parallel programming); Compiling (Electronic computers); Field programmable gate array; Intel HARP (Microprocessor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ceissler, Ciro Luiz Araujo, 1. (2018). Automatic offloading to FPGA accelerators : Transferência automática para aceleradores FPGA. (Masters Thesis). Universidade Estadual de Campinas. Retrieved from http://repositorio.unicamp.br/jspui/handle/REPOSIP/333141

Chicago Manual of Style (16th Edition):

Ceissler, Ciro Luiz Araujo, 1986-. “Automatic offloading to FPGA accelerators : Transferência automática para aceleradores FPGA.” 2018. Masters Thesis, Universidade Estadual de Campinas. Accessed April 11, 2021. http://repositorio.unicamp.br/jspui/handle/REPOSIP/333141.

MLA Handbook (7th Edition):

Ceissler, Ciro Luiz Araujo, 1986-. “Automatic offloading to FPGA accelerators : Transferência automática para aceleradores FPGA.” 2018. Web. 11 Apr 2021.

Vancouver:

Ceissler, Ciro Luiz Araujo 1. Automatic offloading to FPGA accelerators : Transferência automática para aceleradores FPGA. [Internet] [Masters thesis]. Universidade Estadual de Campinas; 2018. [cited 2021 Apr 11]. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/333141.

Council of Science Editors:

Ceissler, Ciro Luiz Araujo 1. Automatic offloading to FPGA accelerators : Transferência automática para aceleradores FPGA. [Masters Thesis]. Universidade Estadual de Campinas; 2018. Available from: http://repositorio.unicamp.br/jspui/handle/REPOSIP/333141

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