subject:(Fault tolerant computing )

Oregon State University

1. Rowley, Robert A. Fault-tolerant ring embedding in De Bruijn networks.

Degree: PhD, Computer Science, 1993, Oregon State University

URL: http://hdl.handle.net/1957/35583

Subjects/Keywords: Fault-tolerant computing

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APA (6^th Edition):

Rowley, R. A. (1993). Fault-tolerant ring embedding in De Bruijn networks. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/35583

Chicago Manual of Style (16^th Edition):

Rowley, Robert A. “Fault-tolerant ring embedding in De Bruijn networks.” 1993. Doctoral Dissertation, Oregon State University. Accessed January 16, 2021. http://hdl.handle.net/1957/35583.

MLA Handbook (7^th Edition):

Rowley, Robert A. “Fault-tolerant ring embedding in De Bruijn networks.” 1993. Web. 16 Jan 2021.

Vancouver:

Rowley RA. Fault-tolerant ring embedding in De Bruijn networks. [Internet] [Doctoral dissertation]. Oregon State University; 1993. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/1957/35583.

Council of Science Editors:

Rowley RA. Fault-tolerant ring embedding in De Bruijn networks. [Doctoral Dissertation]. Oregon State University; 1993. Available from: http://hdl.handle.net/1957/35583

Oregon State University

2. Ramanathan, Gowri. System reliability through Algorithm-Based Fault tolerance and reconfiguration.

Degree: PhD, Computer Science, 1998, Oregon State University

URL: http://hdl.handle.net/1957/19293

Subjects/Keywords: Fault-tolerant computing

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APA (6^th Edition):

Ramanathan, G. (1998). System reliability through Algorithm-Based Fault tolerance and reconfiguration. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/19293

Chicago Manual of Style (16^th Edition):

Ramanathan, Gowri. “System reliability through Algorithm-Based Fault tolerance and reconfiguration.” 1998. Doctoral Dissertation, Oregon State University. Accessed January 16, 2021. http://hdl.handle.net/1957/19293.

MLA Handbook (7^th Edition):

Ramanathan, Gowri. “System reliability through Algorithm-Based Fault tolerance and reconfiguration.” 1998. Web. 16 Jan 2021.

Vancouver:

Ramanathan G. System reliability through Algorithm-Based Fault tolerance and reconfiguration. [Internet] [Doctoral dissertation]. Oregon State University; 1998. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/1957/19293.

Council of Science Editors:

Ramanathan G. System reliability through Algorithm-Based Fault tolerance and reconfiguration. [Doctoral Dissertation]. Oregon State University; 1998. Available from: http://hdl.handle.net/1957/19293

Hong Kong University of Science and Technology

3. Teh, Ying Fei. Link faults analysis and fault tolerant techniques on network-on-chip system.

Degree: 2012, Hong Kong University of Science and Technology

URL: http://repository.ust.hk/ir/Record/1783.1-7575 ; https://doi.org/10.14711/thesis-b1180262 ; http://repository.ust.hk/ir/bitstream/1783.1-7575/1/th_redirect.html

► With reducing feature size of transistors and increasing number of cores on a single chip, system-on-chips (SoCs) are becoming more vulnerable to faults due to… (more)

Subjects/Keywords: Networks on a chip ; Fault-tolerant computing

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APA (6^th Edition):

Teh, Y. F. (2012). Link faults analysis and fault tolerant techniques on network-on-chip system. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-7575 ; https://doi.org/10.14711/thesis-b1180262 ; http://repository.ust.hk/ir/bitstream/1783.1-7575/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Teh, Ying Fei. “Link faults analysis and fault tolerant techniques on network-on-chip system.” 2012. Thesis, Hong Kong University of Science and Technology. Accessed January 16, 2021. http://repository.ust.hk/ir/Record/1783.1-7575 ; https://doi.org/10.14711/thesis-b1180262 ; http://repository.ust.hk/ir/bitstream/1783.1-7575/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Teh, Ying Fei. “Link faults analysis and fault tolerant techniques on network-on-chip system.” 2012. Web. 16 Jan 2021.

Vancouver:

Teh YF. Link faults analysis and fault tolerant techniques on network-on-chip system. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2012. [cited 2021 Jan 16]. Available from: http://repository.ust.hk/ir/Record/1783.1-7575 ; https://doi.org/10.14711/thesis-b1180262 ; http://repository.ust.hk/ir/bitstream/1783.1-7575/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Teh YF. Link faults analysis and fault tolerant techniques on network-on-chip system. [Thesis]. Hong Kong University of Science and Technology; 2012. Available from: http://repository.ust.hk/ir/Record/1783.1-7575 ; https://doi.org/10.14711/thesis-b1180262 ; http://repository.ust.hk/ir/bitstream/1783.1-7575/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Montana State University

4. Amicucci, Phillip Louis. Implementing uniform treatment of hardware and software faults with distributed queues.

Degree: MS, College of Engineering, 1993, Montana State University

URL: https://scholarworks.montana.edu/xmlui/handle/1/6735

Subjects/Keywords: Fault-tolerant computing.

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APA (6^th Edition):

Amicucci, P. L. (1993). Implementing uniform treatment of hardware and software faults with distributed queues. (Masters Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/6735

Chicago Manual of Style (16^th Edition):

Amicucci, Phillip Louis. “Implementing uniform treatment of hardware and software faults with distributed queues.” 1993. Masters Thesis, Montana State University. Accessed January 16, 2021. https://scholarworks.montana.edu/xmlui/handle/1/6735.

MLA Handbook (7^th Edition):

Amicucci, Phillip Louis. “Implementing uniform treatment of hardware and software faults with distributed queues.” 1993. Web. 16 Jan 2021.

Vancouver:

Amicucci PL. Implementing uniform treatment of hardware and software faults with distributed queues. [Internet] [Masters thesis]. Montana State University; 1993. [cited 2021 Jan 16]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/6735.

Council of Science Editors:

Amicucci PL. Implementing uniform treatment of hardware and software faults with distributed queues. [Masters Thesis]. Montana State University; 1993. Available from: https://scholarworks.montana.edu/xmlui/handle/1/6735

University of Texas – Austin

5. Martin, Jean-Philippe Etienne. Byzantine fault-tolerance and beyond.

Degree: PhD, Computer Sciences, 2006, University of Texas – Austin

URL: http://hdl.handle.net/2152/2828

► Byzantine fault-tolerance techniques are useful because they tolerate arbitrary faults regardless of cause: bugs, hardware glitches, even hackers. These techniques have recently gained popularity after… (more)

Subjects/Keywords: Fault-tolerant computing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Martin, J. E. (2006). Byzantine fault-tolerance and beyond. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/2828

Chicago Manual of Style (16^th Edition):

Martin, Jean-Philippe Etienne. “Byzantine fault-tolerance and beyond.” 2006. Doctoral Dissertation, University of Texas – Austin. Accessed January 16, 2021. http://hdl.handle.net/2152/2828.

MLA Handbook (7^th Edition):

Martin, Jean-Philippe Etienne. “Byzantine fault-tolerance and beyond.” 2006. Web. 16 Jan 2021.

Vancouver:

Martin JE. Byzantine fault-tolerance and beyond. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2006. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/2152/2828.

Council of Science Editors:

Martin JE. Byzantine fault-tolerance and beyond. [Doctoral Dissertation]. University of Texas – Austin; 2006. Available from: http://hdl.handle.net/2152/2828

Stellenbosch University

6. Busch, Regardt. Optimised active fault detection for an open loop stable system.

Degree: DPhil, Electrical and Electronic Engineering, 2016, Stellenbosch University

URL: http://hdl.handle.net/10019.1/100083

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Active fault detection for a stable open-loop linear time invariant system is considered. The optimal active fault detection setup is developed around an estimator based… (more)

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Active fault detection for a stable open-loop linear time invariant system is considered. The optimal active fault detection setup is developed around an estimator based architecture. The auxiliary signal and estimator are then The effect of the excitation signal frequency on detector performance is investigated, and a minimum targeted detection time parameter is introduced. This set of equations is then used to minimise the fault detection time for fixed performance constraints and minimum targeted detection time. A conceptual Active Fault Tolerant Control Framework is developed for a small unmanned aerial vehicle, emphasising the role of fault detection. The theoretical framework is then applied to this UAV, illustrating the applicability of the proposed AFD framework to more complex practical problems. designed in order to maximize detection performance. Equations are derived which relate the estimator design to the nominal residual signal covariance. The relationship between the auxiliary input and the system performance degradation constraint is considered. The effect of estimator gain and excitation signal frequency on the dual Youla-Jabr-Bongiorno- Kucera parameter is investigated. An LTI input shaping filter is added to allow for added MIMO system complexity. Theory developed for the general output zeroing problem is combined with the extended MIMO architecture in order to arrive at a solution without the nominal performance penalty usually associated with active fault detection. Furthermore, the effect of the control input is considered and formulated as an additional optimisation criterion, resulting in an average-case optimisation scenario.

AFRIKAANSE OPSOMMING: Aktiewe foutdeteksie vir ’n stabiele oop-lus liniere tyd-onafhanklike stelsel word oorweeg. Die optimale aktiewe foutdeteksie stelsel word ontwerp rondom ’n beramer-gebaseerde argitektuur. Die hulpsein en beramer word dan ontwerp om opsporingsvermoe te maksimeer. Vergelykings wat die verband tussen die beramerontwerp en die nominale residuele sein se kovariansie beskryf word afgelei. Die verhouding tussen die hulpsein en die beperking op die stelsel se prestasie agteruitgang word oorweeg. Die effek van beramer aanwins en die hulpsein frekwensie op die dubbel-Youla- Jabr-Bongiorno-Kucera parameter word ondersoek. ’n Liniere tyd-onafhanklike insetvormende filter word bygevoeg om die addisionele multi-inset multi-uitset kompleksietyd te hanteer. Teorie wat ontwikkel is vir die algemene uitset nulstellingsprobleem word gekombineer met die uitgebreide multi-inset multi-uitset argitektuur om ’n oplossing to vind sonder enige van die nominale stelselprestasie agteruitgang wat gewoonlik geassosieer word met aktiewe foutdeteksie. Verder word die effek van die beheerinset oorweeg, en geformuleer as ’n addisionele optimiseringskriterium, wat lei tot gemiddelde-geval optimisering. Die effek van die hulpsein frekwensie op die foutdeteksie prestasie word ondersoek, en ’n minimum teiken opsporingsparameter word ingestel. Hierdie stel…

Advisors/Committee Members: Jones, T., Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering..

Subjects/Keywords: Fault location (Engineering) – Detection, Signal; Fault tolerant design; Actuators; UCTD; Fault-tolerant computing

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APA (6^th Edition):

Busch, R. (2016). Optimised active fault detection for an open loop stable system. (Thesis). Stellenbosch University. Retrieved from http://hdl.handle.net/10019.1/100083

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Busch, Regardt. “Optimised active fault detection for an open loop stable system.” 2016. Thesis, Stellenbosch University. Accessed January 16, 2021. http://hdl.handle.net/10019.1/100083.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Busch, Regardt. “Optimised active fault detection for an open loop stable system.” 2016. Web. 16 Jan 2021.

Vancouver:

Busch R. Optimised active fault detection for an open loop stable system. [Internet] [Thesis]. Stellenbosch University; 2016. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/10019.1/100083.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Busch R. Optimised active fault detection for an open loop stable system. [Thesis]. Stellenbosch University; 2016. Available from: http://hdl.handle.net/10019.1/100083

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Macquarie University

7. Kieferová, Mária. Quantum algorithmic techniques for fault-tolerant quantum computers.

Degree: 2019, Macquarie University

URL: http://hdl.handle.net/1959.14/1274798

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Empirical thesis.

Degree carried out under a cotutelle program with the University of Waterloo.

Bibliography: pages139-161.

1. Introduction – 2. Background – 3. Quantum sort… (more)

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Empirical thesis.

Degree carried out under a cotutelle program with the University of Waterloo.

Bibliography: pages139-161.

1. Introduction – 2. Background – 3. Quantum sort and shuffle – 4. Simulation of time-dependent Hamiltonians – 5. Training and tomography with quantum Boltzmann machines – 6. Conclusion and future work – Abbreviations – References – Appendices.

Quantum computers have the potential to push the limits of computation in areas such as quantum chemistry, cryptography, optimization, and machine learning. Even though many quantum algorithms show asymptotic improvement compared to classical ones, the overhead of running quantum computers limits when quantum computing becomes useful. Thus, by optimizing components of quantum algorithms, we can bring the regime of quantum advantage closer. My work focuses on developing efficient subroutines for quantum computation. I focus specifically on algorithms for scalable, fault-tolerant quantum computers. While it is possible that even noisy quantum computers can outperform classical ones for specific tasks, high-depth and therefore fault-tolerance is likely required for most applications. In this thesis, I introduce three sets of techniques that can be used by themselves or as subroutines in other algorithms.

The first components are coherent versions of classical sort and shuffle. We require that a quantum shuffle prepares a uniform superposition over all permutations of a sequence. The quantum sort is used within the shuffle and as well as in the next algorithm in this thesis. The quantum shuffle is an essential part of state preparation for quantum chemistry computation in first quantization.

Second, I review the progress of Hamiltonian simulations and give a new algorithm for simulating time-dependent Hamiltonians. This algorithm scales polylogarithmic in the inverse error, and the query complexity does not depend on the derivatives of the Hamiltonian. A time-dependent Hamiltonian simulation was recently used for interaction picture simulation with applications to quantum chemistry.

Next, I present a fully quantum Boltzmann machine. I show that our algorithm can train on quantum data and learn a classical description of quantum states. This type of machine learning can be used for tomography, Hamiltonian learning, and approximate quantum cloning.

1 online resource (xv, 166 pages) colour illustrations

Advisors/Committee Members: Macquarie University. Department of Physics and Astronomy, University of Waterloo.

Subjects/Keywords: Quantum computing; Computer algorithms; Fault-tolerant computing; quantum computing; quantum algorithms

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APA (6^th Edition):

Kieferová, M. (2019). Quantum algorithmic techniques for fault-tolerant quantum computers. (Doctoral Dissertation). Macquarie University. Retrieved from http://hdl.handle.net/1959.14/1274798

Chicago Manual of Style (16^th Edition):

Kieferová, Mária. “Quantum algorithmic techniques for fault-tolerant quantum computers.” 2019. Doctoral Dissertation, Macquarie University. Accessed January 16, 2021. http://hdl.handle.net/1959.14/1274798.

MLA Handbook (7^th Edition):

Kieferová, Mária. “Quantum algorithmic techniques for fault-tolerant quantum computers.” 2019. Web. 16 Jan 2021.

Vancouver:

Kieferová M. Quantum algorithmic techniques for fault-tolerant quantum computers. [Internet] [Doctoral dissertation]. Macquarie University; 2019. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/1959.14/1274798.

Council of Science Editors:

Kieferová M. Quantum algorithmic techniques for fault-tolerant quantum computers. [Doctoral Dissertation]. Macquarie University; 2019. Available from: http://hdl.handle.net/1959.14/1274798

Stellenbosch University

8. Myburgh, Travis Louis. On-line fault detection and end-of-batch quality prediction for batch processes incorporating on-line synchronisation and phase identification.

Degree: MEng, Process Engineering, 2016, Stellenbosch University

URL: http://hdl.handle.net/10019.1/100263

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ENGLISH ABSTRACT: Batch processes are transient processes, which present a unique monitoring challenge. Whereas the expected output variables of a continuous process centre on specific… (more)

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ENGLISH ABSTRACT: Batch processes are transient processes, which present a unique monitoring challenge. Whereas the expected output variables of a continuous process centre on specific target values that represent some steady state, batch process variables inherently change from an initial state to a final state. Abnormal events, or faults, that occur in batch processes can be identified with an appropriate monitoring scheme. Bilinear statistical modelling based on latent methods, such as Partial Least Squares (PLS), have been shown by Nomikos and MacGregor (1995) to be an effective way to detect faults and predict the end-of-batch quality. A batch process monitoring toolbox has previously been developed, which supports off-line modelling and monitoring of batch processes. The limitation of off-line monitoring is that product end-of-batch quality and fault detection can only be assessed once the batch has been completed. On-line fault detection and end-of-batch quality prediction in near-real time endeavors to address this limitation. The aim of this project was to implement an on-line monitoring platform which can detect faults and predict end-of-batch quality in a timely manner. Synchronization of the batch trajectories is a computationally expensive step in off-line monitoring, and the ability of the on-line platform to produce computationally efficient results comparable to off-line synchronization was assessed. The Relaxed Greedy Time Warping (RGTW) approach (González-Martínez et al., 2011) was used to synchronise the trajectories in an on-line fashion. The approach was able to produce comparable results in a computationally efficient way, but some inaccuracies were observed during flat regions of the batch trajectories. The nature of phases for accurate modelling of batch data was also investigated. Models were built for batch data partitioned in three ways: no partitions, partitions based on known process stages and partitions based on linear correlation structure between the variables and the end-of-batch quality prediction accuracy was compared. The multiphase partial least squares (MPPLS) algorithm (Camacho, et al., 2007) was used to find the changes in linear correlation among the process variables and partition the data accordingly. Partitioning the data using the MPPLS algorithm showed comparable or statistically significant reductions in the overall end-of-batch prediction error compared with the other two data partitioning methods. The models were applied on-line to two case studies using the on-line monitoring platform and the fault detection and end-of-batch quality prediction accuracy were assessed for the three data partioning methods. The end-of-batch predictions made using the MPPLS algorithm provided the most accurate end-of-batch predictions. Improper on-line synchronisation caused false alarms in certain areas of the batch trajectory, but faults were detected with relative accuracy.

AFRIKAANSE OPSOMMING: Enkelladingprosesse is oorgangsprosesse, wat ’n unieke…

Advisors/Committee Members: Auret, Lidia, Burger, A. J., Stellenbosch University. Faculty of Engineering. Dept. of Process Engineering..

Subjects/Keywords: Fault location (Engineering); UCTD; Fault-tolerant computing; SR (Computer program language)

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APA (6^th Edition):

Myburgh, T. L. (2016). On-line fault detection and end-of-batch quality prediction for batch processes incorporating on-line synchronisation and phase identification. (Thesis). Stellenbosch University. Retrieved from http://hdl.handle.net/10019.1/100263

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Myburgh, Travis Louis. “On-line fault detection and end-of-batch quality prediction for batch processes incorporating on-line synchronisation and phase identification.” 2016. Thesis, Stellenbosch University. Accessed January 16, 2021. http://hdl.handle.net/10019.1/100263.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Myburgh, Travis Louis. “On-line fault detection and end-of-batch quality prediction for batch processes incorporating on-line synchronisation and phase identification.” 2016. Web. 16 Jan 2021.

Vancouver:

Myburgh TL. On-line fault detection and end-of-batch quality prediction for batch processes incorporating on-line synchronisation and phase identification. [Internet] [Thesis]. Stellenbosch University; 2016. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/10019.1/100263.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Myburgh TL. On-line fault detection and end-of-batch quality prediction for batch processes incorporating on-line synchronisation and phase identification. [Thesis]. Stellenbosch University; 2016. Available from: http://hdl.handle.net/10019.1/100263

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Illinois – Urbana-Champaign

9. Jian, Xun. Common-case optimized memory hierarchy for data centers and HPC systems.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/99448

► The memory hierarchy is predicted to consume up to 40% to 70% of total system power in future data centers and high performance computing (HPC)… (more)

▼ The memory hierarchy is predicted to consume up to 40% to 70% of total system power in future data centers and high performance computing (HPC) systems; as such, it is time to rethink memory system designs. Conventional memory system designs in existing systems often seek to provide uniform performance across time and space. While this design approach is simple, which benefits hardware implementation, the overheads of uncommon operations often dictate overall memory energy and performance. This dissertation explores across the memory hierarchy common-case optimized memory design, which reduces overall overheads by reducing common overheads at the cost of increasing uncommon overheads. For latency-optimized on-chip caches, which require long-latency correction to ensure reliable accesses during low voltage execution, this dissertation reduces common-case correction latency by proposing architectural techniques such as correction prediction, at the cost of increasing uncommon-case correction latency due to occasional operations such as misprediction recovery. For bandwidth-optimized 3D DRAMs, which are power-hungry due to high access frequency, this dissertation de- scribes new data layout and power management policies to improve overall memory access energy-efficiency at the cost of increasing uncommon-case access latencies. For capacity-optimized server main memory, which contains 100’s to 1000’s of memory chips to provide high capacity and, therefore, needs expensive fault-tolerance, this dissertation proposes an adaptive architecture that minimizes energy when memory contains no or minor fault, at the cost of increasing energy as faults slowly accumulate. Finally, for emerging density-optimized NVRAMs, which suffer from very high random bit error rates, this dissertation describes a server memory architecture that reuses the redundant memory budgeted for memory chip failure protection to accelerate the expensive bit error correction before memory chip(s) fail at the cost of increasing correction overheads after memory chip(s) fail. Advisors/Committee Members: Kumar, Rakesh (advisor), Kumar, Rakesh (Committee Chair), Torrellas, Josep (committee member), Hanumolu, Pavan K (committee member), Sridharan, Vilas (committee member).

Subjects/Keywords: Memory hierarchy; Computer architecture; Energy-efficient computing; Fault-tolerant computing

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APA (6^th Edition):

Jian, X. (2017). Common-case optimized memory hierarchy for data centers and HPC systems. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99448

Chicago Manual of Style (16^th Edition):

Jian, Xun. “Common-case optimized memory hierarchy for data centers and HPC systems.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed January 16, 2021. http://hdl.handle.net/2142/99448.

MLA Handbook (7^th Edition):

Jian, Xun. “Common-case optimized memory hierarchy for data centers and HPC systems.” 2017. Web. 16 Jan 2021.

Vancouver:

Jian X. Common-case optimized memory hierarchy for data centers and HPC systems. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/2142/99448.

Council of Science Editors:

Jian X. Common-case optimized memory hierarchy for data centers and HPC systems. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99448

University of Waterloo

10. Chamberland, Christopher. New methods in quantum error correction and fault-tolerant quantum computing.

Degree: 2018, University of Waterloo

URL: http://hdl.handle.net/10012/14049

► Quantum computers have the potential to solve several interesting problems in polynomial time for which no polynomial time classical algorithms have been found. However, one… (more)

▼ Quantum computers have the potential to solve several interesting problems in polynomial time for which no polynomial time classical algorithms have been found. However, one of the major challenges in building quantum devices is that quantum systems are very sensitive to noise arising from undesired interactions with the environment. Noise can lead to errors which can corrupt the results of the computation. Quantum error correction is one way to mitigate the effects of noise arising in quantum devices. With a plethora of quantum error correcting codes that can be used in various settings, one of the main challenges of quantum error correction is understanding how well various codes perform under more realistic noise models that can be observed in experiments. This thesis proposes a new decoding algorithm which can optimize threshold values of error correcting codes under different noise models. The algorithm can be applied to any Markovian noise model. Further, it is shown that for certain noise models, logical Clifford corrections can further improve a code's threshold value if the code obeys certain symmetries. Since gates and measurements cannot in general be performed with perfect precision, the operations required to perform quantum error correction can introduce more errors into the system thus negating the benefits of error correction. Fault-tolerant quantum computing is a way to perform quantum error correction with imperfect operations while retaining the ability to suppress errors as long as the noise is below a code's threshold. One of the main challenges in performing fault-tolerant error correction is the high resource requirements that are needed to obtain very low logical noise rates. With the use of flag qubits, this thesis develops new fault-tolerant error correction protocols that are applicable to arbitrary distance codes. Various code families are shown to satisfy the requirements of flag fault-tolerant error correction. We also provide circuits using a constant number of qubits for these codes. It is shown that the proposed flag fault-tolerant method uses fewer qubits than previous fault-tolerant error correction protocols. It is often the case that the noise afflicting a quantum device cannot be fully characterized. Further, even with some knowledge of the noise, it can be very challenging to use analytic decoding methods to improve the performance of a fault-tolerant scheme. This thesis presents decoding schemes using several state of the art machine learning techniques with a focus on fault-tolerant quantum error correction in regimes that are relevant to near term experiments. It is shown that even in low noise rate regimes and with no knowledge of the noise, noise can be further suppressed for small distance codes. Limitations of machine learning decoders as well as the classical resources required to perform active error correction are discussed. In many cases, gate times can be much shorter than typical measurement times of quantum states.…

Subjects/Keywords: Quantum error correction; Quantum computing; Fault-tolerant quantum computing; Quantum information

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APA (6^th Edition):

Chamberland, C. (2018). New methods in quantum error correction and fault-tolerant quantum computing. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/14049

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chamberland, Christopher. “New methods in quantum error correction and fault-tolerant quantum computing.” 2018. Thesis, University of Waterloo. Accessed January 16, 2021. http://hdl.handle.net/10012/14049.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chamberland, Christopher. “New methods in quantum error correction and fault-tolerant quantum computing.” 2018. Web. 16 Jan 2021.

Vancouver:

Chamberland C. New methods in quantum error correction and fault-tolerant quantum computing. [Internet] [Thesis]. University of Waterloo; 2018. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/10012/14049.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chamberland C. New methods in quantum error correction and fault-tolerant quantum computing. [Thesis]. University of Waterloo; 2018. Available from: http://hdl.handle.net/10012/14049

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Northeastern University

11. Sridharan, Vilas Keshav. Introducing abstraction to vulnerability analysis.

Degree: PhD, Department of Electrical and Computer Engineering, 2010, Northeastern University

URL: http://hdl.handle.net/2047/d20000790

► Tolerance to the effects of transient faults is now a primary design constraint for all major microprocessors. Chip vendors typically set a failure rate target… (more)

Subjects/Keywords: computer engineering; abstraction; vulnerability; Fault-tolerant computing; Computational Engineering

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APA (6^th Edition):

Sridharan, V. K. (2010). Introducing abstraction to vulnerability analysis. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20000790

Chicago Manual of Style (16^th Edition):

Sridharan, Vilas Keshav. “Introducing abstraction to vulnerability analysis.” 2010. Doctoral Dissertation, Northeastern University. Accessed January 16, 2021. http://hdl.handle.net/2047/d20000790.

MLA Handbook (7^th Edition):

Sridharan, Vilas Keshav. “Introducing abstraction to vulnerability analysis.” 2010. Web. 16 Jan 2021.

Vancouver:

Sridharan VK. Introducing abstraction to vulnerability analysis. [Internet] [Doctoral dissertation]. Northeastern University; 2010. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/2047/d20000790.

Council of Science Editors:

Sridharan VK. Introducing abstraction to vulnerability analysis. [Doctoral Dissertation]. Northeastern University; 2010. Available from: http://hdl.handle.net/2047/d20000790

University of Newcastle upon Tyne

12. Mancini, Luigi Vincenzo. Reliability issues in the design of distributed object-based architectures.

Degree: PhD, 1989, University of Newcastle upon Tyne

URL: http://theses.ncl.ac.uk/jspui/handle/10443/2057 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.282939

► This thesis is aimed at enhancing the existing set of techniques for building distributed systems, specifically from the point of view of fault-tolerant com- puting.… (more)

Subjects/Keywords: 005; Fault-tolerant computing

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APA (6^th Edition):

Mancini, L. V. (1989). Reliability issues in the design of distributed object-based architectures. (Doctoral Dissertation). University of Newcastle upon Tyne. Retrieved from http://theses.ncl.ac.uk/jspui/handle/10443/2057 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.282939

Chicago Manual of Style (16^th Edition):

Mancini, Luigi Vincenzo. “Reliability issues in the design of distributed object-based architectures.” 1989. Doctoral Dissertation, University of Newcastle upon Tyne. Accessed January 16, 2021. http://theses.ncl.ac.uk/jspui/handle/10443/2057 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.282939.

MLA Handbook (7^th Edition):

Mancini, Luigi Vincenzo. “Reliability issues in the design of distributed object-based architectures.” 1989. Web. 16 Jan 2021.

Vancouver:

Mancini LV. Reliability issues in the design of distributed object-based architectures. [Internet] [Doctoral dissertation]. University of Newcastle upon Tyne; 1989. [cited 2021 Jan 16]. Available from: http://theses.ncl.ac.uk/jspui/handle/10443/2057 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.282939.

Council of Science Editors:

Mancini LV. Reliability issues in the design of distributed object-based architectures. [Doctoral Dissertation]. University of Newcastle upon Tyne; 1989. Available from: http://theses.ncl.ac.uk/jspui/handle/10443/2057 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.282939

University of Oxford

13. Ballance, Christopher J. High-fidelity quantum logic in Ca+.

Degree: PhD, 2014, University of Oxford

URL: http://ora.ox.ac.uk/objects/uuid:1beb7f67-4d92-4d57-8754-50f92f9d27f4 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.711720

► Trapped atomic ions are one of the most promising systems for building a quantum computer – all of the fundamental operations needed to build a… (more)

▼ Trapped atomic ions are one of the most promising systems for building a quantum computer – all of the fundamental operations needed to build a quantum computer have been demonstrated in such systems. The challenge now is to understand and reduce the operation errors to below the 'fault-tolerant threshold' (the level below which quantum error correction works), and to scale up the current few-qubit experiments to many qubits. This thesis describes experimental work concentrated primarily on the first of these challenges. We demonstrate high-fidelity single-qubit and two-qubit (entangling) gates with errors at or below the fault-tolerant threshold. We also implement an entangling gate between two different species of ions, a tool which may be useful for certain scalable architectures. We study the speed/fidelity trade-off for a two-qubit phase gate implemented in ⁴³Ca+ hyperfine trapped-ion qubits. We develop an error model which describes the fundamental and technical imperfections / limitations that contribute to the measured gate error. We characterize and minimise various error sources contributing to the measured fidelity, allowing us to account for errors due to the single-qubit operations and state readout (each at the 0.1% level), and to identify the leading sources of error in the two-qubit entangling operation. We achieve gate fidelities ranging between 97.1(2)% (for a gate time t_g = 3.8 μs) and 99.9(1)% (for t_g = 100 μs), representing respectively the fastest and lowest-error two-qubit gates reported between trapped-ion qubits by nearly an order of magnitude in each case. We also characterise single-qubit gates with average errors below 10^-4 per operation, over an order of magnitude better than previously achieved with laser-driven operations. Additionally, we present work on a mixed-species entangling gate. We entangle of a single ⁴⁰Ca+ ion and a single ⁴³Ca+ ion with a fidelity of 99.8(5)%, and perform full tomography of the resulting entangled state. We describe how this mixed-species gate mechanism could be used to entangle ⁴³Ca+ and ⁸⁸Sr+, a promising combination of ions for future experiments.

Subjects/Keywords: 539.7; Trapped ions; Quantum logic; Quantum computers; Fault-tolerant computing

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APA (6^th Edition):

Ballance, C. J. (2014). High-fidelity quantum logic in Ca+. (Doctoral Dissertation). University of Oxford. Retrieved from http://ora.ox.ac.uk/objects/uuid:1beb7f67-4d92-4d57-8754-50f92f9d27f4 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.711720

Chicago Manual of Style (16^th Edition):

Ballance, Christopher J. “High-fidelity quantum logic in Ca+.” 2014. Doctoral Dissertation, University of Oxford. Accessed January 16, 2021. http://ora.ox.ac.uk/objects/uuid:1beb7f67-4d92-4d57-8754-50f92f9d27f4 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.711720.

MLA Handbook (7^th Edition):

Ballance, Christopher J. “High-fidelity quantum logic in Ca+.” 2014. Web. 16 Jan 2021.

Vancouver:

Ballance CJ. High-fidelity quantum logic in Ca+. [Internet] [Doctoral dissertation]. University of Oxford; 2014. [cited 2021 Jan 16]. Available from: http://ora.ox.ac.uk/objects/uuid:1beb7f67-4d92-4d57-8754-50f92f9d27f4 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.711720.

Council of Science Editors:

Ballance CJ. High-fidelity quantum logic in Ca+. [Doctoral Dissertation]. University of Oxford; 2014. Available from: http://ora.ox.ac.uk/objects/uuid:1beb7f67-4d92-4d57-8754-50f92f9d27f4 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.711720

University of Newcastle upon Tyne

14. Garnsworthy, Johnathan Randall. Fundamental concepts for fault tolerant systems.

Degree: PhD, 1990, University of Newcastle upon Tyne

URL: http://theses.ncl.ac.uk/jspui/handle/10443/2055 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.330271

► In order to be able to think clearly about any subject we need precise definitions of its basic terminology and concepts. If one reads the… (more)

Subjects/Keywords: 005; Fault tolerant computing

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APA (6^th Edition):

Garnsworthy, J. R. (1990). Fundamental concepts for fault tolerant systems. (Doctoral Dissertation). University of Newcastle upon Tyne. Retrieved from http://theses.ncl.ac.uk/jspui/handle/10443/2055 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.330271

Chicago Manual of Style (16^th Edition):

Garnsworthy, Johnathan Randall. “Fundamental concepts for fault tolerant systems.” 1990. Doctoral Dissertation, University of Newcastle upon Tyne. Accessed January 16, 2021. http://theses.ncl.ac.uk/jspui/handle/10443/2055 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.330271.

MLA Handbook (7^th Edition):

Garnsworthy, Johnathan Randall. “Fundamental concepts for fault tolerant systems.” 1990. Web. 16 Jan 2021.

Vancouver:

Garnsworthy JR. Fundamental concepts for fault tolerant systems. [Internet] [Doctoral dissertation]. University of Newcastle upon Tyne; 1990. [cited 2021 Jan 16]. Available from: http://theses.ncl.ac.uk/jspui/handle/10443/2055 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.330271.

Council of Science Editors:

Garnsworthy JR. Fundamental concepts for fault tolerant systems. [Doctoral Dissertation]. University of Newcastle upon Tyne; 1990. Available from: http://theses.ncl.ac.uk/jspui/handle/10443/2055 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.330271

Florida Atlantic University

15. Buckley, Ingrid A. Towards a methodology for building reliable systems.

Degree: PhD, 2012, Florida Atlantic University

URL: http://purl.flvc.org/FAU/3342037

►

Summary: Reliability is a key system characteristic that is an increasing concern for current systems. Greater reliability is necessary due to the new ways in… (more)

Subjects/Keywords: Computer software – Reliability; Reliability (Engineering) – Computer programs; Fault-tolerant computing

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APA (6^th Edition):

Buckley, I. A. (2012). Towards a methodology for building reliable systems. (Doctoral Dissertation). Florida Atlantic University. Retrieved from http://purl.flvc.org/FAU/3342037

Chicago Manual of Style (16^th Edition):

Buckley, Ingrid A. “Towards a methodology for building reliable systems.” 2012. Doctoral Dissertation, Florida Atlantic University. Accessed January 16, 2021. http://purl.flvc.org/FAU/3342037.

MLA Handbook (7^th Edition):

Buckley, Ingrid A. “Towards a methodology for building reliable systems.” 2012. Web. 16 Jan 2021.

Vancouver:

Buckley IA. Towards a methodology for building reliable systems. [Internet] [Doctoral dissertation]. Florida Atlantic University; 2012. [cited 2021 Jan 16]. Available from: http://purl.flvc.org/FAU/3342037.

Council of Science Editors:

Buckley IA. Towards a methodology for building reliable systems. [Doctoral Dissertation]. Florida Atlantic University; 2012. Available from: http://purl.flvc.org/FAU/3342037

University of Victoria

16. Feldstein, Cary Benjamin. Development of a fault tolerant flight control system.

Degree: Dept. of Computer Science, 2008, University of Victoria

URL: http://hdl.handle.net/1828/496

Subjects/Keywords: Flight control; Fault-tolerant computing

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APA (6^th Edition):

Feldstein, C. B. (2008). Development of a fault tolerant flight control system. (Thesis). University of Victoria. Retrieved from http://hdl.handle.net/1828/496

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Feldstein, Cary Benjamin. “Development of a fault tolerant flight control system.” 2008. Thesis, University of Victoria. Accessed January 16, 2021. http://hdl.handle.net/1828/496.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Feldstein, Cary Benjamin. “Development of a fault tolerant flight control system.” 2008. Web. 16 Jan 2021.

Vancouver:

Feldstein CB. Development of a fault tolerant flight control system. [Internet] [Thesis]. University of Victoria; 2008. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/1828/496.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Feldstein CB. Development of a fault tolerant flight control system. [Thesis]. University of Victoria; 2008. Available from: http://hdl.handle.net/1828/496

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Montana State University

17. Hane, Jennifer Susan. A fault-tolerant computer architecture for space vehicle applications.

Degree: MS, College of Engineering, 2012, Montana State University

URL: https://scholarworks.montana.edu/xmlui/handle/1/1423

► The discovery of new methods to protect electronics from harsh radiation environments outside earth's atmosphere is important to the future of space exploration. Reconfigurable, SRAM-based… (more)

▼ The discovery of new methods to protect electronics from harsh radiation environments outside earth's atmosphere is important to the future of space exploration. Reconfigurable, SRAM-based Field Programmable Gate Arrays (FPGAs) are especially promising candidates for future spacecraft computing platforms; however, their susceptibility to radiation-induced faults in their configuration memory makes their use a challenge. This thesis presents the design and testing of a redundant fault-tolerant architecture targeted at the Xilinx Virtex-6 FPGA. The architecture is based on a combination of triple modulo redundancy (TMR), numerous spare units, repair (scrubbing), and environmental awareness. By using the spares and the partial reconfiguration capabilities of the FPGA, the system can remain operational while repair of damaged modules proceeds in the background. The environmental awareness is supplied by a multi-pixel radiation sensor designed to rest above the FPGA chip, providing information about which areas of the chip have received radiation strikes. The system places these potentially damaged areas first in the queue for scrubbing. Four implementations of the architecture with different types of computing module and numbers of spares reveal its versatility and scalability. These four demonstration systems were modeled with theoretical Markov calculations, for the purpose of determining their reliability. They were also implemented on Xilinx hardware and tested by the injection of simulated faults, based on realistic orbital fault rate data from the Cosmic Ray Effects on Micro-Electronics Code (CREME96) tool. These results confirm that the systems will be highly reliable under typical earth orbit conditions. The results also demonstrate that the inclusion of numerous spares and the sensor both lead to substantial improvements in the Mean Time Before Failure, over a traditional TMR system with only three modules and scrubbing. Advisors/Committee Members: Chairperson, Graduate Committee: Brock LaMeres (advisor).

Subjects/Keywords: Computer architecture.; Fault-tolerant computing.; Field programmable gate arrays.; Aerospace engineering.

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APA (6^th Edition):

Hane, J. S. (2012). A fault-tolerant computer architecture for space vehicle applications. (Masters Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/1423

Chicago Manual of Style (16^th Edition):

Hane, Jennifer Susan. “A fault-tolerant computer architecture for space vehicle applications.” 2012. Masters Thesis, Montana State University. Accessed January 16, 2021. https://scholarworks.montana.edu/xmlui/handle/1/1423.

MLA Handbook (7^th Edition):

Hane, Jennifer Susan. “A fault-tolerant computer architecture for space vehicle applications.” 2012. Web. 16 Jan 2021.

Vancouver:

Hane JS. A fault-tolerant computer architecture for space vehicle applications. [Internet] [Masters thesis]. Montana State University; 2012. [cited 2021 Jan 16]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/1423.

Council of Science Editors:

Hane JS. A fault-tolerant computer architecture for space vehicle applications. [Masters Thesis]. Montana State University; 2012. Available from: https://scholarworks.montana.edu/xmlui/handle/1/1423

University of New Mexico

18. Anderson, Jonas. Fault-tolerance in two-dimensional topological systems.

Degree: Physics & Astronomy, 2012, University of New Mexico

URL: http://hdl.handle.net/1928/21017

► This thesis is a collection of ideas with the general goal of building, at least in the abstract, a local fault-tolerant quantum computer. The connection… (more)

▼ This thesis is a collection of ideas with the general goal of building, at least in the abstract, a local fault-tolerant quantum computer. The connection between quantum information and topology has proven to be an active area of research in several fields. The introduction of the toric code by Alexei Kitaev demonstrated the usefulness of topology for quantum memory and quantum computation. Many quantum codes used for quantum memory are modeled by spin systems on a lattice, with operators that extract syndrome information placed on vertices or faces of the lattice. It is natural to wonder whether the useful codes in such systems can be classified. This thesis presents work that leverages ideas from topology and graph theory to explore the space of such codes. Homological stabilizer codes are introduced and it is shown that, under a set of reasonable assumptions, any qubit homological stabilizer code is equivalent to either a toric code or a color code. Additionally, the toric code and the color code correspond to distinct classes of graphs. Many systems have been proposed as candidate quantum computers. It is very desirable to design quantum computing architectures with two-dimensional layouts and low complexity in parity-checking circuitry. Kitaev's surface codes provided the first example of codes satisfying this property. They provided a new route to fault tolerance with more modest overheads and thresholds approaching 1%. The recently discovered color codes share many properties with the surface codes, such as the ability to perform syndrome extraction locally in two dimensions. Some families of color codes admit a transversal implementation of the entire Clifford group. This work investigates color codes on the 4.8.8 lattice known as triangular codes. I develop a fault-tolerant error-correction strategy for these codes in which repeated syndrome measurements on this lattice generate a three-dimensional space-time combinatorial structure. I then develop an integer program that analyzes this structure and determines the most likely set of errors consistent with the observed syndrome values. I implement this integer program to find the threshold for depolarizing noise on small versions of these triangular codes. Because the threshold for magic-state distillation is likely to be higher than this value and because logical CNOT gates can be performed by code deformation in a single block instead of between pairs of blocks, the threshold for fault-tolerant quantum memory for these codes is also the threshold for fault-tolerant quantum computation with them. Since the advent of a threshold theorem for quantum computers much has been improved upon. Thresholds have increased, architectures have become more local, and gate sets have been simplified. The overhead for magic-state distillation has been studied, but not nearly to the extent of the aforementioned topics. A method for greatly reducing this overhead, known as reusable magic states, is studied here. While examples of reusable magic states exist for… Advisors/Committee Members: Caves, Carlton, Landahl, Andrew, Deutsch, Ivan, Loring, Terry.

Subjects/Keywords: Quantum computers; Low-dimensional topology; Fault-tolerant computing; Clifford algebras.

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APA (6^th Edition):

Anderson, J. (2012). Fault-tolerance in two-dimensional topological systems. (Doctoral Dissertation). University of New Mexico. Retrieved from http://hdl.handle.net/1928/21017

Chicago Manual of Style (16^th Edition):

Anderson, Jonas. “Fault-tolerance in two-dimensional topological systems.” 2012. Doctoral Dissertation, University of New Mexico. Accessed January 16, 2021. http://hdl.handle.net/1928/21017.

MLA Handbook (7^th Edition):

Anderson, Jonas. “Fault-tolerance in two-dimensional topological systems.” 2012. Web. 16 Jan 2021.

Vancouver:

Anderson J. Fault-tolerance in two-dimensional topological systems. [Internet] [Doctoral dissertation]. University of New Mexico; 2012. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/1928/21017.

Council of Science Editors:

Anderson J. Fault-tolerance in two-dimensional topological systems. [Doctoral Dissertation]. University of New Mexico; 2012. Available from: http://hdl.handle.net/1928/21017

University of Hong Kong

19. Ho, Wai-hong. Performance and fault-tolerance studies of wormhole routers in 2D meshes.

Degree: 1997, University of Hong Kong

URL: http://hdl.handle.net/10722/39427

Subjects/Keywords: Computer algorithms.; Fault-tolerant computing.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Ho, W. (1997). Performance and fault-tolerance studies of wormhole routers in 2D meshes. (Thesis). University of Hong Kong. Retrieved from http://hdl.handle.net/10722/39427

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Ho, Wai-hong. “Performance and fault-tolerance studies of wormhole routers in 2D meshes.” 1997. Thesis, University of Hong Kong. Accessed January 16, 2021. http://hdl.handle.net/10722/39427.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Ho, Wai-hong. “Performance and fault-tolerance studies of wormhole routers in 2D meshes.” 1997. Web. 16 Jan 2021.

Vancouver:

Ho W. Performance and fault-tolerance studies of wormhole routers in 2D meshes. [Internet] [Thesis]. University of Hong Kong; 1997. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/10722/39427.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ho W. Performance and fault-tolerance studies of wormhole routers in 2D meshes. [Thesis]. University of Hong Kong; 1997. Available from: http://hdl.handle.net/10722/39427

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Arizona

20. Hay, Karen June. A proof methodology for verification of real-time and fault-tolerance properties of distributed programs.

Degree: 1993, University of Arizona

URL: http://hdl.handle.net/10150/186261

► From the early days of programming, the dependability of software has been a concern. The development of distributed systems that must respond in real-time and… (more)

▼ From the early days of programming, the dependability of software has been a concern. The development of distributed systems that must respond in real-time and continue to function correctly in spite of hardware failure have increased the concern while making the task of ensuring dependability more complex. This dissertation presents a technique for improving confidence in software designed to execute on a distributed system of fail-stop processors. The methodology presented is based on a temporal logic augmented with time intervals and probability distributions. A temporal logic augmented with time intervals, Bounded Time Temporal Logic (BTTL), supports the specification and verification of real-time properties such as, "The program will poll the sensor every t to T time units." Analogously, a temporal logic augmented with probability distributions, Probabilistic Bounded Time Temporal Logic (PBTTL), supports reasoning about fault-tolerant properties such as, "The program will complete with probability less than or equal to p", and a combination of these properties such as, "The program will complete within t and T time units with probability less than or equal to p." The syntax and semantics of the two logics, BTTL and PBTTL, are carefully developed. This includes development of a program state model, state transition model, message passing system model and failure system model. An axiomatic program model is then presented and used for the development of a set of inference rules. The inference rules are designed to simplify use of the logic for reasoning about typical programming language constructs and commonly occurring programming scenarios. In addition to offering a systematic approach for verifying typical behaviors, the inference rules are intended to support the derivation of formulas expressing timing and probabilistic relationships between the execution times and probabilities of individual statements, groups of statements, message passing and failure recovery. Use of the methodology is demonstrated in examples of varying complexity, including five real-time examples and four combined real-time and fault-tolerant examples. Advisors/Committee Members: Downey, Peter J. (committeemember), Debray, Saumya (committeemember), Leonard, John (committeemember).

Subjects/Keywords: Fault-tolerant computing.; Computer science.

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APA (6^th Edition):

Hay, K. J. (1993). A proof methodology for verification of real-time and fault-tolerance properties of distributed programs. (Doctoral Dissertation). University of Arizona. Retrieved from http://hdl.handle.net/10150/186261

Chicago Manual of Style (16^th Edition):

Hay, Karen June. “A proof methodology for verification of real-time and fault-tolerance properties of distributed programs. ” 1993. Doctoral Dissertation, University of Arizona. Accessed January 16, 2021. http://hdl.handle.net/10150/186261.

MLA Handbook (7^th Edition):

Hay, Karen June. “A proof methodology for verification of real-time and fault-tolerance properties of distributed programs. ” 1993. Web. 16 Jan 2021.

Vancouver:

Hay KJ. A proof methodology for verification of real-time and fault-tolerance properties of distributed programs. [Internet] [Doctoral dissertation]. University of Arizona; 1993. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/10150/186261.

Council of Science Editors:

Hay KJ. A proof methodology for verification of real-time and fault-tolerance properties of distributed programs. [Doctoral Dissertation]. University of Arizona; 1993. Available from: http://hdl.handle.net/10150/186261

University of Hong Kong

21. Zhou, Jipeng. Fault-tolerant wormhole routing for mesh computers.

Degree: 2001, University of Hong Kong

URL: http://hdl.handle.net/10722/35583

Subjects/Keywords: Computer algorithms.; Fault-tolerant computing.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Zhou, J. (2001). Fault-tolerant wormhole routing for mesh computers. (Thesis). University of Hong Kong. Retrieved from http://hdl.handle.net/10722/35583

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Zhou, Jipeng. “Fault-tolerant wormhole routing for mesh computers.” 2001. Thesis, University of Hong Kong. Accessed January 16, 2021. http://hdl.handle.net/10722/35583.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Zhou, Jipeng. “Fault-tolerant wormhole routing for mesh computers.” 2001. Web. 16 Jan 2021.

Vancouver:

Zhou J. Fault-tolerant wormhole routing for mesh computers. [Internet] [Thesis]. University of Hong Kong; 2001. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/10722/35583.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhou J. Fault-tolerant wormhole routing for mesh computers. [Thesis]. University of Hong Kong; 2001. Available from: http://hdl.handle.net/10722/35583

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

22. Yueh, Wen, 1985. An efficient architecture for detection of multiple bit upsets in processor register files.

Degree: MS, Electrical and Computer Engineering, 2009, Rutgers University

URL: http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.000051428

► With the semiconductor industry transitioning into the next generation of deep submicron technology such as 40 nm or 32 nm CMOS technology, transistors are becoming… (more)

▼ With the semiconductor industry transitioning into the next generation of deep submicron technology such as 40 nm or 32 nm CMOS technology, transistors are becoming more vulnerable to malfunction due to soft errors. Due to the reduction in the supply and threshold voltages of the transistors in this smaller geometry, soft errors can affect the state of multiple numbers of transistors simultaneously. Hence, the traditional fault model of a single event upset (SEU) due to a soft error needs to be revisited and a new fault model and an associated fault tolerant architecture for circuit structures in deep submicron technology based on multiple-bit upsets (MBUs) needs to be developed. In this reseach work, we propose a novel fault tolerant architecture for the register files in a processor that can detect the MBUs in them efficiently. In this proposed method, we compute and store the Cyclic Redundancy Check (CRC) bits of a complete register which can be 32 bits or 64 bits wide, when new data is loaded into it. The CRC bits are of smaller bit size and are stored in a soft error protected memory structure using well known conventional soft error protection mechanisms such as error-correcting codes (ECCs), etc., for memory structures. When data from a register is read, first the new CRC value is computed based on the existing data value stored in that register and compared against the original CRC value stored previously in the soft error tolerant memory structure. If there is a difference in these two CRC values an error is flagged as it shows that the data is corrupted due to a soft error either by an SEU or MBUs during the time interval between the last write and the current read operation for that register. This operation is done for reading every register in the register file. Although this method introduces timing and area overheads, they are tolerable and this method of detection scales with the increase in the number registers in the register file. Finally, we present simulation results regarding the fault detection capability of this proposed method. Advisors/Committee Members: Yueh, Wen, 1985 (author), Chakraborty, Tapan (chair), Bushnell, Michael (co-chair), Parashar, Manish (internal member).

Subjects/Keywords: Fault-tolerant computing

…nano scaled sensors and devices emerge, fault tolerant hardware becomes critical in ensuring… …redundancy for our fault tolerant approach. Chapter 4 uses the idea of code redundancy and… …technique’s weakness. A fault tolerant system may incorporate one or more of these approaches to… …detected. 2.5.6 Fault Tolerant Systems In many mainframe computers, fault tolerant design is… …cycles. It becomes less attractive to build custom designed fault tolerant processors for large…

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APA (6^th Edition):

Yueh, Wen, 1. (2009). An efficient architecture for detection of multiple bit upsets in processor register files. (Masters Thesis). Rutgers University. Retrieved from http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.000051428

Chicago Manual of Style (16^th Edition):

Yueh, Wen, 1985. “An efficient architecture for detection of multiple bit upsets in processor register files.” 2009. Masters Thesis, Rutgers University. Accessed January 16, 2021. http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.000051428.

MLA Handbook (7^th Edition):

Yueh, Wen, 1985. “An efficient architecture for detection of multiple bit upsets in processor register files.” 2009. Web. 16 Jan 2021.

Vancouver:

Yueh, Wen 1. An efficient architecture for detection of multiple bit upsets in processor register files. [Internet] [Masters thesis]. Rutgers University; 2009. [cited 2021 Jan 16]. Available from: http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.000051428.

Council of Science Editors:

Yueh, Wen 1. An efficient architecture for detection of multiple bit upsets in processor register files. [Masters Thesis]. Rutgers University; 2009. Available from: http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.000051428

Simon Fraser University

23. Chau, Siu-Cheung. Fault-tolerance in multi-computer networks.

Degree: 1989, Simon Fraser University

URL: http://summit.sfu.ca/item/4938

Subjects/Keywords: Computer networks.; Fault-tolerant computing.

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APA (6^th Edition):

Chau, S. (1989). Fault-tolerance in multi-computer networks. (Thesis). Simon Fraser University. Retrieved from http://summit.sfu.ca/item/4938

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chau, Siu-Cheung. “Fault-tolerance in multi-computer networks.” 1989. Thesis, Simon Fraser University. Accessed January 16, 2021. http://summit.sfu.ca/item/4938.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chau, Siu-Cheung. “Fault-tolerance in multi-computer networks.” 1989. Web. 16 Jan 2021.

Vancouver:

Chau S. Fault-tolerance in multi-computer networks. [Internet] [Thesis]. Simon Fraser University; 1989. [cited 2021 Jan 16]. Available from: http://summit.sfu.ca/item/4938.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chau S. Fault-tolerance in multi-computer networks. [Thesis]. Simon Fraser University; 1989. Available from: http://summit.sfu.ca/item/4938

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Simon Fraser University

24. Chau, Siu-Cheung. New methods to generate minimal broadcast networks and fault-tolerant minimal broadcast networks.

Degree: 1984, Simon Fraser University

URL: http://summit.sfu.ca/item/6015

Subjects/Keywords: Computer networks.; Fault-tolerant computing.

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APA (6^th Edition):

Chau, S. (1984). New methods to generate minimal broadcast networks and fault-tolerant minimal broadcast networks. (Thesis). Simon Fraser University. Retrieved from http://summit.sfu.ca/item/6015

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chau, Siu-Cheung. “New methods to generate minimal broadcast networks and fault-tolerant minimal broadcast networks.” 1984. Thesis, Simon Fraser University. Accessed January 16, 2021. http://summit.sfu.ca/item/6015.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chau, Siu-Cheung. “New methods to generate minimal broadcast networks and fault-tolerant minimal broadcast networks.” 1984. Web. 16 Jan 2021.

Vancouver:

Chau S. New methods to generate minimal broadcast networks and fault-tolerant minimal broadcast networks. [Internet] [Thesis]. Simon Fraser University; 1984. [cited 2021 Jan 16]. Available from: http://summit.sfu.ca/item/6015.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chau S. New methods to generate minimal broadcast networks and fault-tolerant minimal broadcast networks. [Thesis]. Simon Fraser University; 1984. Available from: http://summit.sfu.ca/item/6015

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

The Ohio State University

25. Leal, William. A foundation for fault tolerant components.

Degree: PhD, Graduate School, 2001, The Ohio State University

URL: http://rave.ohiolink.edu/etdc/view?acc_num=osu1486402957194912

Subjects/Keywords: Computer Science; Fault-tolerant computing

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APA (6^th Edition):

Leal, W. (2001). A foundation for fault tolerant components. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1486402957194912

Chicago Manual of Style (16^th Edition):

Leal, William. “A foundation for fault tolerant components.” 2001. Doctoral Dissertation, The Ohio State University. Accessed January 16, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=osu1486402957194912.

MLA Handbook (7^th Edition):

Leal, William. “A foundation for fault tolerant components.” 2001. Web. 16 Jan 2021.

Vancouver:

Leal W. A foundation for fault tolerant components. [Internet] [Doctoral dissertation]. The Ohio State University; 2001. [cited 2021 Jan 16]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1486402957194912.

Council of Science Editors:

Leal W. A foundation for fault tolerant components. [Doctoral Dissertation]. The Ohio State University; 2001. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1486402957194912

Michigan State University

26. Lin, Yiyan. Automated addition of fault-tolerance via lazy repair and graceful degradation.

Degree: 2015, Michigan State University

URL: http://etd.lib.msu.edu/islandora/object/etd:3418

► In this dissertation, we concentrate on the problem of automated addition of fault-tolerance that transforms a fault-intolerant program to be a fault-tolerant program. We solve… (more)

▼ In this dissertation, we concentrate on the problem of automated addition of fault-tolerance that transforms a fault-intolerant program to be a fault-tolerant program. We solve this problem via model repair. Model repair is a correct-by-construct technique to revise an existing model so that the revised model satisfies the given correctness criteria, such as safety, liveness, or fault-tolerance. We consider two problems of using model repair to add fault-tolerance. First, if the repaired model violates the assumptions (e.g., partial observability, inability to detect crashed processes, etc) made in the underlying system, then it cannot be implemented. We denote these requirements as realizability constraints. Second, the addition of fault-tolerance may fail if the program cannot fully recover after certain faults occur. In this dissertation, we propose a lazy repair approach to address realizability issues in adding fault-tolerance. Additionally, we propose a technique to automatically add graceful degradation to a program, so that the program can recover with partial functionality (that is identified by the designer to be the critical functionality) if full recovery is impossible.A model repair technique transforms a model to another model that satisfies a new set of properties. Such a transformation should also maintain the mapping between the model and the underlying program. For example, in a distributed program, every process is restricted to read (or write) some variables in other processes. A model that represents this program should also disallow the process to read (or write) those inaccessable variables. If these constraints are violated, then the corresponding model will be unrealizable. An unrealizable model (in this context, a model that violates the read/write restrictions) may make it impossible to obtain the corresponding implementation.%In this dissertation, we call the read (or write) restriction as a realizability constraint in distributed systems. An unrealizable model (a model that violates the realizability constraints) may complicate the implementation by introducing extra amount of modification to the program. Such modification may in turn break the program's correctness.Resolving realizability constraints increases the complexity of model repair. Existing model repair techniques introduce heuristics to reduce the complexity. However, this heuristic-based approach is designed and optimized specifically for distributed programs. We need a more generic model repair approach for other types of programs, e.g., synchronous programs, cyber-physical programs, etc. Hence, in this dissertation, we propose a model repair technique, i.e., lazy repair, to add fault-tolerance to programs with different types of realizability constraints. It involves two steps. First, we only focus on repairing to obtain a model that satisfies correctness criteria while ignoring realizability constraints. In the second step, we repair this model further by removing behaviors while ensuring that the desired specification is… Advisors/Committee Members: Kulkarni, Sandeep, Torng, Eric, Dillon, Laura, Kulkarni, Rajesh.

Subjects/Keywords: Fault-tolerant computing – Mathematical models; Computer science; Lazy repair; Graceful degradation

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APA (6^th Edition):

Lin, Y. (2015). Automated addition of fault-tolerance via lazy repair and graceful degradation. (Thesis). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:3418

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lin, Yiyan. “Automated addition of fault-tolerance via lazy repair and graceful degradation.” 2015. Thesis, Michigan State University. Accessed January 16, 2021. http://etd.lib.msu.edu/islandora/object/etd:3418.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lin, Yiyan. “Automated addition of fault-tolerance via lazy repair and graceful degradation.” 2015. Web. 16 Jan 2021.

Vancouver:

Lin Y. Automated addition of fault-tolerance via lazy repair and graceful degradation. [Internet] [Thesis]. Michigan State University; 2015. [cited 2021 Jan 16]. Available from: http://etd.lib.msu.edu/islandora/object/etd:3418.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin Y. Automated addition of fault-tolerance via lazy repair and graceful degradation. [Thesis]. Michigan State University; 2015. Available from: http://etd.lib.msu.edu/islandora/object/etd:3418

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

27. Vemu, Ramtilak, 1981-. Low-cost assertion-based fault tolerance in hardware and software.

Degree: PhD, Electrical and Computer Engineering, 2008, University of Texas – Austin

URL: http://hdl.handle.net/2152/18263

► In the recent past, there has been an increasing demand for low-cost safety critical applications. Custom-off-the-shelf (COTS) processors are preferred for usage in these applications… (more)

▼ In the recent past, there has been an increasing demand for low-cost safety critical applications. Custom-off-the-shelf (COTS) processors are preferred for usage in these applications due to their low cost. The reliability provided by these processors, however, is not sufficient to meet the safety requirements of these applications. Furthermore, due to the trends followed by the processor industry to enhance the performance of processors, the reliability provided by these processors is projected to decrease in the future. Traditional techniques for enhancing the reliability of computer systems are not viable for these applications due to the high overheads (and hence cost) incurred by them. This thesis describes fault tolerance techniques tailored for these applications, adhering to the tight overhead constraints in the area, memory, and performance dimensions. Techniques at both the hardware level (to be used by the processor manufacturers) and the software level (to be used by the application developers) are presented. At the hardware level, this thesis presents a technique for detecting faults in the processor control logic, for which techniques proposed previously incur very high overheads. Rather than detect all modeled faults, the technique protects against a subset of faults such that the best possible overall protection is achieved while incurring only permissible overheads. This subset of faults is selected depending on the probability of each individual fault causing damage to the architectural state of the processor and the overhead incurred in protecting against the fault. The technique is validated on control logic modules of an industrial processor. At the software level, this thesis concentrates on a category of errors called control flow errors. We describe an error detection technique which incurs lower overheads than any of the previously proposed techniques while at the same time detecting more errors than all of them. Even these low overheads may be too restrictive for some applications. For such applications, we present a technique for providing the best error detection capability possible at the overheads allowed. Once an error is detected, error recovery actions need to be performed. In this thesis, we present an error correction technique which automatically performs error recovery with a very low latency. The technique reuses the information available from the error detection technique to perform the recovery and hence, does not incur any additional performance penalty. All the techniques proposed at the software level have been integrated with GCC, a commonly used software compiler. This permits the fault tolerance to be incorporated into the application automatically as part of the compilation process itself. Evaluations are performed on SPEC and MiBench benchmark programs using an in-house software error injection framework. Advisors/Committee Members: Abraham, Jacob A. (advisor).

Subjects/Keywords: Fault-tolerant computing; Fault-tolerant computing – Cost control

…6.6.2 Application to algorithmically fault tolerant programs . 6.6.3 Evaluation of ACCED… …run till a version which passes the test is found. In the recent past, many fault tolerant… …cost. Extra code is embedded inside the program which performs the fault tolerant actions. In… …overheads. This subset of faults is selected depending on the probability of each individual fault… …protecting against the fault. The technique is validated on control logic modules of an industrial…

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APA (6^th Edition):

Vemu, Ramtilak, 1. (2008). Low-cost assertion-based fault tolerance in hardware and software. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/18263

Chicago Manual of Style (16^th Edition):

Vemu, Ramtilak, 1981-. “Low-cost assertion-based fault tolerance in hardware and software.” 2008. Doctoral Dissertation, University of Texas – Austin. Accessed January 16, 2021. http://hdl.handle.net/2152/18263.

MLA Handbook (7^th Edition):

Vemu, Ramtilak, 1981-. “Low-cost assertion-based fault tolerance in hardware and software.” 2008. Web. 16 Jan 2021.

Vancouver:

Vemu, Ramtilak 1. Low-cost assertion-based fault tolerance in hardware and software. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2008. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/2152/18263.

Council of Science Editors:

Vemu, Ramtilak 1. Low-cost assertion-based fault tolerance in hardware and software. [Doctoral Dissertation]. University of Texas – Austin; 2008. Available from: http://hdl.handle.net/2152/18263

Ryerson University

28. Fernanco, K. C. Hot Pixel Detection For Star Trackers.

Degree: 2012, Ryerson University

URL: https://digital.library.ryerson.ca/islandora/object/RULA%3A1728

► This thesis examines the damage induced by proton radiation on the Sinclair Interplanetary S3S star tracker. The star tracker is made from commercial othe shelve… (more)

Subjects/Keywords: Materials – Effect of space environment on; Space vehicles – Materials; Fault-tolerant computing – Testing; Radiation tolerance

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APA (6^th Edition):

Fernanco, K. C. (2012). Hot Pixel Detection For Star Trackers. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A1728

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Fernanco, K C. “Hot Pixel Detection For Star Trackers.” 2012. Thesis, Ryerson University. Accessed January 16, 2021. https://digital.library.ryerson.ca/islandora/object/RULA%3A1728.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Fernanco, K C. “Hot Pixel Detection For Star Trackers.” 2012. Web. 16 Jan 2021.

Vancouver:

Fernanco KC. Hot Pixel Detection For Star Trackers. [Internet] [Thesis]. Ryerson University; 2012. [cited 2021 Jan 16]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1728.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fernanco KC. Hot Pixel Detection For Star Trackers. [Thesis]. Ryerson University; 2012. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A1728

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Hong Kong

29. Xue, Zhengyuan. Implementation of fault-tolerant quantum computation with superconducting device.

Degree: 2009, University of Hong Kong

URL: http://hdl.handle.net/10722/56584

Subjects/Keywords: Quantum computers.; Superconductors.; Fault-tolerant computing.

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APA (6^th Edition):

Xue, Z. (2009). Implementation of fault-tolerant quantum computation with superconducting device. (Thesis). University of Hong Kong. Retrieved from http://hdl.handle.net/10722/56584

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Xue, Zhengyuan. “Implementation of fault-tolerant quantum computation with superconducting device.” 2009. Thesis, University of Hong Kong. Accessed January 16, 2021. http://hdl.handle.net/10722/56584.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Xue, Zhengyuan. “Implementation of fault-tolerant quantum computation with superconducting device.” 2009. Web. 16 Jan 2021.

Vancouver:

Xue Z. Implementation of fault-tolerant quantum computation with superconducting device. [Internet] [Thesis]. University of Hong Kong; 2009. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/10722/56584.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xue Z. Implementation of fault-tolerant quantum computation with superconducting device. [Thesis]. University of Hong Kong; 2009. Available from: http://hdl.handle.net/10722/56584

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Michigan

30. Feng, Shuguang. Delivering Affordable Fault-tolerance to Commodity Computer Systems.

Degree: PhD, Computer Science & Engineering, 2011, University of Michigan

URL: http://hdl.handle.net/2027.42/86483

► To meet an insatiable consumer demand for greater performance at less power, silicon technology has scaled to unprecedented dimensions. This aggressive scaling has provided designers… (more)

▼ To meet an insatiable consumer demand for greater performance at less power, silicon technology has scaled to unprecedented dimensions. This aggressive scaling has provided designers with an ever increasing budget of cheaper and faster transistors. Unfortunately, this trend has also been accompanied by a decline in individual device reliability as transistors have become increasingly susceptible to a host of threats. With each new technology generation the challenges associated with process variation, wearout, and transient faults gain greater prominence. We are quickly approaching a new era where fault-tolerance is becoming a first-order design constraint, no longer a luxury reserved exclusively for high-reliability, mission-critical domains. Even commodity microprocessors used in mainstream computing will require protection. However, just as the reliability needs of NASA and Apple differ dramatically, so does their ability to absorb the costs necessary to ensure fault-tolerance. Viable solutions targeting commodity systems must not only recognize this fact, but must embrace it. Simply stripping down techniques developed for enterprise servers may not result in the most appropriate designs for your laptop or cellphone. The best solutions will exploit the relaxed reliability constraints of commodity systems, judiciously sacrificing a small degree of fault tolerance to achieve far greater reductions in overhead costs. This thesis proposes a collection of works that can be selectively mixed and matched to assemble reliability solutions tailor-fit for the commodity systems community. Although the works presented address a variety of different issues from wearout to transient faults and prevention to detection, they were all motivated by the same observation–that much of the overhead costs associated with conventional fault tolerance mechanisms are spent in pursuit of the last few “nines” of reliability. This conclusion gave rise to the philosophy permeating the chapters of this work, that summarily dismissing techniques that cannot supply mission-critical fault tolerance is no longer acceptable. In presenting concrete solutions to a few of the more interesting challenges—proactive wear-leveling orchestrated through intelligent job scheduling and software-only transient fault detection and recovery that exploits intrinsic computational patterns within applications—we establish fundamental principles that can be applied more broadly to formulate a comprehensive reliability strategy. Advisors/Committee Members: Mahlke, Scott (committee member), Blaauw, David (committee member), Bose, Pradip (committee member), Mudge, Trevor N. (committee member), Sylvester, Dennis Michael (committee member), Wenisch, Thomas F. (committee member).

Subjects/Keywords: Fault Tolerant Computing; Computer Architecture; Compiler Analysis; Computer Science; Electrical Engineering; Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Feng, S. (2011). Delivering Affordable Fault-tolerance to Commodity Computer Systems. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/86483

Chicago Manual of Style (16^th Edition):

Feng, Shuguang. “Delivering Affordable Fault-tolerance to Commodity Computer Systems.” 2011. Doctoral Dissertation, University of Michigan. Accessed January 16, 2021. http://hdl.handle.net/2027.42/86483.

MLA Handbook (7^th Edition):

Feng, Shuguang. “Delivering Affordable Fault-tolerance to Commodity Computer Systems.” 2011. Web. 16 Jan 2021.

Vancouver:

Feng S. Delivering Affordable Fault-tolerance to Commodity Computer Systems. [Internet] [Doctoral dissertation]. University of Michigan; 2011. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/2027.42/86483.

Council of Science Editors:

Feng S. Delivering Affordable Fault-tolerance to Commodity Computer Systems. [Doctoral Dissertation]. University of Michigan; 2011. Available from: http://hdl.handle.net/2027.42/86483

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Open Access Theses and Dissertations