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You searched for subject:(Fault injection). Showing records 1 – 30 of 120 total matches.

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University of Texas – Austin

1. Chaudhari, Ameya Suhas. Fiesta++ : a software implemented fault injection tool for transient fault injection.

Degree: MSin Engineering, Electrical and Computer Engineering, 2014, University of Texas – Austin

 Computer systems, even when correctly designed, can suffer from temporary errors due to radiation particles striking the circuit or changes in the operating conditions such… (more)

Subjects/Keywords: Fault injection; SWIFI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chaudhari, A. S. (2014). Fiesta++ : a software implemented fault injection tool for transient fault injection. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/28159

Chicago Manual of Style (16th Edition):

Chaudhari, Ameya Suhas. “Fiesta++ : a software implemented fault injection tool for transient fault injection.” 2014. Masters Thesis, University of Texas – Austin. Accessed February 24, 2020. http://hdl.handle.net/2152/28159.

MLA Handbook (7th Edition):

Chaudhari, Ameya Suhas. “Fiesta++ : a software implemented fault injection tool for transient fault injection.” 2014. Web. 24 Feb 2020.

Vancouver:

Chaudhari AS. Fiesta++ : a software implemented fault injection tool for transient fault injection. [Internet] [Masters thesis]. University of Texas – Austin; 2014. [cited 2020 Feb 24]. Available from: http://hdl.handle.net/2152/28159.

Council of Science Editors:

Chaudhari AS. Fiesta++ : a software implemented fault injection tool for transient fault injection. [Masters Thesis]. University of Texas – Austin; 2014. Available from: http://hdl.handle.net/2152/28159


Kennesaw State University

2. Bulusu, Pranahita. Detection of Lightweight Directory Access Protocol Query Injection Attacks in Web Applications.

Degree: MSCS, Computer Science, 2015, Kennesaw State University

  The Lightweight Directory Access Protocol (LDAP) is a common protocol used in organizations for Directory Service. LDAP is popular because of its features such… (more)

Subjects/Keywords: LDAP injection; Web security; Fault injection; Object Constraint Language; SQL injection

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APA (6th Edition):

Bulusu, P. (2015). Detection of Lightweight Directory Access Protocol Query Injection Attacks in Web Applications. (Thesis). Kennesaw State University. Retrieved from https://digitalcommons.kennesaw.edu/cs_etd/1

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bulusu, Pranahita. “Detection of Lightweight Directory Access Protocol Query Injection Attacks in Web Applications.” 2015. Thesis, Kennesaw State University. Accessed February 24, 2020. https://digitalcommons.kennesaw.edu/cs_etd/1.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bulusu, Pranahita. “Detection of Lightweight Directory Access Protocol Query Injection Attacks in Web Applications.” 2015. Web. 24 Feb 2020.

Vancouver:

Bulusu P. Detection of Lightweight Directory Access Protocol Query Injection Attacks in Web Applications. [Internet] [Thesis]. Kennesaw State University; 2015. [cited 2020 Feb 24]. Available from: https://digitalcommons.kennesaw.edu/cs_etd/1.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bulusu P. Detection of Lightweight Directory Access Protocol Query Injection Attacks in Web Applications. [Thesis]. Kennesaw State University; 2015. Available from: https://digitalcommons.kennesaw.edu/cs_etd/1

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

3. Chen, Yi-Chieh. A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 We present an integrated development environment (IDE) with GUI for generating and evaluating the fault-tolerant microprocessor. Designer can select from hardware options (dual-core for microprocessor,… (more)

Subjects/Keywords: Fault-Tolerant; Microprocessor; Memory; Fault Injection; Fault Coverage

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APA (6th Edition):

Chen, Y. (2015). A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1115115-082713

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Yi-Chieh. “A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches.” 2015. Thesis, NSYSU. Accessed February 24, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1115115-082713.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Yi-Chieh. “A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches.” 2015. Web. 24 Feb 2020.

Vancouver:

Chen Y. A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Feb 24]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1115115-082713.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Y. A Workbench for Fault-Tolerant Microprocessor with Multiple HW/SW Approaches. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1115115-082713

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. Espinosa García, Jaime. New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs .

Degree: 2016, Universitat Politècnica de València

 [EN] Relevance of electronics towards safety of common devices has only been growing, as an ever growing stake of the functionality is assigned to them.… (more)

Subjects/Keywords: Fault tolerance; Fault injection; Error detection; Fault mitigation; Fault recovery; Fugacious faults; FALLES; CODESH

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APA (6th Edition):

Espinosa García, J. (2016). New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs . (Doctoral Dissertation). Universitat Politècnica de València. Retrieved from http://hdl.handle.net/10251/73146

Chicago Manual of Style (16th Edition):

Espinosa García, Jaime. “New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs .” 2016. Doctoral Dissertation, Universitat Politècnica de València. Accessed February 24, 2020. http://hdl.handle.net/10251/73146.

MLA Handbook (7th Edition):

Espinosa García, Jaime. “New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs .” 2016. Web. 24 Feb 2020.

Vancouver:

Espinosa García J. New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs . [Internet] [Doctoral dissertation]. Universitat Politècnica de València; 2016. [cited 2020 Feb 24]. Available from: http://hdl.handle.net/10251/73146.

Council of Science Editors:

Espinosa García J. New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs . [Doctoral Dissertation]. Universitat Politècnica de València; 2016. Available from: http://hdl.handle.net/10251/73146


Anna University

5. Paloli mohammed shareef. Study of fault injection patterns in Software development to analyse Defect leakage and amplification;.

Degree: Study of fault injection patterns in Software development to analyse Defect leakage and amplification, 2015, Anna University

Software reliability for business applications is becoming a topic of newlineinterest in IT community Fault injection involves the deliberate insertion of newlinefaults or errors into… (more)

Subjects/Keywords: Amplification Index; Fault Injection Experiments; Software development

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APA (6th Edition):

shareef, P. m. (2015). Study of fault injection patterns in Software development to analyse Defect leakage and amplification;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/40689

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

shareef, Paloli mohammed. “Study of fault injection patterns in Software development to analyse Defect leakage and amplification;.” 2015. Thesis, Anna University. Accessed February 24, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/40689.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

shareef, Paloli mohammed. “Study of fault injection patterns in Software development to analyse Defect leakage and amplification;.” 2015. Web. 24 Feb 2020.

Vancouver:

shareef Pm. Study of fault injection patterns in Software development to analyse Defect leakage and amplification;. [Internet] [Thesis]. Anna University; 2015. [cited 2020 Feb 24]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40689.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

shareef Pm. Study of fault injection patterns in Software development to analyse Defect leakage and amplification;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40689

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

6. Chetia, Jugantor. An efficient AVF estimation technique using circuit partitioning.

Degree: MS, Electrical Engineering, 2012, Vanderbilt University

 Soft errors induced by radiation particles are increasingly becoming a source of concern for reliable design of VLSI systems. An important parameter to quantify the… (more)

Subjects/Keywords: AVF; statistical fault injection; circuit partitioning

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APA (6th Edition):

Chetia, J. (2012). An efficient AVF estimation technique using circuit partitioning. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-01252012-174557/ ;

Chicago Manual of Style (16th Edition):

Chetia, Jugantor. “An efficient AVF estimation technique using circuit partitioning.” 2012. Masters Thesis, Vanderbilt University. Accessed February 24, 2020. http://etd.library.vanderbilt.edu/available/etd-01252012-174557/ ;.

MLA Handbook (7th Edition):

Chetia, Jugantor. “An efficient AVF estimation technique using circuit partitioning.” 2012. Web. 24 Feb 2020.

Vancouver:

Chetia J. An efficient AVF estimation technique using circuit partitioning. [Internet] [Masters thesis]. Vanderbilt University; 2012. [cited 2020 Feb 24]. Available from: http://etd.library.vanderbilt.edu/available/etd-01252012-174557/ ;.

Council of Science Editors:

Chetia J. An efficient AVF estimation technique using circuit partitioning. [Masters Thesis]. Vanderbilt University; 2012. Available from: http://etd.library.vanderbilt.edu/available/etd-01252012-174557/ ;


University of Illinois – Urbana-Champaign

7. Jacques da Silva, Gabriela. Partial fault tolerance in stream processing applications - methods and evaluation techniques.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

 Stream processing emerged as a paradigm to continuously process incoming live data streams, such as audio, video, and business feeds. These applications are assembled as… (more)

Subjects/Keywords: fault tolerance; fault injection; stream processing; model-based evaluation; high-availability

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APA (6th Edition):

Jacques da Silva, G. (2011). Partial fault tolerance in stream processing applications - methods and evaluation techniques. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18383

Chicago Manual of Style (16th Edition):

Jacques da Silva, Gabriela. “Partial fault tolerance in stream processing applications - methods and evaluation techniques.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed February 24, 2020. http://hdl.handle.net/2142/18383.

MLA Handbook (7th Edition):

Jacques da Silva, Gabriela. “Partial fault tolerance in stream processing applications - methods and evaluation techniques.” 2011. Web. 24 Feb 2020.

Vancouver:

Jacques da Silva G. Partial fault tolerance in stream processing applications - methods and evaluation techniques. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2020 Feb 24]. Available from: http://hdl.handle.net/2142/18383.

Council of Science Editors:

Jacques da Silva G. Partial fault tolerance in stream processing applications - methods and evaluation techniques. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18383


Universidade do Rio Grande do Sul

8. Azambuja, José Rodrigo Furlanetto de. Análise de técnicas de tolerância a falhas baseadas em software para a proteção de microprocessadores.

Degree: 2010, Universidade do Rio Grande do Sul

Da mesma maneira que novas tecnologias trouxeram avanços para a indústria de semicondutores, diminuíram a confiabilidade dos transistores e consequentemente dos sistemas digitais. Efeitos causados… (more)

Subjects/Keywords: Microeletrônica; Software-based fault tolerant techniques; Tolerancia : Falhas; Microprocessors; Fault injection

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APA (6th Edition):

Azambuja, J. R. F. d. (2010). Análise de técnicas de tolerância a falhas baseadas em software para a proteção de microprocessadores. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/49076

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Azambuja, José Rodrigo Furlanetto de. “Análise de técnicas de tolerância a falhas baseadas em software para a proteção de microprocessadores.” 2010. Thesis, Universidade do Rio Grande do Sul. Accessed February 24, 2020. http://hdl.handle.net/10183/49076.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Azambuja, José Rodrigo Furlanetto de. “Análise de técnicas de tolerância a falhas baseadas em software para a proteção de microprocessadores.” 2010. Web. 24 Feb 2020.

Vancouver:

Azambuja JRFd. Análise de técnicas de tolerância a falhas baseadas em software para a proteção de microprocessadores. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2010. [cited 2020 Feb 24]. Available from: http://hdl.handle.net/10183/49076.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Azambuja JRFd. Análise de técnicas de tolerância a falhas baseadas em software para a proteção de microprocessadores. [Thesis]. Universidade do Rio Grande do Sul; 2010. Available from: http://hdl.handle.net/10183/49076

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

9. Isaza-González, José. Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación .

Degree: 2018, University of Alicante

 El funcionamiento correcto de un sistema electrónico, aún bajo perturbaciones y fallos causados por la radiación, ha sido siempre un factor crucial en aplicaciones aeroespaciales,… (more)

Subjects/Keywords: Microprocessor reliability; Fault injection; Soft error; Radiation effects fault tolerance

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APA (6th Edition):

Isaza-González, J. (2018). Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación . (Thesis). University of Alicante. Retrieved from http://hdl.handle.net/10045/90359

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Isaza-González, José. “Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación .” 2018. Thesis, University of Alicante. Accessed February 24, 2020. http://hdl.handle.net/10045/90359.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Isaza-González, José. “Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación .” 2018. Web. 24 Feb 2020.

Vancouver:

Isaza-González J. Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación . [Internet] [Thesis]. University of Alicante; 2018. [cited 2020 Feb 24]. Available from: http://hdl.handle.net/10045/90359.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Isaza-González J. Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación . [Thesis]. University of Alicante; 2018. Available from: http://hdl.handle.net/10045/90359

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

10. Deshpande, Chinmay Ravindra. Hardware Fault Attack Detection Methods for Secure Embedded Systems.

Degree: MS, Electrical and Computer Engineering, 2018, Virginia Tech

 In our daily life, we are increasingly putting our trust in embedded software applications, which run on a range of processor-based embedded systems from smartcards… (more)

Subjects/Keywords: Fault Attack; Countermeasures; Detection; Clock glitching; Electromagnetic Fault Injection

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APA (6th Edition):

Deshpande, C. R. (2018). Hardware Fault Attack Detection Methods for Secure Embedded Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/82141

Chicago Manual of Style (16th Edition):

Deshpande, Chinmay Ravindra. “Hardware Fault Attack Detection Methods for Secure Embedded Systems.” 2018. Masters Thesis, Virginia Tech. Accessed February 24, 2020. http://hdl.handle.net/10919/82141.

MLA Handbook (7th Edition):

Deshpande, Chinmay Ravindra. “Hardware Fault Attack Detection Methods for Secure Embedded Systems.” 2018. Web. 24 Feb 2020.

Vancouver:

Deshpande CR. Hardware Fault Attack Detection Methods for Secure Embedded Systems. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2020 Feb 24]. Available from: http://hdl.handle.net/10919/82141.

Council of Science Editors:

Deshpande CR. Hardware Fault Attack Detection Methods for Secure Embedded Systems. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/82141


Brigham Young University

11. Anderson, Jon-Paul. Duplicate with Choose: Using Statistics for Fault Mitigation.

Degree: PhD, 2016, Brigham Young University

 This dissertation presents a novel technique called duplicate with choose (DWCh) which is a modification of the fault detection technique duplicate with compare (DWC). DWCh… (more)

Subjects/Keywords: reliability; fault mitigation; fault injection; concurrent error detection; DWC; DWCh; FPGA

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APA (6th Edition):

Anderson, J. (2016). Duplicate with Choose: Using Statistics for Fault Mitigation. (Doctoral Dissertation). Brigham Young University. Retrieved from https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=6963&context=etd

Chicago Manual of Style (16th Edition):

Anderson, Jon-Paul. “Duplicate with Choose: Using Statistics for Fault Mitigation.” 2016. Doctoral Dissertation, Brigham Young University. Accessed February 24, 2020. https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=6963&context=etd.

MLA Handbook (7th Edition):

Anderson, Jon-Paul. “Duplicate with Choose: Using Statistics for Fault Mitigation.” 2016. Web. 24 Feb 2020.

Vancouver:

Anderson J. Duplicate with Choose: Using Statistics for Fault Mitigation. [Internet] [Doctoral dissertation]. Brigham Young University; 2016. [cited 2020 Feb 24]. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=6963&context=etd.

Council of Science Editors:

Anderson J. Duplicate with Choose: Using Statistics for Fault Mitigation. [Doctoral Dissertation]. Brigham Young University; 2016. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=6963&context=etd


University of Illinois – Urbana-Champaign

12. Jiang, Rui. Detection, diagnosis and modeling of ESD-induced soft failures - a gate-level and mixed-signal approach.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 Electronic systems are an indispensable part of people's lives today. However, the reliability of electronic systems can be threatened by external stimuli such as Electrostatic… (more)

Subjects/Keywords: Electrostatic discharges (ESD); Reliability; Fault modeling; Mixed-signal simulation; Fault injection; Fault detection

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jiang, R. (2017). Detection, diagnosis and modeling of ESD-induced soft failures - a gate-level and mixed-signal approach. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/98317

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jiang, Rui. “Detection, diagnosis and modeling of ESD-induced soft failures - a gate-level and mixed-signal approach.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed February 24, 2020. http://hdl.handle.net/2142/98317.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jiang, Rui. “Detection, diagnosis and modeling of ESD-induced soft failures - a gate-level and mixed-signal approach.” 2017. Web. 24 Feb 2020.

Vancouver:

Jiang R. Detection, diagnosis and modeling of ESD-induced soft failures - a gate-level and mixed-signal approach. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Feb 24]. Available from: http://hdl.handle.net/2142/98317.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jiang R. Detection, diagnosis and modeling of ESD-induced soft failures - a gate-level and mixed-signal approach. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/98317

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. Tian, Ninghan. ETFIDS: Efficient Transient Fault Injection and Detection System.

Degree: MSs, EECS - Electrical Engineering, 2018, Case Western Reserve University School of Graduate Studies

 Computer use in high dependability applications is rapidly increasing. However, even when correctly designed, computer systems can still suffer from temporary errors due to various… (more)

Subjects/Keywords: Electrical Engineering; Fault-injection; dependable system; fault-tolerant system; fault; error; latency; coverage

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APA (6th Edition):

Tian, N. (2018). ETFIDS: Efficient Transient Fault Injection and Detection System. (Masters Thesis). Case Western Reserve University School of Graduate Studies. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=case1544716635499045

Chicago Manual of Style (16th Edition):

Tian, Ninghan. “ETFIDS: Efficient Transient Fault Injection and Detection System.” 2018. Masters Thesis, Case Western Reserve University School of Graduate Studies. Accessed February 24, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=case1544716635499045.

MLA Handbook (7th Edition):

Tian, Ninghan. “ETFIDS: Efficient Transient Fault Injection and Detection System.” 2018. Web. 24 Feb 2020.

Vancouver:

Tian N. ETFIDS: Efficient Transient Fault Injection and Detection System. [Internet] [Masters thesis]. Case Western Reserve University School of Graduate Studies; 2018. [cited 2020 Feb 24]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1544716635499045.

Council of Science Editors:

Tian N. ETFIDS: Efficient Transient Fault Injection and Detection System. [Masters Thesis]. Case Western Reserve University School of Graduate Studies; 2018. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1544716635499045


Université de Grenoble

14. Ben Jirad, Mohamed. Robustesse par conception de circuits implantés sur FPGA SRAM et validation par injection de fautes : Robustness improvement by designing circuits implemented on SRAM FPGAs and validation by fault injection.

Degree: Docteur es, Sciences et technologie industrielles, 2013, Université de Grenoble

Cette thèse s'intéresse en premier lieu à l'évaluation des effets fonctionnels des erreurs survenant dans la mémoire SRAM de configuration de certains FPGAs. La famille… (more)

Subjects/Keywords: FPGA à base de SRAM; Robustesse; Injection de fautes; SRAM-based FPGAs; Robustness; Fault injection

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APA (6th Edition):

Ben Jirad, M. (2013). Robustesse par conception de circuits implantés sur FPGA SRAM et validation par injection de fautes : Robustness improvement by designing circuits implemented on SRAM FPGAs and validation by fault injection. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2013GRENT035

Chicago Manual of Style (16th Edition):

Ben Jirad, Mohamed. “Robustesse par conception de circuits implantés sur FPGA SRAM et validation par injection de fautes : Robustness improvement by designing circuits implemented on SRAM FPGAs and validation by fault injection.” 2013. Doctoral Dissertation, Université de Grenoble. Accessed February 24, 2020. http://www.theses.fr/2013GRENT035.

MLA Handbook (7th Edition):

Ben Jirad, Mohamed. “Robustesse par conception de circuits implantés sur FPGA SRAM et validation par injection de fautes : Robustness improvement by designing circuits implemented on SRAM FPGAs and validation by fault injection.” 2013. Web. 24 Feb 2020.

Vancouver:

Ben Jirad M. Robustesse par conception de circuits implantés sur FPGA SRAM et validation par injection de fautes : Robustness improvement by designing circuits implemented on SRAM FPGAs and validation by fault injection. [Internet] [Doctoral dissertation]. Université de Grenoble; 2013. [cited 2020 Feb 24]. Available from: http://www.theses.fr/2013GRENT035.

Council of Science Editors:

Ben Jirad M. Robustesse par conception de circuits implantés sur FPGA SRAM et validation par injection de fautes : Robustness improvement by designing circuits implemented on SRAM FPGAs and validation by fault injection. [Doctoral Dissertation]. Université de Grenoble; 2013. Available from: http://www.theses.fr/2013GRENT035


Universidade do Rio Grande do Sul

15. Gerchman, Júlio. Integrando injeção de falhas ao perfil UML 2.0 de testes.

Degree: 2008, Universidade do Rio Grande do Sul

Mecanismos de tolerância a falhas são implementados em sistemas computacionais para atingir níveis de dependabilidade mais elevados. O teste desses mecanismos é essencial para validar… (more)

Subjects/Keywords: Processamento distribuido; Fault tolerance; Injecao : Falhas; Fault injection; Software testing; Software engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gerchman, J. (2008). Integrando injeção de falhas ao perfil UML 2.0 de testes. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/14277

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gerchman, Júlio. “Integrando injeção de falhas ao perfil UML 2.0 de testes.” 2008. Thesis, Universidade do Rio Grande do Sul. Accessed February 24, 2020. http://hdl.handle.net/10183/14277.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gerchman, Júlio. “Integrando injeção de falhas ao perfil UML 2.0 de testes.” 2008. Web. 24 Feb 2020.

Vancouver:

Gerchman J. Integrando injeção de falhas ao perfil UML 2.0 de testes. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2008. [cited 2020 Feb 24]. Available from: http://hdl.handle.net/10183/14277.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gerchman J. Integrando injeção de falhas ao perfil UML 2.0 de testes. [Thesis]. Universidade do Rio Grande do Sul; 2008. Available from: http://hdl.handle.net/10183/14277

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

16. Oliveira, Ádria Barros de. Applying dual core lockstep in embedded processors to mitigate radiation induced soft errors.

Degree: 2017, Universidade do Rio Grande do Sul

The embedded processors operating in safety- or mission-critical systems are not allowed to fail. Any failure in such applications could lead to unacceptable consequences as… (more)

Subjects/Keywords: Microeletrônica; Embedded Processors Reliability; Fault Injection; Sistemas embarcados; Radiation Experiments; Soft Errors; Lockstep; Fault Tolerance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Oliveira, . B. d. (2017). Applying dual core lockstep in embedded processors to mitigate radiation induced soft errors. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/173785

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Oliveira, Ádria Barros de. “Applying dual core lockstep in embedded processors to mitigate radiation induced soft errors.” 2017. Thesis, Universidade do Rio Grande do Sul. Accessed February 24, 2020. http://hdl.handle.net/10183/173785.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Oliveira, Ádria Barros de. “Applying dual core lockstep in embedded processors to mitigate radiation induced soft errors.” 2017. Web. 24 Feb 2020.

Vancouver:

Oliveira Bd. Applying dual core lockstep in embedded processors to mitigate radiation induced soft errors. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2017. [cited 2020 Feb 24]. Available from: http://hdl.handle.net/10183/173785.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Oliveira Bd. Applying dual core lockstep in embedded processors to mitigate radiation induced soft errors. [Thesis]. Universidade do Rio Grande do Sul; 2017. Available from: http://hdl.handle.net/10183/173785

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Moro, Nicolas. Sécurisation de programmes assembleur face aux attaques visant les processeurs embarqués : Security of assembly programs against fault attacks on embedded processors.

Degree: Docteur es, Informatique, 2014, Université Pierre et Marie Curie – Paris VI

Cette thèse s'intéresse à la sécurité des programmes embarqués face aux attaques par injection de fautes. La prolifération des composants embarqués et la simplicité de… (more)

Subjects/Keywords: Attaques par injection de fautes; Injection électromagnétique; Modèle de fautes; Contre-Mesures vérifiées; Assembleur; Saut d'instruction; Fault injection attacks; Countermeasures; 005.8

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Moro, N. (2014). Sécurisation de programmes assembleur face aux attaques visant les processeurs embarqués : Security of assembly programs against fault attacks on embedded processors. (Doctoral Dissertation). Université Pierre et Marie Curie – Paris VI. Retrieved from http://www.theses.fr/2014PA066616

Chicago Manual of Style (16th Edition):

Moro, Nicolas. “Sécurisation de programmes assembleur face aux attaques visant les processeurs embarqués : Security of assembly programs against fault attacks on embedded processors.” 2014. Doctoral Dissertation, Université Pierre et Marie Curie – Paris VI. Accessed February 24, 2020. http://www.theses.fr/2014PA066616.

MLA Handbook (7th Edition):

Moro, Nicolas. “Sécurisation de programmes assembleur face aux attaques visant les processeurs embarqués : Security of assembly programs against fault attacks on embedded processors.” 2014. Web. 24 Feb 2020.

Vancouver:

Moro N. Sécurisation de programmes assembleur face aux attaques visant les processeurs embarqués : Security of assembly programs against fault attacks on embedded processors. [Internet] [Doctoral dissertation]. Université Pierre et Marie Curie – Paris VI; 2014. [cited 2020 Feb 24]. Available from: http://www.theses.fr/2014PA066616.

Council of Science Editors:

Moro N. Sécurisation de programmes assembleur face aux attaques visant les processeurs embarqués : Security of assembly programs against fault attacks on embedded processors. [Doctoral Dissertation]. Université Pierre et Marie Curie – Paris VI; 2014. Available from: http://www.theses.fr/2014PA066616


Linköping University

18. Sandberg, Hampus. Radiation Hardened System Design with Mitigation and Detection in FPGA.

Degree: Computer Engineering, 2016, Linköping University

  FPGAs are attractive devices as they enable the designer to make changes to the system during its lifetime. This is important in the early… (more)

Subjects/Keywords: FPGA; radiation; TMR; fault mitigation; fault injection; fault detection; Electrical Engineering, Electronic Engineering, Information Engineering; Elektroteknik och elektronik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sandberg, H. (2016). Radiation Hardened System Design with Mitigation and Detection in FPGA. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-132942

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sandberg, Hampus. “Radiation Hardened System Design with Mitigation and Detection in FPGA.” 2016. Thesis, Linköping University. Accessed February 24, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-132942.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sandberg, Hampus. “Radiation Hardened System Design with Mitigation and Detection in FPGA.” 2016. Web. 24 Feb 2020.

Vancouver:

Sandberg H. Radiation Hardened System Design with Mitigation and Detection in FPGA. [Internet] [Thesis]. Linköping University; 2016. [cited 2020 Feb 24]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-132942.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sandberg H. Radiation Hardened System Design with Mitigation and Detection in FPGA. [Thesis]. Linköping University; 2016. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-132942

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

19. Munaretti, Ruthiano Simioni. Um ambiente para descrição de cenários detalhados de falhas.

Degree: 2010, Universidade do Rio Grande do Sul

A utilização de várias ferramentas de injeção de falhas em um mesmo experimento de testes fornece mais subsídios para os resultados alcançados, tornando a atividade… (more)

Subjects/Keywords: Fault injection; Testes : Software; Scenarios description; Injecao : Falhas; Distributed systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Munaretti, R. S. (2010). Um ambiente para descrição de cenários detalhados de falhas. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/25513

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Munaretti, Ruthiano Simioni. “Um ambiente para descrição de cenários detalhados de falhas.” 2010. Thesis, Universidade do Rio Grande do Sul. Accessed February 24, 2020. http://hdl.handle.net/10183/25513.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Munaretti, Ruthiano Simioni. “Um ambiente para descrição de cenários detalhados de falhas.” 2010. Web. 24 Feb 2020.

Vancouver:

Munaretti RS. Um ambiente para descrição de cenários detalhados de falhas. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2010. [cited 2020 Feb 24]. Available from: http://hdl.handle.net/10183/25513.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Munaretti RS. Um ambiente para descrição de cenários detalhados de falhas. [Thesis]. Universidade do Rio Grande do Sul; 2010. Available from: http://hdl.handle.net/10183/25513

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

20. Tonetto, Rafael Billig. A platform to evaluate the fault sensitivity of superscalar processors.

Degree: 2017, Universidade do Rio Grande do Sul

 A diminuição agressiva dos transistores, a qual levou a reduções na tensão de operação, vem proporcionando enormes benefícios em termos de poder computacional, mantendo o… (more)

Subjects/Keywords: Fault injection; Tolerancia : Falhas; Processamento paralelo; Register-transfer level; Superscalar processor

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APA (6th Edition):

Tonetto, R. B. (2017). A platform to evaluate the fault sensitivity of superscalar processors. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/169905

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tonetto, Rafael Billig. “A platform to evaluate the fault sensitivity of superscalar processors.” 2017. Thesis, Universidade do Rio Grande do Sul. Accessed February 24, 2020. http://hdl.handle.net/10183/169905.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tonetto, Rafael Billig. “A platform to evaluate the fault sensitivity of superscalar processors.” 2017. Web. 24 Feb 2020.

Vancouver:

Tonetto RB. A platform to evaluate the fault sensitivity of superscalar processors. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2017. [cited 2020 Feb 24]. Available from: http://hdl.handle.net/10183/169905.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tonetto RB. A platform to evaluate the fault sensitivity of superscalar processors. [Thesis]. Universidade do Rio Grande do Sul; 2017. Available from: http://hdl.handle.net/10183/169905

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Pham, Cuong. CloudVal: a framework for failure validation of virtualization environment in cloud infrastructure.

Degree: MS, 1200, 2013, University of Illinois – Urbana-Champaign

 We present CloudVal, a framework to validate the reliability of virtualization environment in cloud computing infrastructure. A case study, based on injecting faults in the… (more)

Subjects/Keywords: Virtualization; Fault Injection; Reliability

…techniques (which mainly focus on functional testing), fault injection is widely… …x5D;. Fault injection techniques can create failure scenarios for which normal testing… …software-implemented fault injection (SWIFI) framework to automate the process of… …conducting fault injection-based experiments for black box testing and reliability evaluation of… …injection framework and the fault models are a good starting point toward designing and… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pham, C. (2013). CloudVal: a framework for failure validation of virtualization environment in cloud infrastructure. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/45314

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pham, Cuong. “CloudVal: a framework for failure validation of virtualization environment in cloud infrastructure.” 2013. Thesis, University of Illinois – Urbana-Champaign. Accessed February 24, 2020. http://hdl.handle.net/2142/45314.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pham, Cuong. “CloudVal: a framework for failure validation of virtualization environment in cloud infrastructure.” 2013. Web. 24 Feb 2020.

Vancouver:

Pham C. CloudVal: a framework for failure validation of virtualization environment in cloud infrastructure. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2013. [cited 2020 Feb 24]. Available from: http://hdl.handle.net/2142/45314.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pham C. CloudVal: a framework for failure validation of virtualization environment in cloud infrastructure. [Thesis]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/45314

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

22. Oliveira, Gustavo Menezes. Injeção de falhas de comunicação em ambientes distribuídos.

Degree: 2011, Universidade do Rio Grande do Sul

A busca por características de dependabilidade em aplicações distribuídas está cada vez maior. Para tanto, técnicas de tolerância a falhas são componentes importantes no processo… (more)

Subjects/Keywords: Testes : Software; Communication fault injection; Network partitioning; Injecao : Falhas

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Oliveira, G. M. (2011). Injeção de falhas de comunicação em ambientes distribuídos. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/32864

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Oliveira, Gustavo Menezes. “Injeção de falhas de comunicação em ambientes distribuídos.” 2011. Thesis, Universidade do Rio Grande do Sul. Accessed February 24, 2020. http://hdl.handle.net/10183/32864.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Oliveira, Gustavo Menezes. “Injeção de falhas de comunicação em ambientes distribuídos.” 2011. Web. 24 Feb 2020.

Vancouver:

Oliveira GM. Injeção de falhas de comunicação em ambientes distribuídos. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2011. [cited 2020 Feb 24]. Available from: http://hdl.handle.net/10183/32864.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Oliveira GM. Injeção de falhas de comunicação em ambientes distribuídos. [Thesis]. Universidade do Rio Grande do Sul; 2011. Available from: http://hdl.handle.net/10183/32864

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

23. Le, Michael Vu. Resilient Virtualized Systems.

Degree: Computer Science, 2014, UCLA

 System virtualization allows forthe consolidation of many physicalservers on a single physical host by running theworkload of each physical serverinside a Virtual Machine (VM).This is… (more)

Subjects/Keywords: Computer science; fault injection; hypervisor; microreboot; recovery; reliability; virtualization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Le, M. V. (2014). Resilient Virtualized Systems. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/41d508vc

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Le, Michael Vu. “Resilient Virtualized Systems.” 2014. Thesis, UCLA. Accessed February 24, 2020. http://www.escholarship.org/uc/item/41d508vc.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Le, Michael Vu. “Resilient Virtualized Systems.” 2014. Web. 24 Feb 2020.

Vancouver:

Le MV. Resilient Virtualized Systems. [Internet] [Thesis]. UCLA; 2014. [cited 2020 Feb 24]. Available from: http://www.escholarship.org/uc/item/41d508vc.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Le MV. Resilient Virtualized Systems. [Thesis]. UCLA; 2014. Available from: http://www.escholarship.org/uc/item/41d508vc

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

24. Tambara, Lucas Antunes. Analyzing the Impact of Radiation-induced Failures in All Programmable System-on-Chip Devices.

Degree: 2017, Universidade do Rio Grande do Sul

O recente avanço da indústria de semicondutores tem possibilitado a integração de componentes complexos e arquiteturas de sistemas dentro de um único chip de silício.… (more)

Subjects/Keywords: Microeletrônica; Processor; Radiation effects; Circuitos digitais; Radiação; Fault injection

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APA (6th Edition):

Tambara, L. A. (2017). Analyzing the Impact of Radiation-induced Failures in All Programmable System-on-Chip Devices. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/164461

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tambara, Lucas Antunes. “Analyzing the Impact of Radiation-induced Failures in All Programmable System-on-Chip Devices.” 2017. Thesis, Universidade do Rio Grande do Sul. Accessed February 24, 2020. http://hdl.handle.net/10183/164461.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tambara, Lucas Antunes. “Analyzing the Impact of Radiation-induced Failures in All Programmable System-on-Chip Devices.” 2017. Web. 24 Feb 2020.

Vancouver:

Tambara LA. Analyzing the Impact of Radiation-induced Failures in All Programmable System-on-Chip Devices. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2017. [cited 2020 Feb 24]. Available from: http://hdl.handle.net/10183/164461.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tambara LA. Analyzing the Impact of Radiation-induced Failures in All Programmable System-on-Chip Devices. [Thesis]. Universidade do Rio Grande do Sul; 2017. Available from: http://hdl.handle.net/10183/164461

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


McMaster University

25. Zuzarte, Marvin. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.

Degree: MASc, 2014, McMaster University

Safety and mission critical systems are currently deployed in many different fields where there is a greater presence of high energy particles (e.g. aerospace). The… (more)

Subjects/Keywords: FPGA; Fault injection; Field programmable gate array; runtime; soft error

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APA (6th Edition):

Zuzarte, M. (2014). A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. (Masters Thesis). McMaster University. Retrieved from http://hdl.handle.net/11375/16500

Chicago Manual of Style (16th Edition):

Zuzarte, Marvin. “A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.” 2014. Masters Thesis, McMaster University. Accessed February 24, 2020. http://hdl.handle.net/11375/16500.

MLA Handbook (7th Edition):

Zuzarte, Marvin. “A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.” 2014. Web. 24 Feb 2020.

Vancouver:

Zuzarte M. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. [Internet] [Masters thesis]. McMaster University; 2014. [cited 2020 Feb 24]. Available from: http://hdl.handle.net/11375/16500.

Council of Science Editors:

Zuzarte M. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. [Masters Thesis]. McMaster University; 2014. Available from: http://hdl.handle.net/11375/16500


University of Texas – Austin

26. Park, Jaeyoung, Ph. D. Probabilistic design for emerging memory and nanometer-scale logic.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin

 As semiconductor technology has scaled down, the impact of stochastic behavior in very large scale integrated circuits (VLSI) has become an ever-more important concern. This… (more)

Subjects/Keywords: Memory; Spin-torque-transfer magnetic RAM; Fault injection; Circuit characterization

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APA (6th Edition):

Park, Jaeyoung, P. D. (2018). Probabilistic design for emerging memory and nanometer-scale logic. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/65731

Chicago Manual of Style (16th Edition):

Park, Jaeyoung, Ph D. “Probabilistic design for emerging memory and nanometer-scale logic.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed February 24, 2020. http://hdl.handle.net/2152/65731.

MLA Handbook (7th Edition):

Park, Jaeyoung, Ph D. “Probabilistic design for emerging memory and nanometer-scale logic.” 2018. Web. 24 Feb 2020.

Vancouver:

Park, Jaeyoung PD. Probabilistic design for emerging memory and nanometer-scale logic. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2020 Feb 24]. Available from: http://hdl.handle.net/2152/65731.

Council of Science Editors:

Park, Jaeyoung PD. Probabilistic design for emerging memory and nanometer-scale logic. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/65731


University of Waterloo

27. Liao, Haohao. Electromagnetic Fault Injection On Two Microcontrollers: Methodology, Fault Model, Attack and Countermeasures.

Degree: 2020, University of Waterloo

 Cryptographic algorithms are being applied to various kinds of embedded devices such as credit card, smart phone, etc. Those cryptographic algorithms are designed to be… (more)

Subjects/Keywords: security; computer hardware; hardware security; side channel attack; fault injection attack

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liao, H. (2020). Electromagnetic Fault Injection On Two Microcontrollers: Methodology, Fault Model, Attack and Countermeasures. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/15639

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liao, Haohao. “Electromagnetic Fault Injection On Two Microcontrollers: Methodology, Fault Model, Attack and Countermeasures.” 2020. Thesis, University of Waterloo. Accessed February 24, 2020. http://hdl.handle.net/10012/15639.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liao, Haohao. “Electromagnetic Fault Injection On Two Microcontrollers: Methodology, Fault Model, Attack and Countermeasures.” 2020. Web. 24 Feb 2020.

Vancouver:

Liao H. Electromagnetic Fault Injection On Two Microcontrollers: Methodology, Fault Model, Attack and Countermeasures. [Internet] [Thesis]. University of Waterloo; 2020. [cited 2020 Feb 24]. Available from: http://hdl.handle.net/10012/15639.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liao H. Electromagnetic Fault Injection On Two Microcontrollers: Methodology, Fault Model, Attack and Countermeasures. [Thesis]. University of Waterloo; 2020. Available from: http://hdl.handle.net/10012/15639

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

28. Abdelmalek, Omar. Conception et prototypage d'architectures robustes de tags RFID UHF : Design and prototyping of robust architectures for UHF RFID Tags.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2016, Grenoble Alpes

 Les systèmes RFID sont de plus en plus utilisés dans des applications critiques fonctionnant dans des environnements perturbés (ferroviaire, aéronautique, chaînes de production ou agroalimentaire)… (more)

Subjects/Keywords: Rfid; Fpga; Injection de fautes; Sécurite materielle; Prototypage; Robustesse materielle; Rfid; Fpga; Fault injection; Hardware security; Prototyping; Hardware robustness; 620

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APA (6th Edition):

Abdelmalek, O. (2016). Conception et prototypage d'architectures robustes de tags RFID UHF : Design and prototyping of robust architectures for UHF RFID Tags. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2016GREAT088

Chicago Manual of Style (16th Edition):

Abdelmalek, Omar. “Conception et prototypage d'architectures robustes de tags RFID UHF : Design and prototyping of robust architectures for UHF RFID Tags.” 2016. Doctoral Dissertation, Grenoble Alpes. Accessed February 24, 2020. http://www.theses.fr/2016GREAT088.

MLA Handbook (7th Edition):

Abdelmalek, Omar. “Conception et prototypage d'architectures robustes de tags RFID UHF : Design and prototyping of robust architectures for UHF RFID Tags.” 2016. Web. 24 Feb 2020.

Vancouver:

Abdelmalek O. Conception et prototypage d'architectures robustes de tags RFID UHF : Design and prototyping of robust architectures for UHF RFID Tags. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2016. [cited 2020 Feb 24]. Available from: http://www.theses.fr/2016GREAT088.

Council of Science Editors:

Abdelmalek O. Conception et prototypage d'architectures robustes de tags RFID UHF : Design and prototyping of robust architectures for UHF RFID Tags. [Doctoral Dissertation]. Grenoble Alpes; 2016. Available from: http://www.theses.fr/2016GREAT088


INP Toulouse

29. Pintard, Ludovic. From safety analysis to experimental validation by fault injection - Case of automotive embedded systems : Des analyses de sécurité à la validation expérimentale par injection de fautes - Le cas des systèmes embarqués automobile.

Degree: Docteur es, Informatique, 2015, INP Toulouse

En raison de la complexité croissante des systèmes automobiles embarqués, la sûreté de fonctionnement est devenue un enjeu majeur de l’industrie automobile. Cet intérêt croissant… (more)

Subjects/Keywords: Injection de fautes; Automobile; Systèmes Embarqués; Sécurité; Vérification; ISO 26262; Fault Injection; Automotive; Embedded Systems; Safety; Verification; ISO 26262

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pintard, L. (2015). From safety analysis to experimental validation by fault injection - Case of automotive embedded systems : Des analyses de sécurité à la validation expérimentale par injection de fautes - Le cas des systèmes embarqués automobile. (Doctoral Dissertation). INP Toulouse. Retrieved from http://www.theses.fr/2015INPT0052

Chicago Manual of Style (16th Edition):

Pintard, Ludovic. “From safety analysis to experimental validation by fault injection - Case of automotive embedded systems : Des analyses de sécurité à la validation expérimentale par injection de fautes - Le cas des systèmes embarqués automobile.” 2015. Doctoral Dissertation, INP Toulouse. Accessed February 24, 2020. http://www.theses.fr/2015INPT0052.

MLA Handbook (7th Edition):

Pintard, Ludovic. “From safety analysis to experimental validation by fault injection - Case of automotive embedded systems : Des analyses de sécurité à la validation expérimentale par injection de fautes - Le cas des systèmes embarqués automobile.” 2015. Web. 24 Feb 2020.

Vancouver:

Pintard L. From safety analysis to experimental validation by fault injection - Case of automotive embedded systems : Des analyses de sécurité à la validation expérimentale par injection de fautes - Le cas des systèmes embarqués automobile. [Internet] [Doctoral dissertation]. INP Toulouse; 2015. [cited 2020 Feb 24]. Available from: http://www.theses.fr/2015INPT0052.

Council of Science Editors:

Pintard L. From safety analysis to experimental validation by fault injection - Case of automotive embedded systems : Des analyses de sécurité à la validation expérimentale par injection de fautes - Le cas des systèmes embarqués automobile. [Doctoral Dissertation]. INP Toulouse; 2015. Available from: http://www.theses.fr/2015INPT0052

30. Samynathan, Balavinayaga. Developing a multi-level fault injection environment.

Degree: MSin Engineering, Electrical and Computer Engineering, 2015, University of Texas – Austin

 Dependability and fault tolerance are important aspects of modern computer systems. Particle strikes or electromagnetic interference can cause internal state of the system to change,… (more)

Subjects/Keywords: Fault injection; Synthetic benchmarks; Error injection; FPGA

…Modifications for Fault Injection . . . . . . . . . . . . . . 2.2 System-Level Fault Controller… …Simulation Based Fault Injection 3.1 Synthetic Benchmarks… …3.2 Distributed Statistical Fault Injection Simulation . . . . . . . . 16 17 19 Chapter 4… …x List of Figures 1.1 1.2 Comparison of Fault Injection Methods… …strength of synthetic benchmarks in fault injection Outcome of Synthetic Benchmarks… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Samynathan, B. (2015). Developing a multi-level fault injection environment. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/31864

Chicago Manual of Style (16th Edition):

Samynathan, Balavinayaga. “Developing a multi-level fault injection environment.” 2015. Masters Thesis, University of Texas – Austin. Accessed February 24, 2020. http://hdl.handle.net/2152/31864.

MLA Handbook (7th Edition):

Samynathan, Balavinayaga. “Developing a multi-level fault injection environment.” 2015. Web. 24 Feb 2020.

Vancouver:

Samynathan B. Developing a multi-level fault injection environment. [Internet] [Masters thesis]. University of Texas – Austin; 2015. [cited 2020 Feb 24]. Available from: http://hdl.handle.net/2152/31864.

Council of Science Editors:

Samynathan B. Developing a multi-level fault injection environment. [Masters Thesis]. University of Texas – Austin; 2015. Available from: http://hdl.handle.net/2152/31864

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