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You searched for subject:(FPGA routing). Showing records 1 – 28 of 28 total matches.

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University of Toronto

1. Shah, Niyati. On Pin-to-wire Routing in FPGAs.

Degree: 2012, University of Toronto

While FPGA interconnect networks were originally designed to connect logic block output pins to input pins, FPGA users and architects sometimes become motivated to create… (more)

Subjects/Keywords: FPGA CAD; Pin-to-Wire; Routing; FPGA Routing Architecture; 0544

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APA (6th Edition):

Shah, N. (2012). On Pin-to-wire Routing in FPGAs. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/33523

Chicago Manual of Style (16th Edition):

Shah, Niyati. “On Pin-to-wire Routing in FPGAs.” 2012. Masters Thesis, University of Toronto. Accessed August 14, 2020. http://hdl.handle.net/1807/33523.

MLA Handbook (7th Edition):

Shah, Niyati. “On Pin-to-wire Routing in FPGAs.” 2012. Web. 14 Aug 2020.

Vancouver:

Shah N. On Pin-to-wire Routing in FPGAs. [Internet] [Masters thesis]. University of Toronto; 2012. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/1807/33523.

Council of Science Editors:

Shah N. On Pin-to-wire Routing in FPGAs. [Masters Thesis]. University of Toronto; 2012. Available from: http://hdl.handle.net/1807/33523


Virginia Tech

2. Bhardwaj, Prabhaav. Framework for Hardware Agility on FPGAs.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 As hardware applications become increasingly complex, the supporting technology needs to evolve and adapt to the demands. Field Programmable Gate Array (FPGA), Application Specific Integrated… (more)

Subjects/Keywords: Virtex 5; Dynamic Routing; FPGA; Reconfigurable Computing

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APA (6th Edition):

Bhardwaj, P. (2010). Framework for Hardware Agility on FPGAs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/36347

Chicago Manual of Style (16th Edition):

Bhardwaj, Prabhaav. “Framework for Hardware Agility on FPGAs.” 2010. Masters Thesis, Virginia Tech. Accessed August 14, 2020. http://hdl.handle.net/10919/36347.

MLA Handbook (7th Edition):

Bhardwaj, Prabhaav. “Framework for Hardware Agility on FPGAs.” 2010. Web. 14 Aug 2020.

Vancouver:

Bhardwaj P. Framework for Hardware Agility on FPGAs. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/10919/36347.

Council of Science Editors:

Bhardwaj P. Framework for Hardware Agility on FPGAs. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/36347


University of Dayton

3. Qi, Yangjie. FPGA Based High Throughput Low Power Multi-core Neuromorphic Processor.

Degree: MS(M.S.), Electrical Engineering, 2015, University of Dayton

 The interest in specialized neuromorphic computing architectures has been increasing recently, and several applications have been shown to be capable of being accelerated on such… (more)

Subjects/Keywords: Electrical Engineering; Computer Engineering; FPGA; Neural Network; Static Routing; Dynamic Routing; Low Power; High Throughput

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APA (6th Edition):

Qi, Y. (2015). FPGA Based High Throughput Low Power Multi-core Neuromorphic Processor. (Masters Thesis). University of Dayton. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=dayton1449526140

Chicago Manual of Style (16th Edition):

Qi, Yangjie. “FPGA Based High Throughput Low Power Multi-core Neuromorphic Processor.” 2015. Masters Thesis, University of Dayton. Accessed August 14, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1449526140.

MLA Handbook (7th Edition):

Qi, Yangjie. “FPGA Based High Throughput Low Power Multi-core Neuromorphic Processor.” 2015. Web. 14 Aug 2020.

Vancouver:

Qi Y. FPGA Based High Throughput Low Power Multi-core Neuromorphic Processor. [Internet] [Masters thesis]. University of Dayton; 2015. [cited 2020 Aug 14]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=dayton1449526140.

Council of Science Editors:

Qi Y. FPGA Based High Throughput Low Power Multi-core Neuromorphic Processor. [Masters Thesis]. University of Dayton; 2015. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=dayton1449526140

4. Gustavo Rezende Carvalho. Heurísticas para a fase de roteameneto de circuitos integrados baseados em FPGAs.

Degree: 2010, Universidade Federal da Paraíba

A presente dissertação trata do problema de roteamento de circuitos para Field Programable Gate Arrays (FPGAs). Em função da natureza combinatória do problema, métodos heurísticos… (more)

Subjects/Keywords: VPR; Roteamento; FPGA; GRASP; ILS; CIENCIA DA COMPUTACAO; Routing; FPGA; VPR; GRASP; ILS

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APA (6th Edition):

Carvalho, G. R. (2010). Heurísticas para a fase de roteameneto de circuitos integrados baseados em FPGAs. (Thesis). Universidade Federal da Paraíba. Retrieved from http://bdtd.biblioteca.ufpb.br/tde_busca/arquivo.php?codArquivo=853

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Carvalho, Gustavo Rezende. “Heurísticas para a fase de roteameneto de circuitos integrados baseados em FPGAs.” 2010. Thesis, Universidade Federal da Paraíba. Accessed August 14, 2020. http://bdtd.biblioteca.ufpb.br/tde_busca/arquivo.php?codArquivo=853.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Carvalho, Gustavo Rezende. “Heurísticas para a fase de roteameneto de circuitos integrados baseados em FPGAs.” 2010. Web. 14 Aug 2020.

Vancouver:

Carvalho GR. Heurísticas para a fase de roteameneto de circuitos integrados baseados em FPGAs. [Internet] [Thesis]. Universidade Federal da Paraíba; 2010. [cited 2020 Aug 14]. Available from: http://bdtd.biblioteca.ufpb.br/tde_busca/arquivo.php?codArquivo=853.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Carvalho GR. Heurísticas para a fase de roteameneto de circuitos integrados baseados em FPGAs. [Thesis]. Universidade Federal da Paraíba; 2010. Available from: http://bdtd.biblioteca.ufpb.br/tde_busca/arquivo.php?codArquivo=853

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

5. Qian, Jianshu. Improved bufferless routing via balanced pipeline stages.

Degree: MS, Electrical Engineering, 2013, Vanderbilt University

 Network-on-chip (NoC) architectures with emerging interconnect technologies have been developed to meet the demand for high-performance computational systems while maintaining energy efficiency. The introduction of… (more)

Subjects/Keywords: On-chip networks; FPGA; Multi-core; Bufferless routing

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APA (6th Edition):

Qian, J. (2013). Improved bufferless routing via balanced pipeline stages. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-07072013-145648/ ;

Chicago Manual of Style (16th Edition):

Qian, Jianshu. “Improved bufferless routing via balanced pipeline stages.” 2013. Masters Thesis, Vanderbilt University. Accessed August 14, 2020. http://etd.library.vanderbilt.edu/available/etd-07072013-145648/ ;.

MLA Handbook (7th Edition):

Qian, Jianshu. “Improved bufferless routing via balanced pipeline stages.” 2013. Web. 14 Aug 2020.

Vancouver:

Qian J. Improved bufferless routing via balanced pipeline stages. [Internet] [Masters thesis]. Vanderbilt University; 2013. [cited 2020 Aug 14]. Available from: http://etd.library.vanderbilt.edu/available/etd-07072013-145648/ ;.

Council of Science Editors:

Qian J. Improved bufferless routing via balanced pipeline stages. [Masters Thesis]. Vanderbilt University; 2013. Available from: http://etd.library.vanderbilt.edu/available/etd-07072013-145648/ ;


Univerzitet u Beogradu

6. Stojilović, Mirjana, 1983-. A Method for designing domain-specific reconfigurable arrays.

Degree: Elektrotehnički fakultet, 2016, Univerzitet u Beogradu

Tehničke nauke – elektrotehnika - Elektronika / Technical sciences, Electrical engineering - Electronics

Namenski računarski sistemi se najčesće projektuju tako da mogu da podrže izvršavanje… (more)

Subjects/Keywords: CGRA; datapath; domain-specific customization; flexibility; FPGA routing

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APA (6th Edition):

Stojilović, Mirjana, 1. (2016). A Method for designing domain-specific reconfigurable arrays. (Thesis). Univerzitet u Beogradu. Retrieved from https://fedorabg.bg.ac.rs/fedora/get/o:13568/bdef:Content/get

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Stojilović, Mirjana, 1983-. “A Method for designing domain-specific reconfigurable arrays.” 2016. Thesis, Univerzitet u Beogradu. Accessed August 14, 2020. https://fedorabg.bg.ac.rs/fedora/get/o:13568/bdef:Content/get.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Stojilović, Mirjana, 1983-. “A Method for designing domain-specific reconfigurable arrays.” 2016. Web. 14 Aug 2020.

Vancouver:

Stojilović, Mirjana 1. A Method for designing domain-specific reconfigurable arrays. [Internet] [Thesis]. Univerzitet u Beogradu; 2016. [cited 2020 Aug 14]. Available from: https://fedorabg.bg.ac.rs/fedora/get/o:13568/bdef:Content/get.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Stojilović, Mirjana 1. A Method for designing domain-specific reconfigurable arrays. [Thesis]. Univerzitet u Beogradu; 2016. Available from: https://fedorabg.bg.ac.rs/fedora/get/o:13568/bdef:Content/get

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

7. Gort, Marcel. Fast CAD for FPGAs.

Degree: PhD, 2014, University of Toronto

As field-programmable gate array (FPGA) capacities continue to increase in lockstep with semiconductor process shrinking, they are being used for increasingly complex applications. However, because… (more)

Subjects/Keywords: CAD; FPGA; parallel; placement; routing; run-time; 0464

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APA (6th Edition):

Gort, M. (2014). Fast CAD for FPGAs. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/72837

Chicago Manual of Style (16th Edition):

Gort, Marcel. “Fast CAD for FPGAs.” 2014. Doctoral Dissertation, University of Toronto. Accessed August 14, 2020. http://hdl.handle.net/1807/72837.

MLA Handbook (7th Edition):

Gort, Marcel. “Fast CAD for FPGAs.” 2014. Web. 14 Aug 2020.

Vancouver:

Gort M. Fast CAD for FPGAs. [Internet] [Doctoral dissertation]. University of Toronto; 2014. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/1807/72837.

Council of Science Editors:

Gort M. Fast CAD for FPGAs. [Doctoral Dissertation]. University of Toronto; 2014. Available from: http://hdl.handle.net/1807/72837


Virginia Tech

8. Zha, Wenwei. Facilitating FPGA Reconfiguration through Low-level Manipulation.

Degree: PhD, Electrical and Computer Engineering, 2014, Virginia Tech

 The process of FPGA reconfiguration is to recompile a design and then update the FPGA configuration correspondingly. Traditionally, FPGA design compilation follows the way how… (more)

Subjects/Keywords: FPGA Reconfiguration; Bitstream-level Manipulation; FPGA Routing; Module Reuse; Design Assembly; Autonomous Adaptive Systems; Electronic Design Automation

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APA (6th Edition):

Zha, W. (2014). Facilitating FPGA Reconfiguration through Low-level Manipulation. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/46787

Chicago Manual of Style (16th Edition):

Zha, Wenwei. “Facilitating FPGA Reconfiguration through Low-level Manipulation.” 2014. Doctoral Dissertation, Virginia Tech. Accessed August 14, 2020. http://hdl.handle.net/10919/46787.

MLA Handbook (7th Edition):

Zha, Wenwei. “Facilitating FPGA Reconfiguration through Low-level Manipulation.” 2014. Web. 14 Aug 2020.

Vancouver:

Zha W. Facilitating FPGA Reconfiguration through Low-level Manipulation. [Internet] [Doctoral dissertation]. Virginia Tech; 2014. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/10919/46787.

Council of Science Editors:

Zha W. Facilitating FPGA Reconfiguration through Low-level Manipulation. [Doctoral Dissertation]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/46787


Northeastern University

9. Abdul-Aziz, Mohammed A. Reliability-aware placement and routing for FPGAs.

Degree: MS, Department of Electrical and Computer Engineering, 2010, Northeastern University

 Soft errors are intermittent malfunctions of hardware that are not reproducible. They may affect the data integrity and affect the system operation. These errors are… (more)

Subjects/Keywords: computer engineering; fault tolerance; FPGA placement; FPGA routing; SEU; SRAM FPGA; VPR; Field programmable gate arrays; Reliability (Engineering); Electrical and Computer Engineering; Engineering

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APA (6th Edition):

Abdul-Aziz, M. A. (2010). Reliability-aware placement and routing for FPGAs. (Masters Thesis). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20000905

Chicago Manual of Style (16th Edition):

Abdul-Aziz, Mohammed A. “Reliability-aware placement and routing for FPGAs.” 2010. Masters Thesis, Northeastern University. Accessed August 14, 2020. http://hdl.handle.net/2047/d20000905.

MLA Handbook (7th Edition):

Abdul-Aziz, Mohammed A. “Reliability-aware placement and routing for FPGAs.” 2010. Web. 14 Aug 2020.

Vancouver:

Abdul-Aziz MA. Reliability-aware placement and routing for FPGAs. [Internet] [Masters thesis]. Northeastern University; 2010. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/2047/d20000905.

Council of Science Editors:

Abdul-Aziz MA. Reliability-aware placement and routing for FPGAs. [Masters Thesis]. Northeastern University; 2010. Available from: http://hdl.handle.net/2047/d20000905


Brigham Young University

10. Lamprecht, Jaren Tyler. FPGA Floor-Planning Impact on Implementation Results.

Degree: MS, 2012, Brigham Young University

  The field programmable gate array (FPGA) is an attractive computational platform for many applications because of its customizable nature and modest development cost, in… (more)

Subjects/Keywords: FPGA; floor-plan; area constraint; clock constraint; routing spillover; partial reconfiguration; submodule relocation; Xilinx; Electrical and Computer Engineering

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APA (6th Edition):

Lamprecht, J. T. (2012). FPGA Floor-Planning Impact on Implementation Results. (Masters Thesis). Brigham Young University. Retrieved from https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=4379&context=etd

Chicago Manual of Style (16th Edition):

Lamprecht, Jaren Tyler. “FPGA Floor-Planning Impact on Implementation Results.” 2012. Masters Thesis, Brigham Young University. Accessed August 14, 2020. https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=4379&context=etd.

MLA Handbook (7th Edition):

Lamprecht, Jaren Tyler. “FPGA Floor-Planning Impact on Implementation Results.” 2012. Web. 14 Aug 2020.

Vancouver:

Lamprecht JT. FPGA Floor-Planning Impact on Implementation Results. [Internet] [Masters thesis]. Brigham Young University; 2012. [cited 2020 Aug 14]. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=4379&context=etd.

Council of Science Editors:

Lamprecht JT. FPGA Floor-Planning Impact on Implementation Results. [Masters Thesis]. Brigham Young University; 2012. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=4379&context=etd


Wright State University

11. Wang, Fei, Dr. A Field Programmable Gate Array Architecture for Two-Dimensional Partial Reconfiguration.

Degree: PhD, Computer Science and Engineering PhD, 2006, Wright State University

 Wang, Fei. Ph.D., Department of Computer Science and Engineering, Wright State University, 2006. A Field Programmable Gate Array Architecture for Two-Dimensional Partial Reconfiguration Reconfigurable machines… (more)

Subjects/Keywords: Computer Science; FPGA; architecture; operating system; placement; routing

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APA (6th Edition):

Wang, Fei, D. (2006). A Field Programmable Gate Array Architecture for Two-Dimensional Partial Reconfiguration. (Doctoral Dissertation). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1166735848

Chicago Manual of Style (16th Edition):

Wang, Fei, Dr. “A Field Programmable Gate Array Architecture for Two-Dimensional Partial Reconfiguration.” 2006. Doctoral Dissertation, Wright State University. Accessed August 14, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=wright1166735848.

MLA Handbook (7th Edition):

Wang, Fei, Dr. “A Field Programmable Gate Array Architecture for Two-Dimensional Partial Reconfiguration.” 2006. Web. 14 Aug 2020.

Vancouver:

Wang, Fei D. A Field Programmable Gate Array Architecture for Two-Dimensional Partial Reconfiguration. [Internet] [Doctoral dissertation]. Wright State University; 2006. [cited 2020 Aug 14]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1166735848.

Council of Science Editors:

Wang, Fei D. A Field Programmable Gate Array Architecture for Two-Dimensional Partial Reconfiguration. [Doctoral Dissertation]. Wright State University; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1166735848

12. Kashif, Asmeen. Experimental Evaluation and Comparison of Time-Multiplexed Multi-FPGA Routing Architectures.

Degree: PhD, Electrical and Computer Engineering, 2017, University of Windsor

 Emulating large complex designs require multi-FPGA systems (MFS). However, inter-FPGA communication is confronted by the challenge of lack of interconnect capacity due to limited number… (more)

Subjects/Keywords: Multi-FPGA; Routing Architecture; Serial Optical Interface

…6 Chapter 2 MFS Routing Architectures 2.1. Inter-FPGA Connections & Routing… …86 6.2.2 Intra-FPGA Placement and Routing… …the available physical tracks, I/O resources of the FPGA and the routing architecture of MFS… …certain routing topologies providing full connectivity, signals can be routed from source FPGA… …in other routing architectures, sometimes the signals need an intermediate FPGA or a route… 

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APA (6th Edition):

Kashif, A. (2017). Experimental Evaluation and Comparison of Time-Multiplexed Multi-FPGA Routing Architectures. (Doctoral Dissertation). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/7269

Chicago Manual of Style (16th Edition):

Kashif, Asmeen. “Experimental Evaluation and Comparison of Time-Multiplexed Multi-FPGA Routing Architectures.” 2017. Doctoral Dissertation, University of Windsor. Accessed August 14, 2020. https://scholar.uwindsor.ca/etd/7269.

MLA Handbook (7th Edition):

Kashif, Asmeen. “Experimental Evaluation and Comparison of Time-Multiplexed Multi-FPGA Routing Architectures.” 2017. Web. 14 Aug 2020.

Vancouver:

Kashif A. Experimental Evaluation and Comparison of Time-Multiplexed Multi-FPGA Routing Architectures. [Internet] [Doctoral dissertation]. University of Windsor; 2017. [cited 2020 Aug 14]. Available from: https://scholar.uwindsor.ca/etd/7269.

Council of Science Editors:

Kashif A. Experimental Evaluation and Comparison of Time-Multiplexed Multi-FPGA Routing Architectures. [Doctoral Dissertation]. University of Windsor; 2017. Available from: https://scholar.uwindsor.ca/etd/7269


University of Florida

13. Landy, Aaron M. Intermediate Fabrics Low-Overhead Coarse-Grained Virtual Reconfigurable Fabric to Enable Fast Place and Route.

Degree: MS, Electrical and Computer Engineering, 2013, University of Florida

 Field-programmable gate arrays (FPGAs) have been widely shown to have significant performance and power advantages compared to microprocessors and graphics-processing units (GPUs), but remain a… (more)

Subjects/Keywords: Architectural design; Boxes; Coarse grained; Comparators; Computer technology; Field programmable gate arrays; Multiplexers; Shift registers; Topology; Tradeoffs; fpga  – reconfigurable  – routing

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APA (6th Edition):

Landy, A. M. (2013). Intermediate Fabrics Low-Overhead Coarse-Grained Virtual Reconfigurable Fabric to Enable Fast Place and Route. (Masters Thesis). University of Florida. Retrieved from https://ufdc.ufl.edu/UFE0045513

Chicago Manual of Style (16th Edition):

Landy, Aaron M. “Intermediate Fabrics Low-Overhead Coarse-Grained Virtual Reconfigurable Fabric to Enable Fast Place and Route.” 2013. Masters Thesis, University of Florida. Accessed August 14, 2020. https://ufdc.ufl.edu/UFE0045513.

MLA Handbook (7th Edition):

Landy, Aaron M. “Intermediate Fabrics Low-Overhead Coarse-Grained Virtual Reconfigurable Fabric to Enable Fast Place and Route.” 2013. Web. 14 Aug 2020.

Vancouver:

Landy AM. Intermediate Fabrics Low-Overhead Coarse-Grained Virtual Reconfigurable Fabric to Enable Fast Place and Route. [Internet] [Masters thesis]. University of Florida; 2013. [cited 2020 Aug 14]. Available from: https://ufdc.ufl.edu/UFE0045513.

Council of Science Editors:

Landy AM. Intermediate Fabrics Low-Overhead Coarse-Grained Virtual Reconfigurable Fabric to Enable Fast Place and Route. [Masters Thesis]. University of Florida; 2013. Available from: https://ufdc.ufl.edu/UFE0045513

14. Zhang, Fan. Parallelization of Negotiated Congestion Algorithm in FPGA Routing.

Degree: MS, Engineering and Applied Science: Computer Engineering, 2013, University of Cincinnati

Routing has been one of the most time-consuming process in FPGA design flow.As technology continues to scale down with feature sizes of devices below 20nm,silicon… (more)

Subjects/Keywords: Computer Engineering; FPGA; routing; locality; router; algorithm; CAD

…32 3 EXPLORATION OF LOCALITY IN FPGA ROUTING 34 3.1 Locality in FPGA Design… …34 3.2 Utilize Locality in FPGA Routing… …Anatomy of Switch Box Figure 1.5: FPGA design flow Figure 1.6: Expansion in Lee’s Maze Routing… …left) and FPGA(right) Figure 3.3: Routing Regions generation for a simple… …FPGA there are also other configurable SRAM bits that are used to configure the routing… 

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APA (6th Edition):

Zhang, F. (2013). Parallelization of Negotiated Congestion Algorithm in FPGA Routing. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1367936094

Chicago Manual of Style (16th Edition):

Zhang, Fan. “Parallelization of Negotiated Congestion Algorithm in FPGA Routing.” 2013. Masters Thesis, University of Cincinnati. Accessed August 14, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1367936094.

MLA Handbook (7th Edition):

Zhang, Fan. “Parallelization of Negotiated Congestion Algorithm in FPGA Routing.” 2013. Web. 14 Aug 2020.

Vancouver:

Zhang F. Parallelization of Negotiated Congestion Algorithm in FPGA Routing. [Internet] [Masters thesis]. University of Cincinnati; 2013. [cited 2020 Aug 14]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1367936094.

Council of Science Editors:

Zhang F. Parallelization of Negotiated Congestion Algorithm in FPGA Routing. [Masters Thesis]. University of Cincinnati; 2013. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1367936094

15. Jensen, Joshua E. Preemptive Placement and Routing for In-Field FPGA Repair.

Degree: MS, 2015, Brigham Young University

  With the growing density and shrinking feature size of modern semiconductors, it is increasingly difficult to manufacture defect free semiconductors that maintain acceptable levels… (more)

Subjects/Keywords: FPGA; Repair; Fault-Tolerance; Placement; Routing; Electrical and Computer Engineering

…creating a new FPGA configuration for a specific design with a modified placement and routing of… …router successfully performs FPGA placement and routing that generates valid configurations for… …thesis is to determine a valid FPGA placement and routing on a fully functional device and a… …Tile There are two main types of routing resources on an FPGA used to connect the pins on… …perform routing and generate a valid FPGA bitstream. Figure 4.1: Design Flow for Baseline… 

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APA (6th Edition):

Jensen, J. E. (2015). Preemptive Placement and Routing for In-Field FPGA Repair. (Masters Thesis). Brigham Young University. Retrieved from https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=5416&context=etd

Chicago Manual of Style (16th Edition):

Jensen, Joshua E. “Preemptive Placement and Routing for In-Field FPGA Repair.” 2015. Masters Thesis, Brigham Young University. Accessed August 14, 2020. https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=5416&context=etd.

MLA Handbook (7th Edition):

Jensen, Joshua E. “Preemptive Placement and Routing for In-Field FPGA Repair.” 2015. Web. 14 Aug 2020.

Vancouver:

Jensen JE. Preemptive Placement and Routing for In-Field FPGA Repair. [Internet] [Masters thesis]. Brigham Young University; 2015. [cited 2020 Aug 14]. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=5416&context=etd.

Council of Science Editors:

Jensen JE. Preemptive Placement and Routing for In-Field FPGA Repair. [Masters Thesis]. Brigham Young University; 2015. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=5416&context=etd

16. LOKE WEI TING. POWER-AWARE TECHNOLOGY MAPPING AND ROUTING FOR DUAL-VT FPGAS.

Degree: 2012, National University of Singapore

Subjects/Keywords: Technology Mapping; Routing; Reverse Back Bias; Dual VT; FPGA; EDA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

TING, L. W. (2012). POWER-AWARE TECHNOLOGY MAPPING AND ROUTING FOR DUAL-VT FPGAS. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/32500

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

TING, LOKE WEI. “POWER-AWARE TECHNOLOGY MAPPING AND ROUTING FOR DUAL-VT FPGAS.” 2012. Thesis, National University of Singapore. Accessed August 14, 2020. http://scholarbank.nus.edu.sg/handle/10635/32500.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

TING, LOKE WEI. “POWER-AWARE TECHNOLOGY MAPPING AND ROUTING FOR DUAL-VT FPGAS.” 2012. Web. 14 Aug 2020.

Vancouver:

TING LW. POWER-AWARE TECHNOLOGY MAPPING AND ROUTING FOR DUAL-VT FPGAS. [Internet] [Thesis]. National University of Singapore; 2012. [cited 2020 Aug 14]. Available from: http://scholarbank.nus.edu.sg/handle/10635/32500.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

TING LW. POWER-AWARE TECHNOLOGY MAPPING AND ROUTING FOR DUAL-VT FPGAS. [Thesis]. National University of Singapore; 2012. Available from: http://scholarbank.nus.edu.sg/handle/10635/32500

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. CHEN XIAOLEI. TIME-MULTIPLEXED INTERCONNECTION NETWORK FOR FIELD-PROGRAMMABLE GATE ARRAYS.

Degree: 2012, National University of Singapore

Subjects/Keywords: FPGA; Algorithm Design; Digital Logic; Interconnection Network; Routing; Experimental Evaluation

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APA (6th Edition):

XIAOLEI, C. (2012). TIME-MULTIPLEXED INTERCONNECTION NETWORK FOR FIELD-PROGRAMMABLE GATE ARRAYS. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/34524

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

XIAOLEI, CHEN. “TIME-MULTIPLEXED INTERCONNECTION NETWORK FOR FIELD-PROGRAMMABLE GATE ARRAYS.” 2012. Thesis, National University of Singapore. Accessed August 14, 2020. http://scholarbank.nus.edu.sg/handle/10635/34524.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

XIAOLEI, CHEN. “TIME-MULTIPLEXED INTERCONNECTION NETWORK FOR FIELD-PROGRAMMABLE GATE ARRAYS.” 2012. Web. 14 Aug 2020.

Vancouver:

XIAOLEI C. TIME-MULTIPLEXED INTERCONNECTION NETWORK FOR FIELD-PROGRAMMABLE GATE ARRAYS. [Internet] [Thesis]. National University of Singapore; 2012. [cited 2020 Aug 14]. Available from: http://scholarbank.nus.edu.sg/handle/10635/34524.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

XIAOLEI C. TIME-MULTIPLEXED INTERCONNECTION NETWORK FOR FIELD-PROGRAMMABLE GATE ARRAYS. [Thesis]. National University of Singapore; 2012. Available from: http://scholarbank.nus.edu.sg/handle/10635/34524

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. HOO CHIN HAU. PARALLEL ROUTING FOR FIELD PROGRAMMABLE GATE ARRAYS.

Degree: 2017, National University of Singapore

Subjects/Keywords: FPGA EDA; deterministic parallel routing; non-deterministic parallel routing; Lagrangian relaxation; recursive bi-partitioning; distributed memory

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APA (6th Edition):

HAU, H. C. (2017). PARALLEL ROUTING FOR FIELD PROGRAMMABLE GATE ARRAYS. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/142941

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

HAU, HOO CHIN. “PARALLEL ROUTING FOR FIELD PROGRAMMABLE GATE ARRAYS.” 2017. Thesis, National University of Singapore. Accessed August 14, 2020. http://scholarbank.nus.edu.sg/handle/10635/142941.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

HAU, HOO CHIN. “PARALLEL ROUTING FOR FIELD PROGRAMMABLE GATE ARRAYS.” 2017. Web. 14 Aug 2020.

Vancouver:

HAU HC. PARALLEL ROUTING FOR FIELD PROGRAMMABLE GATE ARRAYS. [Internet] [Thesis]. National University of Singapore; 2017. [cited 2020 Aug 14]. Available from: http://scholarbank.nus.edu.sg/handle/10635/142941.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

HAU HC. PARALLEL ROUTING FOR FIELD PROGRAMMABLE GATE ARRAYS. [Thesis]. National University of Singapore; 2017. Available from: http://scholarbank.nus.edu.sg/handle/10635/142941

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Jönköping University

19. Mahmood, Adnan. DESIGN AND PROTOTYPE OF RESOURCE NETWORK INTERFACES FOR NETWORK ON CHIP.

Degree: Computer and Electrical Engineering, 2009, Jönköping University

  Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for the core based design of System on Chip. Resource (core),… (more)

Subjects/Keywords: Network on Chip (NoC); System on Chip (SoC); Resource Network Interface (RNI); Altera FPGA; Nios II Core; On Chip Communication; Distributed Routing; Source Routing; Electrical engineering; Elektroteknik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mahmood, A. (2009). DESIGN AND PROTOTYPE OF RESOURCE NETWORK INTERFACES FOR NETWORK ON CHIP. (Thesis). Jönköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-11114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mahmood, Adnan. “DESIGN AND PROTOTYPE OF RESOURCE NETWORK INTERFACES FOR NETWORK ON CHIP.” 2009. Thesis, Jönköping University. Accessed August 14, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-11114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mahmood, Adnan. “DESIGN AND PROTOTYPE OF RESOURCE NETWORK INTERFACES FOR NETWORK ON CHIP.” 2009. Web. 14 Aug 2020.

Vancouver:

Mahmood A. DESIGN AND PROTOTYPE OF RESOURCE NETWORK INTERFACES FOR NETWORK ON CHIP. [Internet] [Thesis]. Jönköping University; 2009. [cited 2020 Aug 14]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-11114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mahmood A. DESIGN AND PROTOTYPE OF RESOURCE NETWORK INTERFACES FOR NETWORK ON CHIP. [Thesis]. Jönköping University; 2009. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-11114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

20. Ould Mohamed Moctar, Yehdhih. Parallel Routing for FPGAs with Sparse Intra-Cluster Routing Crossbars.

Degree: Computer Science, 2014, University of California – Riverside

Routing is the most time consuming step of the process of synthesizing an electronic design on a Field Programmable Gate Array (FPGA). It involves the… (more)

Subjects/Keywords: Computer science; Computer engineering; Electrical engineering; CAD; EDA; Floating point support; FPGA; Parallel CAD; Routing Algorithms

…architecture of the FPGA. In this work, we first introduce two scalable routing heuristics for FPGAs… …FPGA routing on Multicore, shared memory CPUs, using a speculation-based approach. The router… …11 2.1.3. FPGA Routing Architecture… …11 Figure 2-6: A Multiplexer in a traditional FPGA routing network… …31 Figure 2-16: Pseudocode for the PathFinder FPGA routing algorithm… 

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APA (6th Edition):

Ould Mohamed Moctar, Y. (2014). Parallel Routing for FPGAs with Sparse Intra-Cluster Routing Crossbars. (Thesis). University of California – Riverside. Retrieved from http://www.escholarship.org/uc/item/53x3x96f

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ould Mohamed Moctar, Yehdhih. “Parallel Routing for FPGAs with Sparse Intra-Cluster Routing Crossbars.” 2014. Thesis, University of California – Riverside. Accessed August 14, 2020. http://www.escholarship.org/uc/item/53x3x96f.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ould Mohamed Moctar, Yehdhih. “Parallel Routing for FPGAs with Sparse Intra-Cluster Routing Crossbars.” 2014. Web. 14 Aug 2020.

Vancouver:

Ould Mohamed Moctar Y. Parallel Routing for FPGAs with Sparse Intra-Cluster Routing Crossbars. [Internet] [Thesis]. University of California – Riverside; 2014. [cited 2020 Aug 14]. Available from: http://www.escholarship.org/uc/item/53x3x96f.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ould Mohamed Moctar Y. Parallel Routing for FPGAs with Sparse Intra-Cluster Routing Crossbars. [Thesis]. University of California – Riverside; 2014. Available from: http://www.escholarship.org/uc/item/53x3x96f

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Yi, Huixiang. Flexible HW-SW design and analysis of an MMT-based MANET system on FPGA.

Degree: Computer Engineering, 2013, Rochester Institute of Technology

 Recently there has been a rapid growth of research interests in Mobile Ad-hoc Networks (MANETs). Their infrastructureless and dynamic nature demands that new strategies be… (more)

Subjects/Keywords: FPGA; Hardware-software co-design; MANET; Multi-meshed tree; Routing protocols

…20 Figure 3.6: Intra-cluster Proactive Routing… …23 Figure 3.9: Inter-cluster Reactive Routing… …48 Figure 6.3: Overall Structure of Fully Digital Hardware MMT system on FPGA… …49 Figure 6.4: Traditional FPGA System Design Flowchart… …52 Figure 6.5: FPGA SoC Hardware-Software Co-design Procedure… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yi, H. (2013). Flexible HW-SW design and analysis of an MMT-based MANET system on FPGA. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/3200

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yi, Huixiang. “Flexible HW-SW design and analysis of an MMT-based MANET system on FPGA.” 2013. Thesis, Rochester Institute of Technology. Accessed August 14, 2020. https://scholarworks.rit.edu/theses/3200.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yi, Huixiang. “Flexible HW-SW design and analysis of an MMT-based MANET system on FPGA.” 2013. Web. 14 Aug 2020.

Vancouver:

Yi H. Flexible HW-SW design and analysis of an MMT-based MANET system on FPGA. [Internet] [Thesis]. Rochester Institute of Technology; 2013. [cited 2020 Aug 14]. Available from: https://scholarworks.rit.edu/theses/3200.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yi H. Flexible HW-SW design and analysis of an MMT-based MANET system on FPGA. [Thesis]. Rochester Institute of Technology; 2013. Available from: https://scholarworks.rit.edu/theses/3200

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of New South Wales

22. So, Keith Kam-Ho. Lexicographic path searches for FPGA routing.

Degree: Computer Science & Engineering, 2008, University of New South Wales

 This dissertation reports on studies of the application of lexicographic graph searches to solve problems in FPGA detailed routing. Our contributions include the derivation of… (more)

Subjects/Keywords: Physical design; FPGA; Routing (Computer network management); Negotiated congestion; Lexicographic path search; Lexicography  – Data processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

So, K. K. (2008). Lexicographic path searches for FPGA routing. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/41295 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:2459/SOURCE2?view=true

Chicago Manual of Style (16th Edition):

So, Keith Kam-Ho. “Lexicographic path searches for FPGA routing.” 2008. Doctoral Dissertation, University of New South Wales. Accessed August 14, 2020. http://handle.unsw.edu.au/1959.4/41295 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:2459/SOURCE2?view=true.

MLA Handbook (7th Edition):

So, Keith Kam-Ho. “Lexicographic path searches for FPGA routing.” 2008. Web. 14 Aug 2020.

Vancouver:

So KK. Lexicographic path searches for FPGA routing. [Internet] [Doctoral dissertation]. University of New South Wales; 2008. [cited 2020 Aug 14]. Available from: http://handle.unsw.edu.au/1959.4/41295 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:2459/SOURCE2?view=true.

Council of Science Editors:

So KK. Lexicographic path searches for FPGA routing. [Doctoral Dissertation]. University of New South Wales; 2008. Available from: http://handle.unsw.edu.au/1959.4/41295 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:2459/SOURCE2?view=true


Iowa State University

23. Keung, Ka-ming. A study of on-chip FPGA system with 2D mesh network.

Degree: 2010, Iowa State University

 The advance in fabrication technology hugely increases the number of available transistors on a single chip. It allows the industry to build the entire system… (more)

Subjects/Keywords: Adaptive Routing; FPGA; Multicast; On-chip network; On-chip system; Placement; Electrical and Computer Engineering

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APA (6th Edition):

Keung, K. (2010). A study of on-chip FPGA system with 2D mesh network. (Thesis). Iowa State University. Retrieved from https://lib.dr.iastate.edu/etd/11251

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Keung, Ka-ming. “A study of on-chip FPGA system with 2D mesh network.” 2010. Thesis, Iowa State University. Accessed August 14, 2020. https://lib.dr.iastate.edu/etd/11251.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Keung, Ka-ming. “A study of on-chip FPGA system with 2D mesh network.” 2010. Web. 14 Aug 2020.

Vancouver:

Keung K. A study of on-chip FPGA system with 2D mesh network. [Internet] [Thesis]. Iowa State University; 2010. [cited 2020 Aug 14]. Available from: https://lib.dr.iastate.edu/etd/11251.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Keung K. A study of on-chip FPGA system with 2D mesh network. [Thesis]. Iowa State University; 2010. Available from: https://lib.dr.iastate.edu/etd/11251

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. Mochizuki, Brent A. Redefining the hardware-software boundary in networked systems.

Degree: MS, 1200, 2010, University of Illinois – Urbana-Champaign

 While the traditional division between hardware and software development provides a useful layer of abstraction that allows developers to create complex software applications with limited… (more)

Subjects/Keywords: Internet routing; Field-Programmable Gate Array (FPGA); network simulation; network hardware; hardware-software boundary

…Figure 4.1: FPGA-based architecture for BGP. BGP is a distributed routing protocol that, to… …4.2 Trie Management . . . . . . . . . . . . . . . . . 4.3 Routing Table Management… …CONSIDERATIONS OF HAIR . . . 24 7.1 Supporting Standard Routing Policies . . . . . . . . . . . . . . 24… …Specifically it explores Internet routing using the Border Gateway Protocol (BGP) [4… …to hardware, guidelines on how often routing updates can be propagated are needed… 

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APA (6th Edition):

Mochizuki, B. A. (2010). Redefining the hardware-software boundary in networked systems. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/16891

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mochizuki, Brent A. “Redefining the hardware-software boundary in networked systems.” 2010. Thesis, University of Illinois – Urbana-Champaign. Accessed August 14, 2020. http://hdl.handle.net/2142/16891.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mochizuki, Brent A. “Redefining the hardware-software boundary in networked systems.” 2010. Web. 14 Aug 2020.

Vancouver:

Mochizuki BA. Redefining the hardware-software boundary in networked systems. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2010. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/2142/16891.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mochizuki BA. Redefining the hardware-software boundary in networked systems. [Thesis]. University of Illinois – Urbana-Champaign; 2010. Available from: http://hdl.handle.net/2142/16891

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. Patil, Shivukumar Basanagouda. On-Chip Communication and Security in FPGAs.

Degree: University of Massachusetts

  Innovations in Field Programmable Gate Array (FPGA) manufacturing processes and architectural design have led to the development of extremely large FPGAs. There has also… (more)

Subjects/Keywords: FPGA; NoCs; Security; Side Channel; Routing; Leakage; Characterization; Electrical and Electronics; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Patil, S. B. (n.d.). On-Chip Communication and Security in FPGAs. (Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/masters_theses_2/724

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Patil, Shivukumar Basanagouda. “On-Chip Communication and Security in FPGAs.” Thesis, University of Massachusetts. Accessed August 14, 2020. https://scholarworks.umass.edu/masters_theses_2/724.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Patil, Shivukumar Basanagouda. “On-Chip Communication and Security in FPGAs.” Web. 14 Aug 2020.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Patil SB. On-Chip Communication and Security in FPGAs. [Internet] [Thesis]. University of Massachusetts; [cited 2020 Aug 14]. Available from: https://scholarworks.umass.edu/masters_theses_2/724.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Patil SB. On-Chip Communication and Security in FPGAs. [Thesis]. University of Massachusetts; Available from: https://scholarworks.umass.edu/masters_theses_2/724

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

26. Taj, Billy. Single Event Upset error detection on routing tracks of Xilinx FPGAs.

Degree: MASc, 2013, McMaster University

This thesis proposes a new method to detect routing switch alterations on FPGAs in real-time. By sampling the circuit path at the source and… (more)

Subjects/Keywords: FPGA; SEU; Xilinx; routing; switchbox; error detection; VLSI and circuits, Embedded and Hardware Systems; VLSI and circuits, Embedded and Hardware Systems

…with Comparison, and redesigning the FPGA. The probe method finds the routing error in one… …cause errors in the FPGA memory, which can affect everything in the FPGA; from LUTs to routing… …restricted to SEU effects on the routing mechanisms of the FPGA. 1.4.2 Coverage and cost Current… …SEUs that affect the routing network of the FPGA. The solution can detect single SEU strikes… …the routing tracks of an FPGA circuit. • Reverse engineering the Xilinx switch fabric in… 

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APA (6th Edition):

Taj, B. (2013). Single Event Upset error detection on routing tracks of Xilinx FPGAs. (Masters Thesis). McMaster University. Retrieved from http://hdl.handle.net/11375/15283

Chicago Manual of Style (16th Edition):

Taj, Billy. “Single Event Upset error detection on routing tracks of Xilinx FPGAs.” 2013. Masters Thesis, McMaster University. Accessed August 14, 2020. http://hdl.handle.net/11375/15283.

MLA Handbook (7th Edition):

Taj, Billy. “Single Event Upset error detection on routing tracks of Xilinx FPGAs.” 2013. Web. 14 Aug 2020.

Vancouver:

Taj B. Single Event Upset error detection on routing tracks of Xilinx FPGAs. [Internet] [Masters thesis]. McMaster University; 2013. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/11375/15283.

Council of Science Editors:

Taj B. Single Event Upset error detection on routing tracks of Xilinx FPGAs. [Masters Thesis]. McMaster University; 2013. Available from: http://hdl.handle.net/11375/15283

27. El-Hassan, Fadi. Hardware Architecture of an XML/XPath Broker/Router for Content-Based Publish/Subscribe Data Dissemination Systems .

Degree: 2014, University of Ottawa

 The dissemination of various types of data faces ongoing challenges with the growing need of accessing manifold information. Since the interest in content is what… (more)

Subjects/Keywords: Publish/Subscribe; Reconfigurable Hardware; Content-Based Networks; Content-based Routing; FPGA; Broker; XML; XPath; Data Dissemination; XML Parsing; Embedded Systems; Future Internet; Router; Hardware Accelerator

…Based Routing . . . . . . . . . . . . . . . . . . . . . . . . 41 3.2.5 Multimedia Support… …Routing Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 The Hardware Broker… …Routing Tasks of the Broker . . . . . . . . . . . . . . . . 108 5.4.1 Separation Between… …Matching and Routing . . . . . . . . . . . . . 108 ix 5.4.2 Identity-Based Matching versus… …Identity-Based Routing . . . . . . 108 5.4.3 Content-Based Routing Mechanisms… 

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APA (6th Edition):

El-Hassan, F. (2014). Hardware Architecture of an XML/XPath Broker/Router for Content-Based Publish/Subscribe Data Dissemination Systems . (Thesis). University of Ottawa. Retrieved from http://hdl.handle.net/10393/30660

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

El-Hassan, Fadi. “Hardware Architecture of an XML/XPath Broker/Router for Content-Based Publish/Subscribe Data Dissemination Systems .” 2014. Thesis, University of Ottawa. Accessed August 14, 2020. http://hdl.handle.net/10393/30660.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

El-Hassan, Fadi. “Hardware Architecture of an XML/XPath Broker/Router for Content-Based Publish/Subscribe Data Dissemination Systems .” 2014. Web. 14 Aug 2020.

Vancouver:

El-Hassan F. Hardware Architecture of an XML/XPath Broker/Router for Content-Based Publish/Subscribe Data Dissemination Systems . [Internet] [Thesis]. University of Ottawa; 2014. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/10393/30660.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

El-Hassan F. Hardware Architecture of an XML/XPath Broker/Router for Content-Based Publish/Subscribe Data Dissemination Systems . [Thesis]. University of Ottawa; 2014. Available from: http://hdl.handle.net/10393/30660

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

28. Cannon, Matthew Joel. Improving the Single Event Effect Response of Triple Modular Redundancy on SRAM FPGAs Through Placement and Routing.

Degree: PhD, 2019, Brigham Young University

  Triple modular redundancy (TMR) with repair is commonly used to improve the reliability of systems. TMR is often employed for circuits implemented on field… (more)

Subjects/Keywords: FPGA; reliability; SEE; SEU; radiation effects; TMR; MTTF; fault injection; radiation testing; Markov chain; single bit failure; single point failure; common mode failure; common cause failure; CAD; incremental placement; incremental routing

FPGA Effects of SEUs in the Routing Network . . . . . . FPGA Board in a Neutron Radiation… …Switchbox Routing Switchbox Figure 1.1: General FPGA Architecture The combination of DSPs… …Implemented on an FPGA • Open - The SEU occurs on a set routing bit, i.e., a configuration bit that… …x28;3-Voter) Implementation Metrics . . . . . . . . . . . . . Routing Nodes Utilized by… …Untriplicated Nets in Common-IO (3-Voter) Split-Clock Routing Nodes Utilized by… 

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APA (6th Edition):

Cannon, M. J. (2019). Improving the Single Event Effect Response of Triple Modular Redundancy on SRAM FPGAs Through Placement and Routing. (Doctoral Dissertation). Brigham Young University. Retrieved from https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=8551&context=etd

Chicago Manual of Style (16th Edition):

Cannon, Matthew Joel. “Improving the Single Event Effect Response of Triple Modular Redundancy on SRAM FPGAs Through Placement and Routing.” 2019. Doctoral Dissertation, Brigham Young University. Accessed August 14, 2020. https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=8551&context=etd.

MLA Handbook (7th Edition):

Cannon, Matthew Joel. “Improving the Single Event Effect Response of Triple Modular Redundancy on SRAM FPGAs Through Placement and Routing.” 2019. Web. 14 Aug 2020.

Vancouver:

Cannon MJ. Improving the Single Event Effect Response of Triple Modular Redundancy on SRAM FPGAs Through Placement and Routing. [Internet] [Doctoral dissertation]. Brigham Young University; 2019. [cited 2020 Aug 14]. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=8551&context=etd.

Council of Science Editors:

Cannon MJ. Improving the Single Event Effect Response of Triple Modular Redundancy on SRAM FPGAs Through Placement and Routing. [Doctoral Dissertation]. Brigham Young University; 2019. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=8551&context=etd

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