subject:(Emulator)

Colorado School of Mines

1. Heer, Kyle B. Design and control of a lower-limb exoskeleton emulator for accelerated development of gait exoskeletons.

Degree: MS(M.S.), Mechanical Engineering, 2017, Colorado School of Mines

URL: http://hdl.handle.net/11124/171178

► Robotic exoskeletons for gait assistance carry the potential to dramatically improve the quality of life for individuals with hemiparesis resulting from a stroke. This thesis… (more)

Subjects/Keywords: exoskeleton; Emulator; Gait

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APA (6^th Edition):

Heer, K. B. (2017). Design and control of a lower-limb exoskeleton emulator for accelerated development of gait exoskeletons. (Masters Thesis). Colorado School of Mines. Retrieved from http://hdl.handle.net/11124/171178

Chicago Manual of Style (16^th Edition):

Heer, Kyle B. “Design and control of a lower-limb exoskeleton emulator for accelerated development of gait exoskeletons.” 2017. Masters Thesis, Colorado School of Mines. Accessed February 28, 2021. http://hdl.handle.net/11124/171178.

MLA Handbook (7^th Edition):

Heer, Kyle B. “Design and control of a lower-limb exoskeleton emulator for accelerated development of gait exoskeletons.” 2017. Web. 28 Feb 2021.

Vancouver:

Heer KB. Design and control of a lower-limb exoskeleton emulator for accelerated development of gait exoskeletons. [Internet] [Masters thesis]. Colorado School of Mines; 2017. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/11124/171178.

Council of Science Editors:

Heer KB. Design and control of a lower-limb exoskeleton emulator for accelerated development of gait exoskeletons. [Masters Thesis]. Colorado School of Mines; 2017. Available from: http://hdl.handle.net/11124/171178

University of Houston

2. Janakiraman, Shyam. AN ADAPTIVE SENSORLESS CONTROL FOR MAXIMUM POWER POINT TRACKING IN WIND ENERGY CONVERSION SYSTEM.

Degree: MSin Electrical Engineering, Electrical Engineering, 2014, University of Houston

URL: http://hdl.handle.net/10657/1398

► This thesis presents a novel mechanical sensorless adaptive control algorithm for Maximum Power Point Tracking (MPPT) in Wind Energy Conversion Systems (WECS). The proposed control… (more)

Subjects/Keywords: MPPT; Wind Turbine Emulator

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APA (6^th Edition):

Janakiraman, S. (2014). AN ADAPTIVE SENSORLESS CONTROL FOR MAXIMUM POWER POINT TRACKING IN WIND ENERGY CONVERSION SYSTEM. (Masters Thesis). University of Houston. Retrieved from http://hdl.handle.net/10657/1398

Chicago Manual of Style (16^th Edition):

Janakiraman, Shyam. “AN ADAPTIVE SENSORLESS CONTROL FOR MAXIMUM POWER POINT TRACKING IN WIND ENERGY CONVERSION SYSTEM.” 2014. Masters Thesis, University of Houston. Accessed February 28, 2021. http://hdl.handle.net/10657/1398.

MLA Handbook (7^th Edition):

Janakiraman, Shyam. “AN ADAPTIVE SENSORLESS CONTROL FOR MAXIMUM POWER POINT TRACKING IN WIND ENERGY CONVERSION SYSTEM.” 2014. Web. 28 Feb 2021.

Vancouver:

Janakiraman S. AN ADAPTIVE SENSORLESS CONTROL FOR MAXIMUM POWER POINT TRACKING IN WIND ENERGY CONVERSION SYSTEM. [Internet] [Masters thesis]. University of Houston; 2014. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/10657/1398.

Council of Science Editors:

Janakiraman S. AN ADAPTIVE SENSORLESS CONTROL FOR MAXIMUM POWER POINT TRACKING IN WIND ENERGY CONVERSION SYSTEM. [Masters Thesis]. University of Houston; 2014. Available from: http://hdl.handle.net/10657/1398

Colorado School of Mines

3. Lee, Jason Y. Lower-limb exoskeleton emulator to be employed in estimation of hip impedance in normal gait, A.

Degree: MS(M.S.), Mechanical Engineering, 2017, Colorado School of Mines

URL: http://hdl.handle.net/11124/171298

► Recent progress in robotic control and technology has contributed to an increase in interest and applications of wearable robotics, also known as exoskeletons. Identification of… (more)

▼ Recent progress in robotic control and technology has contributed to an increase in interest and applications of wearable robotics, also known as exoskeletons. Identification of exoskeleton mechanical and control parameters that will provide the best performance for specific tasks remains as a significant challenge. Exoskeleton emulators, which allow real-time adjustment of device parameters (such as stiffness of an emulated spring) have emerged as valuable tools that enable fast, iterative experimentation and testing. This thesis presents design, implementation, and characterization results of a lower-limb exoskeleton emulator system with offloaded actuation. The emulator is able to apply controlled torques in the ankle, knee and hip joint sagittal degrees of freedom through five braces that were developed. A PID controller was implemented for the emulator to control the torques applied at the brace joints. Characterization of hip joint impedance is essential to the groundwork for design and control system of exoskeletons, orthoses, and prostheses. A pilot test with a single healthy subject was conducted, using the emulator as a perturbation source and focusing on identification of hip impedance parameters during normal walking. A model, that incorporated stiffness, damping, and inertia parameters as polynomial coefficients, was used to calculate the impedance values from the collected data. The results showed that the perturbation amplitudes were inadequate and soft tissues at the leg attachment points prevented effective delivery of the torques to the leg. Future work on impedance estimation of hip will focus on improving brace leg attachments and enhancing the delivered torque. In conclusion, an exoskeleton emulator for the lower-limb was successfully designed, constructed, characterized, and tested. The exoskeleton emulator will enable a variety of future studies on gait augmentation and assistance. Advisors/Committee Members: Celik, Ozkan (advisor), Petrella, Anthony J. (committee member), Silverman, Anne K. (committee member).

Subjects/Keywords: exoskeleton; impedance; hip; emulator

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APA (6^th Edition):

Lee, J. Y. (2017). Lower-limb exoskeleton emulator to be employed in estimation of hip impedance in normal gait, A. (Masters Thesis). Colorado School of Mines. Retrieved from http://hdl.handle.net/11124/171298

Chicago Manual of Style (16^th Edition):

Lee, Jason Y. “Lower-limb exoskeleton emulator to be employed in estimation of hip impedance in normal gait, A.” 2017. Masters Thesis, Colorado School of Mines. Accessed February 28, 2021. http://hdl.handle.net/11124/171298.

MLA Handbook (7^th Edition):

Lee, Jason Y. “Lower-limb exoskeleton emulator to be employed in estimation of hip impedance in normal gait, A.” 2017. Web. 28 Feb 2021.

Vancouver:

Lee JY. Lower-limb exoskeleton emulator to be employed in estimation of hip impedance in normal gait, A. [Internet] [Masters thesis]. Colorado School of Mines; 2017. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/11124/171298.

Council of Science Editors:

Lee JY. Lower-limb exoskeleton emulator to be employed in estimation of hip impedance in normal gait, A. [Masters Thesis]. Colorado School of Mines; 2017. Available from: http://hdl.handle.net/11124/171298

NSYSU

4. Hung, Chih-Yang. OpenGL ES-based Emulator with Performance Tuning in the 3DApplication Development Platform for Embedded Systems.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-161135

► Developing 3D application for low-performance embedded system often contains some limitations as hardware specifications (e.g. memory and processing efficiency). Existing OpenGL ES emulators are designed… (more)

Subjects/Keywords: Emulator; OpenGL ES; Embedded System; Performance Tuning

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APA (6^th Edition):

Hung, C. (2009). OpenGL ES-based Emulator with Performance Tuning in the 3DApplication Development Platform for Embedded Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-161135

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hung, Chih-Yang. “OpenGL ES-based Emulator with Performance Tuning in the 3DApplication Development Platform for Embedded Systems.” 2009. Thesis, NSYSU. Accessed February 28, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-161135.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hung, Chih-Yang. “OpenGL ES-based Emulator with Performance Tuning in the 3DApplication Development Platform for Embedded Systems.” 2009. Web. 28 Feb 2021.

Vancouver:

Hung C. OpenGL ES-based Emulator with Performance Tuning in the 3DApplication Development Platform for Embedded Systems. [Internet] [Thesis]. NSYSU; 2009. [cited 2021 Feb 28]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-161135.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hung C. OpenGL ES-based Emulator with Performance Tuning in the 3DApplication Development Platform for Embedded Systems. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0904109-161135

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

5. Movagharian Pour, Veronika. Web-based data base assembly language editor.

Degree: MS, Computer Science, 2013, California State University – Northridge

URL: http://hdl.handle.net/10211.2/3510

► Assembly programming language is taught to the students with computer science major in COMP 122 Computer Architecture course. Since assembly programming languages are considered low… (more)

Subjects/Keywords: Assembly Emulator; Dissertations, Academic – CSUN – Computer Science.

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APA (6^th Edition):

Movagharian Pour, V. (2013). Web-based data base assembly language editor. (Masters Thesis). California State University – Northridge. Retrieved from http://hdl.handle.net/10211.2/3510

Chicago Manual of Style (16^th Edition):

Movagharian Pour, Veronika. “Web-based data base assembly language editor.” 2013. Masters Thesis, California State University – Northridge. Accessed February 28, 2021. http://hdl.handle.net/10211.2/3510.

MLA Handbook (7^th Edition):

Movagharian Pour, Veronika. “Web-based data base assembly language editor.” 2013. Web. 28 Feb 2021.

Vancouver:

Movagharian Pour V. Web-based data base assembly language editor. [Internet] [Masters thesis]. California State University – Northridge; 2013. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/10211.2/3510.

Council of Science Editors:

Movagharian Pour V. Web-based data base assembly language editor. [Masters Thesis]. California State University – Northridge; 2013. Available from: http://hdl.handle.net/10211.2/3510

KTH

6. Muthu, Arun. Emulating Trust zone feature in Android emulator by extending QEMU.

Degree: Information and Communication Technology (ICT), 2013, KTH

URL: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-128518

► The arrival of smart phones has created the new era in communication between users and internet. Smart phone users are able to run their… (more)

Subjects/Keywords: Trust zone; Emulator; Android; Virtualization; and Security

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APA (6^th Edition):

Muthu, A. (2013). Emulating Trust zone feature in Android emulator by extending QEMU. (Thesis). KTH. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-128518

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Muthu, Arun. “Emulating Trust zone feature in Android emulator by extending QEMU.” 2013. Thesis, KTH. Accessed February 28, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-128518.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Muthu, Arun. “Emulating Trust zone feature in Android emulator by extending QEMU.” 2013. Web. 28 Feb 2021.

Vancouver:

Muthu A. Emulating Trust zone feature in Android emulator by extending QEMU. [Internet] [Thesis]. KTH; 2013. [cited 2021 Feb 28]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-128518.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Muthu A. Emulating Trust zone feature in Android emulator by extending QEMU. [Thesis]. KTH; 2013. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-128518

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

7. Pettersson, Markus. Dynamically Recompiling Emulator - Dynamic recompilation of MOS 6502 machine code through LLVM IR using a JIT compiler .

Degree: Chalmers tekniska högskola / Institutionen för data och informationsteknik, 2020, Chalmers University of Technology

URL: http://hdl.handle.net/20.500.12380/301970

► This report examines the possibility to implement dynamic recompilation of machine code for the central processing unit MOS 6502. Using libraries for compilation and optimizations,… (more)

Subjects/Keywords: emulation; dynamically recompiling emulator; interpreting emulator; dynamic recompilation; JIT; LLVM; MOS 6502

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APA (6^th Edition):

Pettersson, M. (2020). Dynamically Recompiling Emulator - Dynamic recompilation of MOS 6502 machine code through LLVM IR using a JIT compiler . (Thesis). Chalmers University of Technology. Retrieved from http://hdl.handle.net/20.500.12380/301970

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Pettersson, Markus. “Dynamically Recompiling Emulator - Dynamic recompilation of MOS 6502 machine code through LLVM IR using a JIT compiler .” 2020. Thesis, Chalmers University of Technology. Accessed February 28, 2021. http://hdl.handle.net/20.500.12380/301970.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Pettersson, Markus. “Dynamically Recompiling Emulator - Dynamic recompilation of MOS 6502 machine code through LLVM IR using a JIT compiler .” 2020. Web. 28 Feb 2021.

Vancouver:

Pettersson M. Dynamically Recompiling Emulator - Dynamic recompilation of MOS 6502 machine code through LLVM IR using a JIT compiler . [Internet] [Thesis]. Chalmers University of Technology; 2020. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/20.500.12380/301970.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pettersson M. Dynamically Recompiling Emulator - Dynamic recompilation of MOS 6502 machine code through LLVM IR using a JIT compiler . [Thesis]. Chalmers University of Technology; 2020. Available from: http://hdl.handle.net/20.500.12380/301970

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

8. Thota, Himabindu. Design Enhancements And A Validation Framework For ARM Emulator.

Degree: Computer Engineering, 2013, University of California – Santa Cruz

URL: http://www.escholarship.org/uc/item/1p85d705

► Processor emulators allow micro-architecture researchers to evaluate research ideas quickly and at no extra cost. Micro-architecture Santa Cruz (MASC) Laboratory is developing an ARM processor… (more)

Subjects/Keywords: Computer engineering; ARM Emulator; Emulator Validation Framework

…MASC ARM Emulator - Santa Cruz Micro Operation (scuop) Class Members. Register… …Abstract DESIGN ENHANCEMENTS AND A VALIDATION FRAMEWORK FOR ARM EMULATOR by Himabindu Thota… …ARM processor emulator to execute ARM binaries. To ensure correctness of the emulator, it is… …implement a validation infrastructure for the emulator ISA and the second, to improve the emulator… …the ARM emulator. viii Acknowledgments Most importantly, I would like to thank my advisor…

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APA (6^th Edition):

Thota, H. (2013). Design Enhancements And A Validation Framework For ARM Emulator. (Thesis). University of California – Santa Cruz. Retrieved from http://www.escholarship.org/uc/item/1p85d705

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Thota, Himabindu. “Design Enhancements And A Validation Framework For ARM Emulator.” 2013. Thesis, University of California – Santa Cruz. Accessed February 28, 2021. http://www.escholarship.org/uc/item/1p85d705.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Thota, Himabindu. “Design Enhancements And A Validation Framework For ARM Emulator.” 2013. Web. 28 Feb 2021.

Vancouver:

Thota H. Design Enhancements And A Validation Framework For ARM Emulator. [Internet] [Thesis]. University of California – Santa Cruz; 2013. [cited 2021 Feb 28]. Available from: http://www.escholarship.org/uc/item/1p85d705.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Thota H. Design Enhancements And A Validation Framework For ARM Emulator. [Thesis]. University of California – Santa Cruz; 2013. Available from: http://www.escholarship.org/uc/item/1p85d705

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

9. Tsai, Feng-wen. An Emulator for OpenGL ES 2.0 based on C-language Compiler.

Degree: Master, Computer Science and Engineering, 2008, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729108-152706

► OpenGL ES 2.0 is the newest 3D graphics technology for hand-held devices established by Khronos. Users need a shading language compiler and a graphics card… (more)

Subjects/Keywords: Programmable Pipeline; Embedded System; Emulator; OpenGL ES 2.0

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APA (6^th Edition):

Tsai, F. (2008). An Emulator for OpenGL ES 2.0 based on C-language Compiler. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729108-152706

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Tsai, Feng-wen. “An Emulator for OpenGL ES 2.0 based on C-language Compiler.” 2008. Thesis, NSYSU. Accessed February 28, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729108-152706.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Tsai, Feng-wen. “An Emulator for OpenGL ES 2.0 based on C-language Compiler.” 2008. Web. 28 Feb 2021.

Vancouver:

Tsai F. An Emulator for OpenGL ES 2.0 based on C-language Compiler. [Internet] [Thesis]. NSYSU; 2008. [cited 2021 Feb 28]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729108-152706.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsai F. An Emulator for OpenGL ES 2.0 based on C-language Compiler. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729108-152706

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

10. Hsu, Wen-yen. Battery Emulator Circuit for The Application of Energy Measurement.

Degree: Master, Electrical Engineering, 2015, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0913115-130616

► In recent years, electronic products became portable and have lowered power consumption because of the limited energy resource availability. The measurement of energy consumption of… (more)

Subjects/Keywords: capacitor changing; simulating battery lifetime; dynamic emulator; current measurement; energy consumption

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APA (6^th Edition):

Hsu, W. (2015). Battery Emulator Circuit for The Application of Energy Measurement. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0913115-130616

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hsu, Wen-yen. “Battery Emulator Circuit for The Application of Energy Measurement.” 2015. Thesis, NSYSU. Accessed February 28, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0913115-130616.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hsu, Wen-yen. “Battery Emulator Circuit for The Application of Energy Measurement.” 2015. Web. 28 Feb 2021.

Vancouver:

Hsu W. Battery Emulator Circuit for The Application of Energy Measurement. [Internet] [Thesis]. NSYSU; 2015. [cited 2021 Feb 28]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0913115-130616.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu W. Battery Emulator Circuit for The Application of Energy Measurement. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0913115-130616

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

11. Lin, Chun-Shou. Design and verification of an ARM10-like Processor and its System Integration.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0207112-161403

► With the advanced of the technique, we can design more IP in the same area space chip. The embedded system has more powerful about its… (more)

Subjects/Keywords: Integration; Embedded in circuit emulator (EICE); Microprocessor; Verification; Cache/MMU; Coprocessor

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APA (6^th Edition):

Lin, C. (2012). Design and verification of an ARM10-like Processor and its System Integration. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0207112-161403

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lin, Chun-Shou. “Design and verification of an ARM10-like Processor and its System Integration.” 2012. Thesis, NSYSU. Accessed February 28, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0207112-161403.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lin, Chun-Shou. “Design and verification of an ARM10-like Processor and its System Integration.” 2012. Web. 28 Feb 2021.

Vancouver:

Lin C. Design and verification of an ARM10-like Processor and its System Integration. [Internet] [Thesis]. NSYSU; 2012. [cited 2021 Feb 28]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0207112-161403.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin C. Design and verification of an ARM10-like Processor and its System Integration. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0207112-161403

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

12. Nelson, Charles Lloyd. EXPERIMENTS IN OPTIMIZATION OF FREE SPACE OPTICAL COMMUNICATION LINKS FOR APPLICATIONS IN A MARITIME ENVIRONMENT.

Degree: 2013, Johns Hopkins University

URL: http://jhir.library.jhu.edu/handle/1774.2/37025

► The United States Navy relies heavily on radio frequency communication networks and this reliance generates two major operational limitations: bandwidth, and lack of contingency capability… (more)

▼ The United States Navy relies heavily on radio frequency communication networks and this reliance generates two major operational limitations: bandwidth, and lack of contingency capability in the event of jamming or detection by adversaries. One possible complementary solution to current radio frequency systems is through the use of free-space optical communication links. Free-space optical communication links are inherently high-bandwidth and highly directional, making them hard to detect or jam. These links have drawbacks as well. A laser beam propagating in a maritime environment can experience significant random intensity fluctuations due to optical turbulence, which can lead to power loss at the receiver and degraded performance. Understanding the effects of the maritime environment on the propagating laser beam is critical to the improvement of laser communication in this environment. For example, the probability density function of the intensity for a given detector is vital for estimating the fade statistics of an optical signal and its effect on the bit-error rate of a communication system. Understanding the evolution and form of the probability density function as it relates to distance, turbulence level, and detector type holds great benefit for optimizing the maritime communication link in a given optical channel. Our research focuses on how to modify the transmit characteristics of the laser beam in order to minimize the intensity fluctuations and time and depth of fades – which can be on the order of milliseconds and tens of decibels. Specifically, modifying the partial spatial coherence properties of the beam at the transmitter offers significant potential in minimizing the deep fades at the receiver. Also, field experimentation is critical. To that end, two field tests off the Atlantic Coast and five field experiments at the United States Naval Academy were performed. Additionally, working in a controlled laboratory setting capable of simulating some of the scaled effects of the environment holds great advantages in cost, testing methods, and optimization. We built an in-laboratory hot-air turbulence emulator with a modular and extendable design, allowing us to research comparisons between the field and laboratory experiments. This has greatly enhanced our ability to project theory into practice. Thesis Adviser: Dr. Frederic M. Davidson Thesis Readers: Dr. Frederic M. Davidson and Dr. Jacob Khurgin Advisors/Committee Members: Davidson, Frederic (advisor).

Subjects/Keywords: Free space optics; partial spatial coherence; hot air turbulence emulator

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APA (6^th Edition):

Nelson, C. L. (2013). EXPERIMENTS IN OPTIMIZATION OF FREE SPACE OPTICAL COMMUNICATION LINKS FOR APPLICATIONS IN A MARITIME ENVIRONMENT. (Thesis). Johns Hopkins University. Retrieved from http://jhir.library.jhu.edu/handle/1774.2/37025

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Nelson, Charles Lloyd. “EXPERIMENTS IN OPTIMIZATION OF FREE SPACE OPTICAL COMMUNICATION LINKS FOR APPLICATIONS IN A MARITIME ENVIRONMENT.” 2013. Thesis, Johns Hopkins University. Accessed February 28, 2021. http://jhir.library.jhu.edu/handle/1774.2/37025.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Nelson, Charles Lloyd. “EXPERIMENTS IN OPTIMIZATION OF FREE SPACE OPTICAL COMMUNICATION LINKS FOR APPLICATIONS IN A MARITIME ENVIRONMENT.” 2013. Web. 28 Feb 2021.

Vancouver:

Nelson CL. EXPERIMENTS IN OPTIMIZATION OF FREE SPACE OPTICAL COMMUNICATION LINKS FOR APPLICATIONS IN A MARITIME ENVIRONMENT. [Internet] [Thesis]. Johns Hopkins University; 2013. [cited 2021 Feb 28]. Available from: http://jhir.library.jhu.edu/handle/1774.2/37025.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nelson CL. EXPERIMENTS IN OPTIMIZATION OF FREE SPACE OPTICAL COMMUNICATION LINKS FOR APPLICATIONS IN A MARITIME ENVIRONMENT. [Thesis]. Johns Hopkins University; 2013. Available from: http://jhir.library.jhu.edu/handle/1774.2/37025

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Toronto

13. Luces, Mario. An Emulator-based Prediction of Dynamic Stiffness for Redundant Parallel Mechanisms.

Degree: 2015, University of Toronto

URL: http://hdl.handle.net/1807/70477

►

For Parallel Kinematic Mechanisms (PKMs) with kinematic redundancy, mechanism configurations with higher stiffness can be chosen during motion-trajectory planning. However, substantial computational resources would be… (more)

Subjects/Keywords: Dynamic Stiffness; Emulator; MLS; Parallel Kinematic Mechanism; Redundancy; 0548

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APA (6^th Edition):

Luces, M. (2015). An Emulator-based Prediction of Dynamic Stiffness for Redundant Parallel Mechanisms. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/70477

Chicago Manual of Style (16^th Edition):

Luces, Mario. “An Emulator-based Prediction of Dynamic Stiffness for Redundant Parallel Mechanisms.” 2015. Masters Thesis, University of Toronto. Accessed February 28, 2021. http://hdl.handle.net/1807/70477.

MLA Handbook (7^th Edition):

Luces, Mario. “An Emulator-based Prediction of Dynamic Stiffness for Redundant Parallel Mechanisms.” 2015. Web. 28 Feb 2021.

Vancouver:

Luces M. An Emulator-based Prediction of Dynamic Stiffness for Redundant Parallel Mechanisms. [Internet] [Masters thesis]. University of Toronto; 2015. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/1807/70477.

Council of Science Editors:

Luces M. An Emulator-based Prediction of Dynamic Stiffness for Redundant Parallel Mechanisms. [Masters Thesis]. University of Toronto; 2015. Available from: http://hdl.handle.net/1807/70477

14. UMESH, AKELLA. Performance analysis of transmission protocols for H.265 encoder.

Degree: 2015, , Department of Communication Systems

URL: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-10873

► In recent years there has been a predominant increase in multimedia services such as live streaming, Video on Demand (VoD), video conferencing, videos for… (more)

▼ In recent years there has been a predominant increase in multimedia services such as live streaming, Video on Demand (VoD), video conferencing, videos for the learning. Streaming of high quality videos has become a challenge for service providers to enhance the user’s watching experience. The service providers cannot guarantee the perceived quality. In order to enhance the user’s expectations, it is also important to estimate the quality of video perceived by the user. There are different video streaming protocols that are used to stream from server to client. In this research, we aren’t focused on the user’s experience. We are mainly focused on the performance behavior of the protocols. In this study, we investigate the performance of the HTTP, RTSP and WebRTC protocols when streaming is carried out for H.265 encoder. The study addresses for the objective assessment of different protocols over VoD streaming at the network and application layers. Packet loss and delay variations are altered at the network layer using network emulator NetEm when streaming from server to client. The metrics at the network layer and application layer are collected and analyzed. The video is streamed from server to a client, the quality of the video is checked by some of the users. The research method has been carried out using an experimental testbed. The metrics such as packet counts at network layer and stream bitrate at application layer are collected for HTTP, RTSP and WebRTC protocols. Variable delays and packet losses are injected into the network to emulate real world. Based on the results obtained, it was found at the application layer that, out of the three protocols, HTTP, RTSP and WebRTC, the stream bitrate of the video transmitted using HTTP was less when compared to the other. Hence, HTTP performs better in the application layer. At the network layer, the packet counts of the video transmitted were collected using TCP port for HTTP and UDP port for RTSP and WebRTC protocols. The performance of HTTP was found to be stable in most of the scenarios. On comparing RTSP and WebRTC, the number of packet counts collected were more in number for RTSP when compared to WebRTC. This is because, the protocol and also the streamer are using more resources to transmit the video. Hence, both the protocols RTSP and WebRTC are performing better relatively.

Subjects/Keywords: H.265; HTTP; Network Emulator; RTSP; VoD; WebRTC

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APA (6^th Edition):

UMESH, A. (2015). Performance analysis of transmission protocols for H.265 encoder. (Thesis). , Department of Communication Systems. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:bth-10873

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

UMESH, AKELLA. “Performance analysis of transmission protocols for H.265 encoder.” 2015. Thesis, , Department of Communication Systems. Accessed February 28, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-10873.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

UMESH, AKELLA. “Performance analysis of transmission protocols for H.265 encoder.” 2015. Web. 28 Feb 2021.

Vancouver:

UMESH A. Performance analysis of transmission protocols for H.265 encoder. [Internet] [Thesis]. , Department of Communication Systems; 2015. [cited 2021 Feb 28]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-10873.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

UMESH A. Performance analysis of transmission protocols for H.265 encoder. [Thesis]. , Department of Communication Systems; 2015. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-10873

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

15. Nordén, Emil. Generella nätverksarkitekturer för spelemulatorer.

Degree: Business and IT, 2011, University of Borås

URL: http://urn.kb.se/resolve?urn=urn:nbn:se:hb:diva-20390

►

Många gamla spel som spelades på gamla konsoler och datorer kördes på samma maskin med två eller flera spelare anslutna med egna individuella kontroller.… (more)

▼

Många gamla spel som spelades på gamla konsoler och datorer kördes på samma maskin med två eller flera spelare anslutna med egna individuella kontroller. Idag är internet väl utspritt och många spel erbjuder multiplayer-spel via internet. Detta var förstås inte möjligt på de gamla konsolerna och datorerna, men med hjälp av de emulatorer som finns för många gamla plattformar idag kan man skapa möjligheten att spela över internet i de gamla spelen genom att skicka varje knapptryckning en spelare utför mellan spelarnas datorer och på det sättet emulera det existerande flerspelarläget i spelet. Kaillera-protokollet, som är baserat Client-server-arkitekturen, är ett protokoll designat för att spela gamla spel genom emulatorer över nätverk. Det har implementerats i ett antal populära emulatorer med hjälp av ett tredjepartsbibliotek med samma namn. Kaillera fungerar genom att synkronisera spelarnas input for each bild som visas i spelet. Kaillera-protokollet har ett antal tillkortakommanden, till exempel: • Protokollet är enbart Client-server, och det finns ingen peer-to-peer-variant. • Protokollet är stängt och inte dokumenterat. • Protokollet använder UDP för alla överföringar, vilket gör det svårt att föra över kritisk data. • Programmerargränssnittet som tillhör Kaillera-biblioteket är mycket begränsat och ger inte emulatorutvecklaren mycket utrymme närKkaillera ska implementeras. Den här rapporten beskrver en ny öppen implementation av Kaillera-protokollet och en ny variant av Kaillera-protokollet som är peer-to-peer-baserat. Rapporten består till största del av en teknisk beskrivning av ett nytt mjukvarubibliotek som är öppen källkod (LGPL), Plattformsoberoende och med ett mer flexibelt utvecklargränssnitt jämfört med den officiella implementationen av Kaillera-protokollet. Slutligen beskrivs också ett experiment för att testa hur den nya Kaillera-implementationen står sig emot det nya peer-to-peer-protokollet med avseende på prestanda, där man kunde visa att den mellanliggande servern kan vara ett prestandaproblem.

Program: Systemarkitekturutbildningen

Subjects/Keywords: emulator; programstruktur; kaillera; nätverk; spel; Engineering and Technology; Teknik och teknologier

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APA (6^th Edition):

Nordén, E. (2011). Generella nätverksarkitekturer för spelemulatorer. (Thesis). University of Borås. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:hb:diva-20390

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Nordén, Emil. “Generella nätverksarkitekturer för spelemulatorer.” 2011. Thesis, University of Borås. Accessed February 28, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:hb:diva-20390.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Nordén, Emil. “Generella nätverksarkitekturer för spelemulatorer.” 2011. Web. 28 Feb 2021.

Vancouver:

Nordén E. Generella nätverksarkitekturer för spelemulatorer. [Internet] [Thesis]. University of Borås; 2011. [cited 2021 Feb 28]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hb:diva-20390.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nordén E. Generella nätverksarkitekturer för spelemulatorer. [Thesis]. University of Borås; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hb:diva-20390

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Washington

16. Smith, Douglas George. FPGA Development of an Emulator of the RD53A Prototype Chip and its Integration with Various Readout Systems.

Degree: 2019, University of Washington

URL: http://hdl.handle.net/1773/43992

► In 2024 the Large Hadron Collider will be shut down for a major upgrade of the particle detectors and collider systems that will increase the… (more)

Subjects/Keywords: Emulator; FELIX; FPGA; RCE; RD53A; YARR; Electrical engineering; Electrical engineering

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APA (6^th Edition):

Smith, D. G. (2019). FPGA Development of an Emulator of the RD53A Prototype Chip and its Integration with Various Readout Systems. (Thesis). University of Washington. Retrieved from http://hdl.handle.net/1773/43992

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Smith, Douglas George. “FPGA Development of an Emulator of the RD53A Prototype Chip and its Integration with Various Readout Systems.” 2019. Thesis, University of Washington. Accessed February 28, 2021. http://hdl.handle.net/1773/43992.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Smith, Douglas George. “FPGA Development of an Emulator of the RD53A Prototype Chip and its Integration with Various Readout Systems.” 2019. Web. 28 Feb 2021.

Vancouver:

Smith DG. FPGA Development of an Emulator of the RD53A Prototype Chip and its Integration with Various Readout Systems. [Internet] [Thesis]. University of Washington; 2019. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/1773/43992.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Smith DG. FPGA Development of an Emulator of the RD53A Prototype Chip and its Integration with Various Readout Systems. [Thesis]. University of Washington; 2019. Available from: http://hdl.handle.net/1773/43992

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

17. Hanačík, Radim. Bezpečnost RFID: RFID Security.

Degree: 2018, Brno University of Technology

URL: http://hdl.handle.net/11012/4576

► The thesis describes the theory of radio frequency identification and is focused on the security of communication. Smart cards are divided by type of chip… (more)

Subjects/Keywords: RFID; emulátor; bezpečnost; transpondér; čárový kód; RFID; emulator; security; transponder; barcode

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APA (6^th Edition):

Hanačík, R. (2018). Bezpečnost RFID: RFID Security. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/4576

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hanačík, Radim. “Bezpečnost RFID: RFID Security.” 2018. Thesis, Brno University of Technology. Accessed February 28, 2021. http://hdl.handle.net/11012/4576.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hanačík, Radim. “Bezpečnost RFID: RFID Security.” 2018. Web. 28 Feb 2021.

Vancouver:

Hanačík R. Bezpečnost RFID: RFID Security. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/11012/4576.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hanačík R. Bezpečnost RFID: RFID Security. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/4576

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Maryland

18. Taylor, Keith Richard. Using Commercial Ray Tracing Software to Drive an Attenuator-Based Mobile WIreless Testbed.

Degree: Electrical Engineering, 2012, University of Maryland

URL: http://hdl.handle.net/1903/13556

► We propose and build a prototype architecture for a laboratory-based mobile wireless testbed that uses highly detailed, site-specific channel models to dynamically configure a many-to-many… (more)

Subjects/Keywords: Computer engineering; Electrical engineering; Channel Emulator; DTN; Ray Tracing; Wireless Testbed

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APA (6^th Edition):

Taylor, K. R. (2012). Using Commercial Ray Tracing Software to Drive an Attenuator-Based Mobile WIreless Testbed. (Thesis). University of Maryland. Retrieved from http://hdl.handle.net/1903/13556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Taylor, Keith Richard. “Using Commercial Ray Tracing Software to Drive an Attenuator-Based Mobile WIreless Testbed.” 2012. Thesis, University of Maryland. Accessed February 28, 2021. http://hdl.handle.net/1903/13556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Taylor, Keith Richard. “Using Commercial Ray Tracing Software to Drive an Attenuator-Based Mobile WIreless Testbed.” 2012. Web. 28 Feb 2021.

Vancouver:

Taylor KR. Using Commercial Ray Tracing Software to Drive an Attenuator-Based Mobile WIreless Testbed. [Internet] [Thesis]. University of Maryland; 2012. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/1903/13556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Taylor KR. Using Commercial Ray Tracing Software to Drive an Attenuator-Based Mobile WIreless Testbed. [Thesis]. University of Maryland; 2012. Available from: http://hdl.handle.net/1903/13556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

The Ohio State University

19. Zhou, Qi. Optical lattice emulator: How to construct it and what can it do.

Degree: PhD, Physics, 2009, The Ohio State University

URL: http://rave.ohiolink.edu/etdc/view?acc_num=osu1250541844

► Recently, many laboratories around the world are using cold atoms in optical lattices to emulate theoretical models for strongly correlated systems in condensed matter… (more)

▼ Recently, many laboratories around the world are using cold atoms in optical lattices to emulate theoretical models for strongly correlated systems in condensed matter physics. There are great challenges for those efforts to succeed. The first challenge is that the required temperatures for studying strongly correlated physics in optical lattices are much lower than what can be achieved in laboratories nowadays. Another one is that, it requires novel schemes to probe thermodynamic properties and macroscopic quantum phenomena of the trapped atoms. This thesis will present theoretical proposals on how to overcome those challenges. In the first part of this thesis, I will discuss new cooling schemes for trapped atoms in optical lattice so as to construct successful optical lattice emulators. For the bosonic atoms, opening up the confining potential adiabatically can reverse the heating efforts in current experiments, and allow experiments to achieve strongly correlated bosons in optical lattices. For the fermionic atoms, two alternative schemes can be used to decrease the entropy of the systems to a few percent of lowest value obtainable today. Those schemes will allow experimentalist to achieve antiferromagetism or other strongly correlated systems of fermions in optical lattices at the lowest temperature ever in laboratories. In the second part of this thesis, I will propose new probing schemes to fulfill the goal of optical lattice emulators. I will first explain why a method often used in experiments in the past a few years to probe superfluid from the sharpness of the interference pattern is incorrect. I will show that the normal state in optical lattice can also have a sharp interference pattern. I will then discuss schemes to map out the phase diagrams of quantum models, as well as many important thermodynamic quantities, such as the superfluid density and the entropy density, that have so far eluded experimental measurements. Advisors/Committee Members: Ho, Tin-Lun (Advisor).

Subjects/Keywords: Physics; optical lattice emulator

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APA (6^th Edition):

Zhou, Q. (2009). Optical lattice emulator: How to construct it and what can it do. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1250541844

Chicago Manual of Style (16^th Edition):

Zhou, Qi. “Optical lattice emulator: How to construct it and what can it do.” 2009. Doctoral Dissertation, The Ohio State University. Accessed February 28, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=osu1250541844.

MLA Handbook (7^th Edition):

Zhou, Qi. “Optical lattice emulator: How to construct it and what can it do.” 2009. Web. 28 Feb 2021.

Vancouver:

Zhou Q. Optical lattice emulator: How to construct it and what can it do. [Internet] [Doctoral dissertation]. The Ohio State University; 2009. [cited 2021 Feb 28]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1250541844.

Council of Science Editors:

Zhou Q. Optical lattice emulator: How to construct it and what can it do. [Doctoral Dissertation]. The Ohio State University; 2009. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1250541844

Ohio University

20. Kunnamareddi, Sadhishkumar. Programmable logic controller emulator enhancements to facilitate a distributed manufacturing simulation environment.

Degree: MS, Industrial and Manufacturing Systems Engineering (Engineering), 2001, Ohio University

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1173980723

Programmable logic controller emulator enhancements to facilitate a distributed manufacturing simulation environment Advisors/Committee Members: Lipset, Robert (Advisor).

Subjects/Keywords: Engineering, Industrial; Programmable Emulator; Logic Controller Emulator; Distributed Manufacturing; Simulation Environment

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APA (6^th Edition):

Kunnamareddi, S. (2001). Programmable logic controller emulator enhancements to facilitate a distributed manufacturing simulation environment. (Masters Thesis). Ohio University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1173980723

Chicago Manual of Style (16^th Edition):

Kunnamareddi, Sadhishkumar. “Programmable logic controller emulator enhancements to facilitate a distributed manufacturing simulation environment.” 2001. Masters Thesis, Ohio University. Accessed February 28, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1173980723.

MLA Handbook (7^th Edition):

Kunnamareddi, Sadhishkumar. “Programmable logic controller emulator enhancements to facilitate a distributed manufacturing simulation environment.” 2001. Web. 28 Feb 2021.

Vancouver:

Kunnamareddi S. Programmable logic controller emulator enhancements to facilitate a distributed manufacturing simulation environment. [Internet] [Masters thesis]. Ohio University; 2001. [cited 2021 Feb 28]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1173980723.

Council of Science Editors:

Kunnamareddi S. Programmable logic controller emulator enhancements to facilitate a distributed manufacturing simulation environment. [Masters Thesis]. Ohio University; 2001. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1173980723

NSYSU

21. Huang, Shih-tung. Hardware/software co-verification for processor-OpenOCD integration.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715113-211836

► We usually use RVDS [18] (RealView Development Suite) and MUlTI-ICE (protocol converter) as ARM program debug environment by controlling ICE module for controlling CPU. But… (more)

Subjects/Keywords: OpenOCD (Open On-Chip Debugger); GNU Debugger; Co-verification; EICE (Embedded In-Circuit Emulator); JTAG

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APA (6^th Edition):

Huang, S. (2013). Hardware/software co-verification for processor-OpenOCD integration. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715113-211836

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Huang, Shih-tung. “Hardware/software co-verification for processor-OpenOCD integration.” 2013. Thesis, NSYSU. Accessed February 28, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715113-211836.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Huang, Shih-tung. “Hardware/software co-verification for processor-OpenOCD integration.” 2013. Web. 28 Feb 2021.

Vancouver:

Huang S. Hardware/software co-verification for processor-OpenOCD integration. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Feb 28]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715113-211836.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang S. Hardware/software co-verification for processor-OpenOCD integration. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715113-211836

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

22. Chen, Po-chou. Parameterized Hardware/Software modules for Embedded ICE.

Degree: Master, Computer Science and Engineering, 2005, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712105-114115

► The in-circuit emulator (ICE) is commonly adopted as a microprocessor debugging technique which features many advantages, such as low demand for hardware and repeatable use… (more)

▼ The in-circuit emulator (ICE) is commonly adopted as a microprocessor debugging technique which features many advantages, such as low demand for hardware and repeatable use of the pins on the JTAG port. The development of system-on-chip technology has matured significantly in recent years. The microprocessors in system-on-chip designs have been applied in a variety of ways, and different microprocessors are being used in the embedded system. The traditional modus operandi of debug control, in which an ad hoc hardware/software package is required for each microprocessor, is not economical as far as programming and designing are concerned. Thus it is advisable to design a more flexible debug control hardware/software package which can fit into different embedded microprocessors with in-circuit emulators. This thesis reviews several types of embedded in-circuit emulator structure and comes up with a parameterized, modularized hardware/software package for controlling in-circuit emulators. An initial analysis of microprocessor systems and embedded debug circuits helps us to elicit reusable parameters so that we can achieve our desired debug control by simply adjusting parameters when we work on different microprocessor architectures and embedded debug circuits. An ensuing examination of the reusability and functionality of our designed debug control hardware/software enables us to group all the functions of our hardware/software package into different functional modules so that we can simply replace relevant functional modules on different microprocessor architectures and embedded debug circuits. The parameterized design allows us to use a single debug control software program on different microprocessor systems with the slightest change of parameter setting. The modularized model has the merit of minimizing our effort of debug control through module replacement when we need to adapt our software to a new environment (as when we want to use it on a different operating system or when we want to apply it to a different communication interface). Advisors/Committee Members: Ing-Jer Huang (committee member), Chua-Chin Wang (chair), Shiann-Rong Kuang (chair), Alvin Wu (chair), Wei-Fen Lin (chair).

Subjects/Keywords: In-Circuit Emulator; Microprocessor; Parameterized; Debug

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APA (6^th Edition):

Chen, P. (2005). Parameterized Hardware/Software modules for Embedded ICE. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712105-114115

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chen, Po-chou. “Parameterized Hardware/Software modules for Embedded ICE.” 2005. Thesis, NSYSU. Accessed February 28, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712105-114115.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chen, Po-chou. “Parameterized Hardware/Software modules for Embedded ICE.” 2005. Web. 28 Feb 2021.

Vancouver:

Chen P. Parameterized Hardware/Software modules for Embedded ICE. [Internet] [Thesis]. NSYSU; 2005. [cited 2021 Feb 28]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712105-114115.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen P. Parameterized Hardware/Software modules for Embedded ICE. [Thesis]. NSYSU; 2005. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0712105-114115

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

23. Wu, Yen-cheng. A Neuron Emulator and Headstage Circuit for Patch Clamp Setups.

Degree: Master, Electrical Engineering, 2012, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0815112-163439

► This thesis presents a neuron emulator and headstage circuit for patch clamp setups and provides simulation, measurement and verification results. The circuit implemented on a… (more)

Subjects/Keywords: patch clamp; neuron emulator; headstage; single electrode; action potential; current clamp; voltage clamp

Record Details Similar Records Cite « Share

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Wu, Y. (2012). A Neuron Emulator and Headstage Circuit for Patch Clamp Setups. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0815112-163439

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wu, Yen-cheng. “A Neuron Emulator and Headstage Circuit for Patch Clamp Setups.” 2012. Thesis, NSYSU. Accessed February 28, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0815112-163439.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wu, Yen-cheng. “A Neuron Emulator and Headstage Circuit for Patch Clamp Setups.” 2012. Web. 28 Feb 2021.

Vancouver:

Wu Y. A Neuron Emulator and Headstage Circuit for Patch Clamp Setups. [Internet] [Thesis]. NSYSU; 2012. [cited 2021 Feb 28]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0815112-163439.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu Y. A Neuron Emulator and Headstage Circuit for Patch Clamp Setups. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0815112-163439

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

24. Lin, Tsung-Chen. Design and Verification of ARM10 ICE Co-Processor.

Degree: Master, Computer Science and Engineering, 2011, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811111-035510

► Embedded in circuit emulator (EICE) is the most common and widely used debugging techniques for microprocessors. Because the ICE is capable to provide diverse debugging… (more)

Subjects/Keywords: Coprocessor; Embedded in circuit emulator (EICE); Real-time system debug; Microprocessor; Static Debug

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lin, T. (2011). Design and Verification of ARM10 ICE Co-Processor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811111-035510

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lin, Tsung-Chen. “Design and Verification of ARM10 ICE Co-Processor.” 2011. Thesis, NSYSU. Accessed February 28, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811111-035510.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lin, Tsung-Chen. “Design and Verification of ARM10 ICE Co-Processor.” 2011. Web. 28 Feb 2021.

Vancouver:

Lin T. Design and Verification of ARM10 ICE Co-Processor. [Internet] [Thesis]. NSYSU; 2011. [cited 2021 Feb 28]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811111-035510.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin T. Design and Verification of ARM10 ICE Co-Processor. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811111-035510

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. Tekobon, Jerry. Système multi physique de simulation pour l'étude de la production de l'énergie basée sur le couplage éolien offshore-hydrolien : Multi-physical system of simulation for the study of energy production based on offshore wind and tidal power hybrid system.

Degree: Docteur es, Génie électrique, 2016, Le Havre

URL: http://www.theses.fr/2016LEHA0031

►

Les travaux de thèse concernent le développement d’une plateforme d’émulation temps réel destinée aux études théoriques et expérimentales des systèmes hybrides éolien- hydrolien. Diverses architectures… (more)

▼

Les travaux de thèse concernent le développement d’une plateforme d’émulation temps réel destinée aux études théoriques et expérimentales des systèmes hybrides éolien- hydrolien. Diverses architectures de couplages énergétiques sont traitées sur la base des similitudes fonctionnelles des deux systèmes et par des concepts d’émulation à la fois numériques et expérimentaux. La notion de simulation en temps « accéléré » a été développée. Le concept a été validé sur la plateforme expérimentale en utilisant l’évolution de la puissance moyenne délivrée par une turbine éolienne de petite puissance. Cette approche pourra permettre de réduire les temps d’observation des campagnes de mesure, d’accélérer les études sur le potentiel éolien des sites en développement. Nous avons développé également deux types de couplage du système hybride éolien-hydolien. Un couplage électrique basé sur la connexion en parallèle sur un bus continu des deux turbines. Nous avons développé un concept innovant d’un couplage électromécanique basé sur l’utilisation d’une seule génératrice asynchrone sur laquelle sont simultanément couplés les arbres de la turbine éolienne et de la turbine hydrolienne. Pour cela, un servomoteur à commande vectorielle nous a servi à émuler la turbine éolienne pendant qu’un moteur synchrone nous a servi d'émulateur de turbine hydrolienne. L’arbre de la génératrice sert de couplage mécanique entre les deux systèmes. Nous avons mis en évidence dans les expérimentations effectuées, la complémentarité des productions électriques des deux systèmes, et également le besoin de leur adjoindre un système de stockage pour palier à une baisse simultanée de deux productions d’énergie.

The thesis work concerns the development of a real-time emulation platform for theoretical and experimental studies of offshore wind and tidal power hybrid systems. Various energy coupling architectures are processed on the basis of the functional similarities of two systems and by both numerical and experimental emulation concepts. The notion of accelerated time used for real time simulation has been developed. The concept was validated on the experimental platform using the evolution of the mean power delivered by a small wind turbine. This approach can reduce the observation times of the measurement campaigns and could accelerate the studies for the wind potential of developing sites. We have also developed two types of coupling of the wind-tidal hybrid system. An electrical coupling based on the connection in parallel on a continuous bus of two turbines. We have developed an innovative concept of an electromechanical coupling based on the use of a single asynchronous generator on which the wind turbine and tidal turbine are simultaneously coupled. For this purpose, a vector-controlled servomotor was used to emulate the wind turbine while a synchronous motor was used as a tidal turbine emulator. The generator shaft is used as a mechanical coupling between the two systems. We have demonstrated in the experiments that we have developed the…

Advisors/Committee Members: Nichita, Cristian (thesis director).

Subjects/Keywords: Emulateur; Wind turbine; Tidal turbine; Hybrid system; Real time simulation; Emulator; Modelling; Offshore

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Tekobon, J. (2016). Système multi physique de simulation pour l'étude de la production de l'énergie basée sur le couplage éolien offshore-hydrolien : Multi-physical system of simulation for the study of energy production based on offshore wind and tidal power hybrid system. (Doctoral Dissertation). Le Havre. Retrieved from http://www.theses.fr/2016LEHA0031

Chicago Manual of Style (16^th Edition):

Tekobon, Jerry. “Système multi physique de simulation pour l'étude de la production de l'énergie basée sur le couplage éolien offshore-hydrolien : Multi-physical system of simulation for the study of energy production based on offshore wind and tidal power hybrid system.” 2016. Doctoral Dissertation, Le Havre. Accessed February 28, 2021. http://www.theses.fr/2016LEHA0031.

MLA Handbook (7^th Edition):

Tekobon, Jerry. “Système multi physique de simulation pour l'étude de la production de l'énergie basée sur le couplage éolien offshore-hydrolien : Multi-physical system of simulation for the study of energy production based on offshore wind and tidal power hybrid system.” 2016. Web. 28 Feb 2021.

Vancouver:

Tekobon J. Système multi physique de simulation pour l'étude de la production de l'énergie basée sur le couplage éolien offshore-hydrolien : Multi-physical system of simulation for the study of energy production based on offshore wind and tidal power hybrid system. [Internet] [Doctoral dissertation]. Le Havre; 2016. [cited 2021 Feb 28]. Available from: http://www.theses.fr/2016LEHA0031.

Council of Science Editors:

Tekobon J. Système multi physique de simulation pour l'étude de la production de l'énergie basée sur le couplage éolien offshore-hydrolien : Multi-physical system of simulation for the study of energy production based on offshore wind and tidal power hybrid system. [Doctoral Dissertation]. Le Havre; 2016. Available from: http://www.theses.fr/2016LEHA0031

Rochester Institute of Technology

26. Warner, Scott. Linux OS emulator and an application binary loader for a high performance microarchitecture simulator.

Degree: Computer Engineering, 2005, Rochester Institute of Technology

URL: https://scholarworks.rit.edu/theses/5503

► Simulation is a critical step in the development of state of the art microprocessors. Accurate simulation allows designers to confidently investigate various designs, while fast… (more)

▼ Simulation is a critical step in the development of state of the art microprocessors. Accurate simulation allows designers to confidently investigate various designs, while fast simulation times allow designers to thoroughly explore a design space. RITSim is an endeavor to create a high accuracy, high quality microarchitecture simulation infrastructure. This simulation infrastructure will be available for academic research in low power and high performance computer systems. The scope of this work is to provide a Linux OS Emulator, a Binary Application Loader, and a Linux kernel running in a virtual environment for the RITSim project. In order to evaluate standard software loads and benchmark suites on target microarchitectures simulators must provide support for operating system calls. This may be accomplished with various levels of accuracy. Many past simulators chose to sacrifice simulation accuracy to improve simulation time, while others sacrificed portability and execution time for high accuracy results. This work provides three key elements to the RITSim environment in an effort to create a simulation environment that seamlessly combines both approaches to provide a single integrated tool that allows researchers to choose the approach that is best suited to their needs. A first order simulation mode is provided that makes use of emulated system calls that are executed on the host computer?s operating system to provide quick simulation times. This mode also maintains a high level of portability since the host operating system is used to access the hardware. A high accuracy mode is also available that runs in a highly detailed simulated operating system. When running in the high accuracy mode the simulated operating system must be loaded into a virtual environment allowing the actual instructions of the operating system code to be simulated. Another key element is the binary application loader. This is required by the simulator to load executables into the simulator?s virtual memory space and to prepare it for execution. This involves not only mapping or copying the executable into simulated virtual memory, but also the creation and initialization of a new user mode stack and configuration of the simulated processor?s user mode registers. Advisors/Committee Members: Semeraro, Greg - Chair.

Subjects/Keywords: Binary loader; Emulator; Linux; Microarchitecture; Simulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Warner, S. (2005). Linux OS emulator and an application binary loader for a high performance microarchitecture simulator. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/5503

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Warner, Scott. “Linux OS emulator and an application binary loader for a high performance microarchitecture simulator.” 2005. Thesis, Rochester Institute of Technology. Accessed February 28, 2021. https://scholarworks.rit.edu/theses/5503.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Warner, Scott. “Linux OS emulator and an application binary loader for a high performance microarchitecture simulator.” 2005. Web. 28 Feb 2021.

Vancouver:

Warner S. Linux OS emulator and an application binary loader for a high performance microarchitecture simulator. [Internet] [Thesis]. Rochester Institute of Technology; 2005. [cited 2021 Feb 28]. Available from: https://scholarworks.rit.edu/theses/5503.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Warner S. Linux OS emulator and an application binary loader for a high performance microarchitecture simulator. [Thesis]. Rochester Institute of Technology; 2005. Available from: https://scholarworks.rit.edu/theses/5503

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

27. Πρίσκας, Θεόδωρος. Σχεδίαση ενός 8-bit μικροεπεξεργαστή (του μP 8085) σε VHDL και υλοποίηση σε FPGAs.

Degree: 2012, University of Patras

URL: http://hdl.handle.net/10889/5575

► Ο σκοπός της παρούσας Διπλωματικής Εργασίας είναι η μελέτη και η υλοποίηση ενός 8085 προσομοιωτή σε FPGAs με τη χρήση VHDL. H υλοποίηση έγινε με… (more)

▼ Ο σκοπός της παρούσας Διπλωματικής Εργασίας είναι η μελέτη και η υλοποίηση ενός 8085 προσομοιωτή σε FPGAs με τη χρήση VHDL. H υλοποίηση έγινε με την βοήθεια του περιβάλλοντος εξομοίωσης του Quartus v7.2 της ALTERA, με την χρήση της γλώσσας VHDL [8],[10].Η εργασία αυτή χωρίζεται σε 12 κεφάλαια: Στο πρώτο κεφάλαιο γίνεται αναφορά στο μικροεπεξεργαστή και στα τεχνικά του γνωρίσματα [1], [2], [4]. Στο δεύτερο κεφάλαιο γίνεται μια εκτενής αναφορά στη γλώσσα VHDL [3], [10]. Στο τρίτο κεφάλαιο παρουσιάζεται η αναπτυξιακή πλατφόρμα DE2 της εταιρίας ALTERA. Παρουσιάζονται αναλυτικά οι δυνατότητες και τα σχεδιαστικά χαρακτηριστικά της αναπτυξιακής κάρτας DE2 της ALTERA καθώς και τεχνική απεικόνισης video με τη χρήση FPGA [3], [9], [14]. Στο τέταρτο κεφάλαιο αναλύεται η λειτουργία του πρώτου μεγάλου τμήματος του μικροεπεξεργαστή, της ALU. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [5], [6], [12], [13]. Στο πέμπτο κεφάλαιο αναλύεται η λειτουργία του register file. Πρόκειται για το τμήμα των καταχωρητών, το οποίο είναι υπεύθυνο για την μεταφορά δεδομένων και την λειτουργία των διαύλων διευθύνσεων. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [5], [7], [11], [13], [14]. Στο έκτο κεφάλαιο αναλύεται η λειτουργία του τμήματος ελέγχου διακοπών. Πρόκειται για το τμήμα το οποίο εξυπηρετεί οποιαδήποτε αίτηση για διακοπή και το οποίο έχει οριστεί να είναι υπεύθυνο και για την σειριακή επικοινωνία. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [1], [12], [13]. Στο έβδομο κεφάλαιο γίνεται μια πρώτη απόπειρα σύνδεσης των τριών πρώτων μεγάλων τμημάτων του μικροεπεξεργαστή [12], [13]. Στο όγδοο κεφάλαιο αναλύεται η λειτουργία της control unit ως μονάδα ελέγχου και διαχείρισης των σημάτων ελέγχου του όλου κυκλώματος του μικροεπεξεργαστή. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [5], [7], [12], [13]. Στο ένατο κεφάλαιο παρουσιάζεται το κύκλωμα του μικροεπεξεργαστή μέσα από την σύνδεση των επιμέρους τμημάτων του. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [7], [12], [13]. Στο δέκατο κεφάλαιο παρουσιάζεται ο μικροπρογραμματισμός της microprogram ROM της control unit.… Advisors/Committee Members: Ζυγούρης, Ευάγγελος, Priskas, Theodoros, Ψυχαλίνος, Κωνσταντίνος, Μπακάλης, Δημήτριος.

Subjects/Keywords: Προσομοιωτής 8085; Μικροεπεξεργαστές; 004.16; 8085 emulator; Microprocessors; VHDL (VHSIC hardware description language); Quartus

Record Details Similar Records Cite « Share

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Πρίσκας, �. (2012). Σχεδίαση ενός 8-bit μικροεπεξεργαστή (του μP 8085) σε VHDL και υλοποίηση σε FPGAs. (Masters Thesis). University of Patras. Retrieved from http://hdl.handle.net/10889/5575

Chicago Manual of Style (16^th Edition):

Πρίσκας, Θεόδωρος. “Σχεδίαση ενός 8-bit μικροεπεξεργαστή (του μP 8085) σε VHDL και υλοποίηση σε FPGAs.” 2012. Masters Thesis, University of Patras. Accessed February 28, 2021. http://hdl.handle.net/10889/5575.

MLA Handbook (7^th Edition):

Πρίσκας, Θεόδωρος. “Σχεδίαση ενός 8-bit μικροεπεξεργαστή (του μP 8085) σε VHDL και υλοποίηση σε FPGAs.” 2012. Web. 28 Feb 2021.

Vancouver:

Πρίσκας �. Σχεδίαση ενός 8-bit μικροεπεξεργαστή (του μP 8085) σε VHDL και υλοποίηση σε FPGAs. [Internet] [Masters thesis]. University of Patras; 2012. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/10889/5575.

Council of Science Editors:

Πρίσκας �. Σχεδίαση ενός 8-bit μικροεπεξεργαστή (του μP 8085) σε VHDL και υλοποίηση σε FPGAs. [Masters Thesis]. University of Patras; 2012. Available from: http://hdl.handle.net/10889/5575

University of Saskatchewan

28. Fontaine, Andy. Digital implementation of an upstream DOCSIS QAM modulator and channel emulator.

Degree: 2014, University of Saskatchewan

URL: http://hdl.handle.net/10388/ETD-2015-06-1783

► The concept of cable television, originally called community antenna television (CATV), began in the 1940's. The information and services provided by cable operators have changed… (more)

▼ The concept of cable television, originally called community antenna television (CATV), began in the 1940's. The information and services provided by cable operators have changed drastically since the early days. Cable service providers are no longer simply providing their customers with broadcast television but are providing a multi-purpose, two-way link to the digital world. Custom programming, telephone service, radio, and high-speed internet access are just a few of the services offered by cable service providers in the 21st century. At the dawn of the internet the dominant mode of access was through telephone lines. Despite advances in dial-up modem technology, the telephone system was unable to keep pace with the demand for data throughput. In the late 1990's an industry consortium known as Cable Television Laboratories, Inc. developed a standard protocol for providing high-speed internet access through the existing CATV infrastructure. This protocol is known as Data Over Cable Service Interface Specification (DOCSIS) and it helped to usher in the era of the information superhighway. CATV systems use different parts of the radio frequency (RF) spectrum for communication to and from the user. The downstream portion (data destined for the user) consumes the bulk of the spectrum and is located at relatively high frequencies. The upstream portion (data destined to the network from the user) of the spectrum is smaller and located at the low end of the spectrum. This lower frequency region of the RF spectrum is particularly prone to impairments such as micro-reflections, which can be viewed as a type of multipath interference. Upstream data transfer in the presence of these impairments is therefore problematic and requires complex signal correction algorithms to be employed in the receiver. The quality of a receiver is largely determined by how well it mitigates the signal impairments introduced by the channel. For this reason, engineers developing a receiver require a piece of equipment that can emulate the channel impairments in any permutation in order to test their receiver. The conventional test methodology uses a hardware RF channel emulator connected between the transmitter and the receiver under test. This method not only requires an expensive RF channel emulator, but a functioning analog front-end as well. Of these two problems, the expense of the hardware emulator is likely less important than the delay in development caused by waiting for a functional analog front-end. Receiver design is an iterative, time consuming process that requires the receiver's digital signal processing (DSP) algorithms be tested as early as possible to reduce the time-to-market. This thesis presents a digital implementation of a DOCSIS-compliant channel emulator whereby cable micro-reflections and thermal noise at the analog front-end of the receiver are modelled digitally at baseband. The channel emulator and the modulator are integrated into a single hardware structure to produce a compact circuit that, during receiver… Advisors/Committee Members: Johanson, Robert, Wahid, Khan, Hussey, Glenn.

Subjects/Keywords: DOCSIS; QAM; CATV; channel emulator; hardware; implementation; FPGA; DSP; micro-reflections; AWGN

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Fontaine, A. (2014). Digital implementation of an upstream DOCSIS QAM modulator and channel emulator. (Thesis). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/ETD-2015-06-1783

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Fontaine, Andy. “Digital implementation of an upstream DOCSIS QAM modulator and channel emulator.” 2014. Thesis, University of Saskatchewan. Accessed February 28, 2021. http://hdl.handle.net/10388/ETD-2015-06-1783.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Fontaine, Andy. “Digital implementation of an upstream DOCSIS QAM modulator and channel emulator.” 2014. Web. 28 Feb 2021.

Vancouver:

Fontaine A. Digital implementation of an upstream DOCSIS QAM modulator and channel emulator. [Internet] [Thesis]. University of Saskatchewan; 2014. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/10388/ETD-2015-06-1783.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fontaine A. Digital implementation of an upstream DOCSIS QAM modulator and channel emulator. [Thesis]. University of Saskatchewan; 2014. Available from: http://hdl.handle.net/10388/ETD-2015-06-1783

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Brno University of Technology

29. Vilímek, Hynek. Emulátor herní konzole GameBoy Advance pro mobilní platformy: GameBoy Advance Emulator for Mobile Platforms.

Degree: 2020, Brno University of Technology

URL: http://hdl.handle.net/11012/189714

► The GameBoy Advance console was released by Nintendo in 2001 and it has experienced phenomenal success during its existence. It used to control the majority… (more)

Subjects/Keywords: Herní konzole; GameBoy Advance; emulátor; procesor ARM7TDMI; Gaming console; GameBoy Advance; emulator; processor ARM7TDMI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Vilímek, H. (2020). Emulátor herní konzole GameBoy Advance pro mobilní platformy: GameBoy Advance Emulator for Mobile Platforms. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/189714

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Vilímek, Hynek. “Emulátor herní konzole GameBoy Advance pro mobilní platformy: GameBoy Advance Emulator for Mobile Platforms.” 2020. Thesis, Brno University of Technology. Accessed February 28, 2021. http://hdl.handle.net/11012/189714.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Vilímek, Hynek. “Emulátor herní konzole GameBoy Advance pro mobilní platformy: GameBoy Advance Emulator for Mobile Platforms.” 2020. Web. 28 Feb 2021.

Vancouver:

Vilímek H. Emulátor herní konzole GameBoy Advance pro mobilní platformy: GameBoy Advance Emulator for Mobile Platforms. [Internet] [Thesis]. Brno University of Technology; 2020. [cited 2021 Feb 28]. Available from: http://hdl.handle.net/11012/189714.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vilímek H. Emulátor herní konzole GameBoy Advance pro mobilní platformy: GameBoy Advance Emulator for Mobile Platforms. [Thesis]. Brno University of Technology; 2020. Available from: http://hdl.handle.net/11012/189714

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

30. Guniganti, Ramesh Goud. A Comparison of RTMP and HTTP Protocols with respect to Packet Loss and Delay Variation based on QoE.

Degree: 2013, , School of Computing

URL: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5394

► In recent year’s multimedia services like Video-on-Demand (VoD) and mobile video streaming, videos for e-learning, video conferencing are growing predominantly, and the user’s expectations… (more)

Subjects/Keywords: HTTP; Mean Opinion Score; Quality of Experience; RTMP; Subjective Assessment; Network Emulator.

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❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Guniganti, R. G. (2013). A Comparison of RTMP and HTTP Protocols with respect to Packet Loss and Delay Variation based on QoE. (Thesis). , School of Computing. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5394

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Guniganti, Ramesh Goud. “A Comparison of RTMP and HTTP Protocols with respect to Packet Loss and Delay Variation based on QoE.” 2013. Thesis, , School of Computing. Accessed February 28, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5394.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Guniganti, Ramesh Goud. “A Comparison of RTMP and HTTP Protocols with respect to Packet Loss and Delay Variation based on QoE.” 2013. Web. 28 Feb 2021.

Vancouver:

Guniganti RG. A Comparison of RTMP and HTTP Protocols with respect to Packet Loss and Delay Variation based on QoE. [Internet] [Thesis]. , School of Computing; 2013. [cited 2021 Feb 28]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5394.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Guniganti RG. A Comparison of RTMP and HTTP Protocols with respect to Packet Loss and Delay Variation based on QoE. [Thesis]. , School of Computing; 2013. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5394

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Open Access Theses and Dissertations