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You searched for subject:(Embedded processor). Showing records 1 – 30 of 68 total matches.

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University of Limerick

1. Heffernan, Donal. Investigation and development of energy saving techniques for modern x86 platforms: with a special emphasis on embedded environments.

Degree: Electronic & Computer Engineering, 2010, University of Limerick

non-peer-reviewed

In recent times there is a growing emphasis on energy saving solutions for processor-based systems of all types, and there is a particular emphasis… (more)

Subjects/Keywords: embedded systems; processor based systems

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APA (6th Edition):

Heffernan, D. (2010). Investigation and development of energy saving techniques for modern x86 platforms: with a special emphasis on embedded environments. (Thesis). University of Limerick. Retrieved from http://hdl.handle.net/10344/440

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Heffernan, Donal. “Investigation and development of energy saving techniques for modern x86 platforms: with a special emphasis on embedded environments.” 2010. Thesis, University of Limerick. Accessed November 18, 2019. http://hdl.handle.net/10344/440.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Heffernan, Donal. “Investigation and development of energy saving techniques for modern x86 platforms: with a special emphasis on embedded environments.” 2010. Web. 18 Nov 2019.

Vancouver:

Heffernan D. Investigation and development of energy saving techniques for modern x86 platforms: with a special emphasis on embedded environments. [Internet] [Thesis]. University of Limerick; 2010. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/10344/440.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Heffernan D. Investigation and development of energy saving techniques for modern x86 platforms: with a special emphasis on embedded environments. [Thesis]. University of Limerick; 2010. Available from: http://hdl.handle.net/10344/440

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University College Cork

2. Zeinolabedini, Nasim. Average-case analysis of power consumption in embedded systems.

Degree: 2015, University College Cork

 Power efficiency is one of the most important constraints in the design of embedded systems since such systems are generally driven by batteries with limited… (more)

Subjects/Keywords: Embedded systems; Processor power estimation

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APA (6th Edition):

Zeinolabedini, N. (2015). Average-case analysis of power consumption in embedded systems. (Thesis). University College Cork. Retrieved from http://hdl.handle.net/10468/3375

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zeinolabedini, Nasim. “Average-case analysis of power consumption in embedded systems.” 2015. Thesis, University College Cork. Accessed November 18, 2019. http://hdl.handle.net/10468/3375.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zeinolabedini, Nasim. “Average-case analysis of power consumption in embedded systems.” 2015. Web. 18 Nov 2019.

Vancouver:

Zeinolabedini N. Average-case analysis of power consumption in embedded systems. [Internet] [Thesis]. University College Cork; 2015. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/10468/3375.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zeinolabedini N. Average-case analysis of power consumption in embedded systems. [Thesis]. University College Cork; 2015. Available from: http://hdl.handle.net/10468/3375

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Kent State University

3. Batcher, Kenneth William. Cache Miss Reduction Techniques for Embedded CPU Instruction Caches.

Degree: PhD, College of Arts and Sciences / Department of Computer Science, 2008, Kent State University

  Modern embedded systems are usually implemented by integrated circuits that contain commercial microprocessor cores with internal instruction and data caches. Such systems are powerful… (more)

Subjects/Keywords: Computer Science; Instruction Caches; Embedded; CPU; Real-Time; Interrupts; Processor Performance

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APA (6th Edition):

Batcher, K. W. (2008). Cache Miss Reduction Techniques for Embedded CPU Instruction Caches. (Doctoral Dissertation). Kent State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=kent1208966274

Chicago Manual of Style (16th Edition):

Batcher, Kenneth William. “Cache Miss Reduction Techniques for Embedded CPU Instruction Caches.” 2008. Doctoral Dissertation, Kent State University. Accessed November 18, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=kent1208966274.

MLA Handbook (7th Edition):

Batcher, Kenneth William. “Cache Miss Reduction Techniques for Embedded CPU Instruction Caches.” 2008. Web. 18 Nov 2019.

Vancouver:

Batcher KW. Cache Miss Reduction Techniques for Embedded CPU Instruction Caches. [Internet] [Doctoral dissertation]. Kent State University; 2008. [cited 2019 Nov 18]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=kent1208966274.

Council of Science Editors:

Batcher KW. Cache Miss Reduction Techniques for Embedded CPU Instruction Caches. [Doctoral Dissertation]. Kent State University; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=kent1208966274

4. Hicks, M. Energy Efficient Branch Prediction .

Degree: 2010, University of Hertfordshire

 Energy efficiency is of the utmost importance in modern high-performance embedded processor design. As the number of transistors on a chip continues to increase each… (more)

Subjects/Keywords: energy efficient; branch prediction; high performance embedded processor design

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APA (6th Edition):

Hicks, M. (2010). Energy Efficient Branch Prediction . (Thesis). University of Hertfordshire. Retrieved from http://hdl.handle.net/2299/4613

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hicks, M. “Energy Efficient Branch Prediction .” 2010. Thesis, University of Hertfordshire. Accessed November 18, 2019. http://hdl.handle.net/2299/4613.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hicks, M. “Energy Efficient Branch Prediction .” 2010. Web. 18 Nov 2019.

Vancouver:

Hicks M. Energy Efficient Branch Prediction . [Internet] [Thesis]. University of Hertfordshire; 2010. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/2299/4613.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hicks M. Energy Efficient Branch Prediction . [Thesis]. University of Hertfordshire; 2010. Available from: http://hdl.handle.net/2299/4613

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universitat Politècnica de Catalunya

5. Paolieri, Marco. A Multi-core processor for hard real-time systems.

Degree: Departament d'Arquitectura de Computadors, 2011, Universitat Politècnica de Catalunya

 La creciente demanda de nuevas funcionalidades en los sistemas empotrados de tiempo real actuales y futuros en industrias como la automovilística y la de aviación,… (more)

Subjects/Keywords: Real-time; Multi-core; Processor; Embedded systems; Woet; 004

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APA (6th Edition):

Paolieri, M. (2011). A Multi-core processor for hard real-time systems. (Thesis). Universitat Politècnica de Catalunya. Retrieved from http://hdl.handle.net/10803/51578

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Paolieri, Marco. “A Multi-core processor for hard real-time systems.” 2011. Thesis, Universitat Politècnica de Catalunya. Accessed November 18, 2019. http://hdl.handle.net/10803/51578.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Paolieri, Marco. “A Multi-core processor for hard real-time systems.” 2011. Web. 18 Nov 2019.

Vancouver:

Paolieri M. A Multi-core processor for hard real-time systems. [Internet] [Thesis]. Universitat Politècnica de Catalunya; 2011. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/10803/51578.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Paolieri M. A Multi-core processor for hard real-time systems. [Thesis]. Universitat Politècnica de Catalunya; 2011. Available from: http://hdl.handle.net/10803/51578

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

6. Rathore, Uneeb Yaqub. Next Generation Dynamically Reconfigurable DSP in 16nm Technology.

Degree: Electrical Engineering, 2018, UCLA

 An increasing number of dedicated accelerators in modern System on Chips (SoCs) have led to large regions of dark silicon. Although highly efficient, these accelerators… (more)

Subjects/Keywords: Electrical engineering; Circuits and Embedded Systems; UDSP; Universal Digital Signal Processor

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APA (6th Edition):

Rathore, U. Y. (2018). Next Generation Dynamically Reconfigurable DSP in 16nm Technology. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/04h8p0x9

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rathore, Uneeb Yaqub. “Next Generation Dynamically Reconfigurable DSP in 16nm Technology.” 2018. Thesis, UCLA. Accessed November 18, 2019. http://www.escholarship.org/uc/item/04h8p0x9.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rathore, Uneeb Yaqub. “Next Generation Dynamically Reconfigurable DSP in 16nm Technology.” 2018. Web. 18 Nov 2019.

Vancouver:

Rathore UY. Next Generation Dynamically Reconfigurable DSP in 16nm Technology. [Internet] [Thesis]. UCLA; 2018. [cited 2019 Nov 18]. Available from: http://www.escholarship.org/uc/item/04h8p0x9.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rathore UY. Next Generation Dynamically Reconfigurable DSP in 16nm Technology. [Thesis]. UCLA; 2018. Available from: http://www.escholarship.org/uc/item/04h8p0x9

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

7. De Zeeuw, M. Interfacing the ƿ-VEX with the µBlaze processor:.

Degree: 2011, Delft University of Technology

 Developments in reconfigurable platforms result in constantly increasing available area and improving technology. These improvements allow embedded systems to implement increasingly complicated systems. As a… (more)

Subjects/Keywords: VLIW; soft-core processor; MicroBlaze; hybride; Embedded Systems

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APA (6th Edition):

De Zeeuw, M. (2011). Interfacing the ƿ-VEX with the µBlaze processor:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:52874750-4eab-4974-8a42-8da5b700adff

Chicago Manual of Style (16th Edition):

De Zeeuw, M. “Interfacing the ƿ-VEX with the µBlaze processor:.” 2011. Masters Thesis, Delft University of Technology. Accessed November 18, 2019. http://resolver.tudelft.nl/uuid:52874750-4eab-4974-8a42-8da5b700adff.

MLA Handbook (7th Edition):

De Zeeuw, M. “Interfacing the ƿ-VEX with the µBlaze processor:.” 2011. Web. 18 Nov 2019.

Vancouver:

De Zeeuw M. Interfacing the ƿ-VEX with the µBlaze processor:. [Internet] [Masters thesis]. Delft University of Technology; 2011. [cited 2019 Nov 18]. Available from: http://resolver.tudelft.nl/uuid:52874750-4eab-4974-8a42-8da5b700adff.

Council of Science Editors:

De Zeeuw M. Interfacing the ƿ-VEX with the µBlaze processor:. [Masters Thesis]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:52874750-4eab-4974-8a42-8da5b700adff


Virginia Commonwealth University

8. Obeidat, Fadi. Embedded Processor Selection/Performance Estimation using FPGA-based Profiling.

Degree: PhD, Engineering, 2010, Virginia Commonwealth University

 In embedded systems, modeling the performance of the candidate processor architectures is very important to enable the designer to estimate the capability of each architecture… (more)

Subjects/Keywords: Embedded Sysytems; Performance Modeling; FPGA-based Profiling; Processor Selection; Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Obeidat, F. (2010). Embedded Processor Selection/Performance Estimation using FPGA-based Profiling. (Doctoral Dissertation). Virginia Commonwealth University. Retrieved from https://scholarscompass.vcu.edu/etd/2232

Chicago Manual of Style (16th Edition):

Obeidat, Fadi. “Embedded Processor Selection/Performance Estimation using FPGA-based Profiling.” 2010. Doctoral Dissertation, Virginia Commonwealth University. Accessed November 18, 2019. https://scholarscompass.vcu.edu/etd/2232.

MLA Handbook (7th Edition):

Obeidat, Fadi. “Embedded Processor Selection/Performance Estimation using FPGA-based Profiling.” 2010. Web. 18 Nov 2019.

Vancouver:

Obeidat F. Embedded Processor Selection/Performance Estimation using FPGA-based Profiling. [Internet] [Doctoral dissertation]. Virginia Commonwealth University; 2010. [cited 2019 Nov 18]. Available from: https://scholarscompass.vcu.edu/etd/2232.

Council of Science Editors:

Obeidat F. Embedded Processor Selection/Performance Estimation using FPGA-based Profiling. [Doctoral Dissertation]. Virginia Commonwealth University; 2010. Available from: https://scholarscompass.vcu.edu/etd/2232


University of New South Wales

9. Hong, Mei. Memory Data Protection for Single-Processor Based Embedded Systems.

Degree: Computer Science & Engineering, 2013, University of New South Wales

Embedded systems are ubiquitous and widely used in a large spectrum of applications. Sensitive and security critical information is stored and processed in embedded devices,… (more)

Subjects/Keywords: Security; Single-Processor Based Embedded Systems; Memory Protection

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APA (6th Edition):

Hong, M. (2013). Memory Data Protection for Single-Processor Based Embedded Systems. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/52534 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:11207/SOURCE01?view=true

Chicago Manual of Style (16th Edition):

Hong, Mei. “Memory Data Protection for Single-Processor Based Embedded Systems.” 2013. Doctoral Dissertation, University of New South Wales. Accessed November 18, 2019. http://handle.unsw.edu.au/1959.4/52534 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:11207/SOURCE01?view=true.

MLA Handbook (7th Edition):

Hong, Mei. “Memory Data Protection for Single-Processor Based Embedded Systems.” 2013. Web. 18 Nov 2019.

Vancouver:

Hong M. Memory Data Protection for Single-Processor Based Embedded Systems. [Internet] [Doctoral dissertation]. University of New South Wales; 2013. [cited 2019 Nov 18]. Available from: http://handle.unsw.edu.au/1959.4/52534 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:11207/SOURCE01?view=true.

Council of Science Editors:

Hong M. Memory Data Protection for Single-Processor Based Embedded Systems. [Doctoral Dissertation]. University of New South Wales; 2013. Available from: http://handle.unsw.edu.au/1959.4/52534 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:11207/SOURCE01?view=true


University of New South Wales

10. Su, Xuesong. WCET-aware compilation techniques for clustered VLIW processors.

Degree: Computer Science & Engineering, 2018, University of New South Wales

 In real-time systems, it is crucial to guarantee that all the timing constraints are met at design stage. The WCET of each task has a… (more)

Subjects/Keywords: Embedded system; Worst-case execution time; Clustered VLIW processor

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APA (6th Edition):

Su, X. (2018). WCET-aware compilation techniques for clustered VLIW processors. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/61864 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:57802/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Su, Xuesong. “WCET-aware compilation techniques for clustered VLIW processors.” 2018. Doctoral Dissertation, University of New South Wales. Accessed November 18, 2019. http://handle.unsw.edu.au/1959.4/61864 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:57802/SOURCE02?view=true.

MLA Handbook (7th Edition):

Su, Xuesong. “WCET-aware compilation techniques for clustered VLIW processors.” 2018. Web. 18 Nov 2019.

Vancouver:

Su X. WCET-aware compilation techniques for clustered VLIW processors. [Internet] [Doctoral dissertation]. University of New South Wales; 2018. [cited 2019 Nov 18]. Available from: http://handle.unsw.edu.au/1959.4/61864 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:57802/SOURCE02?view=true.

Council of Science Editors:

Su X. WCET-aware compilation techniques for clustered VLIW processors. [Doctoral Dissertation]. University of New South Wales; 2018. Available from: http://handle.unsw.edu.au/1959.4/61864 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:57802/SOURCE02?view=true


Rochester Institute of Technology

11. Verma, Rajeev. Efficient Implementations of Pairing-Based Cryptography on Embedded Systems.

Degree: MS, Computer Engineering, 2015, Rochester Institute of Technology

  Many cryptographic applications use bilinear pairing such as identity based signature, instance identity-based key agreement, searchable public-key encryption, short signature scheme, certificate less encryption… (more)

Subjects/Keywords: Aarch32; ARM processor; Barreto-Naehrig curves; Cryptography; Embedded systems; Pairing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Verma, R. (2015). Efficient Implementations of Pairing-Based Cryptography on Embedded Systems. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/8926

Chicago Manual of Style (16th Edition):

Verma, Rajeev. “Efficient Implementations of Pairing-Based Cryptography on Embedded Systems.” 2015. Masters Thesis, Rochester Institute of Technology. Accessed November 18, 2019. https://scholarworks.rit.edu/theses/8926.

MLA Handbook (7th Edition):

Verma, Rajeev. “Efficient Implementations of Pairing-Based Cryptography on Embedded Systems.” 2015. Web. 18 Nov 2019.

Vancouver:

Verma R. Efficient Implementations of Pairing-Based Cryptography on Embedded Systems. [Internet] [Masters thesis]. Rochester Institute of Technology; 2015. [cited 2019 Nov 18]. Available from: https://scholarworks.rit.edu/theses/8926.

Council of Science Editors:

Verma R. Efficient Implementations of Pairing-Based Cryptography on Embedded Systems. [Masters Thesis]. Rochester Institute of Technology; 2015. Available from: https://scholarworks.rit.edu/theses/8926

12. Fahmi, Youssef. Contribution à l’optimisation de densité de code pour Processeur Embarqué : Contribution to the optimization of Embedded processor code density.

Degree: Docteur es, STIC (sciences et technologies de l'information et de la communication) - Cergy, 2013, Cergy-Pontoise

Les systèmes embarqués prennent une place de plus en plus grande dans le marché actuelavec des dispositifs basée sur des systèmes on-chip. Ces systèmes embarqués… (more)

Subjects/Keywords: Processeur; Embarqué; Gnu; Compression; Processor; Embedded; Gnu; Compression

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fahmi, Y. (2013). Contribution à l’optimisation de densité de code pour Processeur Embarqué : Contribution to the optimization of Embedded processor code density. (Doctoral Dissertation). Cergy-Pontoise. Retrieved from http://www.theses.fr/2013CERG0630

Chicago Manual of Style (16th Edition):

Fahmi, Youssef. “Contribution à l’optimisation de densité de code pour Processeur Embarqué : Contribution to the optimization of Embedded processor code density.” 2013. Doctoral Dissertation, Cergy-Pontoise. Accessed November 18, 2019. http://www.theses.fr/2013CERG0630.

MLA Handbook (7th Edition):

Fahmi, Youssef. “Contribution à l’optimisation de densité de code pour Processeur Embarqué : Contribution to the optimization of Embedded processor code density.” 2013. Web. 18 Nov 2019.

Vancouver:

Fahmi Y. Contribution à l’optimisation de densité de code pour Processeur Embarqué : Contribution to the optimization of Embedded processor code density. [Internet] [Doctoral dissertation]. Cergy-Pontoise; 2013. [cited 2019 Nov 18]. Available from: http://www.theses.fr/2013CERG0630.

Council of Science Editors:

Fahmi Y. Contribution à l’optimisation de densité de code pour Processeur Embarqué : Contribution to the optimization of Embedded processor code density. [Doctoral Dissertation]. Cergy-Pontoise; 2013. Available from: http://www.theses.fr/2013CERG0630

13. Senni, Sophiane. Exploration of non-volatile magnetic memory for processor architecture : Exploration d'architecture de processeur à technologie mémoire non volatile MRAM.

Degree: Docteur es, Systèmes automatiques et micro-électroniques, 2015, Montpellier

De par la réduction continuelle des dimensions du transistor CMOS, concevoir des systèmes sur puce (SoC) à la fois très denses et énergétiquement efficients devient… (more)

Subjects/Keywords: Mram; Processeur embarqué; Memory hierarchy; Mram; Embedded processor; Memory hierarchy

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APA (6th Edition):

Senni, S. (2015). Exploration of non-volatile magnetic memory for processor architecture : Exploration d'architecture de processeur à technologie mémoire non volatile MRAM. (Doctoral Dissertation). Montpellier. Retrieved from http://www.theses.fr/2015MONTS264

Chicago Manual of Style (16th Edition):

Senni, Sophiane. “Exploration of non-volatile magnetic memory for processor architecture : Exploration d'architecture de processeur à technologie mémoire non volatile MRAM.” 2015. Doctoral Dissertation, Montpellier. Accessed November 18, 2019. http://www.theses.fr/2015MONTS264.

MLA Handbook (7th Edition):

Senni, Sophiane. “Exploration of non-volatile magnetic memory for processor architecture : Exploration d'architecture de processeur à technologie mémoire non volatile MRAM.” 2015. Web. 18 Nov 2019.

Vancouver:

Senni S. Exploration of non-volatile magnetic memory for processor architecture : Exploration d'architecture de processeur à technologie mémoire non volatile MRAM. [Internet] [Doctoral dissertation]. Montpellier; 2015. [cited 2019 Nov 18]. Available from: http://www.theses.fr/2015MONTS264.

Council of Science Editors:

Senni S. Exploration of non-volatile magnetic memory for processor architecture : Exploration d'architecture de processeur à technologie mémoire non volatile MRAM. [Doctoral Dissertation]. Montpellier; 2015. Available from: http://www.theses.fr/2015MONTS264


Universidade do Rio Grande do Sul

14. Barcelos, Daniel. Modelo de migração de tarefas para MPSoCs baseados em redes-em-chip.

Degree: 2008, Universidade do Rio Grande do Sul

Em relação a sistemas multiprocessados integrados em uma única pastilha (MPSoC), tanto a alocação dinâmica quanto a migração de tarefas são áreas de pesquisa recentes… (more)

Subjects/Keywords: Task migration; Microeletrônica; Embedded systems; Network-on-chip; Multi-processor systems; Distributed systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Barcelos, D. (2008). Modelo de migração de tarefas para MPSoCs baseados em redes-em-chip. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/14783

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Barcelos, Daniel. “Modelo de migração de tarefas para MPSoCs baseados em redes-em-chip.” 2008. Thesis, Universidade do Rio Grande do Sul. Accessed November 18, 2019. http://hdl.handle.net/10183/14783.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Barcelos, Daniel. “Modelo de migração de tarefas para MPSoCs baseados em redes-em-chip.” 2008. Web. 18 Nov 2019.

Vancouver:

Barcelos D. Modelo de migração de tarefas para MPSoCs baseados em redes-em-chip. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2008. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/10183/14783.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Barcelos D. Modelo de migração de tarefas para MPSoCs baseados em redes-em-chip. [Thesis]. Universidade do Rio Grande do Sul; 2008. Available from: http://hdl.handle.net/10183/14783

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Halmstad University

15. Kågesson, Filip. Resource Optimization of MPSoC for Industrial Use-cases.

Degree: Information Technology, 2019, Halmstad University

Today’s embedded systems require more and more performance but they are still required to meet power constraints. Single processor systems can deliver high performance… (more)

Subjects/Keywords: MPSoC; inter-processor communication; message passing; Computer Systems; Datorsystem; Embedded Systems; Inbäddad systemteknik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kågesson, F. (2019). Resource Optimization of MPSoC for Industrial Use-cases. (Thesis). Halmstad University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-39729

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kågesson, Filip. “Resource Optimization of MPSoC for Industrial Use-cases.” 2019. Thesis, Halmstad University. Accessed November 18, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-39729.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kågesson, Filip. “Resource Optimization of MPSoC for Industrial Use-cases.” 2019. Web. 18 Nov 2019.

Vancouver:

Kågesson F. Resource Optimization of MPSoC for Industrial Use-cases. [Internet] [Thesis]. Halmstad University; 2019. [cited 2019 Nov 18]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-39729.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kågesson F. Resource Optimization of MPSoC for Industrial Use-cases. [Thesis]. Halmstad University; 2019. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-39729

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

16. Zhou, Wenjia. A lightweight DSP framework for OMAP3530-driven embedded devices.

Degree: MS, 1200, 2015, University of Illinois – Urbana-Champaign

 This thesis provides a lightweight framework, called MiniDSP, for OMAP3530 heterogeneous dual core SoC to run tasks on its DSP co-processor. This framework is composed… (more)

Subjects/Keywords: Digital signal processor (DSP); Embedded system; Multi-core system on chip (SoC); Device driver

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhou, W. (2015). A lightweight DSP framework for OMAP3530-driven embedded devices. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/73020

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhou, Wenjia. “A lightweight DSP framework for OMAP3530-driven embedded devices.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed November 18, 2019. http://hdl.handle.net/2142/73020.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhou, Wenjia. “A lightweight DSP framework for OMAP3530-driven embedded devices.” 2015. Web. 18 Nov 2019.

Vancouver:

Zhou W. A lightweight DSP framework for OMAP3530-driven embedded devices. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/2142/73020.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhou W. A lightweight DSP framework for OMAP3530-driven embedded devices. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/73020

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Pereira, Erinaldo da Silva. Projeto de um processador open source em Bluespec baseado no processador soft-core Nios II da Altera.

Degree: Mestrado, Ciências de Computação e Matemática Computacional, 2014, University of São Paulo

Este trabalho apresenta o desenvolvimento de um processador open source baseado no processador Nios II da Altera. O processador desenvolvido permite a customização de instruções,… (more)

Subjects/Keywords: Bluespec; Bluespec; Computação reconfigurável; Embedded systems; FPGA; FPGA; Processador soft-core; Reconfigurable computing; Sistemas embarcados; Soft-core processor

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APA (6th Edition):

Pereira, E. d. S. (2014). Projeto de um processador open source em Bluespec baseado no processador soft-core Nios II da Altera. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/55/55134/tde-25092014-094648/ ;

Chicago Manual of Style (16th Edition):

Pereira, Erinaldo da Silva. “Projeto de um processador open source em Bluespec baseado no processador soft-core Nios II da Altera.” 2014. Masters Thesis, University of São Paulo. Accessed November 18, 2019. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-25092014-094648/ ;.

MLA Handbook (7th Edition):

Pereira, Erinaldo da Silva. “Projeto de um processador open source em Bluespec baseado no processador soft-core Nios II da Altera.” 2014. Web. 18 Nov 2019.

Vancouver:

Pereira EdS. Projeto de um processador open source em Bluespec baseado no processador soft-core Nios II da Altera. [Internet] [Masters thesis]. University of São Paulo; 2014. [cited 2019 Nov 18]. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-25092014-094648/ ;.

Council of Science Editors:

Pereira EdS. Projeto de um processador open source em Bluespec baseado no processador soft-core Nios II da Altera. [Masters Thesis]. University of São Paulo; 2014. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-25092014-094648/ ;


Universidade do Rio Grande do Sul

18. Casagrande, Luiz Gustavo. Soft error analysis with and without operating system.

Degree: 2016, Universidade do Rio Grande do Sul

The complexity of integrated system on-chips as well as commercial processor’s architecture has increased dramatically in recent years. Thus, the effort for assessing the susceptibility… (more)

Subjects/Keywords: Open virtual platform (OVP); Microeletrônica; Sistemas operacionais; Soft error; ARM cortex-A9; Injecao : Falhas; Bare metal; Linux operating system; Embedded processor

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APA (6th Edition):

Casagrande, L. G. (2016). Soft error analysis with and without operating system. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/149633

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Casagrande, Luiz Gustavo. “Soft error analysis with and without operating system.” 2016. Thesis, Universidade do Rio Grande do Sul. Accessed November 18, 2019. http://hdl.handle.net/10183/149633.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Casagrande, Luiz Gustavo. “Soft error analysis with and without operating system.” 2016. Web. 18 Nov 2019.

Vancouver:

Casagrande LG. Soft error analysis with and without operating system. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2016. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/10183/149633.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Casagrande LG. Soft error analysis with and without operating system. [Thesis]. Universidade do Rio Grande do Sul; 2016. Available from: http://hdl.handle.net/10183/149633

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. ANUPAM MAZUMDAR. AUTOMATIC DETECTION AND RECOGNITION OF MINE-LIKE OBJECTS IN SIDE-SCAN SONAR IMAGES.

Degree: 2009, National University of Singapore

Subjects/Keywords: Side-scan Sonar; Sea Mine; Wavelet; Shadow; Embedded Processor

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APA (6th Edition):

MAZUMDAR, A. (2009). AUTOMATIC DETECTION AND RECOGNITION OF MINE-LIKE OBJECTS IN SIDE-SCAN SONAR IMAGES. (Thesis). National University of Singapore. Retrieved from https://scholarbank.nus.edu.sg/handle/10635/153668

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

MAZUMDAR, ANUPAM. “AUTOMATIC DETECTION AND RECOGNITION OF MINE-LIKE OBJECTS IN SIDE-SCAN SONAR IMAGES.” 2009. Thesis, National University of Singapore. Accessed November 18, 2019. https://scholarbank.nus.edu.sg/handle/10635/153668.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

MAZUMDAR, ANUPAM. “AUTOMATIC DETECTION AND RECOGNITION OF MINE-LIKE OBJECTS IN SIDE-SCAN SONAR IMAGES.” 2009. Web. 18 Nov 2019.

Vancouver:

MAZUMDAR A. AUTOMATIC DETECTION AND RECOGNITION OF MINE-LIKE OBJECTS IN SIDE-SCAN SONAR IMAGES. [Internet] [Thesis]. National University of Singapore; 2009. [cited 2019 Nov 18]. Available from: https://scholarbank.nus.edu.sg/handle/10635/153668.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

MAZUMDAR A. AUTOMATIC DETECTION AND RECOGNITION OF MINE-LIKE OBJECTS IN SIDE-SCAN SONAR IMAGES. [Thesis]. National University of Singapore; 2009. Available from: https://scholarbank.nus.edu.sg/handle/10635/153668

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

20. CHAN KIT WAI. Embedded machine vision - a parallel architecture approach -.

Degree: 2006, National University of Singapore

Subjects/Keywords: Embedded; Real-Time; Vision; Parallelism; Processor; FPGA

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APA (6th Edition):

WAI, C. K. (2006). Embedded machine vision - a parallel architecture approach -. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/15305

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

WAI, CHAN KIT. “Embedded machine vision - a parallel architecture approach -.” 2006. Thesis, National University of Singapore. Accessed November 18, 2019. http://scholarbank.nus.edu.sg/handle/10635/15305.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

WAI, CHAN KIT. “Embedded machine vision - a parallel architecture approach -.” 2006. Web. 18 Nov 2019.

Vancouver:

WAI CK. Embedded machine vision - a parallel architecture approach -. [Internet] [Thesis]. National University of Singapore; 2006. [cited 2019 Nov 18]. Available from: http://scholarbank.nus.edu.sg/handle/10635/15305.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

WAI CK. Embedded machine vision - a parallel architecture approach -. [Thesis]. National University of Singapore; 2006. Available from: http://scholarbank.nus.edu.sg/handle/10635/15305

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of New South Wales

21. Li, Tuo. Cost-Efficient Soft-Error Resiliency for ASIP-based Embedded Systems.

Degree: Computer Science & Engineering, 2013, University of New South Wales

 Recent decades have witnessed the rapid growth of embedded systems. At present, embedded systems are widely applied in a broad range of critical applications including… (more)

Subjects/Keywords: Recovery; Application-specific instruction-set processor; Soft error; Fault tolerance; Embedded system; Checkpoint recovery; Instruction set extension; Single event upset

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APA (6th Edition):

Li, T. (2013). Cost-Efficient Soft-Error Resiliency for ASIP-based Embedded Systems. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/53542 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:12237/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Li, Tuo. “Cost-Efficient Soft-Error Resiliency for ASIP-based Embedded Systems.” 2013. Doctoral Dissertation, University of New South Wales. Accessed November 18, 2019. http://handle.unsw.edu.au/1959.4/53542 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:12237/SOURCE02?view=true.

MLA Handbook (7th Edition):

Li, Tuo. “Cost-Efficient Soft-Error Resiliency for ASIP-based Embedded Systems.” 2013. Web. 18 Nov 2019.

Vancouver:

Li T. Cost-Efficient Soft-Error Resiliency for ASIP-based Embedded Systems. [Internet] [Doctoral dissertation]. University of New South Wales; 2013. [cited 2019 Nov 18]. Available from: http://handle.unsw.edu.au/1959.4/53542 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:12237/SOURCE02?view=true.

Council of Science Editors:

Li T. Cost-Efficient Soft-Error Resiliency for ASIP-based Embedded Systems. [Doctoral Dissertation]. University of New South Wales; 2013. Available from: http://handle.unsw.edu.au/1959.4/53542 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:12237/SOURCE02?view=true


Université de Montréal

22. Zhou, Tongyao. SCIL processor : a common intermediate language processor for embedded systems .

Degree: 2008, Université de Montréal

Subjects/Keywords: Embedded processor; Softcore; CIL; SCIL processor; Embedded system; .Net language; Processeur embarqué; Softcore; CIL; SCIL processeur; Système embarqué; .Net langage

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhou, T. (2008). SCIL processor : a common intermediate language processor for embedded systems . (Thesis). Université de Montréal. Retrieved from http://hdl.handle.net/1866/7209

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhou, Tongyao. “SCIL processor : a common intermediate language processor for embedded systems .” 2008. Thesis, Université de Montréal. Accessed November 18, 2019. http://hdl.handle.net/1866/7209.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhou, Tongyao. “SCIL processor : a common intermediate language processor for embedded systems .” 2008. Web. 18 Nov 2019.

Vancouver:

Zhou T. SCIL processor : a common intermediate language processor for embedded systems . [Internet] [Thesis]. Université de Montréal; 2008. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/1866/7209.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhou T. SCIL processor : a common intermediate language processor for embedded systems . [Thesis]. Université de Montréal; 2008. Available from: http://hdl.handle.net/1866/7209

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Kentucky

23. Hegde, Sridhar. FUNCTIONAL ENHANCEMENT AND APPLICATIONS DEVELOPMENT FOR A HYBRID, HETEROGENEOUS SINGLE-CHIP MULTIPROCESSOR ARCHITECTURE.

Degree: 2004, University of Kentucky

 Reconfigurable and dynamic computer architecture is an exciting area of research that is rapidly expanding to meet the requirements of compute intense real and non-real… (more)

Subjects/Keywords: Reconfigurable Computing; System on a Chip; Embedded Systems; Multi-Processor System

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hegde, S. (2004). FUNCTIONAL ENHANCEMENT AND APPLICATIONS DEVELOPMENT FOR A HYBRID, HETEROGENEOUS SINGLE-CHIP MULTIPROCESSOR ARCHITECTURE. (Masters Thesis). University of Kentucky. Retrieved from http://uknowledge.uky.edu/gradschool_theses/252

Chicago Manual of Style (16th Edition):

Hegde, Sridhar. “FUNCTIONAL ENHANCEMENT AND APPLICATIONS DEVELOPMENT FOR A HYBRID, HETEROGENEOUS SINGLE-CHIP MULTIPROCESSOR ARCHITECTURE.” 2004. Masters Thesis, University of Kentucky. Accessed November 18, 2019. http://uknowledge.uky.edu/gradschool_theses/252.

MLA Handbook (7th Edition):

Hegde, Sridhar. “FUNCTIONAL ENHANCEMENT AND APPLICATIONS DEVELOPMENT FOR A HYBRID, HETEROGENEOUS SINGLE-CHIP MULTIPROCESSOR ARCHITECTURE.” 2004. Web. 18 Nov 2019.

Vancouver:

Hegde S. FUNCTIONAL ENHANCEMENT AND APPLICATIONS DEVELOPMENT FOR A HYBRID, HETEROGENEOUS SINGLE-CHIP MULTIPROCESSOR ARCHITECTURE. [Internet] [Masters thesis]. University of Kentucky; 2004. [cited 2019 Nov 18]. Available from: http://uknowledge.uky.edu/gradschool_theses/252.

Council of Science Editors:

Hegde S. FUNCTIONAL ENHANCEMENT AND APPLICATIONS DEVELOPMENT FOR A HYBRID, HETEROGENEOUS SINGLE-CHIP MULTIPROCESSOR ARCHITECTURE. [Masters Thesis]. University of Kentucky; 2004. Available from: http://uknowledge.uky.edu/gradschool_theses/252


University of Kentucky

24. Bondehagen, Brent. FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT.

Degree: 2013, University of Kentucky

 Structured Light Illumination (SLI) is the process where spatially varied patterns are projected onto a 3-D surface and based on the distortion by the surface… (more)

Subjects/Keywords: Structured Light Illumination; Phase Measuring Profilometry; 3-D Shape Measurement; Hardware Description Language; Processor Architecture; Computer and Systems Architecture; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Bondehagen, B. (2013). FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT. (Masters Thesis). University of Kentucky. Retrieved from http://uknowledge.uky.edu/ece_etds/23

Chicago Manual of Style (16th Edition):

Bondehagen, Brent. “FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT.” 2013. Masters Thesis, University of Kentucky. Accessed November 18, 2019. http://uknowledge.uky.edu/ece_etds/23.

MLA Handbook (7th Edition):

Bondehagen, Brent. “FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT.” 2013. Web. 18 Nov 2019.

Vancouver:

Bondehagen B. FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT. [Internet] [Masters thesis]. University of Kentucky; 2013. [cited 2019 Nov 18]. Available from: http://uknowledge.uky.edu/ece_etds/23.

Council of Science Editors:

Bondehagen B. FPGA-BASED IMPLEMENTATION OF DUAL-FREQUENCY PATTERN SCHEME FOR 3-D SHAPE MEASUREMENT. [Masters Thesis]. University of Kentucky; 2013. Available from: http://uknowledge.uky.edu/ece_etds/23

25. Đukić Miodrag. Ново решење компајлерске инфраструктуре за наменске процесоре.

Degree: 2015, University of Novi Sad

Ова докторска теза описује и анализира приступ развоју Це компајлера за наменске процесоре. Такав компајлер захтева имплементацију посебних техника и алгоритама, претежно специфичних за… (more)

Subjects/Keywords: Дигитални сигнал процесор, наменски процесори, програмски алати, компајлери; Digitalni signal procesor, namenski procesori, programski alati, kompajleri; Digital signal processor, embedded system, software tools, compilers

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APA (6th Edition):

Miodrag, . (2015). Ново решење компајлерске инфраструктуре за наменске процесоре. (Thesis). University of Novi Sad. Retrieved from http://www.cris.uns.ac.rs/DownloadFileServlet/Disertacija144766976130099.pdf?controlNumber=(BISIS)92654&fileName=144766976130099.pdf&id=4601&source=OATD&language=en ; http://www.cris.uns.ac.rs/record.jsf?recordId=92654&source=OATD&language=en

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Miodrag, Đukić. “Ново решење компајлерске инфраструктуре за наменске процесоре.” 2015. Thesis, University of Novi Sad. Accessed November 18, 2019. http://www.cris.uns.ac.rs/DownloadFileServlet/Disertacija144766976130099.pdf?controlNumber=(BISIS)92654&fileName=144766976130099.pdf&id=4601&source=OATD&language=en ; http://www.cris.uns.ac.rs/record.jsf?recordId=92654&source=OATD&language=en.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Miodrag, Đukić. “Ново решење компајлерске инфраструктуре за наменске процесоре.” 2015. Web. 18 Nov 2019.

Vancouver:

Miodrag . Ново решење компајлерске инфраструктуре за наменске процесоре. [Internet] [Thesis]. University of Novi Sad; 2015. [cited 2019 Nov 18]. Available from: http://www.cris.uns.ac.rs/DownloadFileServlet/Disertacija144766976130099.pdf?controlNumber=(BISIS)92654&fileName=144766976130099.pdf&id=4601&source=OATD&language=en ; http://www.cris.uns.ac.rs/record.jsf?recordId=92654&source=OATD&language=en.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Miodrag . Ново решење компајлерске инфраструктуре за наменске процесоре. [Thesis]. University of Novi Sad; 2015. Available from: http://www.cris.uns.ac.rs/DownloadFileServlet/Disertacija144766976130099.pdf?controlNumber=(BISIS)92654&fileName=144766976130099.pdf&id=4601&source=OATD&language=en ; http://www.cris.uns.ac.rs/record.jsf?recordId=92654&source=OATD&language=en

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

26. Valentine, Brian Evans. Embedded early vision techniques for efficient background modeling and midground detection.

Degree: PhD, Electrical and Computer Engineering, 2010, Georgia Tech

 An automated vision system performs critical tasks in video surveillance, while decreasing costs and increasing efficiency. It can provide high quality scene monitoring without the… (more)

Subjects/Keywords: Embedded processor; Computer vision; Computer vision; Video surveillance

…data. When applied to the multimodal mean, and run on an embedded x86 200 MHz processor, a 45… …42 Figure 15: eBox 2300 VESAPC embedded platform… …without the limitations of human distraction and fatigue. Advances in embedded processors… …modeling algorithms for surveillance on embedded platforms. Our contributions are as follows… …efficient chromatic clustering-based background model for embedded vision platforms that leverages… 

Page 1 Page 2 Page 3 Page 4 Page 5

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APA (6th Edition):

Valentine, B. E. (2010). Embedded early vision techniques for efficient background modeling and midground detection. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/33894

Chicago Manual of Style (16th Edition):

Valentine, Brian Evans. “Embedded early vision techniques for efficient background modeling and midground detection.” 2010. Doctoral Dissertation, Georgia Tech. Accessed November 18, 2019. http://hdl.handle.net/1853/33894.

MLA Handbook (7th Edition):

Valentine, Brian Evans. “Embedded early vision techniques for efficient background modeling and midground detection.” 2010. Web. 18 Nov 2019.

Vancouver:

Valentine BE. Embedded early vision techniques for efficient background modeling and midground detection. [Internet] [Doctoral dissertation]. Georgia Tech; 2010. [cited 2019 Nov 18]. Available from: http://hdl.handle.net/1853/33894.

Council of Science Editors:

Valentine BE. Embedded early vision techniques for efficient background modeling and midground detection. [Doctoral Dissertation]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/33894


Jönköping University

27. Ljungberg, Jan. SYSTEM ON CHIP : Fördelar i konstruktion med system on chip i förhållande till fristående FPGA och processor.

Degree: Computer and Electrical Engineering, 2015, Jönköping University

In this exam project the investigation has been done to determine, which profits that can be made by switching an internal bus between two… (more)

Subjects/Keywords: ARM Cortex A9; AXI3; AXI4; AXI4-Lite; Chipscope; FPGA; GP buss; interconnect; internbuss; kostnader; Modelsim; processor; System on Chip (SoC); Vivado; Xilinx; Zynq-7000; Embedded Systems; Inbäddad systemteknik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ljungberg, J. (2015). SYSTEM ON CHIP : Fördelar i konstruktion med system on chip i förhållande till fristående FPGA och processor. (Thesis). Jönköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-28263

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ljungberg, Jan. “SYSTEM ON CHIP : Fördelar i konstruktion med system on chip i förhållande till fristående FPGA och processor.” 2015. Thesis, Jönköping University. Accessed November 18, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-28263.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ljungberg, Jan. “SYSTEM ON CHIP : Fördelar i konstruktion med system on chip i förhållande till fristående FPGA och processor.” 2015. Web. 18 Nov 2019.

Vancouver:

Ljungberg J. SYSTEM ON CHIP : Fördelar i konstruktion med system on chip i förhållande till fristående FPGA och processor. [Internet] [Thesis]. Jönköping University; 2015. [cited 2019 Nov 18]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-28263.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ljungberg J. SYSTEM ON CHIP : Fördelar i konstruktion med system on chip i förhållande till fristående FPGA och processor. [Thesis]. Jönköping University; 2015. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-28263

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

28. Ocklind, Henrik. Driver Circuit for an Ultrasonic Motor.

Degree: The Institute of Technology, 2013, Linköping UniversityLinköping University

  To make a camera more user friendly or let it operate without an user the camera objective needs to be able to put thecamera… (more)

Subjects/Keywords: Ultrasonic motor; electronics; regulator; CPLD; micro processor; embedded system

Processor . . . . . . . . 1.6.2 Complex Programmable Logic 1.7 Environment… …developed by Philips Microcontroller, a simple processor with extra features Pencil, 12 mm, the… …of the microprocessor and the CPLD. 1.6.1 Micro Processor Texas Instrument MSC1202Y2 is… …the processor used in the circuit, it has a built in ADC/DAC and a 4 kB flash memory The… …processor core is based on the 8051 architecture which was developed by Intel in the early 1980s… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ocklind, H. (2013). Driver Circuit for an Ultrasonic Motor. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-101013

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ocklind, Henrik. “Driver Circuit for an Ultrasonic Motor.” 2013. Thesis, Linköping UniversityLinköping University. Accessed November 18, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-101013.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ocklind, Henrik. “Driver Circuit for an Ultrasonic Motor.” 2013. Web. 18 Nov 2019.

Vancouver:

Ocklind H. Driver Circuit for an Ultrasonic Motor. [Internet] [Thesis]. Linköping UniversityLinköping University; 2013. [cited 2019 Nov 18]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-101013.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ocklind H. Driver Circuit for an Ultrasonic Motor. [Thesis]. Linköping UniversityLinköping University; 2013. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-101013

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Krishnamurthy, Akilesh. Design of an FPGA-based Array Formatter for Casa Phase-Tilt Radar System.

Degree: MS, Electrical & Computer Engineering, 2011, University of Massachusetts

  Weather monitoring and forecasting systems have witnessed rapid advancement in recent years. However, one of the main challenges faced by these systems is poor… (more)

Subjects/Keywords: Field Programmable Gate Array (FPGA); System Design; Data Processing; Soft Processor; Radar Controller; Phased-Arrays; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Krishnamurthy, A. (2011). Design of an FPGA-based Array Formatter for Casa Phase-Tilt Radar System. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/691

Chicago Manual of Style (16th Edition):

Krishnamurthy, Akilesh. “Design of an FPGA-based Array Formatter for Casa Phase-Tilt Radar System.” 2011. Masters Thesis, University of Massachusetts. Accessed November 18, 2019. https://scholarworks.umass.edu/theses/691.

MLA Handbook (7th Edition):

Krishnamurthy, Akilesh. “Design of an FPGA-based Array Formatter for Casa Phase-Tilt Radar System.” 2011. Web. 18 Nov 2019.

Vancouver:

Krishnamurthy A. Design of an FPGA-based Array Formatter for Casa Phase-Tilt Radar System. [Internet] [Masters thesis]. University of Massachusetts; 2011. [cited 2019 Nov 18]. Available from: https://scholarworks.umass.edu/theses/691.

Council of Science Editors:

Krishnamurthy A. Design of an FPGA-based Array Formatter for Casa Phase-Tilt Radar System. [Masters Thesis]. University of Massachusetts; 2011. Available from: https://scholarworks.umass.edu/theses/691

30. Unnikrishnan, Deepak C. Application Specific Customization and Scalability of Soft Multiprocessors.

Degree: MS, Electrical & Computer Engineering, 2009, University of Massachusetts

 Soft multiprocessor systems exploit the plentiful computational resources available in field programmable devices. By virtue of their adaptability and ability to support coarse grained parallelism,… (more)

Subjects/Keywords: soft processor; FPGA; multi core; automatic synthesis; application specific customization; scalability; Computer and Systems Architecture; Computer Engineering; Digital Circuits; Hardware Systems; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Unnikrishnan, D. C. (2009). Application Specific Customization and Scalability of Soft Multiprocessors. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/274

Chicago Manual of Style (16th Edition):

Unnikrishnan, Deepak C. “Application Specific Customization and Scalability of Soft Multiprocessors.” 2009. Masters Thesis, University of Massachusetts. Accessed November 18, 2019. https://scholarworks.umass.edu/theses/274.

MLA Handbook (7th Edition):

Unnikrishnan, Deepak C. “Application Specific Customization and Scalability of Soft Multiprocessors.” 2009. Web. 18 Nov 2019.

Vancouver:

Unnikrishnan DC. Application Specific Customization and Scalability of Soft Multiprocessors. [Internet] [Masters thesis]. University of Massachusetts; 2009. [cited 2019 Nov 18]. Available from: https://scholarworks.umass.edu/theses/274.

Council of Science Editors:

Unnikrishnan DC. Application Specific Customization and Scalability of Soft Multiprocessors. [Masters Thesis]. University of Massachusetts; 2009. Available from: https://scholarworks.umass.edu/theses/274

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