Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(Embedded DRAM). Showing records 1 – 10 of 10 total matches.

Search Limiters

Last 2 Years | English Only

No search limiters apply to these results.

▼ Search Limiters


University of Minnesota

1. Chun, Ki Chul. Design techniques for dense embedded memory in advanced CMOS technologies.

Degree: PhD, Electrical Engineering, 2012, University of Minnesota

 On-die cache memory is a key component in advanced processors since it can boost micro-architectural level performance at a moderate power penalty. Demand for denser… (more)

Subjects/Keywords: 2T DRAM; 3T DRAM; Cache; Embedded memory; Microprocessor; STT-MRAM

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chun, K. C. (2012). Design techniques for dense embedded memory in advanced CMOS technologies. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/162804

Chicago Manual of Style (16th Edition):

Chun, Ki Chul. “Design techniques for dense embedded memory in advanced CMOS technologies.” 2012. Doctoral Dissertation, University of Minnesota. Accessed October 18, 2019. http://hdl.handle.net/11299/162804.

MLA Handbook (7th Edition):

Chun, Ki Chul. “Design techniques for dense embedded memory in advanced CMOS technologies.” 2012. Web. 18 Oct 2019.

Vancouver:

Chun KC. Design techniques for dense embedded memory in advanced CMOS technologies. [Internet] [Doctoral dissertation]. University of Minnesota; 2012. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/11299/162804.

Council of Science Editors:

Chun KC. Design techniques for dense embedded memory in advanced CMOS technologies. [Doctoral Dissertation]. University of Minnesota; 2012. Available from: http://hdl.handle.net/11299/162804


University of Waterloo

2. Hassan, Mohamed. Predictable Shared Memory Resources for Multi-Core Real-Time Systems.

Degree: 2017, University of Waterloo

 A major challenge in multi-core real-time systems is the interference problem on the shared hardware components amongst cores. Examples of these shared components include buses,… (more)

Subjects/Keywords: Real-time; Embedded Systems; Comptuer Hardware; Memory Systems; DRAM; Timing analysis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hassan, M. (2017). Predictable Shared Memory Resources for Multi-Core Real-Time Systems. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/11676

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hassan, Mohamed. “Predictable Shared Memory Resources for Multi-Core Real-Time Systems.” 2017. Thesis, University of Waterloo. Accessed October 18, 2019. http://hdl.handle.net/10012/11676.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hassan, Mohamed. “Predictable Shared Memory Resources for Multi-Core Real-Time Systems.” 2017. Web. 18 Oct 2019.

Vancouver:

Hassan M. Predictable Shared Memory Resources for Multi-Core Real-Time Systems. [Internet] [Thesis]. University of Waterloo; 2017. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/10012/11676.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hassan M. Predictable Shared Memory Resources for Multi-Core Real-Time Systems. [Thesis]. University of Waterloo; 2017. Available from: http://hdl.handle.net/10012/11676

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

3. Liu, Qunzeng. Statistical analysis techniques for logic and memory circuits.

Degree: PhD, Electrical Engineering, 2010, University of Minnesota

 Process variations have become increasingly important as feature sizes enter the sub- 100nm regime and continue to shrink. Both logic and memory circuits have seen… (more)

Subjects/Keywords: Embedded DRAM; Post-silicon optimization; SSTA; Statistical analysis; Electrical Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, Q. (2010). Statistical analysis techniques for logic and memory circuits. (Doctoral Dissertation). University of Minnesota. Retrieved from http://purl.umn.edu/95019

Chicago Manual of Style (16th Edition):

Liu, Qunzeng. “Statistical analysis techniques for logic and memory circuits.” 2010. Doctoral Dissertation, University of Minnesota. Accessed October 18, 2019. http://purl.umn.edu/95019.

MLA Handbook (7th Edition):

Liu, Qunzeng. “Statistical analysis techniques for logic and memory circuits.” 2010. Web. 18 Oct 2019.

Vancouver:

Liu Q. Statistical analysis techniques for logic and memory circuits. [Internet] [Doctoral dissertation]. University of Minnesota; 2010. [cited 2019 Oct 18]. Available from: http://purl.umn.edu/95019.

Council of Science Editors:

Liu Q. Statistical analysis techniques for logic and memory circuits. [Doctoral Dissertation]. University of Minnesota; 2010. Available from: http://purl.umn.edu/95019


NSYSU

4. Chen, Wei-Shiun. Study of High Performance Circuits for 2.0V Embedded Dynamic Random Access Memory.

Degree: Master, Electrical Engineering, 2000, NSYSU

 Abstract Four high-performance circuits design techniques for embedded DRAM are proposed. First, a negative voltage generator having high efficiency is proposed to provide the negative… (more)

Subjects/Keywords: wordline driver; reduced clock-swing driver; embedded dram; read bus amplifier

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, W. (2000). Study of High Performance Circuits for 2.0V Embedded Dynamic Random Access Memory. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727100-013623

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Wei-Shiun. “Study of High Performance Circuits for 2.0V Embedded Dynamic Random Access Memory.” 2000. Thesis, NSYSU. Accessed October 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727100-013623.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Wei-Shiun. “Study of High Performance Circuits for 2.0V Embedded Dynamic Random Access Memory.” 2000. Web. 18 Oct 2019.

Vancouver:

Chen W. Study of High Performance Circuits for 2.0V Embedded Dynamic Random Access Memory. [Internet] [Thesis]. NSYSU; 2000. [cited 2019 Oct 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727100-013623.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen W. Study of High Performance Circuits for 2.0V Embedded Dynamic Random Access Memory. [Thesis]. NSYSU; 2000. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0727100-013623

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Boise State University

5. Harvard, Qawi IbnZayd. Wide I/O Dram Architecture Utilizing Proximity Communication.

Degree: 2009, Boise State University

 The bandwidth and power consumption of dynamic random access memory, used as the main memory of a computer system, impacts the computer’s execution rate even… (more)

Subjects/Keywords: DRAM; Proximity Communication; capacitive interface; low power; VLSI and Circuits, Embedded and Hardware Systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Harvard, Q. I. (2009). Wide I/O Dram Architecture Utilizing Proximity Communication. (Thesis). Boise State University. Retrieved from https://scholarworks.boisestate.edu/td/72

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Harvard, Qawi IbnZayd. “Wide I/O Dram Architecture Utilizing Proximity Communication.” 2009. Thesis, Boise State University. Accessed October 18, 2019. https://scholarworks.boisestate.edu/td/72.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Harvard, Qawi IbnZayd. “Wide I/O Dram Architecture Utilizing Proximity Communication.” 2009. Web. 18 Oct 2019.

Vancouver:

Harvard QI. Wide I/O Dram Architecture Utilizing Proximity Communication. [Internet] [Thesis]. Boise State University; 2009. [cited 2019 Oct 18]. Available from: https://scholarworks.boisestate.edu/td/72.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Harvard QI. Wide I/O Dram Architecture Utilizing Proximity Communication. [Thesis]. Boise State University; 2009. Available from: https://scholarworks.boisestate.edu/td/72

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

6. Harvard, Qawi IbnZayd. Low-Power, High-Bandwidth and Ultra-Small Memory Module Design.

Degree: 2011, Boise State University

 The main memory subsystem has become inefficient. The performance gained has come at the expenses of power consumption, capacity, and cost. This dissertation proposes novel… (more)

Subjects/Keywords: DRAM; Low Power; Memory Module; Interconnect; VLSI and Circuits, Embedded and Hardware Systems

…12 Figure 2.5 – Power Consumption Versus Maximum Frequency in DRAM… …13 Figure 2.6 – Power Consumption of DRAM Versus Capacity and Bandwidth… …44 Figure 4.1 – A 4 Gb DRAM Architecture… …47 Figure 4.2 – DRAM Architecture with Edge I/O… …52 Figure 4.4 – Final 4 Gb DRAM Architecture… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Harvard, Q. I. (2011). Low-Power, High-Bandwidth and Ultra-Small Memory Module Design. (Thesis). Boise State University. Retrieved from https://scholarworks.boisestate.edu/td/172

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Harvard, Qawi IbnZayd. “Low-Power, High-Bandwidth and Ultra-Small Memory Module Design.” 2011. Thesis, Boise State University. Accessed October 18, 2019. https://scholarworks.boisestate.edu/td/172.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Harvard, Qawi IbnZayd. “Low-Power, High-Bandwidth and Ultra-Small Memory Module Design.” 2011. Web. 18 Oct 2019.

Vancouver:

Harvard QI. Low-Power, High-Bandwidth and Ultra-Small Memory Module Design. [Internet] [Thesis]. Boise State University; 2011. [cited 2019 Oct 18]. Available from: https://scholarworks.boisestate.edu/td/172.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Harvard QI. Low-Power, High-Bandwidth and Ultra-Small Memory Module Design. [Thesis]. Boise State University; 2011. Available from: https://scholarworks.boisestate.edu/td/172

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

7. Agrawal, Aditya. Refresh reduction in dynamic memories.

Degree: PhD, 1200, 2015, University of Illinois – Urbana-Champaign

 An effective approach to reduce the static energy consumption of large on-chip memories is to use a low-leakage technology such as embedded DRAM (eDRAM). Unfortunately,… (more)

Subjects/Keywords: dynamic random-access memory (DRAM); embedded dynamic random-access memory (eDRAM); Cache; dynamic memory; refresh; three-dimensional (3D); stacking; retention time; Through Silicon Vias (TSV); Thermal Through Silicon Vias (TTSV); temperature; leakage; variation; spatial

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Agrawal, A. (2015). Refresh reduction in dynamic memories. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/72970

Chicago Manual of Style (16th Edition):

Agrawal, Aditya. “Refresh reduction in dynamic memories.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 18, 2019. http://hdl.handle.net/2142/72970.

MLA Handbook (7th Edition):

Agrawal, Aditya. “Refresh reduction in dynamic memories.” 2015. Web. 18 Oct 2019.

Vancouver:

Agrawal A. Refresh reduction in dynamic memories. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/2142/72970.

Council of Science Editors:

Agrawal A. Refresh reduction in dynamic memories. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/72970

8. Lee, Dongwon. High-performance computer system architectures for embedded computing.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 The main objective of this thesis is to propose new methods for designing high-performance embedded computer system architectures. To achieve the goal, three major components… (more)

Subjects/Keywords: Turbo decoding; GPU architecture; SDF graph; DRAM system; Embedded computer systems; High performance computing; Electronic data processing; Parallel processing (Electronic computers)

…processor embedded 1 systems: multi-core processing elements (PEs), DRAM main memory… …44 Figure 27: Contemporary DRAM main memory system. 50 Figure 28: SDF application graph… …objective of this thesis is to propose new methods for designing highperformance embedded computer… …elements (PEs), DRAM main memory systems, and on/off-chip interconnection networks - in… …multi-processor embedded systems are examined in each section respectively. The first section… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lee, D. (2011). High-performance computer system architectures for embedded computing. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/42766

Chicago Manual of Style (16th Edition):

Lee, Dongwon. “High-performance computer system architectures for embedded computing.” 2011. Doctoral Dissertation, Georgia Tech. Accessed October 18, 2019. http://hdl.handle.net/1853/42766.

MLA Handbook (7th Edition):

Lee, Dongwon. “High-performance computer system architectures for embedded computing.” 2011. Web. 18 Oct 2019.

Vancouver:

Lee D. High-performance computer system architectures for embedded computing. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1853/42766.

Council of Science Editors:

Lee D. High-performance computer system architectures for embedded computing. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/42766

9. Park, Youn Sung. Energy-Efficient Decoders of Near-Capacity Channel Codes.

Degree: PhD, Electrical Engineering, 2014, University of Michigan

 Channel coding has become essential in state-of-the-art communication and storage systems for ensuring reliable transmission and storage of information. Their goal is to achieve high… (more)

Subjects/Keywords: Energy-Efficient Decoders of Near-Capacity Channel Codes; Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM; A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating; A Belief Propagation Polar Decoder With Bit-Splitting Register File; Electrical Engineering; Engineering

…bandwidth. A non-refresh embedded DRAM is proposed as a new memory solution to replace the most… …Codes Logic-compatible embedded DRAM (eDRAM) [4, 51, 52, 53] is proposed… …of 780 Mb/s, at 475 mV and 50 MHz. 14 CHAPTER II LDPC Decoder with Embedded DRAM 2.1… …new techniques developed in this work, including non-refresh embedded memory, bit-splitting… …throughput LDPC decoders. Logic-compatible eDRAM does not require a special DRAM process and it is… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Park, Y. S. (2014). Energy-Efficient Decoders of Near-Capacity Channel Codes. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/108731

Chicago Manual of Style (16th Edition):

Park, Youn Sung. “Energy-Efficient Decoders of Near-Capacity Channel Codes.” 2014. Doctoral Dissertation, University of Michigan. Accessed October 18, 2019. http://hdl.handle.net/2027.42/108731.

MLA Handbook (7th Edition):

Park, Youn Sung. “Energy-Efficient Decoders of Near-Capacity Channel Codes.” 2014. Web. 18 Oct 2019.

Vancouver:

Park YS. Energy-Efficient Decoders of Near-Capacity Channel Codes. [Internet] [Doctoral dissertation]. University of Michigan; 2014. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/2027.42/108731.

Council of Science Editors:

Park YS. Energy-Efficient Decoders of Near-Capacity Channel Codes. [Doctoral Dissertation]. University of Michigan; 2014. Available from: http://hdl.handle.net/2027.42/108731

10. Mancuso, Renato. Next-generation safety-critical systems on multi-core platforms.

Degree: PhD, Computer Science, 2017, University of Illinois – Urbana-Champaign

 Multi-core platforms represent the answer of the industry to the increasing demand for computational capabilities. In fact, multi-core platforms can deliver large computational power together… (more)

Subjects/Keywords: Real-time systems; Multi-core systems; Commercial-off-the-shelf (COTS); Single-core equivalence; Single-core equivalent; Hardware resource management; Operating system (OS); Real-time operating system (RTOS); Worst case execution time (WCET); Scheduling; Schedulability analysis; Multi-core real-time operating system (RTOS); Profiling; Avionics; Safety-critical; Cyber-physical systems (CPS); Memguard; Colored lockdown; Palloc; Kernel verification; Scratchpad-centric operating system (OS); Scratchpad memories operating system (SPM-OS); Scratchpad scheduling; Direct memory access (DMA) scheduling; Flow-shop task; Flow-shop scheduling; Hardware scheduler; Field-programmable gate array (FPGA) scheduler; Real-time Linux; Automotive; Smart manufacturing; Real-time networking; Embedded systems; Multi-core avionics; Multi-core automotive; Self-driving cars; Multi-core safety-critical; Many-core; Reconfigurable computing; Internet of things; Real-time cloud computing; Provably safe cyber-physical systems (CPS); Multi-core scheduling; Performance isolation; Real-time resource management; Real-time cache; Real-time dynamic random access memory (DRAM); P4080; MPC5777M; Inter-core interference; Interference channels; CAST32; CAST32A; Federal Aviation Administration (FAA); Minimal multicore avionics certification guidance; Multi-core automotive open system architecture (AUTOSAR); DO-178C; DO-178B; Resource partitioning; Multi-core resource partitioning; Predictable execution model (PREM); Multi-core predictable execution model (PREM)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mancuso, R. (2017). Next-generation safety-critical systems on multi-core platforms. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97399

Chicago Manual of Style (16th Edition):

Mancuso, Renato. “Next-generation safety-critical systems on multi-core platforms.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 18, 2019. http://hdl.handle.net/2142/97399.

MLA Handbook (7th Edition):

Mancuso, Renato. “Next-generation safety-critical systems on multi-core platforms.” 2017. Web. 18 Oct 2019.

Vancouver:

Mancuso R. Next-generation safety-critical systems on multi-core platforms. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/2142/97399.

Council of Science Editors:

Mancuso R. Next-generation safety-critical systems on multi-core platforms. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97399

.