You searched for subject:(Electronics packaging).
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1.
Guo, Yuanbo.
Development of a high current high temperature SiC MOSFET based solid-state power controller.
Degree: 2011, State University of New York at Buffalo
URL: http://pqdtopen.proquest.com/#viewpdf?dispub=1488901 
► Solid-State Power Controllers (SSPCs) are critical components in the development of electric aircraft and must be small in size, fast in response, and have…
(more)
▼ Solid-State Power Controllers (SSPCs) are critical components in the development of electric aircraft and must be small in size, fast in response, and have high reliability. They are also proposed for use in microgrids to improve the power quality and system reliability. The development of Silicon Carbide (SiC) semiconductor switches provides a series of improvements for the SSPCs in both electrical and thermal performances. In the proposed SSPC design investigation, SiC MOSFETs die are mounted on cast-aluminum traces, under which are an aluminum nitride (AlN) layer and an aluminum composite base plate. The concept of <i>i2t</i> and its application in solid state protection is discussed in detail. Transient thermal characterizations of SiC MOSFETs are provided for a nearly-all-aluminum package by Finite Element Analysis (FEA). The SSPC is targeted for 120A nominal, 1200A fault current, 270V DC system, and working at 105°C environment with a maximum 350°C transient junction temperature capability.
Subjects/Keywords: Engineering, Electronics and Electrical; Engineering, Packaging; Energy
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APA (6th Edition):
Guo, Y. (2011). Development of a high current high temperature SiC MOSFET based solid-state power controller. (Thesis). State University of New York at Buffalo. Retrieved from http://pqdtopen.proquest.com/#viewpdf?dispub=1488901
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Guo, Yuanbo. “Development of a high current high temperature SiC MOSFET based solid-state power controller.” 2011. Thesis, State University of New York at Buffalo. Accessed February 28, 2021.
http://pqdtopen.proquest.com/#viewpdf?dispub=1488901.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Guo, Yuanbo. “Development of a high current high temperature SiC MOSFET based solid-state power controller.” 2011. Web. 28 Feb 2021.
Vancouver:
Guo Y. Development of a high current high temperature SiC MOSFET based solid-state power controller. [Internet] [Thesis]. State University of New York at Buffalo; 2011. [cited 2021 Feb 28].
Available from: http://pqdtopen.proquest.com/#viewpdf?dispub=1488901.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Guo Y. Development of a high current high temperature SiC MOSFET based solid-state power controller. [Thesis]. State University of New York at Buffalo; 2011. Available from: http://pqdtopen.proquest.com/#viewpdf?dispub=1488901
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
2.
Ruppi, Robert.
Substrates for Packaging of Silicon Carbide Power Electronics
.
Degree: Chalmers tekniska högskola / Institutionen för mikroteknologi och nanovetenskap (MC2), 2011, Chalmers University of Technology
URL: http://hdl.handle.net/20.500.12380/300278
► Silicon based power semiconductor devices are the fundamental components of electronic systems and circuits today. The need for high voltage devices that can operate at…
(more)
▼ Silicon based power semiconductor devices are the fundamental components of electronic systems and circuits today. The need for high voltage devices that can operate at high ambient temperatures and switching speeds are growing; especially for the military, automotive and aerospace industries. Si based power electronics dominate the current market. However, Si suffers from limitations such as low band gap and low thermal conductivity, leading to limitations in switching speeds, blocking voltages and operating temperatures. Due to these limitations, there is an increasing interest in wide band gap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN). To meet the future demands of high power and high temperature components based on wide band gap semiconductors, new packaging concepts are also required. Materials such as aluminium nitride (AlN) and alumina (Al2O3) are appropriate for high power packaging, due to their high thermal conductivity and superior mechanical stability. In this master thesis project I have evaluated a new packaging concept for power electronics based on substrates of Al2O3 and AlN. A method to deposit nano silver ink by ink jet printing directly on Al2O3 is developed and the nano silver ink performance has been evaluated. It is shown that parameters like surface preparation and sintering conditions are essential for the final result. The resistivity of the printed ink is evaluated and results indicate that the resistivity is close to bulk silver. Experiments show that the nano silver can be sintered at temperatures as low as 250 °C to achieve sufficient electrical conductivity. Further, a packaging concept based on existing substrate technology (Direct Bonded Copper (DBC) with AlN core) is designed, simulated and manufactured by conventional etching technology.
Subjects/Keywords: Packaging; silicon carbide; SiC power electronics; printed electronics; substrates for power electronics
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APA (6th Edition):
Ruppi, R. (2011). Substrates for Packaging of Silicon Carbide Power Electronics
. (Thesis). Chalmers University of Technology. Retrieved from http://hdl.handle.net/20.500.12380/300278
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Ruppi, Robert. “Substrates for Packaging of Silicon Carbide Power Electronics
.” 2011. Thesis, Chalmers University of Technology. Accessed February 28, 2021.
http://hdl.handle.net/20.500.12380/300278.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Ruppi, Robert. “Substrates for Packaging of Silicon Carbide Power Electronics
.” 2011. Web. 28 Feb 2021.
Vancouver:
Ruppi R. Substrates for Packaging of Silicon Carbide Power Electronics
. [Internet] [Thesis]. Chalmers University of Technology; 2011. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/20.500.12380/300278.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Ruppi R. Substrates for Packaging of Silicon Carbide Power Electronics
. [Thesis]. Chalmers University of Technology; 2011. Available from: http://hdl.handle.net/20.500.12380/300278
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
San Jose State University
3.
Werdowatz, Andrew Richard.
Developing an Empirical Correlation for the Thermal Spreading Resistance of a Heat Sink.
Degree: MS, Mechanical Engineering, 2016, San Jose State University
URL: https://doi.org/10.31979/etd.pq68-tx7x
;
https://scholarworks.sjsu.edu/etd_theses/4711
► Heat sinks are a critical component in numerous thermal management strategies, ranging from consumer electronics to data centers. The ability to perform an accurate…
(more)
▼ Heat sinks are a critical component in numerous thermal management strategies, ranging from consumer electronics to data centers. The ability to perform an accurate thermal performance analysis of a heat sink is a crucial step in the design process. In situations where the heat sink is larger in area than the component it is being used to cool, a phenomena known as thermal spreading resistance takes effect. Thermal spreading resistance is not as easily calculated as other components of the thermal resistance of a heat sink (i.e. material and external thermal resistance). However, multiple solutions have been proposed and published that can be used to calculate thermal spreading resistance. The difficulty lies in that most of these solutions contain a very complex set of equations and are not very practical for use by the industry. As a result, the present research is aimed at developing a simple equation that can be used to calculate the thermal spreading resistance of a heat sink based on certain geometric and thermal characteristics.
Using a commercial CFD software package, a model was developed that was shown to accurately model the spreading resistance within a heat. Using this model, a set parametric studies was conducted that varied the base thickness, heat source/heat sink side length ratio, heat sink material, external resistance, and the aspect ratio in order to obtain the effects they have on the spreading resistance. Using these results, an extensive data analysis was conducted and resulted in the development of a much simpler equation that can be used to calculate the thermal spreading resistance of heat sink. The developed equation was shown to be in excellent agreement with previous analytical solutions, in most cases with +/- 5%. As a result, it was confirmed that the developed equation can be used to accurately calculate spreading resistance over the stated range of valid parameters.
Subjects/Keywords: constriction resistance; electronics cooling; electronics packaging; heat sink; heat transfer; spreading resistance
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APA (6th Edition):
Werdowatz, A. R. (2016). Developing an Empirical Correlation for the Thermal Spreading Resistance of a Heat Sink. (Masters Thesis). San Jose State University. Retrieved from https://doi.org/10.31979/etd.pq68-tx7x ; https://scholarworks.sjsu.edu/etd_theses/4711
Chicago Manual of Style (16th Edition):
Werdowatz, Andrew Richard. “Developing an Empirical Correlation for the Thermal Spreading Resistance of a Heat Sink.” 2016. Masters Thesis, San Jose State University. Accessed February 28, 2021.
https://doi.org/10.31979/etd.pq68-tx7x ; https://scholarworks.sjsu.edu/etd_theses/4711.
MLA Handbook (7th Edition):
Werdowatz, Andrew Richard. “Developing an Empirical Correlation for the Thermal Spreading Resistance of a Heat Sink.” 2016. Web. 28 Feb 2021.
Vancouver:
Werdowatz AR. Developing an Empirical Correlation for the Thermal Spreading Resistance of a Heat Sink. [Internet] [Masters thesis]. San Jose State University; 2016. [cited 2021 Feb 28].
Available from: https://doi.org/10.31979/etd.pq68-tx7x ; https://scholarworks.sjsu.edu/etd_theses/4711.
Council of Science Editors:
Werdowatz AR. Developing an Empirical Correlation for the Thermal Spreading Resistance of a Heat Sink. [Masters Thesis]. San Jose State University; 2016. Available from: https://doi.org/10.31979/etd.pq68-tx7x ; https://scholarworks.sjsu.edu/etd_theses/4711
University of California – Berkeley
4.
PARK, EUNG SEOK.
Application of Inkjet-Printing Technology to Micro-Electro-Mechanical Systems.
Degree: Electrical Engineering, 2013, University of California – Berkeley
URL: http://www.escholarship.org/uc/item/8ts5n583
► Printed electronics employing solution-processed materials is considered to be the key to realizing low-cost large-area electronic systems, but the performance of printed transistors is not…
(more)
▼ Printed electronics employing solution-processed materials is considered to be the key to realizing low-cost large-area electronic systems, but the performance of printed transistors is not generally adequate for most intended applications due to limited performance of printable semiconductors. In this dissertation, I propose an alternative approach of a printed switch, where the use of semiconductors can be avoided by building mechanical switches with printed metal nanoparticles. I provide the first demonstration of inkjet-printed micro-electro-mechanical (MEM) switches with abrupt switching characteristics, very low on-state resistance (~10 Ohm), and nearly perfect off-state behavior with immeasurable leakage with on/off current ratio of 107. The devices are fabricated using a novel process scheme to build 3-dimensional cantilever structures from solution-processed metallic nanoparticles and sacrificial polymers. These printed MEM switches thus represent a uniquely attractive path for realizing printed electronics. I will also discuss an inkjet-printed microshell encapsulation as a new zero-level packaging technology. Inkjet-printing of silver nanoparticle ink is demonstrated to form porous microshells through which sacrificial oxide can be selectively removed to release MEMS structures. A second inkjet printing process using finer gold nanoparticle ink or polymer is demonstrated to effectively seal the microshells. This inkjet-printed microshell encapsulation technology is successfully applied to a MEM relay, and is demonstrated to mitigate the issue of contact oxidation. Specifically, the stability of the relay ON-state resistance is dramatically improved by more than a factor of 100.
Subjects/Keywords: Engineering; Electrical engineering; Inkjet Printing; MEMS; Metals; Nanoparticles; Packaging; Printed Electronics
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APA (6th Edition):
PARK, E. S. (2013). Application of Inkjet-Printing Technology to Micro-Electro-Mechanical Systems. (Thesis). University of California – Berkeley. Retrieved from http://www.escholarship.org/uc/item/8ts5n583
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
PARK, EUNG SEOK. “Application of Inkjet-Printing Technology to Micro-Electro-Mechanical Systems.” 2013. Thesis, University of California – Berkeley. Accessed February 28, 2021.
http://www.escholarship.org/uc/item/8ts5n583.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
PARK, EUNG SEOK. “Application of Inkjet-Printing Technology to Micro-Electro-Mechanical Systems.” 2013. Web. 28 Feb 2021.
Vancouver:
PARK ES. Application of Inkjet-Printing Technology to Micro-Electro-Mechanical Systems. [Internet] [Thesis]. University of California – Berkeley; 2013. [cited 2021 Feb 28].
Available from: http://www.escholarship.org/uc/item/8ts5n583.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
PARK ES. Application of Inkjet-Printing Technology to Micro-Electro-Mechanical Systems. [Thesis]. University of California – Berkeley; 2013. Available from: http://www.escholarship.org/uc/item/8ts5n583
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Texas A&M University
5.
Humood, Mohammad Muneer Mutlaq.
Nanomechanics, Nanotribology and Fabrication of Flexible Multilayer Nanocomposites.
Degree: PhD, Mechanical Engineering, 2018, Texas A&M University
URL: http://hdl.handle.net/1969.1/174053
► Polymer-based multilayer nanocomposites have become favorable material choice for many applications such as gas barriers, water membranes, optoelectronic devices, biosensors, corrosion inhibitors and energy devices.…
(more)
▼ Polymer-based multilayer nanocomposites have become favorable material choice for
many applications such as gas barriers, water membranes, optoelectronic devices, biosensors,
corrosion inhibitors and energy devices. They are finding their ways as a replacement of traditional
metal, silicon oxides and hard inorganic coatings. The present work is dedicated to addressing the
fabrication of new polymer flexible nanocomposites and their mechanical response against normal
and lateral deformation modes, known as nanoindentation and nanoscratch. Particularly, the
scratch resistance of these nanocomposites is critical for many applications.
Little is known in the literature about their nanomechanics, hence reliability and durability
for long-term applications. Better understanding of the nanomechanics and nanotribology of 2D
multilayered thin films and 3D multilayered structures was achieved in this thesis through a series
of different experiments using low and high load nanoindentation, nanoscratch and flat-punch
compression. Complementary computational modeling supported the experimental findings and
further explains their nano- and micromechanical behaviors.
Based on the findings of these nanomechanical experiments, functional multilayered
polymeric coatings consisting of different arrangements of polymers, graphene oxide and clay
were found to be potential material choices for a range of different applications such as low-friction
tribological coatings, vapor/gas barriers and self-healing coatings. Furthermore, 3D
silicon/polymer structures specifically under extreme deformation were found to be a potential
candidate for wearable
electronics and flexible microelectromechanical systems (MEMS) sensors
due to the resilient and elastic behavior driven by the geometry-dependent deformation of these
structures.
The last part discusses the development of a new material pertaining to the development of
nanocomposites. On the quest of continuous search of 2D materials, which can act as
reinforcements, a new material, Aluminum diboride (AlBv2) flakes, was introduced and discussed.
High aspect ratio AlBv2 flakes is a potential reinforcement for conductive polymer nanocomposites
due to the metallic conductivity in the axis parallel to the basal hexagonal plane.
In summary, the findings above focused on the mechanics and tribology of nanocomposites
at the nanoscale mainly for gas barrier applications and MEMS devices. However, the knowledge
can also be extended to other devices such as energy harvesting devices and membranes where
tribology issues at the nanoscale are of important concerns.
Advisors/Committee Members: Polycarpou, Andreas A. (advisor), Grunlan, Jaime C (committee member), Hipwell, M. Cynthia (committee member), Naraghi, Mohammad (committee member), Pharr, Matt (committee member).
Subjects/Keywords: Nanomechanics; Nanoindentation; Nanocomposites; Flexible; Wearable Electronics; Food Packaging
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APA (6th Edition):
Humood, M. M. M. (2018). Nanomechanics, Nanotribology and Fabrication of Flexible Multilayer Nanocomposites. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/174053
Chicago Manual of Style (16th Edition):
Humood, Mohammad Muneer Mutlaq. “Nanomechanics, Nanotribology and Fabrication of Flexible Multilayer Nanocomposites.” 2018. Doctoral Dissertation, Texas A&M University. Accessed February 28, 2021.
http://hdl.handle.net/1969.1/174053.
MLA Handbook (7th Edition):
Humood, Mohammad Muneer Mutlaq. “Nanomechanics, Nanotribology and Fabrication of Flexible Multilayer Nanocomposites.” 2018. Web. 28 Feb 2021.
Vancouver:
Humood MMM. Nanomechanics, Nanotribology and Fabrication of Flexible Multilayer Nanocomposites. [Internet] [Doctoral dissertation]. Texas A&M University; 2018. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/1969.1/174053.
Council of Science Editors:
Humood MMM. Nanomechanics, Nanotribology and Fabrication of Flexible Multilayer Nanocomposites. [Doctoral Dissertation]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/174053
Delft University of Technology
6.
Popovic, J.
Improving packaging and increasing the level of integration in power electronics.
Degree: 2005, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1
;
urn:NBN:nl:ui:24-uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1
;
urn:NBN:nl:ui:24-uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1
;
http://resolver.tudelft.nl/uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1
► The use of power electronics is growing extensively in applications such as the automotive field, lighting, power supplies, motor drives, etc. The ultimate goal is…
(more)
▼ The use of power
electronics is growing extensively in applications such as the automotive field, lighting, power supplies, motor drives, etc. The ultimate goal is to make power
electronics as transparent to the final user as possible, which means little extra cost, use of existing space and little or no extra thermal management. This sets very stringent requirements on power
electronics concerning performance, cost and size. It has been recognized that the physical construction of power electronic converters represents one of the main frontiers in fulfilling these ever-increasing requirements. This thesis deals with improving the physical implementation of power electronic converters by increasing the level of integration through the use of multifunctional parts. A systematic approach to integration and
packaging, on the basis of power electronic converters construction parts and functions that the parts perform, is introduced. Methods of reducing the number of construction parts in the converter by integrating the functionality of several parts into one are devised. This includes not only electrical and thermal (functional) parts but also non-electrical (
packaging) parts, since
packaging parts represent a large portion of the total number of parts in a converters assembly. Furthermore, technologies that can be used to implement these methods in converters are reviewed. The integration methods and technologies are merged into an algorithm that maps the design of the fundamental functions (electrical and thermal) onto the design of physical parts. Lastly, a tool for choosing the optimal solution among different construction technology options derived in the introduced algorithm is presented.
Advisors/Committee Members: Ferreira, J.A..
Subjects/Keywords: integration; packaging; power electronics
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APA (6th Edition):
Popovic, J. (2005). Improving packaging and increasing the level of integration in power electronics. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1 ; urn:NBN:nl:ui:24-uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1 ; urn:NBN:nl:ui:24-uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1 ; http://resolver.tudelft.nl/uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1
Chicago Manual of Style (16th Edition):
Popovic, J. “Improving packaging and increasing the level of integration in power electronics.” 2005. Doctoral Dissertation, Delft University of Technology. Accessed February 28, 2021.
http://resolver.tudelft.nl/uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1 ; urn:NBN:nl:ui:24-uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1 ; urn:NBN:nl:ui:24-uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1 ; http://resolver.tudelft.nl/uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1.
MLA Handbook (7th Edition):
Popovic, J. “Improving packaging and increasing the level of integration in power electronics.” 2005. Web. 28 Feb 2021.
Vancouver:
Popovic J. Improving packaging and increasing the level of integration in power electronics. [Internet] [Doctoral dissertation]. Delft University of Technology; 2005. [cited 2021 Feb 28].
Available from: http://resolver.tudelft.nl/uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1 ; urn:NBN:nl:ui:24-uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1 ; urn:NBN:nl:ui:24-uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1 ; http://resolver.tudelft.nl/uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1.
Council of Science Editors:
Popovic J. Improving packaging and increasing the level of integration in power electronics. [Doctoral Dissertation]. Delft University of Technology; 2005. Available from: http://resolver.tudelft.nl/uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1 ; urn:NBN:nl:ui:24-uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1 ; urn:NBN:nl:ui:24-uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1 ; http://resolver.tudelft.nl/uuid:68ef1d61-f3c3-43e8-bacd-d2e97bd0baa1
7.
Dimarino, Christina Marie.
Design and Validation of a High-Density 10 kV Silicon Carbide MOSFET Power Module with Reduced Electric Field Strength and Integrated Common-Mode Screen.
Degree: PhD, Electrical Engineering, 2019, Virginia Tech
URL: http://hdl.handle.net/10919/86596
► Electricity is the fastest-growing type of end-use energy consumption in the world, and its generation and usage trends are changing. Hence, the power electronics that…
(more)
▼ Electricity is the fastest-growing type of end-use energy consumption in the world, and its generation and usage trends are changing. Hence, the power
electronics that control the flow and conversion of electrical energy are an important research area. Advanced power
electronics with improved efficiency, power density, reliability, and functionality are critical in data center, transportation, motor drive, renewable energy, and grid applications, among others. Wide-bandgap power semiconductors are enabling power
electronics to meet these growing demands, and have thus begun appearing in commercial products, such as traction and solar inverters. Looking ahead, even greater strides can be made in medium-voltage systems due to the development of silicon carbide power devices with voltage ratings exceeding 10 kV. The ability of these devices to switch higher voltages faster and with lower losses than existing semiconductor technologies will drastically reduce the size, weight, and complexity of medium-voltage systems. However, these devices also bring new challenges for designers. This dissertation will present a package for 10 kV silicon carbide power MOSFETs that addresses the enhanced electric fields, greater electromagnetic interference, worsened dynamic imbalance, and higher heat flux issues associated with the
packaging of these unique devices. Specifically, due to the low and balanced parasitic inductances, the power module prototype is able to switch at record speeds of tens of nanoseconds with negligible ringing and voltage overshoot. An integrated common-mode current screen contains the current that is generated by these fast voltage transients within the power module, rather than flowing to the system ground. This screen connection simultaneously increases the partial discharge inception voltage by reducing the electric field strength at the triple point of the insulating ceramic substrate. Further, field-grading plates are used in the bus bar to reduce the electric field strength at the module terminations. The heat flux is addressed by employing direct-substrate, jet-impingement cooling. The cooler is integrated into the module housing for increased power density.
Advisors/Committee Members: Burgos, Rolando (committeechair), Boroyevich, Dushan (committeechair), Guido, Louis J. (committee member), Johnson, Mark (committee member), De La Reelopez, Jaime (committee member).
Subjects/Keywords: power electronics; silicon carbide; packaging; high voltage; electromagnetic interference
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APA (6th Edition):
Dimarino, C. M. (2019). Design and Validation of a High-Density 10 kV Silicon Carbide MOSFET Power Module with Reduced Electric Field Strength and Integrated Common-Mode Screen. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/86596
Chicago Manual of Style (16th Edition):
Dimarino, Christina Marie. “Design and Validation of a High-Density 10 kV Silicon Carbide MOSFET Power Module with Reduced Electric Field Strength and Integrated Common-Mode Screen.” 2019. Doctoral Dissertation, Virginia Tech. Accessed February 28, 2021.
http://hdl.handle.net/10919/86596.
MLA Handbook (7th Edition):
Dimarino, Christina Marie. “Design and Validation of a High-Density 10 kV Silicon Carbide MOSFET Power Module with Reduced Electric Field Strength and Integrated Common-Mode Screen.” 2019. Web. 28 Feb 2021.
Vancouver:
Dimarino CM. Design and Validation of a High-Density 10 kV Silicon Carbide MOSFET Power Module with Reduced Electric Field Strength and Integrated Common-Mode Screen. [Internet] [Doctoral dissertation]. Virginia Tech; 2019. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/10919/86596.
Council of Science Editors:
Dimarino CM. Design and Validation of a High-Density 10 kV Silicon Carbide MOSFET Power Module with Reduced Electric Field Strength and Integrated Common-Mode Screen. [Doctoral Dissertation]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/86596
Virginia Tech
8.
Lostetter, Alexander B.
Miniaturization, Packaging, and Thermal Analysis of Power Electronics Modules.
Degree: MS, Electrical and Computer Engineering, 1998, Virginia Tech
URL: http://hdl.handle.net/10919/30909
► High power circuits, those involving high levels of voltages and currents to produce several kilowatts of power, would possess an optimized efficiency when driven at…
(more)
▼ High power circuits, those involving high levels of voltages and currents to produce several kilowatts of power, would possess an optimized efficiency when driven at high frequencies (on the order of MHz). Such an approach would greatly reduce the size of capacitive and magnetic components, and thus ultimately reduce the cost of the power electronic circuits. The problem with this strategy in conventional
packaging, however, is that at high frequencies, interconnects between the power devices on one board (such as Power MOSFETs or IGBTs) and components on another board (such as the coasting diodes) suffer from severe parasitic effects, thus affecting the overall electrical performance of the system. A conceivable solution to this problem is the design and construction of a power
electronics module which would incorporate all power devices and supporting circuitry into one very simple and compact module. Such an approach would reduce interconnect inductances (thus reducing costly parasitic effects), increase system efficiency and electrical performance, produce a standardization for power electronic modules, and through this standardization, lower overall industry-wide system costs and increase power electronic system reliability. This technology would prove especially valuable for power
electronics in industry, where prevalent power systems such as half bridge or full bridge converters would benefit greatly from the large reduction of inductances which currently exist between separate bridge legs.
This thesis will discuss a novel multilayer approach towards the described issues. A power module has been designed and fabricated which contains one metallization power layer for the power devices, and a second metallization control layer for the low power signal components. The two layers are separated by a dielectric layer which serves as an electrical separation and as a physical spacer. In addition, issues have been addressed towards optimal physical layout and construction (with regards to thermal dissipation), materials comparisons have been made, and thermal simulations and experimental verifications performed.
Issues relating to standardized power electronic module design and the efforts of this researcher at the Microelectronics Laboratories at Virginia Polytechnic Institute and State University to contribute to this quickly evolving field will be discussed. Such topics as power electronic module design, control and driver circuitry design, material issues, and thermal issues will be discussed.
Advisors/Committee Members: Elshabini-Riad, Aicha A. (committeechair), Besieris, Ioannis M. (committee member), Raman, Sanjay (committee member).
Subjects/Keywords: power electronics; thermal analysis; packaging
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APA (6th Edition):
Lostetter, A. B. (1998). Miniaturization, Packaging, and Thermal Analysis of Power Electronics Modules. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/30909
Chicago Manual of Style (16th Edition):
Lostetter, Alexander B. “Miniaturization, Packaging, and Thermal Analysis of Power Electronics Modules.” 1998. Masters Thesis, Virginia Tech. Accessed February 28, 2021.
http://hdl.handle.net/10919/30909.
MLA Handbook (7th Edition):
Lostetter, Alexander B. “Miniaturization, Packaging, and Thermal Analysis of Power Electronics Modules.” 1998. Web. 28 Feb 2021.
Vancouver:
Lostetter AB. Miniaturization, Packaging, and Thermal Analysis of Power Electronics Modules. [Internet] [Masters thesis]. Virginia Tech; 1998. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/10919/30909.
Council of Science Editors:
Lostetter AB. Miniaturization, Packaging, and Thermal Analysis of Power Electronics Modules. [Masters Thesis]. Virginia Tech; 1998. Available from: http://hdl.handle.net/10919/30909
Virginia Tech
9.
Webster, James R.
Thin Film Polymer Dielectrics for High-Voltage Applications under Severe Environments.
Degree: MS, Electrical Engineering, 1998, Virginia Tech
URL: http://hdl.handle.net/10919/36887
► This thesis presents the results of research into the performance of advanced polymer dielectrics for the realization of high-power electronic circuits in a miniature form.…
(more)
▼ This thesis presents the results of research into the performance of advanced polymer
dielectrics for the realization of high-power electronic circuits in a miniature form. These
polymeric materials must satisfy a number of critical thermal, environmental, and
electrical requirements to meet the required performance criteria for microelectronics
applications. These desired attributes include thermal stability, low moisture uptake, high
breakdown voltage (low leakage current), low dielectric constant, low loss tangent, high
glass transition temperature, and low surface roughness. The use of these polymers
allows for advanced electronic
packaging techniques, resulting in improved system
performance and reliability.
Research was performed using a commercially available polymer dielectric and evaluated
the feasibility of utilizing these materials as interlayer dielectrics in multilayer power
electronic circuits. Historically, efforts to develop advanced interlayer dielectric
materials have concentrated on promoting their use in high speed digital circuits.
However, dielectrics used in power
electronics must meet requirements not commonly
stressed in designs for digital circuits. Multilayer circuits used in power
electronics place
a particular emphasis on the material properties of high dielectric strength or breakdown
voltage and small values for loss tangent or dissipation factor. The focus of this research
has been to characterize these particular properties for a commercially available polymer
dielectric.
Advisors/Committee Members: Elshabini-Riad, Aicha A. (committeechair), Desu, Seshu B. (committee member), Murphy, Kent A. (committee member), McGrath, James E. (committee member), Garrou, Philip E. (committee member).
Subjects/Keywords: Polymer; Dielectric; Electronics; Packaging
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APA (6th Edition):
Webster, J. R. (1998). Thin Film Polymer Dielectrics for High-Voltage Applications under Severe Environments. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/36887
Chicago Manual of Style (16th Edition):
Webster, James R. “Thin Film Polymer Dielectrics for High-Voltage Applications under Severe Environments.” 1998. Masters Thesis, Virginia Tech. Accessed February 28, 2021.
http://hdl.handle.net/10919/36887.
MLA Handbook (7th Edition):
Webster, James R. “Thin Film Polymer Dielectrics for High-Voltage Applications under Severe Environments.” 1998. Web. 28 Feb 2021.
Vancouver:
Webster JR. Thin Film Polymer Dielectrics for High-Voltage Applications under Severe Environments. [Internet] [Masters thesis]. Virginia Tech; 1998. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/10919/36887.
Council of Science Editors:
Webster JR. Thin Film Polymer Dielectrics for High-Voltage Applications under Severe Environments. [Masters Thesis]. Virginia Tech; 1998. Available from: http://hdl.handle.net/10919/36887
Virginia Tech
10.
Ralston, Parrish Elaine.
Design and Characterization of Liquid Metal Flip Chip Interconnections for Heterogeneous Microwave Assemblies.
Degree: PhD, Electrical Engineering, 2013, Virginia Tech
URL: http://hdl.handle.net/10919/50641
► Flip chip interconnections have superior performance for microwave applications compared to wire bond interconnections because of their reduced parasitics, more compact architecture, and flexibility in…
(more)
▼ Flip chip interconnections have superior performance for microwave applications compared to wire bond interconnections because of their reduced parasitics, more compact architecture, and flexibility in laying out flip chip bond pads. Reduction in interconnect parasitics enables these interconnects to support broadband signals, therefore increasing the bandwidth capabilities of flip chip-assembled systems. Traditional flip chip designs provide mechanical and electrical connections from a top chip to a carrier substrate with rigid solder joints. For heterogeneous assemblies, flip chip connections suffer from thermo-mechanical failures caused by coefficient of thermal expansion mismatches. As an alternative, flexible flip chip interconnections incorporating a metal, which is liquid at room temperature, mitigates the possibility of such thermo-mechanical failures. Additionally, liquid metal, flip chip interconnections allow for room temperature assembly, simplifying assembly and rework processes.
This dissertation focuses on the design and characterization of liquid metal interconnections, specifically using Galinstan, an alloy of gallium indium and tin, for the heterogeneous assembly of active monolithic microwave integrated circuits (MMICs) onto a CTE mismatched substrate. Carrier substrates designed for liquid metal transitions were fabricated on high resistivity Si and on three dimensional copper structures. The three dimensional copper structures were fabricated in the PolyStrata™ process. Individual MMIC chips were post-processed to mate with carrier substrates in a liquid metal, flip chip configuration. S-parameter measurements of prototype MMIC assemblies with liquid metal, flip chip interconnections showed an average transition loss of 0.7dB over the MMIC's frequency of operation (4.9 - 8.5 GHz). Passive assemblies were also fabricated to characterize the power and temperature performance of liquid metal transitions. Liquid metal interconnections show excellent power handling, maintaining consistent RF performance while transmitting 100W of continuous wave power for an hour. Liquid metal interconnections were also tested following 200 temperature cycles over the -140°C – 125°C range. A comparison of S parameter measurements taken before and after temperature cycling, over a frequency range of 10MHz - 40GHz showed no significant changes in performance. These passive assemblies were also used to develop a lumped element model of the interconnection which is useful for the verification the interconnection\'s performance and for comparison of liquid metal interconnection parasitic to wire bond and flip chip interconnect parasitics.
The experimental results presented in this dissertation confirm that liquid metal interconnect are viable for wider use in military and commercial applications. In the future, additional environmental testing and further refinement of the processing flow, such as improved contact metallurgy, are needed to make this interconnect approach more viable for large volume manufacturing.
Advisors/Committee Members: Raman, Sanjay (committeechair), Orlowski, Mariusz Kriysztof (committee member), Agah, Masoud (committee member), Bostian, Charles W. (committee member), Paul, Mark R. (committee member).
Subjects/Keywords: liquid metal; electronics packaging; flip chip; 3D integration; MMIC integration
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APA (6th Edition):
Ralston, P. E. (2013). Design and Characterization of Liquid Metal Flip Chip Interconnections for Heterogeneous Microwave Assemblies. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/50641
Chicago Manual of Style (16th Edition):
Ralston, Parrish Elaine. “Design and Characterization of Liquid Metal Flip Chip Interconnections for Heterogeneous Microwave Assemblies.” 2013. Doctoral Dissertation, Virginia Tech. Accessed February 28, 2021.
http://hdl.handle.net/10919/50641.
MLA Handbook (7th Edition):
Ralston, Parrish Elaine. “Design and Characterization of Liquid Metal Flip Chip Interconnections for Heterogeneous Microwave Assemblies.” 2013. Web. 28 Feb 2021.
Vancouver:
Ralston PE. Design and Characterization of Liquid Metal Flip Chip Interconnections for Heterogeneous Microwave Assemblies. [Internet] [Doctoral dissertation]. Virginia Tech; 2013. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/10919/50641.
Council of Science Editors:
Ralston PE. Design and Characterization of Liquid Metal Flip Chip Interconnections for Heterogeneous Microwave Assemblies. [Doctoral Dissertation]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/50641
Virginia Tech
11.
Collins, Gustina Bernette.
Laser Processing of Polyimide on Copper.
Degree: MS, Electrical and Computer Engineering, 2001, Virginia Tech
URL: http://hdl.handle.net/10919/32559
► While work using a laser for processing a polymer dielectric is currently being studied, the purpose of this thesis is to present an effective and…
(more)
▼ While work using a laser for processing a polymer dielectric is currently being studied, the purpose of this thesis is to present an effective and economical approach using laboratory equipment that is most commonly used and available for the processing of materials including polymers and metals. The use of a laser allows for a more cost effective and flexible method for processing polyimide over other wet and dry processes.
This thesis represents the results of research on the laser processing of polyimide on copper. The research examines the effect of the laser processing parameters using a CO2 laser. The parameters examined include the pulse width, repetition rate, and number of pulses. The processed samples include freestanding Kapton with no adhesive layer, freestanding Kapton with an adhesive layer, and Kapton with adhesive layered on copper. The laser processing used a single laser shot with the parameters being varied over a series of shots fired. The effect of the parameters was observed over large and small ranges. The characteristics of processed freestanding samples were graphically presented along with captured images. The results demonstrate that the laser processing of polyimide is strongly dependent on the laser pulse width and that the optimum value from these experiments suggest the use of a pulse width of 60ms for using a CO2 laser. From these results, further considerations for the laser processing of polyimide on copper were given.
Advisors/Committee Members: Lu, Guo-Quan (committeechair), Scales, Wayne A. (committee member), Raman, Sanjay (committee member).
Subjects/Keywords: electronics; packaging; copper; laser; polymer
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APA (6th Edition):
Collins, G. B. (2001). Laser Processing of Polyimide on Copper. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/32559
Chicago Manual of Style (16th Edition):
Collins, Gustina Bernette. “Laser Processing of Polyimide on Copper.” 2001. Masters Thesis, Virginia Tech. Accessed February 28, 2021.
http://hdl.handle.net/10919/32559.
MLA Handbook (7th Edition):
Collins, Gustina Bernette. “Laser Processing of Polyimide on Copper.” 2001. Web. 28 Feb 2021.
Vancouver:
Collins GB. Laser Processing of Polyimide on Copper. [Internet] [Masters thesis]. Virginia Tech; 2001. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/10919/32559.
Council of Science Editors:
Collins GB. Laser Processing of Polyimide on Copper. [Masters Thesis]. Virginia Tech; 2001. Available from: http://hdl.handle.net/10919/32559
Delft University of Technology
12.
Giannoulakis, Evangelos (author).
Optimizing Packaging Availability for Reverse Logistics: A case study at ASML.
Degree: 2018, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:5d4b42b5-685c-4bec-b347-62c4d45a6c99
► Background: The domain of Reverse Logistics, which is lately coming more in the forefront, will serve as the focal point of this project. In the…
(more)
▼ Background: The domain of Reverse Logistics, which is lately coming more in the forefront, will serve as the focal point of this project. In the
electronics industry, the importance of facilitating safe movements is constantly increasing. In order to prevent escalating the chances of damage, products have to be transported with adequate protective layers. Nevertheless, shipments with incomplete
packaging are occurring, leading to damaged products arriving at the supplier side. This research aims to explore how can the
packaging availability for reverse logistics be optimized in order to reduce the risk of non-repairable parts. Research Approach: The steps of the Lean approach named Define Measure Analyze Design Evaluate (DMADE) will form the backbone of the project. Literature revealed congruence on the fact that Reverse Logistics
packaging is a common barrier for establishing efficient return flows. A case study at ASML is performed and the structure of the supply chain and the
packaging flows are explained. Next to that, the most relevant product family is identified and the current performance of the system, in terms of
packaging availability, is measured. The analysis of the current state, with the usage of 3 Lean tools (VSM-I, TIMWOODS, Ishikawa diagram), follows and based on the analysis outcomes, 9 conceptual designs are introduced in the design phase. In order to eliminate the less relevant ones, a Multi-Criteria Analysis is performed and after the requirement analysis is taken into consideration, the 2 most promising design alternatives are explained in more detail. Lastly, the evaluation phase with the mathematical model comes to assess how well each of the generated scenarios score in the decision parameter criteria. These are the Repair Success Rate, the Financial Performance and the fit with the Lean strategy. Results: After the evaluation took place, it was proved that scenario 1 results in the higher Repair Success Rate (70%), but the associated financial performance of €4,5K is barely positive. This scenario also leads to the shortest replenishment lead times of 45 days and the minimum stock levels. Scenario 3 proves to yield the highest earnings, leading to €485K, with significant tied-up capital release. As for scenario 2, the financial loss of €144K combined with the intermediate lead time and Repair Success Rate of 61% make it less attractive. Finally, scenario 4 is expected to have the highest risk of non-repairable parts (52%) and the greatest lead time of 64 days. Nevertheless, the economic gains of €267K might still place this alternative in the favorable bucket. Conclusion: The risk of supplying vendors with non-repairable parts can be truly alleviated by the installation of inspections gates and more precisely with clean bench equipment. This design will form a structural solution enabling a feedback loop towards the required stakeholders (CS Engineers, Development & Engineering) while allowing at the same time root-cause resolution of the issues found. Clean bench inspections will…
Advisors/Committee Members: Vleugel, Jaap (mentor), Beelaerts van Blokland, Wouter (mentor), Negenborn, Rudy (mentor), Delft University of Technology (degree granting institution).
Subjects/Keywords: Reverse logistics; Supply Chain Management; Electronics; Value stream mapping; packaging; ASML
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APA (6th Edition):
Giannoulakis, E. (. (2018). Optimizing Packaging Availability for Reverse Logistics: A case study at ASML. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:5d4b42b5-685c-4bec-b347-62c4d45a6c99
Chicago Manual of Style (16th Edition):
Giannoulakis, Evangelos (author). “Optimizing Packaging Availability for Reverse Logistics: A case study at ASML.” 2018. Masters Thesis, Delft University of Technology. Accessed February 28, 2021.
http://resolver.tudelft.nl/uuid:5d4b42b5-685c-4bec-b347-62c4d45a6c99.
MLA Handbook (7th Edition):
Giannoulakis, Evangelos (author). “Optimizing Packaging Availability for Reverse Logistics: A case study at ASML.” 2018. Web. 28 Feb 2021.
Vancouver:
Giannoulakis E(. Optimizing Packaging Availability for Reverse Logistics: A case study at ASML. [Internet] [Masters thesis]. Delft University of Technology; 2018. [cited 2021 Feb 28].
Available from: http://resolver.tudelft.nl/uuid:5d4b42b5-685c-4bec-b347-62c4d45a6c99.
Council of Science Editors:
Giannoulakis E(. Optimizing Packaging Availability for Reverse Logistics: A case study at ASML. [Masters Thesis]. Delft University of Technology; 2018. Available from: http://resolver.tudelft.nl/uuid:5d4b42b5-685c-4bec-b347-62c4d45a6c99
13.
Letowski, Bastien.
Intégration technologique alternative pour l'élaboration de modules électroniques de puissance : Advanced technological integration for power electronics modules.
Degree: Docteur es, Génie électrique, 2016, Université Grenoble Alpes (ComUE)
URL: http://www.theses.fr/2016GREAT114
► Les performances, l’encombrement, l’efficacité et la fiabilité des dispositifs sont parmi les enjeux majeurs de l’électronique de puissance. Ils se traduisent sur la conception, la…
(more)
▼ Les performances, l’encombrement, l’efficacité et la fiabilité des dispositifs sont parmi les enjeux majeurs de l’électronique de puissance. Ils se traduisent sur la conception, la fabrication et le packaging des semiconducteurs. Aujourd’hui, le packaging 3D apporte des réponses concrètes à ces problématiques en regard de l’approche standard (2D). Malgré les excellentes propriétés de ces modules 3D au niveau de la réduction de la signature CEM et du refroidissement, la réalisation, notamment les interconnexions, est complexe. Une approche globale prenant en compte un maximum de paramètres a été développée dans cette thèse. L’ensemble de ce travail s’appuie sur deux propositions que sont la conception couplée entre les composants et le packaging ainsi qu’une fabrication collective à l’échelle de la plaque des modules de puissance. Elles se combinent par la mise en place d’une filière d’étapes technologiques appuyée sur une boite à outils de procédés génériques. Cette approche est concrétisée par la réalisation d’un module de puissance 3D performant et robuste adressant des convertisseurs polyphasés avec des gains aussi bien sur les procédés de fabrication que le module lui-même ainsi que sur le système final.Ce travail offre une nouvelle vision alternative pour l’élaboration des modules électroniques de puissance. Il ouvre également des opportunités pour une fabrication et un packaging plus performants pour les nouveaux semiconducteurs grand gap.
Performances, efficiency and reliability are among the main issues in power electronics. Nowadays, 3D packaging solutions increase standard planar module (2D) performances, for instance EMC. However such integrations are based on complex manufacturing, especially concerning interconnections. Improvements require global and advanced solutions. This work depends on two proposed concepts: a coupled design of the power devices and their associated package and a collective wafer-level process fabrication. A technological offer is proposed based on an innovative power packaging toolbox. Our approach is materialized by the fabrication of a 3D polyphase power module which proved to be more efficient and reliable. The benefits are more precise process manufacturing, lower EMI generation and lower inductive interconnections.As a matter of fact, this work offers a new and advanced technological integration for future power electronics modules, perfectly suitable for the wide bandgap semiconductors.
Advisors/Committee Members: Crebier, Jean-Christophe (thesis director).
Subjects/Keywords: Electronique de puissance; Packaging 3D; Conception couplé composant/packaging; Collage direct métal-Métal; Fabrication collective; Packaging à l’échelle de la plaque; Power Electronics; 3D packaging; Wire-Bond-Less module; Wafer-Level packaging; Direct copper bonding; Coupled design device/package; 620
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APA (6th Edition):
Letowski, B. (2016). Intégration technologique alternative pour l'élaboration de modules électroniques de puissance : Advanced technological integration for power electronics modules. (Doctoral Dissertation). Université Grenoble Alpes (ComUE). Retrieved from http://www.theses.fr/2016GREAT114
Chicago Manual of Style (16th Edition):
Letowski, Bastien. “Intégration technologique alternative pour l'élaboration de modules électroniques de puissance : Advanced technological integration for power electronics modules.” 2016. Doctoral Dissertation, Université Grenoble Alpes (ComUE). Accessed February 28, 2021.
http://www.theses.fr/2016GREAT114.
MLA Handbook (7th Edition):
Letowski, Bastien. “Intégration technologique alternative pour l'élaboration de modules électroniques de puissance : Advanced technological integration for power electronics modules.” 2016. Web. 28 Feb 2021.
Vancouver:
Letowski B. Intégration technologique alternative pour l'élaboration de modules électroniques de puissance : Advanced technological integration for power electronics modules. [Internet] [Doctoral dissertation]. Université Grenoble Alpes (ComUE); 2016. [cited 2021 Feb 28].
Available from: http://www.theses.fr/2016GREAT114.
Council of Science Editors:
Letowski B. Intégration technologique alternative pour l'élaboration de modules électroniques de puissance : Advanced technological integration for power electronics modules. [Doctoral Dissertation]. Université Grenoble Alpes (ComUE); 2016. Available from: http://www.theses.fr/2016GREAT114
Texas A&M University
14.
Chiang, Juei-Chun.
Design and characterization of nanowire array as thermal interface material for electronics packaging.
Degree: MS, Mechanical Engineering, 2009, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-3188
► To allow electronic devices to operate within allowable temperatures, heat sinks and fans are employed to cool down computer chips. However, cooling performance is limited…
(more)
▼ To allow electronic devices to operate within allowable temperatures, heat sinks and fans are employed to cool down computer chips. However, cooling performance is limited by air gaps between the computer chip and the heat sink, due to the fact that air is a poor heat conductor. To alleviate this problem, thermal interface material (TIM) is often applied between mating substrates to fill air gaps. Carbon nanotube (CNT) based TIM has been reported to have excellent thermal impedance; however, because it is non biodegradable, its potential impact on the environment is a concern. In this thesis research, two types of TIMs were designed, synthesized, and characterized. The first type, Designed TIM 1, consisted of anodic aluminum oxide (AAO) templates with nanochannels (pore size=80nm) embedded with copper nanowires by electrodeposition. This type of nanostructure was expected to have low thermal impedance because the forest-like structure of copper nanowires can bridge two mating surfaces and efficiently transport heat one dimensionally from one substrate to the other.
The second type, Designed TIM 2, was fabricated by sandwiching Designed TIM 1 with commercially available thermal grease to further reduce thermal impedance. It was expected that the copper nanowire structures would secure the thermal grease in place, thus preventing grease pump-out under contact pressure, which is a common problem associated with the usage of thermal grease. The morphologies of the two designed TIMs were studied using scanning electron microscopy (SEM), and their thermal properties were determined using ASTM D5470-06, the standard method for testing thermal transmission properties of thermally conductive materials. Experiments were conducted to evaluate the proposed TIMs, as well as commercially available TIMs, under different temperature and pressure settings. Experimental results suggest that the thermal impedance of TIMs can be reduced by increasing contact pressure or reducing thickness. Designed TIM 2 yielded 0.255℃-cm2/W, which is lower than thermal grease and other available TIMs at the operating temperature of 50 to 60℃. Considering the application limitations and safety issues of thermal grease, phase change material, and CNT-based TIMs, our designed TIMs are safe and promising for future applications.
Advisors/Committee Members: Hsieh, Sheng-Jen (Tony) (advisor), Kameoka, Jun (committee member), Suh, Steve (committee member).
Subjects/Keywords: Nanowire; thermal interface material; electronics packaging
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APA (6th Edition):
Chiang, J. (2009). Design and characterization of nanowire array as thermal interface material for electronics packaging. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-3188
Chicago Manual of Style (16th Edition):
Chiang, Juei-Chun. “Design and characterization of nanowire array as thermal interface material for electronics packaging.” 2009. Masters Thesis, Texas A&M University. Accessed February 28, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-3188.
MLA Handbook (7th Edition):
Chiang, Juei-Chun. “Design and characterization of nanowire array as thermal interface material for electronics packaging.” 2009. Web. 28 Feb 2021.
Vancouver:
Chiang J. Design and characterization of nanowire array as thermal interface material for electronics packaging. [Internet] [Masters thesis]. Texas A&M University; 2009. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-3188.
Council of Science Editors:
Chiang J. Design and characterization of nanowire array as thermal interface material for electronics packaging. [Masters Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-3188
Western Michigan University
15.
Ma, Ruoxi.
Screen Printed Moisture Sensor On Barrier Coated SBS Board: The Characterizations of the Hemicellulose-Based Biofilms and Their Applications for Smart Packaging.
Degree: PhD, Chemical and Paper Engineering, 2018, Western Michigan University
URL: https://scholarworks.wmich.edu/dissertations/3327
► Fiber-based packaging materials have many advantages over their petroleum-based plastic competitors, such as sustainability, recyclability and stiffness/weight ratio. However, the poor barrier properties and…
(more)
▼ Fiber-based
packaging materials have many advantages over their petroleum-based plastic competitors, such as sustainability, recyclability and stiffness/weight ratio. However, the poor barrier properties and sensitivity towards moisture are the main challenges for their extended use. Therefore, there has been a need to provide a biodegradable and biocompatible biopolymer
packaging material with improved barrier properties for food and pharmaceutical
packaging. Also, the moisture loss/gain problem causes a lot of waste every year. Therefore, there is a need of better tracking and sensing methods attached to the package in order to control the moisture level along the supply chain. To accomplish these goals, three studies have been designed: a) The preparation of the hemicellulose-based films and the characterization of surface, strength and printability properties. b) The barrier properties of the hemicellulose-based biofilm were characterized with moisture vapor transmission rate. The hydrophobic property and moisture barrier property of hemicellulose-based biopolymer were improved by crosslinking with citric acid and further characterized by moisture vapor transmission rate (MVTR). c) The barrier coating was formulated and applied to the back side of solid bleached sulphate (SBS) board and was screen printed with a moisture sensor. The moisture sensor was characterized by its impedance with various relative humidity ranges. The findings provide the possibility of combining the hemicellulose-based biodegradable barrier coatings with printed moisture sensors in order to boost their capabilities in smart
packaging applications.
Advisors/Committee Members: Dr. Alexandra Pekarovicova, Dr. Paul D. Fleming III, Dr. Veronika Husovska.
Subjects/Keywords: Barrier coating; smart packaging; printed electronics; moisture sensor; glucomannan; hemicellulose; Chemical Engineering
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APA (6th Edition):
Ma, R. (2018). Screen Printed Moisture Sensor On Barrier Coated SBS Board: The Characterizations of the Hemicellulose-Based Biofilms and Their Applications for Smart Packaging. (Doctoral Dissertation). Western Michigan University. Retrieved from https://scholarworks.wmich.edu/dissertations/3327
Chicago Manual of Style (16th Edition):
Ma, Ruoxi. “Screen Printed Moisture Sensor On Barrier Coated SBS Board: The Characterizations of the Hemicellulose-Based Biofilms and Their Applications for Smart Packaging.” 2018. Doctoral Dissertation, Western Michigan University. Accessed February 28, 2021.
https://scholarworks.wmich.edu/dissertations/3327.
MLA Handbook (7th Edition):
Ma, Ruoxi. “Screen Printed Moisture Sensor On Barrier Coated SBS Board: The Characterizations of the Hemicellulose-Based Biofilms and Their Applications for Smart Packaging.” 2018. Web. 28 Feb 2021.
Vancouver:
Ma R. Screen Printed Moisture Sensor On Barrier Coated SBS Board: The Characterizations of the Hemicellulose-Based Biofilms and Their Applications for Smart Packaging. [Internet] [Doctoral dissertation]. Western Michigan University; 2018. [cited 2021 Feb 28].
Available from: https://scholarworks.wmich.edu/dissertations/3327.
Council of Science Editors:
Ma R. Screen Printed Moisture Sensor On Barrier Coated SBS Board: The Characterizations of the Hemicellulose-Based Biofilms and Their Applications for Smart Packaging. [Doctoral Dissertation]. Western Michigan University; 2018. Available from: https://scholarworks.wmich.edu/dissertations/3327
16.
Bajad, Nupur.
Design of Experiment Analysis of an Electronics Package Lid Using Finite Element Analysis.
Degree: MSIE, 2017, Binghamton University
URL: https://orb.binghamton.edu/dissertation_and_theses/53
► A design of experiment analysis is reported on data from warpage simulations using finite element analysis of a lidded electronics package. Warpage in a…
(more)
▼ A design of experiment analysis is reported on data from warpage simulations using finite element analysis of a lidded
electronics package. Warpage in a lid of an optical
electronics package can detrimentally affect the reliability of the package as well as its optical performance. The present study focuses on the variety of materials and designs of lids relevant to recent technologies in
electronics packaging. The finite element analysis (FEA) formulation in this study accurately predicts deformation and warpage in the elastic region with optimal computational time achieved through a choice of boundary conditions and mesh sensitivity studies.
The results from FEA are compared to analytical calculations made using the classical laminate plate theory (CLPT) as well as the modified Suhir’s theory. It is observed that FEA results are more accurate as they account for the performance of die attach/ underfill materials regardless of the small thickness of the layer. The FEA data are finally used to conduct a design of experiments (DOE) analysis to investigate the influence of 3 distinct designs and 6 material choices on warpage of a lid. The analysis indicates that there is no significant interaction between the two parameters expected to affect the warpage in the lid. Material properties of the lid are found to have a greater effect on the warpage of the lid as compared to variabilities introduced in lid designs in this study. The FEA simulations performed consider only material behavior within the elastic limit and, in some situations, plastic deformation may occur which is more permanent and as such requires a more comprehensive analysis in the plastic region to enhance the data set for DOE studies.
Advisors/Committee Members: Dr. Daryl Santos.
Subjects/Keywords: Applied sciences; Design of experiment; Electronics packaging; Finite element analysis; Parametric analysis; Engineering
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APA (6th Edition):
Bajad, N. (2017). Design of Experiment Analysis of an Electronics Package Lid Using Finite Element Analysis. (Thesis). Binghamton University. Retrieved from https://orb.binghamton.edu/dissertation_and_theses/53
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Bajad, Nupur. “Design of Experiment Analysis of an Electronics Package Lid Using Finite Element Analysis.” 2017. Thesis, Binghamton University. Accessed February 28, 2021.
https://orb.binghamton.edu/dissertation_and_theses/53.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Bajad, Nupur. “Design of Experiment Analysis of an Electronics Package Lid Using Finite Element Analysis.” 2017. Web. 28 Feb 2021.
Vancouver:
Bajad N. Design of Experiment Analysis of an Electronics Package Lid Using Finite Element Analysis. [Internet] [Thesis]. Binghamton University; 2017. [cited 2021 Feb 28].
Available from: https://orb.binghamton.edu/dissertation_and_theses/53.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Bajad N. Design of Experiment Analysis of an Electronics Package Lid Using Finite Element Analysis. [Thesis]. Binghamton University; 2017. Available from: https://orb.binghamton.edu/dissertation_and_theses/53
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Hong Kong University of Science and Technology
17.
Bi, Xianghong.
Evaluation of graphene oxide - silicone die attach adhesive in LED packaging.
Degree: 2014, Hong Kong University of Science and Technology
URL: http://repository.ust.hk/ir/Record/1783.1-70835
;
https://doi.org/10.14711/thesis-b1333627
;
http://repository.ust.hk/ir/bitstream/1783.1-70835/1/th_redirect.html
► The successful wide application of LED lighting in general lighting market requires reduction in product cost, among which, LED packaging cost is proved to be…
(more)
▼ The successful wide application of LED lighting in general lighting market requires reduction in product cost, among which, LED packaging cost is proved to be the majority. Apparently, direct decline production expense on package can efficiently reduce the production cost. Besides, LED luminous flux increase is another way to reach the similar target. In this way, thermal management in LED packaging should be considered as to adjust luminous performance of LED. Lower junction temperature can result in higher luminous flux, especially for high power LED. Considering all the structures, die attach adhesive (DAA) is proved to have great influence on heat dissipation in LED packaging. Therefore, in order to enhance thermal dissipation, a good method is to increase the thermal conductivity of DAA, which is exactly what we conducted in this thesis. Specifically, multilayer graphene oxide (GO) was successfully synthesized and characterized. After adding GO into silicone DAA, the transmittance and die shear strength of the mixture were comparable with origins. The thermal conductivity performance was characterized by 3ω method and laser flash method. The former experimental results showed big deviations of the local thermal conductivity between different test places. The average results indicate there was a 66% increase in local thermal conductivity of GO-silicone DAA (0.4 ωt% GO loading), comparing with the origins. However, the laser flash method results showed there was no apparent change in overall thermal conductivity when introducing GO. Nanoscale corrugation, crumpling, wrinkling and folding of GO were found in silicone matrix, which resulted in low K∗eff. GO tended to be perpendicular to the heat flux, resulting in no effort on the overall thermal conductivity of the composite. In conclusion, there are three highlights for the thesis: 1) From the viewpoint of improving thermal management so as to reduce product cost, this study successfully build up the connection between LED packaging industry and market, which will be a great guidance for LED manufacturers; 2) This study discovered the critical K∗eff for LED DAA, which was 0.5W/(m ∙ K). Lower thermal conductivity values generated bad thermal dissipation while higher values led to neglectable enhancement ; 3) Controlling GO orientation is crucial to improve the thermal conductivity of GO-silicone. It is practical to reach the critical K∗eff in this way, so that the final lighting cost can be reduced;
Subjects/Keywords: Light emitting diodes
; Graphene
; Oxidation
; Solid state electronics
; Synthesis
; Microelectronic packaging
; Materials
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APA (6th Edition):
Bi, X. (2014). Evaluation of graphene oxide - silicone die attach adhesive in LED packaging. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-70835 ; https://doi.org/10.14711/thesis-b1333627 ; http://repository.ust.hk/ir/bitstream/1783.1-70835/1/th_redirect.html
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Bi, Xianghong. “Evaluation of graphene oxide - silicone die attach adhesive in LED packaging.” 2014. Thesis, Hong Kong University of Science and Technology. Accessed February 28, 2021.
http://repository.ust.hk/ir/Record/1783.1-70835 ; https://doi.org/10.14711/thesis-b1333627 ; http://repository.ust.hk/ir/bitstream/1783.1-70835/1/th_redirect.html.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Bi, Xianghong. “Evaluation of graphene oxide - silicone die attach adhesive in LED packaging.” 2014. Web. 28 Feb 2021.
Vancouver:
Bi X. Evaluation of graphene oxide - silicone die attach adhesive in LED packaging. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2014. [cited 2021 Feb 28].
Available from: http://repository.ust.hk/ir/Record/1783.1-70835 ; https://doi.org/10.14711/thesis-b1333627 ; http://repository.ust.hk/ir/bitstream/1783.1-70835/1/th_redirect.html.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Bi X. Evaluation of graphene oxide - silicone die attach adhesive in LED packaging. [Thesis]. Hong Kong University of Science and Technology; 2014. Available from: http://repository.ust.hk/ir/Record/1783.1-70835 ; https://doi.org/10.14711/thesis-b1333627 ; http://repository.ust.hk/ir/bitstream/1783.1-70835/1/th_redirect.html
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Arizona
18.
Omer, Ahmed Adan, 1964-.
Capacitance calculations for three-dimensional VLSI interconnection geometries
.
Degree: 1991, University of Arizona
URL: http://hdl.handle.net/10150/291396
► An integral equation formulation for the calculation of the capacitance of three-dimensional VLSI geometries is presented. A proper combination of 2D and 3D methods is…
(more)
▼ An integral equation formulation for the calculation of the capacitance of three-dimensional VLSI geometries is presented. A proper combination of 2D and 3D methods is used for efficient numerical computations. The method of moments is used for the solution of the integral equation. In addition, Green's functions that satisfy the boundary conditions at the dielectric interfaces are implemented in order to minimize the number of unknowns involved in the numerical solution. The mathematical formulation presented here and the associated computer program are appropriate for obtaining the capacitance matrix of complex three-dimensional multi-conductor configurations of the microstrip and the stripline type. Finally, numerical results for the per-unit-length capacitance and total capacitance of several interconnections are provided and compared with known results. Applications include the extraction of lumped capacitive elements used in the equivalent circuit representations of coupled conductor bends, vias and crossovers. In addition, calculations of per-unit-length capacitance of coupled flaring lines are performed.
Advisors/Committee Members: Cangellaris, Andreas (advisor).
Subjects/Keywords: Engineering, Electronics and Electrical.;
Engineering, Packaging.
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APA (6th Edition):
Omer, Ahmed Adan, 1. (1991). Capacitance calculations for three-dimensional VLSI interconnection geometries
. (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/291396
Chicago Manual of Style (16th Edition):
Omer, Ahmed Adan, 1964-. “Capacitance calculations for three-dimensional VLSI interconnection geometries
.” 1991. Masters Thesis, University of Arizona. Accessed February 28, 2021.
http://hdl.handle.net/10150/291396.
MLA Handbook (7th Edition):
Omer, Ahmed Adan, 1964-. “Capacitance calculations for three-dimensional VLSI interconnection geometries
.” 1991. Web. 28 Feb 2021.
Vancouver:
Omer, Ahmed Adan 1. Capacitance calculations for three-dimensional VLSI interconnection geometries
. [Internet] [Masters thesis]. University of Arizona; 1991. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/10150/291396.
Council of Science Editors:
Omer, Ahmed Adan 1. Capacitance calculations for three-dimensional VLSI interconnection geometries
. [Masters Thesis]. University of Arizona; 1991. Available from: http://hdl.handle.net/10150/291396
University of South Florida
19.
Carballo, Jose Miguel.
Self-Assembly Kinetics of Microscale Components: A Parametric Evaluation.
Degree: 2015, University of South Florida
URL: https://scholarcommons.usf.edu/etd/5653
► The goal of the present work is to develop, and evaluate a parametric model of a basic microscale Self-Assembly (SA) interaction that provides scaling predictions…
(more)
▼ The goal of the present work is to develop, and evaluate a parametric model of a basic microscale Self-Assembly (SA) interaction that provides scaling predictions of process rates as a function of key process variables. At the microscale, assembly by “grasp and release” is generally challenging. Recent research efforts have proposed adapting nanoscale self-assembly (SA) processes to the microscale. SA offers the potential for reduced equipment cost and increased throughput by harnessing attractive forces (most commonly, capillary) to spontaneously assemble components. However, there are challenges for implementing microscale SA as a commercial process. The existing lack of design tools prevents simple process optimization. Previous efforts have characterized a specific aspect of the SA process. However, the existing microscale SA models do not characterize the inter-component interactions. All existing models have simplified the outcome of SA interactions as an experimentally-derived value specific to a particular configuration, instead of evaluating it outcome as a function of component level parameters (such as speed, geometry, bonding energy and direction). The present study parameterizes the outcome of interactions, and evaluates the effect of key parameters. The present work closes the gap between existing microscale SA models to add a key piece towards a complete design tool for general microscale SA process modeling.
First, this work proposes a simple model for defining the probability of assembly of basic SA interactions. A basic SA interaction is defined as the event where a single part arrives on an assembly site. The model describes the probability of assembly as a function of kinetic energy, binding energy, orientation and incidence angle for the component and the assembly site. Secondly, an experimental SA system was designed, and implemented to create individual SA interactions while controlling process parameters independently. SA experiments measured the outcome of SA interactions, while studying the independent effects of each parameter.
As a first step towards a complete scaling model, experiments were performed to evaluate the effects of part geometry and part travel direction under low kinetic energy conditions. Experimental results show minimal dependence of assembly yield on the incidence angle of the parts, and significant effects induced by changes in part geometry. The results from this work indicate that SA could be modeled as an energy-based process due to the small path dependence effects. Assembly probability is linearly related to the orientation probability. The proportionality constant is based on the area fraction of the sites with an amplification factor. This amplification factor accounts for the ability of capillary forces to align parts with only very small areas of contact when they have a low kinetic energy. Results provide unprecedented insight about SA interactions. The present study is a key step towards completing a basic model of a general SA process. Moreover, the…
Subjects/Keywords: Electronics packaging; Measurement; Microassembly; Modeling; Performance evaluation; Surface tension; Materials Science and Engineering; Mechanical Engineering
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APA ·
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CSE |
Export
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APA (6th Edition):
Carballo, J. M. (2015). Self-Assembly Kinetics of Microscale Components: A Parametric Evaluation. (Thesis). University of South Florida. Retrieved from https://scholarcommons.usf.edu/etd/5653
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Carballo, Jose Miguel. “Self-Assembly Kinetics of Microscale Components: A Parametric Evaluation.” 2015. Thesis, University of South Florida. Accessed February 28, 2021.
https://scholarcommons.usf.edu/etd/5653.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Carballo, Jose Miguel. “Self-Assembly Kinetics of Microscale Components: A Parametric Evaluation.” 2015. Web. 28 Feb 2021.
Vancouver:
Carballo JM. Self-Assembly Kinetics of Microscale Components: A Parametric Evaluation. [Internet] [Thesis]. University of South Florida; 2015. [cited 2021 Feb 28].
Available from: https://scholarcommons.usf.edu/etd/5653.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Carballo JM. Self-Assembly Kinetics of Microscale Components: A Parametric Evaluation. [Thesis]. University of South Florida; 2015. Available from: https://scholarcommons.usf.edu/etd/5653
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Maryland
20.
Greve, Hannes Martin Hinrich.
ASSESSMENT OF PROPERTIES OF TRANSIENT LIQUID PHASE SINTERED (TLPS) INTERCONNECTS BY SIMULATION AND EXPERIMENTS.
Degree: Mechanical Engineering, 2017, University of Maryland
URL: http://hdl.handle.net/1903/19469
► Growing power densities of electronic products and application of electronic systems in high temperature environment increase the temperature requirements on electronic packaging systems. Conventional interconnect…
(more)
▼ Growing power densities of electronic products and application of electronic systems in high temperature environment increase the temperature requirements on electronic
packaging systems. Conventional interconnect technology was designed for devices based on silicon semiconductor technology limited to 175 °C and below. The introduction of wide bandgap semiconductor materials such as silicon carbide and gallium nitride expands the potential application temperature range to 500 °C beyond the range of conventional electronic
packaging solutions.
Transient Liquid Phase Sintering (TLPS) is a promising high temperature, high strength, low cost interconnect technology solution. TLPS is a liquid-assisted sintering process during which a low melting temperature constituent melts, surrounds, and diffuses with a high melting temperature constituent. A shift towards higher melting temperatures occurs as the low melting temperature phase is transformed into high melting temperature intermetallic compounds (IMCs). In this work, three TLPS sinter paste systems based on the copper-tin (Cu-Sn), nickel-tin (Ni-Sn), and copper-nickel-tin (Cu-Ni-Sn) material systems are designed. A novel process for their application as electronic interconnects is developed. Processing and thermal aging studies are performed to determine times to process completion characterized by high-temperature capability of the joints. Microstructural convergence durations are studied for each of the material systems. A
modeling approach is developed to model realistic joint geometries with varying types, sizes, and distributions of metal particles and voids in intermetallic matrices. These are used to predict the constitutive (elastic-plastic) stress-strain responses and thermal properties of these systems by simulation. The constitutive models derived by this approach are compared to constitutive properties determined experimentally by Iosipescu shear samples with TLPS joints. The thermal properties of TLPS joints are determined experimentally by transient thermal response analyses. Failure mechanisms driven by thermal and thermo-mechanical stressors are predicted and verified, and mitigation techniques are developed.
Advisors/Committee Members: McCluskey, Patrick (advisor).
Subjects/Keywords: Mechanical engineering; Electronic Packaging; High Temperature Electronics; Intermetallic Compounds; Sintering; Soldering; Transient Liquid Phase Sintering
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APA (6th Edition):
Greve, H. M. H. (2017). ASSESSMENT OF PROPERTIES OF TRANSIENT LIQUID PHASE SINTERED (TLPS) INTERCONNECTS BY SIMULATION AND EXPERIMENTS. (Thesis). University of Maryland. Retrieved from http://hdl.handle.net/1903/19469
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Greve, Hannes Martin Hinrich. “ASSESSMENT OF PROPERTIES OF TRANSIENT LIQUID PHASE SINTERED (TLPS) INTERCONNECTS BY SIMULATION AND EXPERIMENTS.” 2017. Thesis, University of Maryland. Accessed February 28, 2021.
http://hdl.handle.net/1903/19469.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Greve, Hannes Martin Hinrich. “ASSESSMENT OF PROPERTIES OF TRANSIENT LIQUID PHASE SINTERED (TLPS) INTERCONNECTS BY SIMULATION AND EXPERIMENTS.” 2017. Web. 28 Feb 2021.
Vancouver:
Greve HMH. ASSESSMENT OF PROPERTIES OF TRANSIENT LIQUID PHASE SINTERED (TLPS) INTERCONNECTS BY SIMULATION AND EXPERIMENTS. [Internet] [Thesis]. University of Maryland; 2017. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/1903/19469.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Greve HMH. ASSESSMENT OF PROPERTIES OF TRANSIENT LIQUID PHASE SINTERED (TLPS) INTERCONNECTS BY SIMULATION AND EXPERIMENTS. [Thesis]. University of Maryland; 2017. Available from: http://hdl.handle.net/1903/19469
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Virginia Tech
21.
Cao, Xiao.
Optimization of Bonding Geometry for a Planar Power Module to Minimize Thermal Impedance and Thermo-Mechanical Stress.
Degree: PhD, Electrical and Computer Engineering, 2011, Virginia Tech
URL: http://hdl.handle.net/10919/77252
► This study focuses on development a planar power module with low thermal impedance and thermo-mechanical stress for high density integration of power electronics systems. With…
(more)
▼ This study focuses on development a planar power module with low thermal impedance and thermo-mechanical stress for high density integration of power
electronics systems. With the development semiconductor technology, the heat flux generated in power device keeps increasing. As a result, more and more stringent requirements were imposed on the thermal and reliability design of power
electronics packaging.
In this dissertation, a boundary-dependent RC transient thermal model was developed to predict the peak transient temperature of semiconductor device in the power module. Compared to conventional RC thermal models, the RC values in the proposed model are functions of boundary conditions, geometries, and the material properties of the power module. Thus, the proposed model can provide more accurate prediction for the junction temperature of power devices under variable conditions. In addition, the transient thermal model can be extracted based on only steady-state thermal simulation, which significantly reduced the computing time.
To detect the peak transient temperature in a fully packaged power module, a method for thermal impedance measurement was proposed. In the proposed method, the gate-emitter voltage of an IGBT which is much more sensitive to the temperature change than the widely used forward voltage drop of a pn junction was monitored and used as temperature sensitive parameter. A completed test circuit was designed to measure the thermal impedance of the power module using the gate-emitter voltage. With the designed test set-up, in spite of the temperature dependency of the IGBT electrical characteristics, the power dissipation in the IGBT can be regulated to be constant by adjusting the gate voltage via feedback control during the heating phase. The developed measurement system was used to evaluate thermal performance and reliability of three different die-attach materials.
From the prediction of the proposed thermal model, it was found that the conventional single-sided power module with wirebond connection cannot achieve both good steady-state and transient thermal performance under high heat transfer coefficient conditions. As a result, a plate-bonded planar power module was designed to resolve the issue. The comparison of thermal performance for conventional power module and the plate-bonded power module shows that the plate-bonded power module has both better steady-state and transient thermal performance than the wirebonded power module. However, due to CTE mismatch between the copper plate and the silicon device, large thermo-mechanical stress is induced in the bonding layer of the power module. To reduce the stress in the plate-bonded power module, an improved structure called trenched copper plate structure was proposed. In the proposed structure, the large copper plate on top of the semiconductor can be partitioned into several smaller pieces that are connected together using a thin layer copper foil. The FEM simulation shows that, with the improved structure, the maximum von Mises stress and…
Advisors/Committee Members: Ngo, Khai D. T. (committeechair), Lu, Guo-Quan (committee member), Meehan, Kathleen (committee member), Bailey, Scott M. (committee member), Ekkad, Srinath V. (committee member).
Subjects/Keywords: thermal management; high density integration; power module; thermo-mechanical stress; power electronics packaging; reliability test
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APA ·
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Export
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APA (6th Edition):
Cao, X. (2011). Optimization of Bonding Geometry for a Planar Power Module to Minimize Thermal Impedance and Thermo-Mechanical Stress. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/77252
Chicago Manual of Style (16th Edition):
Cao, Xiao. “Optimization of Bonding Geometry for a Planar Power Module to Minimize Thermal Impedance and Thermo-Mechanical Stress.” 2011. Doctoral Dissertation, Virginia Tech. Accessed February 28, 2021.
http://hdl.handle.net/10919/77252.
MLA Handbook (7th Edition):
Cao, Xiao. “Optimization of Bonding Geometry for a Planar Power Module to Minimize Thermal Impedance and Thermo-Mechanical Stress.” 2011. Web. 28 Feb 2021.
Vancouver:
Cao X. Optimization of Bonding Geometry for a Planar Power Module to Minimize Thermal Impedance and Thermo-Mechanical Stress. [Internet] [Doctoral dissertation]. Virginia Tech; 2011. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/10919/77252.
Council of Science Editors:
Cao X. Optimization of Bonding Geometry for a Planar Power Module to Minimize Thermal Impedance and Thermo-Mechanical Stress. [Doctoral Dissertation]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/77252
University of Dayton
22.
Smarra, Devin A.
Low Temperature Co-Fired Ceramic (LTCC) Substrate for High
Temperature Microelectronics.
Degree: MS(M.S.), Electrical Engineering, 2017, University of Dayton
URL: http://rave.ohiolink.edu/etdc/view?acc_num=dayton1493386231571894
► Advances in aerospace technologies demand new ways to package electronics for high temperature and harsh environments. One packaging method of interest in academia and industry…
(more)
▼ Advances in aerospace technologies demand new ways to
package
electronics for high temperature and harsh environments.
One
packaging method of interest in academia and industry is Low
Temperature Co-fired Ceramic (LTCC). LTCC is a multi-layer design
and
packaging system that can embed passive components and thermal
management structures within a substrate. This thesis compiles
research done to evaluate LTCC as a high-performance electronic
packaging technique by determining the performance of embedded
passives and thermal management structures at temperatures from
-55
oC to 225
oC. The
passive structures and thermal management structures are evaluated
using theoretical calculations, simulations, and measurements of
fabricated devices.
Advisors/Committee Members: Chodavarapu, Vamsy (Advisor), Subramanyam, Guru (Committee Co-Chair).
Subjects/Keywords: Electrical Engineering; LTCC; Electronic Packaging; Low Temperature Co-Fired Ceramic; High Temperature Electronics; Microelectronics
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APA (6th Edition):
Smarra, D. A. (2017). Low Temperature Co-Fired Ceramic (LTCC) Substrate for High
Temperature Microelectronics. (Masters Thesis). University of Dayton. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=dayton1493386231571894
Chicago Manual of Style (16th Edition):
Smarra, Devin A. “Low Temperature Co-Fired Ceramic (LTCC) Substrate for High
Temperature Microelectronics.” 2017. Masters Thesis, University of Dayton. Accessed February 28, 2021.
http://rave.ohiolink.edu/etdc/view?acc_num=dayton1493386231571894.
MLA Handbook (7th Edition):
Smarra, Devin A. “Low Temperature Co-Fired Ceramic (LTCC) Substrate for High
Temperature Microelectronics.” 2017. Web. 28 Feb 2021.
Vancouver:
Smarra DA. Low Temperature Co-Fired Ceramic (LTCC) Substrate for High
Temperature Microelectronics. [Internet] [Masters thesis]. University of Dayton; 2017. [cited 2021 Feb 28].
Available from: http://rave.ohiolink.edu/etdc/view?acc_num=dayton1493386231571894.
Council of Science Editors:
Smarra DA. Low Temperature Co-Fired Ceramic (LTCC) Substrate for High
Temperature Microelectronics. [Masters Thesis]. University of Dayton; 2017. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=dayton1493386231571894
University of New Mexico
23.
Suszko, Arthur.
Enhancement of Nucleate Boiling on Rough and Dimpled Surfaces with Application to Composite Spreaders for Microprocessors Immersion Cooling.
Degree: Mechanical Engineering, 2015, University of New Mexico
URL: http://hdl.handle.net/1928/30421
► Microprocessors have substantially increased total power dissipation and transistors density over the past two decades, owing to the growth in complexity, performance, and parallelism of…
(more)
▼ Microprocessors have substantially increased total power dissipation and transistors density over the past two decades, owing to the growth in complexity, performance, and parallelism of computational systems. To continue to effectively and safely dissipate larger amounts of power, advanced methods of cooling such as immersion cooling by nucleate boiling of dielectric liquids are being considered. For electronic cooling applications, dielectric liquids are chemically inert, environmentally friendly, and have low saturation temperatures (34 — 56 °C at 0.1 MPa) advantageous for keeping the chips junction temperature below that recommended by the manufacturer (85 — 115 °C), depending on the application. This research experimentally investigated the enhancement of pool nucleate boiling of PF-5060 dielectric liquid on uniformly heated, 10 x 10 x 1.6 mm rough and dimpled Cu surfaces. Fabricating these surfaces is cost effective and scalable, making them suitable for immersion nucleate boiling cooling of high powered microprocessors requiring heat spreaders of different sizes. The PF-5060 has a saturation temperature of 51.4 °C at ~0.085MPa — the local pressure in Albuquerque NM, where the experiments were carried out. Because various circuit board orientations and the perpendicular mounting of add-in cards such as graphics processing units results in chip orientations that vary from 0o — 180o with respect to gravity, the effects of these surface inclinations on nucleate boiling of saturated and subcooled PF-5060, are thoroughly investigated for both the rough and dimpled Cu surfaces. In the experiments, liquid subcooling was varied up to 30 K. Experimental nucleate boiling heat transfer coefficient curves for rough Cu surfaces were used to computationally investigate the performance of composite spreaders. These spreaders removed the thermal power dissipated by a 20 x 20 mm microprocessor with and without hot spots, by saturation nucleate boiling of PF-5060. To ensure the consistency of the experimental results, all pool boiling experiments reported in this dissertation are for degassed PF-5060 liquid and uniformly heated 10 x 10 x 1.6 mm Cu surfaces. Multiple experiments performed for the same conditions, separated by at least 2 hours, and sometimes a few days, verified the reproducibility of the results. The absence of boiling hysteresis confirmed no influence by the thermal inertia of the heated Cu surface, but rather the thermophysical properties of the PF-5060 dielectric liquid and surface characteristics solely influenced the nucleate boiling results. Results on the effect of the average surface roughness, (Ra = 0.039 — 1.79μm), inclination angle (θ = 0o — 180o), and liquid subcooling (ΔTsub = 0 — 30 K) on nucleate boiling enhancement and CHF on plain Cu surfaces are presented and discussed throughout the dissertation, along with several developed correlations and comparisons with prior work. In the upward facing surface inclination (θ = 0o), increasing…
Advisors/Committee Members: El-Genk, Mohamed, Shen, Yu-Lin, Tehrani, Mehran, Taha, Mahmoud.
Subjects/Keywords: Enhancement of nucleate boiling; dielectric liquids; immersion cooling; thermally anistropic composite heat spreasders; electronics cooling; thermal management; electronics packaging
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APA (6th Edition):
Suszko, A. (2015). Enhancement of Nucleate Boiling on Rough and Dimpled Surfaces with Application to Composite Spreaders for Microprocessors Immersion Cooling. (Doctoral Dissertation). University of New Mexico. Retrieved from http://hdl.handle.net/1928/30421
Chicago Manual of Style (16th Edition):
Suszko, Arthur. “Enhancement of Nucleate Boiling on Rough and Dimpled Surfaces with Application to Composite Spreaders for Microprocessors Immersion Cooling.” 2015. Doctoral Dissertation, University of New Mexico. Accessed February 28, 2021.
http://hdl.handle.net/1928/30421.
MLA Handbook (7th Edition):
Suszko, Arthur. “Enhancement of Nucleate Boiling on Rough and Dimpled Surfaces with Application to Composite Spreaders for Microprocessors Immersion Cooling.” 2015. Web. 28 Feb 2021.
Vancouver:
Suszko A. Enhancement of Nucleate Boiling on Rough and Dimpled Surfaces with Application to Composite Spreaders for Microprocessors Immersion Cooling. [Internet] [Doctoral dissertation]. University of New Mexico; 2015. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/1928/30421.
Council of Science Editors:
Suszko A. Enhancement of Nucleate Boiling on Rough and Dimpled Surfaces with Application to Composite Spreaders for Microprocessors Immersion Cooling. [Doctoral Dissertation]. University of New Mexico; 2015. Available from: http://hdl.handle.net/1928/30421
University of Arkansas
24.
Bourland, Charles R.
Environmental Reliability of Thin Film Sealing on Thick Film LTCC.
Degree: MS, 2015, University of Arkansas
URL: https://scholarworks.uark.edu/etd/1178
► As electronic components and systems become more intricate and expand into new realms of use case scenarios, new materials systems must be explored. With…
(more)
▼ As electronic components and systems become more intricate and expand into new realms of use case scenarios, new materials systems must be explored. With new systems comes the balancing acts of cost and reliability. Presented here is a thesis that explores a new hybrid-
electronics packaging system using low temperature co-fired ceramics, referred to as LTCC. An LTCC system was designed to explore the environmental reliability of numerous thick film LTCC features and parameters. A key element was to explore how a thin film metallization stack up used to cap or seal underlying thick film structures would decrease environmental susceptibility while at the same time optimizing costs. A material matrix of 16 recipes was developed with 14 primary feature types to be evaluated. It was decided that the LTCC systems undergo five environmental reliability tests which were as follows: lifetime at elevated temperature, thermal cycling, humidity, thermal shock, and corrosion via salt fog spay. All environmental reliability tests were performed in accordance to either MIL or JEDEC standards or specifications. An investigation of occurring phenomena through each environmental test is presented.
Advisors/Committee Members: H. Alan Mantooth, Michael Glover, Simon Ang.
Subjects/Keywords: Applied sciences; Advanced electronic packaging; Advanced thin films; Ceramics; Extreme environment electronics; LTCC; Reliability of electronics; Electrical and Electronics; Electronic Devices and Semiconductor Manufacturing; Industrial Organization
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APA (6th Edition):
Bourland, C. R. (2015). Environmental Reliability of Thin Film Sealing on Thick Film LTCC. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1178
Chicago Manual of Style (16th Edition):
Bourland, Charles R. “Environmental Reliability of Thin Film Sealing on Thick Film LTCC.” 2015. Masters Thesis, University of Arkansas. Accessed February 28, 2021.
https://scholarworks.uark.edu/etd/1178.
MLA Handbook (7th Edition):
Bourland, Charles R. “Environmental Reliability of Thin Film Sealing on Thick Film LTCC.” 2015. Web. 28 Feb 2021.
Vancouver:
Bourland CR. Environmental Reliability of Thin Film Sealing on Thick Film LTCC. [Internet] [Masters thesis]. University of Arkansas; 2015. [cited 2021 Feb 28].
Available from: https://scholarworks.uark.edu/etd/1178.
Council of Science Editors:
Bourland CR. Environmental Reliability of Thin Film Sealing on Thick Film LTCC. [Masters Thesis]. University of Arkansas; 2015. Available from: https://scholarworks.uark.edu/etd/1178
INP Toulouse
25.
Msolli, Sabeur.
Modélisation thermomécanique de l'assemblage d'un composant diamant pour l'électronique de puissance haute température : Thermomechanical modeling of a diamond based packaging for high temperature power electronics.
Degree: Docteur es, Génie Mécanique, Mécanique des Matériaux, 2011, INP Toulouse
URL: http://www.theses.fr/2011INPT0088
► L'utilisation du diamant comme composant d'électronique de puissance est une perspective intéressante tant en ce qui concerne les applications hautes température que forte puissance. La…
(more)
▼ L'utilisation du diamant comme composant d'électronique de puissance est une perspective intéressante tant en ce qui concerne les applications hautes température que forte puissance. La problématique principale de ces travaux réalisés dans le cadre du programme Diamonix, réside dans l'étude et l'élaboration d'un packaging permettant la mise en oeuvre d'une puce diamant devant fonctionner à des températures variant entre -50°C et 300°C. Nous nous sommes intéressés au choix des matériaux de connexion de la puce avec son environnement. Suite à l'étude bibliographique, nous proposons différentes solutions de matériaux envisageables pour le substrat métallisé, les brasures et les métallisations. Dans un second temps, les différents éléments ont été réalisés puis caractérisés à partir d'essais de nanoindentation et de nanorayage. Des essais mécaniques ont permis de caractériser le comportement élastoviscoplastique et l'endommagement des brasures. Ces derniers essais ont servi de base expérimentale à l'identification des paramètres d'un modèle de comportement viscoplastique couplé avec l'endommagement et qui a été spécialement élaboré pour cette étude. Le modèle de comportement a été implémenté dans un code de calcul par éléments finis via une sous-routine. Il permet notamment de simuler le processus de dégradation d'un assemblage. Enfin, ce modèle de comportement a été mis en oeuvre dans des modélisations thermomécaniques de différentes configurations de véhicules test.
Use of diamond as constitutive component in power electronics devices is an interesting prospect for the high temperature and high power applications. The main challenge of this research work included in the Diamonix program is the study and the elaboration of a single-crystal diamond substrate with electronic quality and its associated packaging. The designed packaging has to resist to temperatures varying between -50°C and 300°C. We contributed to the choice of the connection materials intended to be used in the final test vehicle and which can handle such temperature gaps. In the first part, we present a state-of-the-art of the various materials solutions for extreme temperatures. Following this study, we propose a set of materials which considered as potential candidates for high temperature packaging. Special focus is given for the most critical elements in power electronic assemblies which are metallizations and solders. Once the materials choice carried out, thin substrate metallizations, solders and DBC coatings are studied using nanoindentation and nanoscratch tests. Mechanical tests were also carried out on solders to study their elastoviscoplastic and damage behavior. The experimental results are used as database for the identification of the parameters of the viscoplastic model coupled with a porous damage law, worked out for the case of solders. The behavior model is implemented as a user subroutine UMAT in a FE code to predict the degradation of a 2D power electronic assembly and various materials configuration for a 3D test vehicle.
Advisors/Committee Members: Karama, Moussa (thesis director), Dalverny, Olivier (thesis director).
Subjects/Keywords: Packaging électronique de puissance; Diamant; Viscoplasticité; Endommagement; Mef; Brasures; Métallisations; Haute température; Power electronics packaging; Diamond; Viscoplasticity; Damage; Fem; Solder joints; Metallization; High temperature
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APA ·
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to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Msolli, S. (2011). Modélisation thermomécanique de l'assemblage d'un composant diamant pour l'électronique de puissance haute température : Thermomechanical modeling of a diamond based packaging for high temperature power electronics. (Doctoral Dissertation). INP Toulouse. Retrieved from http://www.theses.fr/2011INPT0088
Chicago Manual of Style (16th Edition):
Msolli, Sabeur. “Modélisation thermomécanique de l'assemblage d'un composant diamant pour l'électronique de puissance haute température : Thermomechanical modeling of a diamond based packaging for high temperature power electronics.” 2011. Doctoral Dissertation, INP Toulouse. Accessed February 28, 2021.
http://www.theses.fr/2011INPT0088.
MLA Handbook (7th Edition):
Msolli, Sabeur. “Modélisation thermomécanique de l'assemblage d'un composant diamant pour l'électronique de puissance haute température : Thermomechanical modeling of a diamond based packaging for high temperature power electronics.” 2011. Web. 28 Feb 2021.
Vancouver:
Msolli S. Modélisation thermomécanique de l'assemblage d'un composant diamant pour l'électronique de puissance haute température : Thermomechanical modeling of a diamond based packaging for high temperature power electronics. [Internet] [Doctoral dissertation]. INP Toulouse; 2011. [cited 2021 Feb 28].
Available from: http://www.theses.fr/2011INPT0088.
Council of Science Editors:
Msolli S. Modélisation thermomécanique de l'assemblage d'un composant diamant pour l'électronique de puissance haute température : Thermomechanical modeling of a diamond based packaging for high temperature power electronics. [Doctoral Dissertation]. INP Toulouse; 2011. Available from: http://www.theses.fr/2011INPT0088
Brno University of Technology
26.
Skácel, Josef.
Studie srovnání vlastností pouzder QFN a BGA: Study of BGA and QFN package properties.
Degree: 2018, Brno University of Technology
URL: http://hdl.handle.net/11012/40254
► This work deals with the issue of packaging and heat transfer. Especially this work focused on QFN and BGA packages. Nowadays most sophisticated conventional solution.…
(more)
▼ This work deals with the issue of
packaging and heat transfer. Especially this work focused on QFN and BGA packages. Nowadays most sophisticated conventional solution. First part deals with analysis of the current status of packages. Next part is analyze the issue of heat transfer in electronic systems. The following section is an experimental dealing with simulation in ANSYS Workbench and validation of these simulations by designed test structures. At the end is evaluated properties and behavior of these packages.
Advisors/Committee Members: Szendiuch, Ivan (advisor), Psota, Boleslav (referee).
Subjects/Keywords: Pouzdření v elektronice; ANSYS Workbench; teplotní simulace; pouzdřící materiály; koeficient teplotní roztažnosti; TKR; Packaging in electronics; ANSYS Workbench; thermal simulation; packaging materials; coefficient of thermal expansion; CTE
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APA (6th Edition):
Skácel, J. (2018). Studie srovnání vlastností pouzder QFN a BGA: Study of BGA and QFN package properties. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/40254
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Skácel, Josef. “Studie srovnání vlastností pouzder QFN a BGA: Study of BGA and QFN package properties.” 2018. Thesis, Brno University of Technology. Accessed February 28, 2021.
http://hdl.handle.net/11012/40254.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Skácel, Josef. “Studie srovnání vlastností pouzder QFN a BGA: Study of BGA and QFN package properties.” 2018. Web. 28 Feb 2021.
Vancouver:
Skácel J. Studie srovnání vlastností pouzder QFN a BGA: Study of BGA and QFN package properties. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/11012/40254.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Skácel J. Studie srovnání vlastností pouzder QFN a BGA: Study of BGA and QFN package properties. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/40254
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Ryerson University
27.
Zhou., Ming.
Testing and analysis of solder joint reliability for BGA assembly under flexural loading.
Degree: 2009, Ryerson University
URL: https://digital.library.ryerson.ca/islandora/object/RULA%3A6699
► The solder joint reliability for BGA (Ball Grid Array) assembly is becoming a more concerned issue as these packages are featuring higher density interconnections, multiple…
(more)
▼ The solder joint reliability for BGA (Ball Grid Array) assembly is becoming a more concerned issue as these packages are featuring higher density interconnections, multiple functionality and higher speed combined with smaller size. The traditional test methods for second level PCBA (Printed Circuit Board Assembly) mechanical reliability monitor the electric resistance changes of Daisy chains in the test samples under 4-point bending. The method has been documented by Interconnecting and Packaging Electronic Circuits and Joint Electronic Devices Engineering Council in PC/JEDEC 9702 standard. The effectiveness of the test has been questioned when applied to the new lead-free soldered packages. Due to the failure mode shift from solder joinicopper pad interface cracking in Tin-lead PCBAs to pad-cratering cracking in leadfree packages, the electrical continuity monitoring becomes ineffective in detecting the interconneCt failure. On the other hand, the strain gauges recorded PCB strains during bend tests show little increase that would be indicative of an onset failure.
This project applies Fiber Bragg Grating (FBG) strain sensors to detect the pad-cratering failure. FBO have been employed widely in different areas of engineering due to its advantages of small size, light weight and high sensitivity. In this project the FBG sensors are laid to the vicinity of the BGA substrate comers. By detecting and recording the solder joint fracture induced strain release, the onset of pad-cratering is explicitly revealed. The study has demonstrated that the FBG sensors are much more sensitive than electric resistance strain gauges in detecting the substrate strain release in BGA assembly 4-point bend testing due primarily to the sensor's much smaller geometric size. By placing the sensors very close to the comer solder joints, the new test obtains accurate strain information related to the first solder joint cracking. Furthermore, the recorded strain release enables the detecting, understanding and analysis of the critical load of the solder joint fracture, the brittle and ductile fractures and related strain relaxation phenomenon during the PBGA flexural loading, etc.
Subjects/Keywords: Ball grid array technology.; Electronic packaging.; Joints (Engineering) – Reliability; Electric connectors; Lead-free electronics manufacturing processes.
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APA (6th Edition):
Zhou., M. (2009). Testing and analysis of solder joint reliability for BGA assembly under flexural loading. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A6699
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Zhou., Ming. “Testing and analysis of solder joint reliability for BGA assembly under flexural loading.” 2009. Thesis, Ryerson University. Accessed February 28, 2021.
https://digital.library.ryerson.ca/islandora/object/RULA%3A6699.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Zhou., Ming. “Testing and analysis of solder joint reliability for BGA assembly under flexural loading.” 2009. Web. 28 Feb 2021.
Vancouver:
Zhou. M. Testing and analysis of solder joint reliability for BGA assembly under flexural loading. [Internet] [Thesis]. Ryerson University; 2009. [cited 2021 Feb 28].
Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6699.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Zhou. M. Testing and analysis of solder joint reliability for BGA assembly under flexural loading. [Thesis]. Ryerson University; 2009. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6699
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Tampere University
28.
Laurila, Mika-Matti.
High-Precision Digital Printing Processes for Electronics Fabrication
.
Degree: 2019, Tampere University
URL: https://trepo.tuni.fi/handle/10024/116831
► This thesis investigates the capabilities of high-precision digital printing technologies in the fabrication of miniaturized components for electronics packaging, transistor intercon- nects and monolithically integrated…
(more)
▼ This thesis investigates the capabilities of high-precision digital printing technologies in the fabrication of miniaturized components for electronics packaging, transistor intercon- nects and monolithically integrated lab-on-skin systems for biosignal monitoring. In gen- eral, the printing technologies suffer from poor resolution compared to conventional lith- ographic fabrication methods, which limits the level of miniaturization for printed elec- tronics components, devices, and circuits. This leads to their significantly lower perfor- mance compared to conventional electronics. However, certain application areas exist where pushing the envelope of printing technologies towards higher resolution and pre- cision would result in the addition of new functionalities.
Replacing lithographic fabrication of high-density circuitries of electronics packages with high-resolution electrohydrodynamic inkjet (E-jet) printing could result in higher levels of customizability and reduced environmental impacts. In this thesis, the parameters affect- ing E-jet printing resolution were studied using statistical tools; the resulting regression model applied for droplet diameters of 3.5 µm to 20 µm and had a coefficient of determi- nation (R2) of 94 % with a residual of 1.1 µm. Finally, the combination of E-jet and inkjet printing is demonstrated in the fabrication of a high-density (5/5 µm width/spacing) mul- tilayer redistribution layer (RDL) for a silicon interposer.
E-jet printing could be also used to enhance the interconnect density, and concomitant performance of application specific printed electronic circuits (ASPEC), which in them- selves are already an enhancement of the existing application specific integrated circuits (ASIC) in that they allow field configurability of the prefabricated logic circuits. In this thesis, E-jet printing was compared to aerosol jet (AJ), piezoelectric inkjet and litho- graphic fabrication methods for the fabrication of ASPECs. Two different interconnect structures were used and in both cases the E-jet printing compared favourably to AJ and piezoelectric inkjet printing technologies.
Piezoelectric inkjet printing cannot be considered a true high-resolution technology sim- ilar to E-jet printing due to its large droplet volume (pL vs. fL), However, it may still be used to print small (i.e., high-precision) structures required for example in transistor fab- rication. The high-precision printing capability coupled with a large droplet volume ena- bles higher throughput when fabricating amplifiers with monolithically integrated active and passive components. In this thesis, a piezoelectric inkjet was used for the fabrication of source/drain (S/D) electrodes for transistors with ~10 µm channel length together with monolithically integrated large area parallel plate capacitors and resistors. The resulting charge amplifier optimized for pulse wave (PW) measurements had a gain of 1.6 V/nC with a pass band of 50 MHz to 32 Hz. Furthermore, the performance of the amplifier was…
Subjects/Keywords: Printed electronics
;
digital fabrication
;
high-resolution inkjet
;
MEMS packaging
;
biosignal measurement
;
Painettava elektroniikka
;
digitaaliset valmistusmenetelmät
;
korkean resolution mustesuihkutulostus
;
MEMS pakkaus
;
biosignaalimittaus
Record Details
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APA ·
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to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Laurila, M. (2019). High-Precision Digital Printing Processes for Electronics Fabrication
. (Doctoral Dissertation). Tampere University. Retrieved from https://trepo.tuni.fi/handle/10024/116831
Chicago Manual of Style (16th Edition):
Laurila, Mika-Matti. “High-Precision Digital Printing Processes for Electronics Fabrication
.” 2019. Doctoral Dissertation, Tampere University. Accessed February 28, 2021.
https://trepo.tuni.fi/handle/10024/116831.
MLA Handbook (7th Edition):
Laurila, Mika-Matti. “High-Precision Digital Printing Processes for Electronics Fabrication
.” 2019. Web. 28 Feb 2021.
Vancouver:
Laurila M. High-Precision Digital Printing Processes for Electronics Fabrication
. [Internet] [Doctoral dissertation]. Tampere University; 2019. [cited 2021 Feb 28].
Available from: https://trepo.tuni.fi/handle/10024/116831.
Council of Science Editors:
Laurila M. High-Precision Digital Printing Processes for Electronics Fabrication
. [Doctoral Dissertation]. Tampere University; 2019. Available from: https://trepo.tuni.fi/handle/10024/116831
University of Michigan
29.
Li, Chen.
Thermal Management of Electronics and Optoelectronics: From Heat Source Characterization to Heat Mitigation at the Device and Package Levels.
Degree: PhD, Mechanical Engineering, 2019, University of Michigan
URL: http://hdl.handle.net/2027.42/150013
► Thermal management of electronic and optoelectronic devices has become increasingly challenging. For electronic devices, the challenge arises primarily from the drive for miniaturized, high-performance devices,…
(more)
▼ Thermal management of electronic and optoelectronic devices has become increasingly challenging. For electronic devices, the challenge arises primarily from the drive for miniaturized, high-performance devices, leading to escalating power density. For optoelectronics, the recent widespread use of organic light emitting diode (OLED) displays in mobile platforms and flexible
electronics presents new challenges for heat dissipation. Furthermore, the performance and reliability of increasingly high-power semiconductor lasers used for telecommunications and other applications hinge on proper thermal management. For example, small, concentrated hotspots may trigger thermal runaway and premature device destruction.
Emerging challenges in thermal management of devices require innovative methods to characterize and mitigate heat generation and temperature rise at the device level as well as the package level. The first part of this dissertation discusses device-level thermal management. A thermal imaging microscope with high spatial resolution (~450nm) is created for hotspot detection in the context of diode lasers under back-irradiance (BI). Laser facet temperature maps reveal the existence of a critical BI spot location that increases the laser’s active region temperature by nearly a factor of 3. An active solid-state cooling strategy that could scale down to the size of hotspots in modern devices is then explored, utilizing energy filtering at carbon nanotube (CNT) junctions as a means to provide thermionic cooling at nanometer spatial scales. The CNT cooler exhibits a large effective Seebeck coefficient of 386μV/K and a relatively moderate thermal conductivity, together giving rise to a high cooling capacity (2.3 × 106 W/cm2).
Thermal management at the package level is then considered. Heat transfer in polymers is first studied, owing to their prevalence in thermal interface materials as well as organic devices (e.g., OLEDs). Employing molecular design principles developed to engineer the thermal properties of polymers, molecular-scale electrostatic repulsive forces are utilized to modify chain morphologies in amorphous polymers, leading to spin-cast films that are free of ceramic or metallic fillers yet have thermal conductivities as high as 1.17 Wm-1K-1, which is approximately 6 times that of typical amorphous polymers.
Electronics packaging designs incorporating phase change materials (PCMs) are then considered as a means to mitigate bursty heat sources; PCM incorporation in a packaged accelerator chip intended for large-scale object identification is found to suppress the peak die temperature by 17%.
Advisors/Committee Members: Pipe, Kevin Patrick (committee member), Kim, Jinsang (committee member), Arruda, Ellen M (committee member), Guo, L Jay (committee member), Leisher, Paul O. (committee member).
Subjects/Keywords: thermal management; nanoscale heat transfer; diode laser reliability; thermal management materials; phase change material; electronics packaging; Mechanical Engineering; Engineering
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APA ·
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Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Li, C. (2019). Thermal Management of Electronics and Optoelectronics: From Heat Source Characterization to Heat Mitigation at the Device and Package Levels. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/150013
Chicago Manual of Style (16th Edition):
Li, Chen. “Thermal Management of Electronics and Optoelectronics: From Heat Source Characterization to Heat Mitigation at the Device and Package Levels.” 2019. Doctoral Dissertation, University of Michigan. Accessed February 28, 2021.
http://hdl.handle.net/2027.42/150013.
MLA Handbook (7th Edition):
Li, Chen. “Thermal Management of Electronics and Optoelectronics: From Heat Source Characterization to Heat Mitigation at the Device and Package Levels.” 2019. Web. 28 Feb 2021.
Vancouver:
Li C. Thermal Management of Electronics and Optoelectronics: From Heat Source Characterization to Heat Mitigation at the Device and Package Levels. [Internet] [Doctoral dissertation]. University of Michigan; 2019. [cited 2021 Feb 28].
Available from: http://hdl.handle.net/2027.42/150013.
Council of Science Editors:
Li C. Thermal Management of Electronics and Optoelectronics: From Heat Source Characterization to Heat Mitigation at the Device and Package Levels. [Doctoral Dissertation]. University of Michigan; 2019. Available from: http://hdl.handle.net/2027.42/150013
Queensland University of Technology
30.
Enchelmaier, David Samuel.
A miniaturised wideband frequency synthesiser.
Degree: 2009, Queensland University of Technology
URL: https://eprints.qut.edu.au/31851/
► Wideband frequency synthesisers have application in many areas, including test instrumentation and defence electronics. Miniaturisation of these devices provides many advantages to system designers, particularly…
(more)
▼ Wideband frequency synthesisers have application in many areas, including test instrumentation and defence electronics. Miniaturisation of these devices provides many advantages to system designers, particularly in applications where extra space and weight are expensive.
The purpose of this project was to miniaturise a wideband frequency synthesiser and package it for operation in several different environmental conditions while satisfying demanding technical specifications. The four primary and secondary goals to be achieved were:
1. an operating frequency range from low MHz to greater than 40 GHz, with resolution better than 1 MHz,
2. typical RF output power of +10 dBm, with maximum DC supply of 15 W,
3. synthesiser package of only 150 100 30 mm, and
4. operating temperatures from 20C to +71C, and vibration levels over 7 grms.
This task was approached from multiple angles. Electrically, the system is designed to have as few functional blocks as possible. Off the shelf components are used for active functions instead of customised circuits. Mechanically, the synthesiser package is designed for efficient use of the available space. Two identical prototype synthesisers were manufactured to evaluate the design methodology and to show the repeatability of the design.
Although further engineering development will improve the synthesiser’s performance, this project has successfully demonstrated a level of miniaturisation which sets a new benchmark for wideband synthesiser design. These synthesisers will meet the demands for smaller, lighter wideband sources. Potential applications include portable test equipment, radar and electronic surveillance systems on unmanned aerial vehicles. They are also useful for reducing the overall weight and power consumption of other systems, even if small dimensions are not essential.
Subjects/Keywords: Broadband; electronics; frequency synthesiser; microwave; microwave circuit design; microwave packaging; millimetre wave; wideband; phase locked loop; voltage controlled oscillator; wideband
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APA (6th Edition):
Enchelmaier, D. S. (2009). A miniaturised wideband frequency synthesiser. (Thesis). Queensland University of Technology. Retrieved from https://eprints.qut.edu.au/31851/
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Enchelmaier, David Samuel. “A miniaturised wideband frequency synthesiser.” 2009. Thesis, Queensland University of Technology. Accessed February 28, 2021.
https://eprints.qut.edu.au/31851/.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Enchelmaier, David Samuel. “A miniaturised wideband frequency synthesiser.” 2009. Web. 28 Feb 2021.
Vancouver:
Enchelmaier DS. A miniaturised wideband frequency synthesiser. [Internet] [Thesis]. Queensland University of Technology; 2009. [cited 2021 Feb 28].
Available from: https://eprints.qut.edu.au/31851/.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Enchelmaier DS. A miniaturised wideband frequency synthesiser. [Thesis]. Queensland University of Technology; 2009. Available from: https://eprints.qut.edu.au/31851/
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
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