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You searched for subject:(Electronic design automation). Showing records 1 – 30 of 55 total matches.

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University of Illinois – Urbana-Champaign

1. Lin, Chun-Xun. Advances in parallel programming for electronic design automation.

Degree: PhD, Electrical & Computer Engr, 2020, University of Illinois – Urbana-Champaign

 The continued miniaturization of the technology node increases not only the chip capacity but also the circuit design complexity. How does one efficiently design a… (more)

Subjects/Keywords: Electronic design automation; Parallel programming

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APA (6th Edition):

Lin, C. (2020). Advances in parallel programming for electronic design automation. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/108425

Chicago Manual of Style (16th Edition):

Lin, Chun-Xun. “Advances in parallel programming for electronic design automation.” 2020. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 11, 2021. http://hdl.handle.net/2142/108425.

MLA Handbook (7th Edition):

Lin, Chun-Xun. “Advances in parallel programming for electronic design automation.” 2020. Web. 11 Apr 2021.

Vancouver:

Lin C. Advances in parallel programming for electronic design automation. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2020. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2142/108425.

Council of Science Editors:

Lin C. Advances in parallel programming for electronic design automation. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2020. Available from: http://hdl.handle.net/2142/108425


University of Illinois – Urbana-Champaign

2. Ma, Qiang. Routing algorithms for electronic design automation.

Degree: PhD, 1200, 2013, University of Illinois – Urbana-Champaign

 In electronic design automation (EDA), routing is one of the most important tasks for both printed circuit boards (PCB) and integration circuits (IC). After placement,… (more)

Subjects/Keywords: Routing; Algorithm; Electronic Design Automation

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APA (6th Edition):

Ma, Q. (2013). Routing algorithms for electronic design automation. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/42184

Chicago Manual of Style (16th Edition):

Ma, Qiang. “Routing algorithms for electronic design automation.” 2013. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 11, 2021. http://hdl.handle.net/2142/42184.

MLA Handbook (7th Edition):

Ma, Qiang. “Routing algorithms for electronic design automation.” 2013. Web. 11 Apr 2021.

Vancouver:

Ma Q. Routing algorithms for electronic design automation. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2013. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2142/42184.

Council of Science Editors:

Ma Q. Routing algorithms for electronic design automation. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/42184


University of Illinois – Urbana-Champaign

3. Guo, Daifeng. Algorithms for DFM in electronic design automation.

Degree: PhD, Electrical & Computer Engr, 2019, University of Illinois – Urbana-Champaign

 As the dimension of features in integrated circuits (IC) keeps shrinking to fulfill Moore’s law, the manufacturing process has no choice but confronting the limit… (more)

Subjects/Keywords: Algorithm; Optimization; Design for Manufacturing; Electronic Design Automation; Computer-Aided Design

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APA (6th Edition):

Guo, D. (2019). Algorithms for DFM in electronic design automation. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/104852

Chicago Manual of Style (16th Edition):

Guo, Daifeng. “Algorithms for DFM in electronic design automation.” 2019. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 11, 2021. http://hdl.handle.net/2142/104852.

MLA Handbook (7th Edition):

Guo, Daifeng. “Algorithms for DFM in electronic design automation.” 2019. Web. 11 Apr 2021.

Vancouver:

Guo D. Algorithms for DFM in electronic design automation. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2019. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2142/104852.

Council of Science Editors:

Guo D. Algorithms for DFM in electronic design automation. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2019. Available from: http://hdl.handle.net/2142/104852


University of Texas – Austin

4. -2180-8629. Layout automation for analog and mixed-signal integrated circuits.

Degree: PhD, Electrical and Computer Engineering, 2019, University of Texas – Austin

 Recently, the demand for analog and mixed-signal (AMS) integrated circuits (ICs) has increased significantly due to various emerging applications. However, most of the AMS IC… (more)

Subjects/Keywords: Analog and mixed-signal integrated circuits; Layout; Physical design automation; Placement; Electronic design automation

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APA (6th Edition):

-2180-8629. (2019). Layout automation for analog and mixed-signal integrated circuits. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/3213

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-2180-8629. “Layout automation for analog and mixed-signal integrated circuits.” 2019. Doctoral Dissertation, University of Texas – Austin. Accessed April 11, 2021. http://dx.doi.org/10.26153/tsw/3213.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-2180-8629. “Layout automation for analog and mixed-signal integrated circuits.” 2019. Web. 11 Apr 2021.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-2180-8629. Layout automation for analog and mixed-signal integrated circuits. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2019. [cited 2021 Apr 11]. Available from: http://dx.doi.org/10.26153/tsw/3213.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-2180-8629. Layout automation for analog and mixed-signal integrated circuits. [Doctoral Dissertation]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/3213

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


University of California – Santa Cruz

5. Trapani Possignolo, Rafael. Improving the Productivity of Hardware Design.

Degree: Computer Engineering, 2018, University of California – Santa Cruz

 Current hardware development techniques contrast with agile methods that became popular in modern software development. This has been mitigated with technology scaling, when performance gains… (more)

Subjects/Keywords: Computer engineering; Computer science; Digital Design; Electronic Design Automation; Pipelining; Productivity

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APA (6th Edition):

Trapani Possignolo, R. (2018). Improving the Productivity of Hardware Design. (Thesis). University of California – Santa Cruz. Retrieved from http://www.escholarship.org/uc/item/6bd5n1c7

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Trapani Possignolo, Rafael. “Improving the Productivity of Hardware Design.” 2018. Thesis, University of California – Santa Cruz. Accessed April 11, 2021. http://www.escholarship.org/uc/item/6bd5n1c7.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Trapani Possignolo, Rafael. “Improving the Productivity of Hardware Design.” 2018. Web. 11 Apr 2021.

Vancouver:

Trapani Possignolo R. Improving the Productivity of Hardware Design. [Internet] [Thesis]. University of California – Santa Cruz; 2018. [cited 2021 Apr 11]. Available from: http://www.escholarship.org/uc/item/6bd5n1c7.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Trapani Possignolo R. Improving the Productivity of Hardware Design. [Thesis]. University of California – Santa Cruz; 2018. Available from: http://www.escholarship.org/uc/item/6bd5n1c7

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

6. Fogaça, Mateus Paiva. A new quadratic formulation for incremental timing-driven placement.

Degree: 2016, Brazil

O tempo de propagação dos sinais nas interconexões é um fator dominante para atingir a frequência de operação desejada em circuitos nanoCMOS. Durante a síntese… (more)

Subjects/Keywords: Microeletrônica; Otimização; Timing optimization; Placement; Physical design; Electronic design automation; Microelectronics

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APA (6th Edition):

Fogaça, M. P. (2016). A new quadratic formulation for incremental timing-driven placement. (Masters Thesis). Brazil. Retrieved from http://hdl.handle.net/10183/164067

Chicago Manual of Style (16th Edition):

Fogaça, Mateus Paiva. “A new quadratic formulation for incremental timing-driven placement.” 2016. Masters Thesis, Brazil. Accessed April 11, 2021. http://hdl.handle.net/10183/164067.

MLA Handbook (7th Edition):

Fogaça, Mateus Paiva. “A new quadratic formulation for incremental timing-driven placement.” 2016. Web. 11 Apr 2021.

Vancouver:

Fogaça MP. A new quadratic formulation for incremental timing-driven placement. [Internet] [Masters thesis]. Brazil; 2016. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10183/164067.

Council of Science Editors:

Fogaça MP. A new quadratic formulation for incremental timing-driven placement. [Masters Thesis]. Brazil; 2016. Available from: http://hdl.handle.net/10183/164067


Clemson University

7. Qiu, Ling. Designing Approximate Computing Circuits with Scalable and Systematic Data-Driven Techniques.

Degree: MS, Electrical and Computer Engineering (Holcomb Dept. of), 2019, Clemson University

  Semiconductor feature size has been shrinking significantly in the past decades. This decreasing trend of feature size leads to faster processing speed as well… (more)

Subjects/Keywords: Approximate Computing; Data Driven Design; Electronic Design Automation; Low Power Circuit Design; Machine Learning

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APA (6th Edition):

Qiu, L. (2019). Designing Approximate Computing Circuits with Scalable and Systematic Data-Driven Techniques. (Masters Thesis). Clemson University. Retrieved from https://tigerprints.clemson.edu/all_theses/3114

Chicago Manual of Style (16th Edition):

Qiu, Ling. “Designing Approximate Computing Circuits with Scalable and Systematic Data-Driven Techniques.” 2019. Masters Thesis, Clemson University. Accessed April 11, 2021. https://tigerprints.clemson.edu/all_theses/3114.

MLA Handbook (7th Edition):

Qiu, Ling. “Designing Approximate Computing Circuits with Scalable and Systematic Data-Driven Techniques.” 2019. Web. 11 Apr 2021.

Vancouver:

Qiu L. Designing Approximate Computing Circuits with Scalable and Systematic Data-Driven Techniques. [Internet] [Masters thesis]. Clemson University; 2019. [cited 2021 Apr 11]. Available from: https://tigerprints.clemson.edu/all_theses/3114.

Council of Science Editors:

Qiu L. Designing Approximate Computing Circuits with Scalable and Systematic Data-Driven Techniques. [Masters Thesis]. Clemson University; 2019. Available from: https://tigerprints.clemson.edu/all_theses/3114


Virginia Tech

8. Frangieh, Tannous. A Design Assembly Technique for FPGA Back-End Acceleration.

Degree: PhD, Electrical and Computer Engineering, 2012, Virginia Tech

 Long wait times constitute a bottleneck limiting the number of compilation runs performed in a day, thus risking to restrict Field-Programmable Gate Array (FPGA) adaptation… (more)

Subjects/Keywords: Configurable Computing; FPGA Productivity; Design Assembly Flow; Electronic Design Automation; Design Reuse

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APA (6th Edition):

Frangieh, T. (2012). A Design Assembly Technique for FPGA Back-End Acceleration. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/29225

Chicago Manual of Style (16th Edition):

Frangieh, Tannous. “A Design Assembly Technique for FPGA Back-End Acceleration.” 2012. Doctoral Dissertation, Virginia Tech. Accessed April 11, 2021. http://hdl.handle.net/10919/29225.

MLA Handbook (7th Edition):

Frangieh, Tannous. “A Design Assembly Technique for FPGA Back-End Acceleration.” 2012. Web. 11 Apr 2021.

Vancouver:

Frangieh T. A Design Assembly Technique for FPGA Back-End Acceleration. [Internet] [Doctoral dissertation]. Virginia Tech; 2012. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10919/29225.

Council of Science Editors:

Frangieh T. A Design Assembly Technique for FPGA Back-End Acceleration. [Doctoral Dissertation]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/29225


Anna University

9. Sivakumar P. Application of effective memetic algorithm for vlsi physical design;.

Degree: Application of effective memetic algorithm for vlsi physical design, 2014, Anna University

Electronic Design Automation EDA encompasses algorithms and newlinemethodologies for designing VLSI circuits and is concerned with the design newlineand production of VLSI systems One of… (more)

Subjects/Keywords: Electronic Design Automation; Floorplanning Routing; Information and communication engineering

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APA (6th Edition):

P, S. (2014). Application of effective memetic algorithm for vlsi physical design;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/24328

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

P, Sivakumar. “Application of effective memetic algorithm for vlsi physical design;.” 2014. Thesis, Anna University. Accessed April 11, 2021. http://shodhganga.inflibnet.ac.in/handle/10603/24328.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

P, Sivakumar. “Application of effective memetic algorithm for vlsi physical design;.” 2014. Web. 11 Apr 2021.

Vancouver:

P S. Application of effective memetic algorithm for vlsi physical design;. [Internet] [Thesis]. Anna University; 2014. [cited 2021 Apr 11]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/24328.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

P S. Application of effective memetic algorithm for vlsi physical design;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/24328

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universitat Autònoma de Barcelona

10. Vila Garcia, Francesc. From characterization strategies to PDK & EDA Tools for Printed Electronics.

Degree: Departament de Microelectrònica i Sistemes Electrònics, 2015, Universitat Autònoma de Barcelona

 During last years, Printed Electronics technologies have attracted a great deal of attention due to being a low-cost, large area electronics manufacturing process. From all… (more)

Subjects/Keywords: Printed electronics; Electronic design automation; Characterization; Tecnologies; 004

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APA (6th Edition):

Vila Garcia, F. (2015). From characterization strategies to PDK & EDA Tools for Printed Electronics. (Thesis). Universitat Autònoma de Barcelona. Retrieved from http://hdl.handle.net/10803/322813

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vila Garcia, Francesc. “From characterization strategies to PDK & EDA Tools for Printed Electronics.” 2015. Thesis, Universitat Autònoma de Barcelona. Accessed April 11, 2021. http://hdl.handle.net/10803/322813.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vila Garcia, Francesc. “From characterization strategies to PDK & EDA Tools for Printed Electronics.” 2015. Web. 11 Apr 2021.

Vancouver:

Vila Garcia F. From characterization strategies to PDK & EDA Tools for Printed Electronics. [Internet] [Thesis]. Universitat Autònoma de Barcelona; 2015. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10803/322813.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vila Garcia F. From characterization strategies to PDK & EDA Tools for Printed Electronics. [Thesis]. Universitat Autònoma de Barcelona; 2015. Available from: http://hdl.handle.net/10803/322813

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Guelph

11. Al-Hyari, Abeer. Towards Smart FPGA Placement Using Machine Learning.

Degree: PhD, School of Engineering, 2019, University of Guelph

 Recently, the application of machine learning to problems in the area of Electronic Design Automation (EDA) has received increased attention due to ease of integration… (more)

Subjects/Keywords: FPGA; Placement; CAD Flow; Machine learning; deep learning; electronic design automation

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APA (6th Edition):

Al-Hyari, A. (2019). Towards Smart FPGA Placement Using Machine Learning. (Doctoral Dissertation). University of Guelph. Retrieved from https://atrium.lib.uoguelph.ca/xmlui/handle/10214/17377

Chicago Manual of Style (16th Edition):

Al-Hyari, Abeer. “Towards Smart FPGA Placement Using Machine Learning.” 2019. Doctoral Dissertation, University of Guelph. Accessed April 11, 2021. https://atrium.lib.uoguelph.ca/xmlui/handle/10214/17377.

MLA Handbook (7th Edition):

Al-Hyari, Abeer. “Towards Smart FPGA Placement Using Machine Learning.” 2019. Web. 11 Apr 2021.

Vancouver:

Al-Hyari A. Towards Smart FPGA Placement Using Machine Learning. [Internet] [Doctoral dissertation]. University of Guelph; 2019. [cited 2021 Apr 11]. Available from: https://atrium.lib.uoguelph.ca/xmlui/handle/10214/17377.

Council of Science Editors:

Al-Hyari A. Towards Smart FPGA Placement Using Machine Learning. [Doctoral Dissertation]. University of Guelph; 2019. Available from: https://atrium.lib.uoguelph.ca/xmlui/handle/10214/17377


University of Illinois – Chicago

12. Shi, Ouwen. Operation Scheduling Algorithms for Power, Energy and Resource Minimization in High-Level Synthesis.

Degree: 2017, University of Illinois – Chicago

 Power, energy and resource minimization subject to a latency constraint are important optimization objectives in operation scheduling in high-level synthesis. The research work presented herein… (more)

Subjects/Keywords: VLSI; Computer Aided Design; Electronic Design Automation; High Level Synthesis; Operation Scheduling

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APA (6th Edition):

Shi, O. (2017). Operation Scheduling Algorithms for Power, Energy and Resource Minimization in High-Level Synthesis. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/22122

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shi, Ouwen. “Operation Scheduling Algorithms for Power, Energy and Resource Minimization in High-Level Synthesis.” 2017. Thesis, University of Illinois – Chicago. Accessed April 11, 2021. http://hdl.handle.net/10027/22122.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shi, Ouwen. “Operation Scheduling Algorithms for Power, Energy and Resource Minimization in High-Level Synthesis.” 2017. Web. 11 Apr 2021.

Vancouver:

Shi O. Operation Scheduling Algorithms for Power, Energy and Resource Minimization in High-Level Synthesis. [Internet] [Thesis]. University of Illinois – Chicago; 2017. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10027/22122.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shi O. Operation Scheduling Algorithms for Power, Energy and Resource Minimization in High-Level Synthesis. [Thesis]. University of Illinois – Chicago; 2017. Available from: http://hdl.handle.net/10027/22122

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Cornell University

13. Liu, Gai. Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors.

Degree: PhD, Electrical and Computer Engineering, 2018, Cornell University

 Technology scaling, architectural innovations, and electronic design automation (EDA) are the three pillars supporting the exponential growth in computer hardware performance for the past six… (more)

Subjects/Keywords: Architectural Synthesis; Cross-Stage Optimization; Electronic Design Automation; Logic Synthesis; Computer engineering; Engineering

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APA (6th Edition):

Liu, G. (2018). Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors. (Doctoral Dissertation). Cornell University. Retrieved from http://hdl.handle.net/1813/64855

Chicago Manual of Style (16th Edition):

Liu, Gai. “Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors.” 2018. Doctoral Dissertation, Cornell University. Accessed April 11, 2021. http://hdl.handle.net/1813/64855.

MLA Handbook (7th Edition):

Liu, Gai. “Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors.” 2018. Web. 11 Apr 2021.

Vancouver:

Liu G. Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors. [Internet] [Doctoral dissertation]. Cornell University; 2018. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1813/64855.

Council of Science Editors:

Liu G. Cross-Stage Logic and Architectural Synthesis: with Applications to Specialized Circuits and Programmable Processors. [Doctoral Dissertation]. Cornell University; 2018. Available from: http://hdl.handle.net/1813/64855


Texas A&M University

14. Wang, Ya. Efficient and Robust Simulation, Modeling and Characterization of IC Power Delivery Circuits.

Degree: PhD, Computer Engineering, 2017, Texas A&M University

 As the Moore’s Law continues to drive IC technology, power delivery has become one of the most difficult design challenges. Two of the major components… (more)

Subjects/Keywords: Circuit Simulation; Electronic Design Automation; Linear System Solution; Power Electronics; Average Modeling

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APA (6th Edition):

Wang, Y. (2017). Efficient and Robust Simulation, Modeling and Characterization of IC Power Delivery Circuits. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/187303

Chicago Manual of Style (16th Edition):

Wang, Ya. “Efficient and Robust Simulation, Modeling and Characterization of IC Power Delivery Circuits.” 2017. Doctoral Dissertation, Texas A&M University. Accessed April 11, 2021. http://hdl.handle.net/1969.1/187303.

MLA Handbook (7th Edition):

Wang, Ya. “Efficient and Robust Simulation, Modeling and Characterization of IC Power Delivery Circuits.” 2017. Web. 11 Apr 2021.

Vancouver:

Wang Y. Efficient and Robust Simulation, Modeling and Characterization of IC Power Delivery Circuits. [Internet] [Doctoral dissertation]. Texas A&M University; 2017. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1969.1/187303.

Council of Science Editors:

Wang Y. Efficient and Robust Simulation, Modeling and Characterization of IC Power Delivery Circuits. [Doctoral Dissertation]. Texas A&M University; 2017. Available from: http://hdl.handle.net/1969.1/187303


University of California – Santa Cruz

15. Skinner, Haven Blake. Pyrope: A Latency-Insensitive Digital Architecture Toolchain.

Degree: Computer Engineering, 2018, University of California – Santa Cruz

 This paper proposes a new toolchain for digital architecture development which is designed to leverage Fluid Pipelines, a variant of latency-insensitive (LI) systems developed at… (more)

Subjects/Keywords: Computer science; Computer engineering; architecture; compilers; electronic design automation; hardware description languages; programming languages; Pyrope

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APA (6th Edition):

Skinner, H. B. (2018). Pyrope: A Latency-Insensitive Digital Architecture Toolchain. (Thesis). University of California – Santa Cruz. Retrieved from http://www.escholarship.org/uc/item/9md197hq

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Skinner, Haven Blake. “Pyrope: A Latency-Insensitive Digital Architecture Toolchain.” 2018. Thesis, University of California – Santa Cruz. Accessed April 11, 2021. http://www.escholarship.org/uc/item/9md197hq.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Skinner, Haven Blake. “Pyrope: A Latency-Insensitive Digital Architecture Toolchain.” 2018. Web. 11 Apr 2021.

Vancouver:

Skinner HB. Pyrope: A Latency-Insensitive Digital Architecture Toolchain. [Internet] [Thesis]. University of California – Santa Cruz; 2018. [cited 2021 Apr 11]. Available from: http://www.escholarship.org/uc/item/9md197hq.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Skinner HB. Pyrope: A Latency-Insensitive Digital Architecture Toolchain. [Thesis]. University of California – Santa Cruz; 2018. Available from: http://www.escholarship.org/uc/item/9md197hq

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

16. Wu, Pei-Ci. New methods for electronic design automation problems.

Degree: PhD, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 As the semiconductor technology marches towards the 14nm node and beyond, EDA (electronic design automation) has rapidly increased in importance with ever more complicated modern… (more)

Subjects/Keywords: Electronic Design Automation (EDA); Timing Closure; Buffer Insertion; Aerial Image Simulation; Escape Routing; Bus Planner

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, P. (2015). New methods for electronic design automation problems. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78447

Chicago Manual of Style (16th Edition):

Wu, Pei-Ci. “New methods for electronic design automation problems.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 11, 2021. http://hdl.handle.net/2142/78447.

MLA Handbook (7th Edition):

Wu, Pei-Ci. “New methods for electronic design automation problems.” 2015. Web. 11 Apr 2021.

Vancouver:

Wu P. New methods for electronic design automation problems. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2142/78447.

Council of Science Editors:

Wu P. New methods for electronic design automation problems. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78447


University of Illinois – Urbana-Champaign

17. Xiao, Zigang. Design automation algorithms for advanced lithography.

Degree: PhD, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 In circuit manufacturing, as the technology nodes keep shrinking, conventional 193 nm immersion lithography (193i) has reached its printability limit. To continue the scaling with… (more)

Subjects/Keywords: Electronic Design Automation; Compute-aided Design; Lithography; Self-aligned Double Patterning; Directed Self-Assembly; Machine Learning; Design-Technology Co-optimization

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APA (6th Edition):

Xiao, Z. (2015). Design automation algorithms for advanced lithography. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/88991

Chicago Manual of Style (16th Edition):

Xiao, Zigang. “Design automation algorithms for advanced lithography.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 11, 2021. http://hdl.handle.net/2142/88991.

MLA Handbook (7th Edition):

Xiao, Zigang. “Design automation algorithms for advanced lithography.” 2015. Web. 11 Apr 2021.

Vancouver:

Xiao Z. Design automation algorithms for advanced lithography. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2142/88991.

Council of Science Editors:

Xiao Z. Design automation algorithms for advanced lithography. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/88991


University of Toronto

18. Lo, Charles. Improving Hardware Design Reuse through Design-space Exploration.

Degree: PhD, 2020, University of Toronto

 The continued demand for higher performance and more energy efficient systems has fueled interest in specialized hardware. However, the design of such systems has large… (more)

Subjects/Keywords: Bayesian Optimization; Computer-Aided Design (CAD); Electronic Design Automation (EDA); Field-Programmable Gate Array (FPGA); Gaussian Process; Kriging; 0464

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APA (6th Edition):

Lo, C. (2020). Improving Hardware Design Reuse through Design-space Exploration. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/101092

Chicago Manual of Style (16th Edition):

Lo, Charles. “Improving Hardware Design Reuse through Design-space Exploration.” 2020. Doctoral Dissertation, University of Toronto. Accessed April 11, 2021. http://hdl.handle.net/1807/101092.

MLA Handbook (7th Edition):

Lo, Charles. “Improving Hardware Design Reuse through Design-space Exploration.” 2020. Web. 11 Apr 2021.

Vancouver:

Lo C. Improving Hardware Design Reuse through Design-space Exploration. [Internet] [Doctoral dissertation]. University of Toronto; 2020. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1807/101092.

Council of Science Editors:

Lo C. Improving Hardware Design Reuse through Design-space Exploration. [Doctoral Dissertation]. University of Toronto; 2020. Available from: http://hdl.handle.net/1807/101092


University of Toronto

19. Moudallal, Zahi. Voltage-drop and Electromigration in Chip Power Grids.

Degree: PhD, 2019, University of Toronto

 A major challenge in modern chip design is the design and analysis of the chip's power grid  – the network that relays power from the… (more)

Subjects/Keywords: Chip Power Grids; Computer-Aided Design; Electronic Design Automation; Power Distribution Network; VLSI; Voltage Integrity Verification; 0464

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APA (6th Edition):

Moudallal, Z. (2019). Voltage-drop and Electromigration in Chip Power Grids. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/95976

Chicago Manual of Style (16th Edition):

Moudallal, Zahi. “Voltage-drop and Electromigration in Chip Power Grids.” 2019. Doctoral Dissertation, University of Toronto. Accessed April 11, 2021. http://hdl.handle.net/1807/95976.

MLA Handbook (7th Edition):

Moudallal, Zahi. “Voltage-drop and Electromigration in Chip Power Grids.” 2019. Web. 11 Apr 2021.

Vancouver:

Moudallal Z. Voltage-drop and Electromigration in Chip Power Grids. [Internet] [Doctoral dissertation]. University of Toronto; 2019. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1807/95976.

Council of Science Editors:

Moudallal Z. Voltage-drop and Electromigration in Chip Power Grids. [Doctoral Dissertation]. University of Toronto; 2019. Available from: http://hdl.handle.net/1807/95976


Virginia Tech

20. Zha, Wenwei. Facilitating FPGA Reconfiguration through Low-level Manipulation.

Degree: PhD, Electrical Engineering, 2014, Virginia Tech

 The process of FPGA reconfiguration is to recompile a design and then update the FPGA configuration correspondingly. Traditionally, FPGA design compilation follows the way how… (more)

Subjects/Keywords: FPGA Reconfiguration; Bitstream-level Manipulation; FPGA Routing; Module Reuse; Design Assembly; Autonomous Adaptive Systems; Electronic Design Automation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zha, W. (2014). Facilitating FPGA Reconfiguration through Low-level Manipulation. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/46787

Chicago Manual of Style (16th Edition):

Zha, Wenwei. “Facilitating FPGA Reconfiguration through Low-level Manipulation.” 2014. Doctoral Dissertation, Virginia Tech. Accessed April 11, 2021. http://hdl.handle.net/10919/46787.

MLA Handbook (7th Edition):

Zha, Wenwei. “Facilitating FPGA Reconfiguration through Low-level Manipulation.” 2014. Web. 11 Apr 2021.

Vancouver:

Zha W. Facilitating FPGA Reconfiguration through Low-level Manipulation. [Internet] [Doctoral dissertation]. Virginia Tech; 2014. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10919/46787.

Council of Science Editors:

Zha W. Facilitating FPGA Reconfiguration through Low-level Manipulation. [Doctoral Dissertation]. Virginia Tech; 2014. Available from: http://hdl.handle.net/10919/46787


University of Texas – Austin

21. Chung, Jae Yong, 1981-. Refactoring-based statistical timing analysis and its applications to robust design and test synthesis.

Degree: PhD, Electrical and Computer Engineering, 2011, University of Texas – Austin

 Technology scaling in the nanometer era comes with a significant amount of process variation, leading to lower yield and new types of defective parts. These… (more)

Subjects/Keywords: Applied algorithms; Electronic design automation; Computer-aided design; Statistical timing; Process variation; At-speed test; Delay test; Max-plus algebra

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chung, Jae Yong, 1. (2011). Refactoring-based statistical timing analysis and its applications to robust design and test synthesis. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2011-05-3252

Chicago Manual of Style (16th Edition):

Chung, Jae Yong, 1981-. “Refactoring-based statistical timing analysis and its applications to robust design and test synthesis.” 2011. Doctoral Dissertation, University of Texas – Austin. Accessed April 11, 2021. http://hdl.handle.net/2152/ETD-UT-2011-05-3252.

MLA Handbook (7th Edition):

Chung, Jae Yong, 1981-. “Refactoring-based statistical timing analysis and its applications to robust design and test synthesis.” 2011. Web. 11 Apr 2021.

Vancouver:

Chung, Jae Yong 1. Refactoring-based statistical timing analysis and its applications to robust design and test synthesis. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2011. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2152/ETD-UT-2011-05-3252.

Council of Science Editors:

Chung, Jae Yong 1. Refactoring-based statistical timing analysis and its applications to robust design and test synthesis. [Doctoral Dissertation]. University of Texas – Austin; 2011. Available from: http://hdl.handle.net/2152/ETD-UT-2011-05-3252


University of California – Irvine

22. Harris, Christopher Bryant. Generating Formal Verification Properties from Natural Language Hardware Specifications.

Degree: Electrical and Computer Engineering, 2015, University of California – Irvine

 Verification of modern digital systems can consume up to 70% of the design cycle. Verification engineers must create formal properties which reflect correct operation from… (more)

Subjects/Keywords: Computer engineering; Electrical engineering; Computer science; Assertion Based Verification; Computer Architecture; Electronic Design Automation; Formal Verification; Natural Language Processing

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APA (6th Edition):

Harris, C. B. (2015). Generating Formal Verification Properties from Natural Language Hardware Specifications. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/11d7k48g

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Harris, Christopher Bryant. “Generating Formal Verification Properties from Natural Language Hardware Specifications.” 2015. Thesis, University of California – Irvine. Accessed April 11, 2021. http://www.escholarship.org/uc/item/11d7k48g.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Harris, Christopher Bryant. “Generating Formal Verification Properties from Natural Language Hardware Specifications.” 2015. Web. 11 Apr 2021.

Vancouver:

Harris CB. Generating Formal Verification Properties from Natural Language Hardware Specifications. [Internet] [Thesis]. University of California – Irvine; 2015. [cited 2021 Apr 11]. Available from: http://www.escholarship.org/uc/item/11d7k48g.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Harris CB. Generating Formal Verification Properties from Natural Language Hardware Specifications. [Thesis]. University of California – Irvine; 2015. Available from: http://www.escholarship.org/uc/item/11d7k48g

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Mississippi State University

23. Holland, Wesley. A FRAMEWORK FOR AUTOMATICALLY GENERATING OPTIMIZED DIGITAL DESIGNS FROM C-LANGUAGE LOOPS.

Degree: MS, Electrical and Computer Engineering, 2008, Mississippi State University

 Reconfigurable computing has the potential for providing significant performance increases to a number of computing applications. However, realizing these benefits requires digital design experience and… (more)

Subjects/Keywords: temporal relocation; electronic design automation; reconfigurable computing

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APA (6th Edition):

Holland, W. (2008). A FRAMEWORK FOR AUTOMATICALLY GENERATING OPTIMIZED DIGITAL DESIGNS FROM C-LANGUAGE LOOPS. (Masters Thesis). Mississippi State University. Retrieved from http://sun.library.msstate.edu/ETD-db/theses/available/etd-04012008-162427/ ;

Chicago Manual of Style (16th Edition):

Holland, Wesley. “A FRAMEWORK FOR AUTOMATICALLY GENERATING OPTIMIZED DIGITAL DESIGNS FROM C-LANGUAGE LOOPS.” 2008. Masters Thesis, Mississippi State University. Accessed April 11, 2021. http://sun.library.msstate.edu/ETD-db/theses/available/etd-04012008-162427/ ;.

MLA Handbook (7th Edition):

Holland, Wesley. “A FRAMEWORK FOR AUTOMATICALLY GENERATING OPTIMIZED DIGITAL DESIGNS FROM C-LANGUAGE LOOPS.” 2008. Web. 11 Apr 2021.

Vancouver:

Holland W. A FRAMEWORK FOR AUTOMATICALLY GENERATING OPTIMIZED DIGITAL DESIGNS FROM C-LANGUAGE LOOPS. [Internet] [Masters thesis]. Mississippi State University; 2008. [cited 2021 Apr 11]. Available from: http://sun.library.msstate.edu/ETD-db/theses/available/etd-04012008-162427/ ;.

Council of Science Editors:

Holland W. A FRAMEWORK FOR AUTOMATICALLY GENERATING OPTIMIZED DIGITAL DESIGNS FROM C-LANGUAGE LOOPS. [Masters Thesis]. Mississippi State University; 2008. Available from: http://sun.library.msstate.edu/ETD-db/theses/available/etd-04012008-162427/ ;


University of Michigan

24. Kim, Joonyoung. Incremental Boolean satisfiability and its application to electronic design automation.

Degree: PhD, Electrical engineering, 2001, University of Michigan

 Boolean satisfiability has been successfully applied to various problems in electronic design automation. These applications typically involve targeting and solving a set of related satisfiability… (more)

Subjects/Keywords: Application; Boolean Satisfiability; Electronic Design Automation; Incremental

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, J. (2001). Incremental Boolean satisfiability and its application to electronic design automation. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/123247

Chicago Manual of Style (16th Edition):

Kim, Joonyoung. “Incremental Boolean satisfiability and its application to electronic design automation.” 2001. Doctoral Dissertation, University of Michigan. Accessed April 11, 2021. http://hdl.handle.net/2027.42/123247.

MLA Handbook (7th Edition):

Kim, Joonyoung. “Incremental Boolean satisfiability and its application to electronic design automation.” 2001. Web. 11 Apr 2021.

Vancouver:

Kim J. Incremental Boolean satisfiability and its application to electronic design automation. [Internet] [Doctoral dissertation]. University of Michigan; 2001. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2027.42/123247.

Council of Science Editors:

Kim J. Incremental Boolean satisfiability and its application to electronic design automation. [Doctoral Dissertation]. University of Michigan; 2001. Available from: http://hdl.handle.net/2027.42/123247

25. Kim, Myung Chul. Multiobjective Placement Optimization for High-performance Nanoscale Integrated Circuits.

Degree: PhD, Electrical Engineering, 2012, University of Michigan

 With aggressive scaling of semiconductor manufacturing technology in recent decades, the complexity of integrated circuits has increased rapidly leading to multi-million gate chips that require… (more)

Subjects/Keywords: Electronic Design Automation; Placement; Electrical Engineering; Engineering

…timing closure and require major improvements in physical design automation to maintain the… …circuit where StWL of the manually placed design is better than that of the automated placement… …from gate delay to interconnect delay. These trends confound modern design technologies for… …current pace of innovation in chip architecture. Modern VLSI design flows require considerable… …advanced VLSI processes and design styles. xiv Our research addresses new challenges in… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, M. C. (2012). Multiobjective Placement Optimization for High-performance Nanoscale Integrated Circuits. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/96055

Chicago Manual of Style (16th Edition):

Kim, Myung Chul. “Multiobjective Placement Optimization for High-performance Nanoscale Integrated Circuits.” 2012. Doctoral Dissertation, University of Michigan. Accessed April 11, 2021. http://hdl.handle.net/2027.42/96055.

MLA Handbook (7th Edition):

Kim, Myung Chul. “Multiobjective Placement Optimization for High-performance Nanoscale Integrated Circuits.” 2012. Web. 11 Apr 2021.

Vancouver:

Kim MC. Multiobjective Placement Optimization for High-performance Nanoscale Integrated Circuits. [Internet] [Doctoral dissertation]. University of Michigan; 2012. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/2027.42/96055.

Council of Science Editors:

Kim MC. Multiobjective Placement Optimization for High-performance Nanoscale Integrated Circuits. [Doctoral Dissertation]. University of Michigan; 2012. Available from: http://hdl.handle.net/2027.42/96055


Vanderbilt University

26. Assis, Thiago Rocha de. Soft error aware physical synthesis.

Degree: PhD, Electrical Engineering, 2015, Vanderbilt University

 To allow accurate analysis of Soft Errors by Electronic Design Automation (EDA) tools, analytical models were developed to estimate electrical characteristics of the single event.… (more)

Subjects/Keywords: single event transient; set pulse width; collected charge; radiation effects; electronic design automation; physical synthesis; soft error; reliability

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Assis, T. R. d. (2015). Soft error aware physical synthesis. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14789

Chicago Manual of Style (16th Edition):

Assis, Thiago Rocha de. “Soft error aware physical synthesis.” 2015. Doctoral Dissertation, Vanderbilt University. Accessed April 11, 2021. http://hdl.handle.net/1803/14789.

MLA Handbook (7th Edition):

Assis, Thiago Rocha de. “Soft error aware physical synthesis.” 2015. Web. 11 Apr 2021.

Vancouver:

Assis TRd. Soft error aware physical synthesis. [Internet] [Doctoral dissertation]. Vanderbilt University; 2015. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/1803/14789.

Council of Science Editors:

Assis TRd. Soft error aware physical synthesis. [Doctoral Dissertation]. Vanderbilt University; 2015. Available from: http://hdl.handle.net/1803/14789

27. Mirsaeedi, Minoo. EDA Solutions for Double Patterning Lithography.

Degree: 2012, University of Waterloo

 Expanding the optical lithography to 32-nm node and beyond is impossible using existing single exposure systems. As such, double patterning lithography (DPL) is the most… (more)

Subjects/Keywords: Electronic Design Automation; Double Patterning Lithography

…Different levels of physical design flow studied in this thesis. . . . . . . . . 4 2.1 Major… …23 2.19 CDU and overlay errors dictate the design rule decisions. . . . . . . . . . . 24… …patterns should not violate design constraints, (b) Stronger protection is achievable… …design flow yet because their large time complexity makes them inapplicable for large layouts… …automated techniques for DPL design are very immature. Motivated by the above facts, automated… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mirsaeedi, M. (2012). EDA Solutions for Double Patterning Lithography. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/6936

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mirsaeedi, Minoo. “EDA Solutions for Double Patterning Lithography.” 2012. Thesis, University of Waterloo. Accessed April 11, 2021. http://hdl.handle.net/10012/6936.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mirsaeedi, Minoo. “EDA Solutions for Double Patterning Lithography.” 2012. Web. 11 Apr 2021.

Vancouver:

Mirsaeedi M. EDA Solutions for Double Patterning Lithography. [Internet] [Thesis]. University of Waterloo; 2012. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10012/6936.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mirsaeedi M. EDA Solutions for Double Patterning Lithography. [Thesis]. University of Waterloo; 2012. Available from: http://hdl.handle.net/10012/6936

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of South Africa

28. Molepo, Isaih Kgabe. Data acquisition system for pilot mill.

Degree: 2016, University of South Africa

 This dissertation describes the development, design, implementation and evaluation of a data acquisition system, with the main aim of using it for data collection on… (more)

Subjects/Keywords: Data Acquisition System; Digital Signal Processing; Electronic Design Automation; Peripheral Component Interconnect; Real-Time Operating System

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Molepo, I. K. (2016). Data acquisition system for pilot mill. (Masters Thesis). University of South Africa. Retrieved from http://hdl.handle.net/10500/22967

Chicago Manual of Style (16th Edition):

Molepo, Isaih Kgabe. “Data acquisition system for pilot mill.” 2016. Masters Thesis, University of South Africa. Accessed April 11, 2021. http://hdl.handle.net/10500/22967.

MLA Handbook (7th Edition):

Molepo, Isaih Kgabe. “Data acquisition system for pilot mill.” 2016. Web. 11 Apr 2021.

Vancouver:

Molepo IK. Data acquisition system for pilot mill. [Internet] [Masters thesis]. University of South Africa; 2016. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10500/22967.

Council of Science Editors:

Molepo IK. Data acquisition system for pilot mill. [Masters Thesis]. University of South Africa; 2016. Available from: http://hdl.handle.net/10500/22967

29. Gunter, Alexander Keith. Design and Investigation of Genetic Algorithmic and Reinforcement Learning Approaches to Wire Crossing Reductions for pNML Devices.

Degree: M.S. in Engineering Science, Electrical Engineering, 2019, University of Mississippi

 Perpendicular nanomagnet logic (pNML) is an emerging post-CMOS technology which encodes binary data in the polarization of single-domain nanomagnets and performs operations via fringing field… (more)

Subjects/Keywords: Crossing Reduction; Electronic Design Automation; Genetic Algorithm; Nanomagnet Logic; Quantum-Dot Cellular Automata; Reinforcement Learning; Electrical and Computer Engineering

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APA (6th Edition):

Gunter, A. K. (2019). Design and Investigation of Genetic Algorithmic and Reinforcement Learning Approaches to Wire Crossing Reductions for pNML Devices. (Thesis). University of Mississippi. Retrieved from https://egrove.olemiss.edu/etd/1597

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gunter, Alexander Keith. “Design and Investigation of Genetic Algorithmic and Reinforcement Learning Approaches to Wire Crossing Reductions for pNML Devices.” 2019. Thesis, University of Mississippi. Accessed April 11, 2021. https://egrove.olemiss.edu/etd/1597.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gunter, Alexander Keith. “Design and Investigation of Genetic Algorithmic and Reinforcement Learning Approaches to Wire Crossing Reductions for pNML Devices.” 2019. Web. 11 Apr 2021.

Vancouver:

Gunter AK. Design and Investigation of Genetic Algorithmic and Reinforcement Learning Approaches to Wire Crossing Reductions for pNML Devices. [Internet] [Thesis]. University of Mississippi; 2019. [cited 2021 Apr 11]. Available from: https://egrove.olemiss.edu/etd/1597.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gunter AK. Design and Investigation of Genetic Algorithmic and Reinforcement Learning Approaches to Wire Crossing Reductions for pNML Devices. [Thesis]. University of Mississippi; 2019. Available from: https://egrove.olemiss.edu/etd/1597

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

30. Owaida, Muhsen. Using a parallel programming model for architectural synthesis.

Degree: 2012, University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας

The problem of automatically generating hardware modules from high level application representations has been at the forefront of EDA research during the last few years.… (more)

Subjects/Keywords: Αυτόματη ηλεκτρονική σχεδίαση; Επαναπροσδιοριζόμενος υπολογισμός; Ενσωματωμένα τηλεπικοινωνιακά συστήματα; OpenCL; FPGA; Electronic design automation; Reconfigurable computing; Embedded systems

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APA (6th Edition):

Owaida, M. (2012). Using a parallel programming model for architectural synthesis. (Thesis). University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας. Retrieved from http://hdl.handle.net/10442/hedi/27597

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Owaida, Muhsen. “Using a parallel programming model for architectural synthesis.” 2012. Thesis, University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας. Accessed April 11, 2021. http://hdl.handle.net/10442/hedi/27597.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Owaida, Muhsen. “Using a parallel programming model for architectural synthesis.” 2012. Web. 11 Apr 2021.

Vancouver:

Owaida M. Using a parallel programming model for architectural synthesis. [Internet] [Thesis]. University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας; 2012. [cited 2021 Apr 11]. Available from: http://hdl.handle.net/10442/hedi/27597.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Owaida M. Using a parallel programming model for architectural synthesis. [Thesis]. University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας; 2012. Available from: http://hdl.handle.net/10442/hedi/27597

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2]

.