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You searched for subject:(Electronic Gate Delay Modeling). Showing records 1 – 30 of 51696 total matches.

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Indian Institute of Science

1. Das, Bishnu Prasad. Random Local Delay Variability : On-chip Measurement And Modeling.

Degree: 2009, Indian Institute of Science

 This thesis focuses on random local delay variability measurement and its modeling. It explains a circuit technique to measure the individual logic gate delay in… (more)

Subjects/Keywords: Electronic Gates - Design; On-chip Management And Construction; Electronic Gate Delay - Modeling; Random Local Delay Variation; On-chip Gate Delay Measurement; Process Voltage And Temperature Gate Delay Model; Electronic Gate Delay - Measurement; Statistical Static Timing Analysis (SSTA); Gate Delay Variability Measurement; Delay Variability; On-chip Measurement; Gate Delay Models; Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Das, B. P. (2009). Random Local Delay Variability : On-chip Measurement And Modeling. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1008

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Das, Bishnu Prasad. “Random Local Delay Variability : On-chip Measurement And Modeling.” 2009. Thesis, Indian Institute of Science. Accessed April 02, 2020. http://hdl.handle.net/2005/1008.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Das, Bishnu Prasad. “Random Local Delay Variability : On-chip Measurement And Modeling.” 2009. Web. 02 Apr 2020.

Vancouver:

Das BP. Random Local Delay Variability : On-chip Measurement And Modeling. [Internet] [Thesis]. Indian Institute of Science; 2009. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/2005/1008.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Das BP. Random Local Delay Variability : On-chip Measurement And Modeling. [Thesis]. Indian Institute of Science; 2009. Available from: http://hdl.handle.net/2005/1008

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

2. Harish, B P. Process Variability-Aware Performance Modeling In 65 nm CMOS.

Degree: 2006, Indian Institute of Science

 With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all… (more)

Subjects/Keywords: Complementary Metal Oxide Semiconductors; Semiconductors; NAND Gate; Gate Delay Models; CMOS Digital Circuits; Circuit Design; Circuit Delay Performance; Circuit Delay Distribution; CMOS Designs; 65nm CMOS; Electronic Engineering

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APA (6th Edition):

Harish, B. P. (2006). Process Variability-Aware Performance Modeling In 65 nm CMOS. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1080

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Harish, B P. “Process Variability-Aware Performance Modeling In 65 nm CMOS.” 2006. Thesis, Indian Institute of Science. Accessed April 02, 2020. http://hdl.handle.net/2005/1080.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Harish, B P. “Process Variability-Aware Performance Modeling In 65 nm CMOS.” 2006. Web. 02 Apr 2020.

Vancouver:

Harish BP. Process Variability-Aware Performance Modeling In 65 nm CMOS. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/2005/1080.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Harish BP. Process Variability-Aware Performance Modeling In 65 nm CMOS. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/1080

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

3. Srivatsava, J. Compact Modeling Of Asymmetric/Independent Double Gate MOSFET.

Degree: 2012, Indian Institute of Science

 For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. In order to continue the technology… (more)

Subjects/Keywords: Asymmetric Double Gate MOSFET; Asymmetric Double Gate Transistor - Compact Modeling; Transistor Performance; Common-Gate Asymmetric Double Gate MOSFET; Independent-gate Asymmetric Double Gate MOSFET; DG MOSFET; Double Gate MOSFET; Metal Oxide Semiconductor Field Effect Transistor; Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Srivatsava, J. (2012). Compact Modeling Of Asymmetric/Independent Double Gate MOSFET. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2346

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Srivatsava, J. “Compact Modeling Of Asymmetric/Independent Double Gate MOSFET.” 2012. Thesis, Indian Institute of Science. Accessed April 02, 2020. http://hdl.handle.net/2005/2346.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Srivatsava, J. “Compact Modeling Of Asymmetric/Independent Double Gate MOSFET.” 2012. Web. 02 Apr 2020.

Vancouver:

Srivatsava J. Compact Modeling Of Asymmetric/Independent Double Gate MOSFET. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/2005/2346.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Srivatsava J. Compact Modeling Of Asymmetric/Independent Double Gate MOSFET. [Thesis]. Indian Institute of Science; 2012. Available from: http://hdl.handle.net/2005/2346

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

4. Srivatsava, J. Compact Modeling Of Asymmetric/Independent Double Gate MOSFET.

Degree: 2012, Indian Institute of Science

 For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. In order to continue the technology… (more)

Subjects/Keywords: Asymmetric Double Gate MOSFET; Asymmetric Double Gate Transistor - Compact Modeling; Transistor Performance; Common-Gate Asymmetric Double Gate MOSFET; Independent-gate Asymmetric Double Gate MOSFET; DG MOSFET; Double Gate MOSFET; Metal Oxide Semiconductor Field Effect Transistor; Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Srivatsava, J. (2012). Compact Modeling Of Asymmetric/Independent Double Gate MOSFET. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2346 ; http://etd.ncsi.iisc.ernet.in/abstracts/3017/G25480-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Srivatsava, J. “Compact Modeling Of Asymmetric/Independent Double Gate MOSFET.” 2012. Thesis, Indian Institute of Science. Accessed April 02, 2020. http://etd.iisc.ernet.in/handle/2005/2346 ; http://etd.ncsi.iisc.ernet.in/abstracts/3017/G25480-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Srivatsava, J. “Compact Modeling Of Asymmetric/Independent Double Gate MOSFET.” 2012. Web. 02 Apr 2020.

Vancouver:

Srivatsava J. Compact Modeling Of Asymmetric/Independent Double Gate MOSFET. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2020 Apr 02]. Available from: http://etd.iisc.ernet.in/handle/2005/2346 ; http://etd.ncsi.iisc.ernet.in/abstracts/3017/G25480-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Srivatsava J. Compact Modeling Of Asymmetric/Independent Double Gate MOSFET. [Thesis]. Indian Institute of Science; 2012. Available from: http://etd.iisc.ernet.in/handle/2005/2346 ; http://etd.ncsi.iisc.ernet.in/abstracts/3017/G25480-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

5. Sharan, Neha. Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry.

Degree: 2014, Indian Institute of Science

 Compact Models are the physically based accurate mathematical description of the cir-cuit elements, which are computationally efficient enough to be incorporated in circuit simulators so… (more)

Subjects/Keywords: Metal Semiconductor Field Effect Transistors (MOSFET); Common Double Gate (CDG) MOSFETs-Compact Modeling; Electronic Circuits-Design; Transistor Circuits; MOSFETs-Core Model; Double Gate MOSFETs; Asymmetric CDG MOSFETs; Semiconductor Device Modeling; Gate Oxide Thickness Asymmetry; Gate Oxide Asymmetry; Electronic Systems Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sharan, N. (2014). Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3489 ; http://etd.iisc.ernet.in/abstracts/4356/G26589-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sharan, Neha. “Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry.” 2014. Thesis, Indian Institute of Science. Accessed April 02, 2020. http://etd.iisc.ernet.in/2005/3489 ; http://etd.iisc.ernet.in/abstracts/4356/G26589-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sharan, Neha. “Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry.” 2014. Web. 02 Apr 2020.

Vancouver:

Sharan N. Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry. [Internet] [Thesis]. Indian Institute of Science; 2014. [cited 2020 Apr 02]. Available from: http://etd.iisc.ernet.in/2005/3489 ; http://etd.iisc.ernet.in/abstracts/4356/G26589-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sharan N. Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry. [Thesis]. Indian Institute of Science; 2014. Available from: http://etd.iisc.ernet.in/2005/3489 ; http://etd.iisc.ernet.in/abstracts/4356/G26589-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

6. Kumar, P Rakesh. Analytical Modeling Of Quantum Thershold Voltage For Short Channel Multi Gate Silicon Nanowire Transistors.

Degree: 2009, Indian Institute of Science

 Silicon nanowire based multiple gate metal oxide field effect transistors(MG-MOSFET) appear as replacements for conventional bulk transistors in post 45nm technology nodes. In such transistors… (more)

Subjects/Keywords: Transistors; Silicon Nanowire Transistors; Quantum Threshold Voltage; Threshold Voltage Models; Transistors - Modeling; Double Gate Transistor; Cylindrical Gate Transistor; Quad Gate Transistor; Tri Gate Transistor; Cylindrical Gate All-around Transistor; Silicon Nanowire Transistor; MOSFET; Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kumar, P. R. (2009). Analytical Modeling Of Quantum Thershold Voltage For Short Channel Multi Gate Silicon Nanowire Transistors. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kumar, P Rakesh. “Analytical Modeling Of Quantum Thershold Voltage For Short Channel Multi Gate Silicon Nanowire Transistors.” 2009. Thesis, Indian Institute of Science. Accessed April 02, 2020. http://hdl.handle.net/2005/969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kumar, P Rakesh. “Analytical Modeling Of Quantum Thershold Voltage For Short Channel Multi Gate Silicon Nanowire Transistors.” 2009. Web. 02 Apr 2020.

Vancouver:

Kumar PR. Analytical Modeling Of Quantum Thershold Voltage For Short Channel Multi Gate Silicon Nanowire Transistors. [Internet] [Thesis]. Indian Institute of Science; 2009. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/2005/969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kumar PR. Analytical Modeling Of Quantum Thershold Voltage For Short Channel Multi Gate Silicon Nanowire Transistors. [Thesis]. Indian Institute of Science; 2009. Available from: http://hdl.handle.net/2005/969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

7. Ray, Biswajit. Impact Of Body Center Potential On The Electrostatics Of Undoped Body Multi Gate Transistors : A Modeling Perspective.

Degree: 2008, Indian Institute of Science

 Undoped body multi gate (MG) Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are appearing as replacements for single gate bulk MOSFET in forthcoming sub-45nm technology… (more)

Subjects/Keywords: Transistors (Electronics); Electrostatics; Transistors - Modeling; Gate-All-Around (GAA) Transistor; Double Gate Transistor; Omega Gate Nanowire Transistor; Metal Oxide Semiconductor Field Effect Transistors(MOSFET); Undoped Body Multi Gate Transistor; Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ray, B. (2008). Impact Of Body Center Potential On The Electrostatics Of Undoped Body Multi Gate Transistors : A Modeling Perspective. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/741

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ray, Biswajit. “Impact Of Body Center Potential On The Electrostatics Of Undoped Body Multi Gate Transistors : A Modeling Perspective.” 2008. Thesis, Indian Institute of Science. Accessed April 02, 2020. http://hdl.handle.net/2005/741.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ray, Biswajit. “Impact Of Body Center Potential On The Electrostatics Of Undoped Body Multi Gate Transistors : A Modeling Perspective.” 2008. Web. 02 Apr 2020.

Vancouver:

Ray B. Impact Of Body Center Potential On The Electrostatics Of Undoped Body Multi Gate Transistors : A Modeling Perspective. [Internet] [Thesis]. Indian Institute of Science; 2008. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/2005/741.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ray B. Impact Of Body Center Potential On The Electrostatics Of Undoped Body Multi Gate Transistors : A Modeling Perspective. [Thesis]. Indian Institute of Science; 2008. Available from: http://hdl.handle.net/2005/741

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

8. Jackson, Meredith A. Do Roundabouts Work? An Evaluation for Uniform Approach Demands.

Degree: MS, Civil Engineering, 2011, Virginia Tech

 With the increased prevalence of roundabouts in the United States, there is a need to evaluate the performance of roundabouts relative to other intersection control… (more)

Subjects/Keywords: Delay; Emissions modeling; Roundabouts

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APA (6th Edition):

Jackson, M. A. (2011). Do Roundabouts Work? An Evaluation for Uniform Approach Demands. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/76831

Chicago Manual of Style (16th Edition):

Jackson, Meredith A. “Do Roundabouts Work? An Evaluation for Uniform Approach Demands.” 2011. Masters Thesis, Virginia Tech. Accessed April 02, 2020. http://hdl.handle.net/10919/76831.

MLA Handbook (7th Edition):

Jackson, Meredith A. “Do Roundabouts Work? An Evaluation for Uniform Approach Demands.” 2011. Web. 02 Apr 2020.

Vancouver:

Jackson MA. Do Roundabouts Work? An Evaluation for Uniform Approach Demands. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/10919/76831.

Council of Science Editors:

Jackson MA. Do Roundabouts Work? An Evaluation for Uniform Approach Demands. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/76831


Indian Institute of Science

9. Ramesha, A. Sub-Threshold Slope Modeling & Gate Alignment Issues In Tunnel Field Effect Transistor.

Degree: 2008, Indian Institute of Science

 The Tunnel Field Effect Transistor (TFET) with sub-60mV/decade Sub-threshold slope and extremely high ION/IOFF ratio has attracted enough attention for low standby power (LSTP) applications… (more)

Subjects/Keywords: Tunnel-FET; Tunnel Field Effect Transistor (TFET); Band-to-Band Tunneling; Double Gate Tunnel Field Effect Transistor; Tunnel Field Effect Transistors - Modeling; Tunnel Field Effect Transistors - Gate Alignment; n-channel Double Gate TFET (nDGTFET); Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ramesha, A. (2008). Sub-Threshold Slope Modeling & Gate Alignment Issues In Tunnel Field Effect Transistor. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ramesha, A. “Sub-Threshold Slope Modeling & Gate Alignment Issues In Tunnel Field Effect Transistor.” 2008. Thesis, Indian Institute of Science. Accessed April 02, 2020. http://hdl.handle.net/2005/792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ramesha, A. “Sub-Threshold Slope Modeling & Gate Alignment Issues In Tunnel Field Effect Transistor.” 2008. Web. 02 Apr 2020.

Vancouver:

Ramesha A. Sub-Threshold Slope Modeling & Gate Alignment Issues In Tunnel Field Effect Transistor. [Internet] [Thesis]. Indian Institute of Science; 2008. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/2005/792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ramesha A. Sub-Threshold Slope Modeling & Gate Alignment Issues In Tunnel Field Effect Transistor. [Thesis]. Indian Institute of Science; 2008. Available from: http://hdl.handle.net/2005/792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universitat Rovira i Virgili

10. Weidemann, Michaela Patricia. Analytical predictive 2d modeling of pinch-off behavior in nanoscale multi-gate mosfets.

Degree: Departament d'Enginyeria Electrònica, Elèctrica i Automàtica, 2011, Universitat Rovira i Virgili

 In this thesis the pinch-off behavior in nanoscale Multi-Gate MOSFETs was reviewed and with compact models described. For this a 2D approach with Schwarz-Christoffel conformal… (more)

Subjects/Keywords: Modeling; Nanoscale; Multi-gate; Mosfet; 621.3

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Weidemann, M. P. (2011). Analytical predictive 2d modeling of pinch-off behavior in nanoscale multi-gate mosfets. (Thesis). Universitat Rovira i Virgili. Retrieved from http://hdl.handle.net/10803/52800

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Weidemann, Michaela Patricia. “Analytical predictive 2d modeling of pinch-off behavior in nanoscale multi-gate mosfets.” 2011. Thesis, Universitat Rovira i Virgili. Accessed April 02, 2020. http://hdl.handle.net/10803/52800.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Weidemann, Michaela Patricia. “Analytical predictive 2d modeling of pinch-off behavior in nanoscale multi-gate mosfets.” 2011. Web. 02 Apr 2020.

Vancouver:

Weidemann MP. Analytical predictive 2d modeling of pinch-off behavior in nanoscale multi-gate mosfets. [Internet] [Thesis]. Universitat Rovira i Virgili; 2011. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/10803/52800.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Weidemann MP. Analytical predictive 2d modeling of pinch-off behavior in nanoscale multi-gate mosfets. [Thesis]. Universitat Rovira i Virgili; 2011. Available from: http://hdl.handle.net/10803/52800

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arkansas

11. Perez, Sonia. Compact Modeling of SiC Insulated Gate Bipolar Transistors.

Degree: MS, 2016, University of Arkansas

  This thesis presents a unified (n-channel and p-channel) silicon/silicon carbide Insulated Gate Bipolar Transistor (IGBT) compact model in both MAST and Verilog-A formats. Initially,… (more)

Subjects/Keywords: Applied sciences; Compact modeling; IGBT; Insulated gate bipolar transistors; SiC; Silicon carbide; Electronic Devices and Semiconductor Manufacturing; VLSI and Circuits, Embedded and Hardware Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Perez, S. (2016). Compact Modeling of SiC Insulated Gate Bipolar Transistors. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1708

Chicago Manual of Style (16th Edition):

Perez, Sonia. “Compact Modeling of SiC Insulated Gate Bipolar Transistors.” 2016. Masters Thesis, University of Arkansas. Accessed April 02, 2020. https://scholarworks.uark.edu/etd/1708.

MLA Handbook (7th Edition):

Perez, Sonia. “Compact Modeling of SiC Insulated Gate Bipolar Transistors.” 2016. Web. 02 Apr 2020.

Vancouver:

Perez S. Compact Modeling of SiC Insulated Gate Bipolar Transistors. [Internet] [Masters thesis]. University of Arkansas; 2016. [cited 2020 Apr 02]. Available from: https://scholarworks.uark.edu/etd/1708.

Council of Science Editors:

Perez S. Compact Modeling of SiC Insulated Gate Bipolar Transistors. [Masters Thesis]. University of Arkansas; 2016. Available from: https://scholarworks.uark.edu/etd/1708


Purdue University

12. Sperduto, Brian M. Evaluating Flight Delay Benefits From The NextGen Program.

Degree: MS, Aviation Technology, 2014, Purdue University

  This research proposes a method to simulate the flight delay effects of the NextGen program against an actual flight schedule. With the advent of… (more)

Subjects/Keywords: Social sciences; Applied sciences; Flight delay; Flight delay modeling; Flight delay propagation; Nextgen; Transportation

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APA (6th Edition):

Sperduto, B. M. (2014). Evaluating Flight Delay Benefits From The NextGen Program. (Thesis). Purdue University. Retrieved from http://docs.lib.purdue.edu/open_access_theses/263

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sperduto, Brian M. “Evaluating Flight Delay Benefits From The NextGen Program.” 2014. Thesis, Purdue University. Accessed April 02, 2020. http://docs.lib.purdue.edu/open_access_theses/263.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sperduto, Brian M. “Evaluating Flight Delay Benefits From The NextGen Program.” 2014. Web. 02 Apr 2020.

Vancouver:

Sperduto BM. Evaluating Flight Delay Benefits From The NextGen Program. [Internet] [Thesis]. Purdue University; 2014. [cited 2020 Apr 02]. Available from: http://docs.lib.purdue.edu/open_access_theses/263.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sperduto BM. Evaluating Flight Delay Benefits From The NextGen Program. [Thesis]. Purdue University; 2014. Available from: http://docs.lib.purdue.edu/open_access_theses/263

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Florida

13. Nezvadovitz, Brian. Reliable FPGA Overclocking through Cycle Time Borrowing.

Degree: 2013, University of Florida

 Field programmable gate arrays (FPGAs) are reconfigurable devices that are commonly used to accelerate many high performance computing applications, including those in signal processing, numerical… (more)

Subjects/Keywords: Design optimization; Electric potential; Field programmable gate arrays; Microprocessors; Phase shift; Pipelines; Propagation delay; Recycling; Signals; Timber; Field programmable gate arrays

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APA (6th Edition):

Nezvadovitz, B. (2013). Reliable FPGA Overclocking through Cycle Time Borrowing. (Thesis). University of Florida. Retrieved from http://ufdc.ufl.edu/AA00059588

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nezvadovitz, Brian. “Reliable FPGA Overclocking through Cycle Time Borrowing.” 2013. Thesis, University of Florida. Accessed April 02, 2020. http://ufdc.ufl.edu/AA00059588.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nezvadovitz, Brian. “Reliable FPGA Overclocking through Cycle Time Borrowing.” 2013. Web. 02 Apr 2020.

Vancouver:

Nezvadovitz B. Reliable FPGA Overclocking through Cycle Time Borrowing. [Internet] [Thesis]. University of Florida; 2013. [cited 2020 Apr 02]. Available from: http://ufdc.ufl.edu/AA00059588.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nezvadovitz B. Reliable FPGA Overclocking through Cycle Time Borrowing. [Thesis]. University of Florida; 2013. Available from: http://ufdc.ufl.edu/AA00059588

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

14. Nelson, Shawna. Population Modeling with Delay Differential Equations.

Degree: MS, School of Mathematical Sciences (COS), 2013, Rochester Institute of Technology

  We investigate a delay differential equation system version of a model designed to describe finite time population collapse. The most commonly utilized population models… (more)

Subjects/Keywords: Delay; Differential; Easter Island; Equations; Modeling; Population

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APA (6th Edition):

Nelson, S. (2013). Population Modeling with Delay Differential Equations. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9078

Chicago Manual of Style (16th Edition):

Nelson, Shawna. “Population Modeling with Delay Differential Equations.” 2013. Masters Thesis, Rochester Institute of Technology. Accessed April 02, 2020. https://scholarworks.rit.edu/theses/9078.

MLA Handbook (7th Edition):

Nelson, Shawna. “Population Modeling with Delay Differential Equations.” 2013. Web. 02 Apr 2020.

Vancouver:

Nelson S. Population Modeling with Delay Differential Equations. [Internet] [Masters thesis]. Rochester Institute of Technology; 2013. [cited 2020 Apr 02]. Available from: https://scholarworks.rit.edu/theses/9078.

Council of Science Editors:

Nelson S. Population Modeling with Delay Differential Equations. [Masters Thesis]. Rochester Institute of Technology; 2013. Available from: https://scholarworks.rit.edu/theses/9078


Universidade do Rio Grande do Sul

15. Posser, Gracieli. Dimensionamento de portas lógicas usando programação geométrica.

Degree: 2011, Universidade do Rio Grande do Sul

Neste trabalho é desenvolvida uma ferramenta de dimensionamento de portas lógicas para circuitos integrados, utilizando técnicas de otimização de problemas baseadas em Programação Geométrica (PG).… (more)

Subjects/Keywords: Gate sizing; Microeletrônica; Physical synthesis; Circuitos integrados; Sintese automatica; Geometric programming; Elmore delay model; Microelectronics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Posser, G. (2011). Dimensionamento de portas lógicas usando programação geométrica. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/29571

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Posser, Gracieli. “Dimensionamento de portas lógicas usando programação geométrica.” 2011. Thesis, Universidade do Rio Grande do Sul. Accessed April 02, 2020. http://hdl.handle.net/10183/29571.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Posser, Gracieli. “Dimensionamento de portas lógicas usando programação geométrica.” 2011. Web. 02 Apr 2020.

Vancouver:

Posser G. Dimensionamento de portas lógicas usando programação geométrica. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2011. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/10183/29571.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Posser G. Dimensionamento de portas lógicas usando programação geométrica. [Thesis]. Universidade do Rio Grande do Sul; 2011. Available from: http://hdl.handle.net/10183/29571

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

16. Tang, Aoxiang. Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures .

Degree: PhD, 2015, Princeton University

 Technology scaling has been one of the most fundamental ways to improve chip performance and reduce power consumption. However, as the industry dives deeper into… (more)

Subjects/Keywords: delay modeling; FinFET; genetic algorithm; power modeling; PVT variation; SSTA

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APA (6th Edition):

Tang, A. (2015). Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01z890rw568

Chicago Manual of Style (16th Edition):

Tang, Aoxiang. “Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures .” 2015. Doctoral Dissertation, Princeton University. Accessed April 02, 2020. http://arks.princeton.edu/ark:/88435/dsp01z890rw568.

MLA Handbook (7th Edition):

Tang, Aoxiang. “Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures .” 2015. Web. 02 Apr 2020.

Vancouver:

Tang A. Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures . [Internet] [Doctoral dissertation]. Princeton University; 2015. [cited 2020 Apr 02]. Available from: http://arks.princeton.edu/ark:/88435/dsp01z890rw568.

Council of Science Editors:

Tang A. Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures . [Doctoral Dissertation]. Princeton University; 2015. Available from: http://arks.princeton.edu/ark:/88435/dsp01z890rw568


Montana State University

17. Dack, Connor Aquila. Development of a smart camera system using a system on module FPGA.

Degree: College of Engineering, 2017, Montana State University

 Imaging systems can now produce more data than conventional PCs with frame grabbers can process in real-time. Moving real-time custom computation as close as possible… (more)

Subjects/Keywords: Field programmable gate arrays.; Cameras.; Optical spectroscopy.; Electronic data processing.; Algorithms.

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APA (6th Edition):

Dack, C. A. (2017). Development of a smart camera system using a system on module FPGA. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/14902

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dack, Connor Aquila. “Development of a smart camera system using a system on module FPGA.” 2017. Thesis, Montana State University. Accessed April 02, 2020. https://scholarworks.montana.edu/xmlui/handle/1/14902.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dack, Connor Aquila. “Development of a smart camera system using a system on module FPGA.” 2017. Web. 02 Apr 2020.

Vancouver:

Dack CA. Development of a smart camera system using a system on module FPGA. [Internet] [Thesis]. Montana State University; 2017. [cited 2020 Apr 02]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/14902.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dack CA. Development of a smart camera system using a system on module FPGA. [Thesis]. Montana State University; 2017. Available from: https://scholarworks.montana.edu/xmlui/handle/1/14902

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. Riccardi, Elisa. Spectroscopie raman des excitations électroniques du graphène : Raman spectroscopy of electronic excitations in graphene.

Degree: Docteur es, Physique, 2017, Sorbonne Paris Cité

Depuis sa découverte, les propriétés électroniques exceptionnelles du graphène ont fait l'objet d'un nombre impressionnant d'études, faisant émerger un nouveau domaine de recherche autour des… (more)

Subjects/Keywords: Dispositifs; Effet de grille; Excitations electroniques; Devices; Gate Effect; Electronic excitations

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Riccardi, E. (2017). Spectroscopie raman des excitations électroniques du graphène : Raman spectroscopy of electronic excitations in graphene. (Doctoral Dissertation). Sorbonne Paris Cité. Retrieved from http://www.theses.fr/2017USPCC166

Chicago Manual of Style (16th Edition):

Riccardi, Elisa. “Spectroscopie raman des excitations électroniques du graphène : Raman spectroscopy of electronic excitations in graphene.” 2017. Doctoral Dissertation, Sorbonne Paris Cité. Accessed April 02, 2020. http://www.theses.fr/2017USPCC166.

MLA Handbook (7th Edition):

Riccardi, Elisa. “Spectroscopie raman des excitations électroniques du graphène : Raman spectroscopy of electronic excitations in graphene.” 2017. Web. 02 Apr 2020.

Vancouver:

Riccardi E. Spectroscopie raman des excitations électroniques du graphène : Raman spectroscopy of electronic excitations in graphene. [Internet] [Doctoral dissertation]. Sorbonne Paris Cité; 2017. [cited 2020 Apr 02]. Available from: http://www.theses.fr/2017USPCC166.

Council of Science Editors:

Riccardi E. Spectroscopie raman des excitations électroniques du graphène : Raman spectroscopy of electronic excitations in graphene. [Doctoral Dissertation]. Sorbonne Paris Cité; 2017. Available from: http://www.theses.fr/2017USPCC166


Universitat Rovira i Virgili

19. Nae, Bogdan Mihai. Compact modeling of the rf and noise behavior of multiple-gate mosfets.

Degree: Departament d'Enginyeria Electrònica, Elèctrica i Automàtica, 2011, Universitat Rovira i Virgili

 La reducción de la tecnología MOSFET planar ha sido la opción tecnológica dominante en las últimas décadas. Sin embargo, hemos llegado a un punto en… (more)

Subjects/Keywords: Multiple-Gate MOSFET; Noise; RF; Compact modeling; 53; 621

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APA (6th Edition):

Nae, B. M. (2011). Compact modeling of the rf and noise behavior of multiple-gate mosfets. (Thesis). Universitat Rovira i Virgili. Retrieved from http://hdl.handle.net/10803/38883

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nae, Bogdan Mihai. “Compact modeling of the rf and noise behavior of multiple-gate mosfets.” 2011. Thesis, Universitat Rovira i Virgili. Accessed April 02, 2020. http://hdl.handle.net/10803/38883.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nae, Bogdan Mihai. “Compact modeling of the rf and noise behavior of multiple-gate mosfets.” 2011. Web. 02 Apr 2020.

Vancouver:

Nae BM. Compact modeling of the rf and noise behavior of multiple-gate mosfets. [Internet] [Thesis]. Universitat Rovira i Virgili; 2011. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/10803/38883.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nae BM. Compact modeling of the rf and noise behavior of multiple-gate mosfets. [Thesis]. Universitat Rovira i Virgili; 2011. Available from: http://hdl.handle.net/10803/38883

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arkansas

20. Curbow, William Austin. Model Development and Assessment of the Gate Network in a High-Performance SiC Power Module.

Degree: MSEE, 2019, University of Arkansas

  The main objective of this effort is to determine points of weakness in the gate network of a high-performance SiC power module and to… (more)

Subjects/Keywords: gate signal modeling; die-to-die interactions; miller clamp; parameter variance; parasitic inductance; power packaging; SiC power module; Electronic Devices and Semiconductor Manufacturing; OS and Networks; Power and Energy; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Curbow, W. A. (2019). Model Development and Assessment of the Gate Network in a High-Performance SiC Power Module. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/3189

Chicago Manual of Style (16th Edition):

Curbow, William Austin. “Model Development and Assessment of the Gate Network in a High-Performance SiC Power Module.” 2019. Masters Thesis, University of Arkansas. Accessed April 02, 2020. https://scholarworks.uark.edu/etd/3189.

MLA Handbook (7th Edition):

Curbow, William Austin. “Model Development and Assessment of the Gate Network in a High-Performance SiC Power Module.” 2019. Web. 02 Apr 2020.

Vancouver:

Curbow WA. Model Development and Assessment of the Gate Network in a High-Performance SiC Power Module. [Internet] [Masters thesis]. University of Arkansas; 2019. [cited 2020 Apr 02]. Available from: https://scholarworks.uark.edu/etd/3189.

Council of Science Editors:

Curbow WA. Model Development and Assessment of the Gate Network in a High-Performance SiC Power Module. [Masters Thesis]. University of Arkansas; 2019. Available from: https://scholarworks.uark.edu/etd/3189


University of Florida

21. Wu, Jer-Wei James, 1965-. Evaluation and enhancement of opposed left-turn flow analysis methodology.

Degree: PhD, Civil Engineering, 1995, University of Florida

Subjects/Keywords: Flow velocity; Left turns; Modeling; Propagation delay; Signals; Simulations; Sneakers; Traffic delay; Traffic estimation; Transportation; Electronic traffic controls  – Mathematical models; Traffic signs and signals  – Mathematical models

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APA (6th Edition):

Wu, Jer-Wei James, 1. (1995). Evaluation and enhancement of opposed left-turn flow analysis methodology. (Doctoral Dissertation). University of Florida. Retrieved from http://ufdc.ufl.edu/AA00040494

Chicago Manual of Style (16th Edition):

Wu, Jer-Wei James, 1965-. “Evaluation and enhancement of opposed left-turn flow analysis methodology.” 1995. Doctoral Dissertation, University of Florida. Accessed April 02, 2020. http://ufdc.ufl.edu/AA00040494.

MLA Handbook (7th Edition):

Wu, Jer-Wei James, 1965-. “Evaluation and enhancement of opposed left-turn flow analysis methodology.” 1995. Web. 02 Apr 2020.

Vancouver:

Wu, Jer-Wei James 1. Evaluation and enhancement of opposed left-turn flow analysis methodology. [Internet] [Doctoral dissertation]. University of Florida; 1995. [cited 2020 Apr 02]. Available from: http://ufdc.ufl.edu/AA00040494.

Council of Science Editors:

Wu, Jer-Wei James 1. Evaluation and enhancement of opposed left-turn flow analysis methodology. [Doctoral Dissertation]. University of Florida; 1995. Available from: http://ufdc.ufl.edu/AA00040494


University of Toronto

22. Xie, Shuang. VLSI Thermal Sensing and Management using Low Power Self-calibrated Delay-line Based Temperature Sensors.

Degree: PhD, 2014, University of Toronto

 The power density of microprocessor chips continues to rise due to the growing demand on microprocessor performance and technology scaling. The resulting temperature rise and… (more)

Subjects/Keywords: delay lines; digital temperature sensor; field programmable gate arrays; power management; self-calibration; thermal management; 0544

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APA (6th Edition):

Xie, S. (2014). VLSI Thermal Sensing and Management using Low Power Self-calibrated Delay-line Based Temperature Sensors. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/68366

Chicago Manual of Style (16th Edition):

Xie, Shuang. “VLSI Thermal Sensing and Management using Low Power Self-calibrated Delay-line Based Temperature Sensors.” 2014. Doctoral Dissertation, University of Toronto. Accessed April 02, 2020. http://hdl.handle.net/1807/68366.

MLA Handbook (7th Edition):

Xie, Shuang. “VLSI Thermal Sensing and Management using Low Power Self-calibrated Delay-line Based Temperature Sensors.” 2014. Web. 02 Apr 2020.

Vancouver:

Xie S. VLSI Thermal Sensing and Management using Low Power Self-calibrated Delay-line Based Temperature Sensors. [Internet] [Doctoral dissertation]. University of Toronto; 2014. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/1807/68366.

Council of Science Editors:

Xie S. VLSI Thermal Sensing and Management using Low Power Self-calibrated Delay-line Based Temperature Sensors. [Doctoral Dissertation]. University of Toronto; 2014. Available from: http://hdl.handle.net/1807/68366


University of Florida

23. Orozco, Reinaldo. Demonstration Tool for Intermediate Fabrics on FPGA with Audio Effects.

Degree: 2011, University of Florida

 Intermediate fabric is a very useful and fast approach to VHDL hardware design that provides the capabilities of fast placement and routing. It provides a… (more)

Subjects/Keywords: Audio signals; Communications protocols; Delay circuits; Design analysis; Feedback circuits; FIR filters; Propagation delay; Signals; Software; Tremolo; Electric circuits; Field programmable gate arrays; VHDL (Computer hardware description language)

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APA (6th Edition):

Orozco, R. (2011). Demonstration Tool for Intermediate Fabrics on FPGA with Audio Effects. (Thesis). University of Florida. Retrieved from http://ufdc.ufl.edu/AA00057232

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Orozco, Reinaldo. “Demonstration Tool for Intermediate Fabrics on FPGA with Audio Effects.” 2011. Thesis, University of Florida. Accessed April 02, 2020. http://ufdc.ufl.edu/AA00057232.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Orozco, Reinaldo. “Demonstration Tool for Intermediate Fabrics on FPGA with Audio Effects.” 2011. Web. 02 Apr 2020.

Vancouver:

Orozco R. Demonstration Tool for Intermediate Fabrics on FPGA with Audio Effects. [Internet] [Thesis]. University of Florida; 2011. [cited 2020 Apr 02]. Available from: http://ufdc.ufl.edu/AA00057232.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Orozco R. Demonstration Tool for Intermediate Fabrics on FPGA with Audio Effects. [Thesis]. University of Florida; 2011. Available from: http://ufdc.ufl.edu/AA00057232

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. Knezevic, Bojana. Modeling the Multidimensional Nature of Impulsivity and its Relation to Functional Outcomes.

Degree: PhD, Psychology, 2013, National Library of Canada

  The present studies examined the role that impulsivity plays in personality development and emotion dysregulation both concurrently and longitudinally. The three studies utilized two… (more)

Subjects/Keywords: Psychology; Delay discounting; Emotion dysregulation; Impulsivity; Personality; Rewardseeking; Structural equation modeling

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APA (6th Edition):

Knezevic, B. (2013). Modeling the Multidimensional Nature of Impulsivity and its Relation to Functional Outcomes. (Doctoral Dissertation). National Library of Canada. Retrieved from http://scholar.uwindsor.ca/etd/4948

Chicago Manual of Style (16th Edition):

Knezevic, Bojana. “Modeling the Multidimensional Nature of Impulsivity and its Relation to Functional Outcomes.” 2013. Doctoral Dissertation, National Library of Canada. Accessed April 02, 2020. http://scholar.uwindsor.ca/etd/4948.

MLA Handbook (7th Edition):

Knezevic, Bojana. “Modeling the Multidimensional Nature of Impulsivity and its Relation to Functional Outcomes.” 2013. Web. 02 Apr 2020.

Vancouver:

Knezevic B. Modeling the Multidimensional Nature of Impulsivity and its Relation to Functional Outcomes. [Internet] [Doctoral dissertation]. National Library of Canada; 2013. [cited 2020 Apr 02]. Available from: http://scholar.uwindsor.ca/etd/4948.

Council of Science Editors:

Knezevic B. Modeling the Multidimensional Nature of Impulsivity and its Relation to Functional Outcomes. [Doctoral Dissertation]. National Library of Canada; 2013. Available from: http://scholar.uwindsor.ca/etd/4948


Virginia Tech

25. Rajasekhar, Lakshmi. Microscopic Control Delay Modeling at Signalized Arterials Using Bluetooth Technology.

Degree: MS, Civil Engineering, 2011, Virginia Tech

 Real-time control delay estimation is an important performance measure for any intersection to improve the signal timing plans dynamically in real-time and hence improve the… (more)

Subjects/Keywords: Bluetooth based traffic data collection; Control delay modeling; Bluetooth MAC ID

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APA (6th Edition):

Rajasekhar, L. (2011). Microscopic Control Delay Modeling at Signalized Arterials Using Bluetooth Technology. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/36214

Chicago Manual of Style (16th Edition):

Rajasekhar, Lakshmi. “Microscopic Control Delay Modeling at Signalized Arterials Using Bluetooth Technology.” 2011. Masters Thesis, Virginia Tech. Accessed April 02, 2020. http://hdl.handle.net/10919/36214.

MLA Handbook (7th Edition):

Rajasekhar, Lakshmi. “Microscopic Control Delay Modeling at Signalized Arterials Using Bluetooth Technology.” 2011. Web. 02 Apr 2020.

Vancouver:

Rajasekhar L. Microscopic Control Delay Modeling at Signalized Arterials Using Bluetooth Technology. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/10919/36214.

Council of Science Editors:

Rajasekhar L. Microscopic Control Delay Modeling at Signalized Arterials Using Bluetooth Technology. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/36214


Virginia Tech

26. Peviani, Kristin M. Longitudinal Associations among Adolescent Socioeconomic Status, Delay Discounting, and Substance Use.

Degree: MS, Psychology, 2018, Virginia Tech

 Adolescence is a period of heightened risk for substance use and heightened vulnerability to the effects of substances. Yet, little is known about how socioeconomic… (more)

Subjects/Keywords: socioeconomic status; substance use; delay discounting; adolescence; growth curve modeling

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APA (6th Edition):

Peviani, K. M. (2018). Longitudinal Associations among Adolescent Socioeconomic Status, Delay Discounting, and Substance Use. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/82446

Chicago Manual of Style (16th Edition):

Peviani, Kristin M. “Longitudinal Associations among Adolescent Socioeconomic Status, Delay Discounting, and Substance Use.” 2018. Masters Thesis, Virginia Tech. Accessed April 02, 2020. http://hdl.handle.net/10919/82446.

MLA Handbook (7th Edition):

Peviani, Kristin M. “Longitudinal Associations among Adolescent Socioeconomic Status, Delay Discounting, and Substance Use.” 2018. Web. 02 Apr 2020.

Vancouver:

Peviani KM. Longitudinal Associations among Adolescent Socioeconomic Status, Delay Discounting, and Substance Use. [Internet] [Masters thesis]. Virginia Tech; 2018. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/10919/82446.

Council of Science Editors:

Peviani KM. Longitudinal Associations among Adolescent Socioeconomic Status, Delay Discounting, and Substance Use. [Masters Thesis]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/82446


Utah State University

27. DeHart, W. Brady. Identifying the Underlying Components of Delay Discounting Using Latent Factor Modeling.

Degree: PhD, Psychology, 2017, Utah State University

  Many problematic behaviors can be conceptualized as choosing a smaller, immediate outcome over a larger, delayed outcome. For example, drug abuse involves choosing between… (more)

Subjects/Keywords: Delay Discounting; Behavioral Economics; Structural Equation Modeling; Impulsivity; Psychology

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APA (6th Edition):

DeHart, W. B. (2017). Identifying the Underlying Components of Delay Discounting Using Latent Factor Modeling. (Doctoral Dissertation). Utah State University. Retrieved from https://digitalcommons.usu.edu/etd/6339

Chicago Manual of Style (16th Edition):

DeHart, W Brady. “Identifying the Underlying Components of Delay Discounting Using Latent Factor Modeling.” 2017. Doctoral Dissertation, Utah State University. Accessed April 02, 2020. https://digitalcommons.usu.edu/etd/6339.

MLA Handbook (7th Edition):

DeHart, W Brady. “Identifying the Underlying Components of Delay Discounting Using Latent Factor Modeling.” 2017. Web. 02 Apr 2020.

Vancouver:

DeHart WB. Identifying the Underlying Components of Delay Discounting Using Latent Factor Modeling. [Internet] [Doctoral dissertation]. Utah State University; 2017. [cited 2020 Apr 02]. Available from: https://digitalcommons.usu.edu/etd/6339.

Council of Science Editors:

DeHart WB. Identifying the Underlying Components of Delay Discounting Using Latent Factor Modeling. [Doctoral Dissertation]. Utah State University; 2017. Available from: https://digitalcommons.usu.edu/etd/6339


New Jersey Institute of Technology

28. Zhang, Yang. A modeling study of the history-dependence of conduction delay in unmyelinated axons.

Degree: PhD, Mathematical Sciences, 2013, New Jersey Institute of Technology

  Conduction delay in an axon is the time required for an action potential to propagate between two positions. It is a function of the… (more)

Subjects/Keywords: Unmyelinated axon; Conduction delay; Computational modeling; History-dependence; Mathematics

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APA (6th Edition):

Zhang, Y. (2013). A modeling study of the history-dependence of conduction delay in unmyelinated axons. (Doctoral Dissertation). New Jersey Institute of Technology. Retrieved from https://digitalcommons.njit.edu/dissertations/155

Chicago Manual of Style (16th Edition):

Zhang, Yang. “A modeling study of the history-dependence of conduction delay in unmyelinated axons.” 2013. Doctoral Dissertation, New Jersey Institute of Technology. Accessed April 02, 2020. https://digitalcommons.njit.edu/dissertations/155.

MLA Handbook (7th Edition):

Zhang, Yang. “A modeling study of the history-dependence of conduction delay in unmyelinated axons.” 2013. Web. 02 Apr 2020.

Vancouver:

Zhang Y. A modeling study of the history-dependence of conduction delay in unmyelinated axons. [Internet] [Doctoral dissertation]. New Jersey Institute of Technology; 2013. [cited 2020 Apr 02]. Available from: https://digitalcommons.njit.edu/dissertations/155.

Council of Science Editors:

Zhang Y. A modeling study of the history-dependence of conduction delay in unmyelinated axons. [Doctoral Dissertation]. New Jersey Institute of Technology; 2013. Available from: https://digitalcommons.njit.edu/dissertations/155


Georgia State University

29. Hrabic, Melissa. Social Models Influence Children's Delay of Gratification Strategy Use and Delay Performance.

Degree: MA, Psychology, 2015, Georgia State University

Delay of gratification is the ability to forego an immediate indulgence in lieu of a later, greater reward. Past research has shown that using… (more)

Subjects/Keywords: Delay of gratification; imitation; strategy; modeling; social influence; accumulation task

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hrabic, M. (2015). Social Models Influence Children's Delay of Gratification Strategy Use and Delay Performance. (Thesis). Georgia State University. Retrieved from https://scholarworks.gsu.edu/psych_theses/131

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hrabic, Melissa. “Social Models Influence Children's Delay of Gratification Strategy Use and Delay Performance.” 2015. Thesis, Georgia State University. Accessed April 02, 2020. https://scholarworks.gsu.edu/psych_theses/131.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hrabic, Melissa. “Social Models Influence Children's Delay of Gratification Strategy Use and Delay Performance.” 2015. Web. 02 Apr 2020.

Vancouver:

Hrabic M. Social Models Influence Children's Delay of Gratification Strategy Use and Delay Performance. [Internet] [Thesis]. Georgia State University; 2015. [cited 2020 Apr 02]. Available from: https://scholarworks.gsu.edu/psych_theses/131.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hrabic M. Social Models Influence Children's Delay of Gratification Strategy Use and Delay Performance. [Thesis]. Georgia State University; 2015. Available from: https://scholarworks.gsu.edu/psych_theses/131

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

30. Marck, Julien. A Nonlinear Dynamical Model of Borehole Spiraling.

Degree: PhD, Civil Engineering, 2015, University of Minnesota

 With the emergence of new measurement devices, the non-smooth nature of the borehole geometry has been comprehended more accurately. In many happenstances, the borehole has… (more)

Subjects/Keywords: Borehole propagation; Borehole spiraling; Delay differential equations; Directional drilling; Modeling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Marck, J. (2015). A Nonlinear Dynamical Model of Borehole Spiraling. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/177131

Chicago Manual of Style (16th Edition):

Marck, Julien. “A Nonlinear Dynamical Model of Borehole Spiraling.” 2015. Doctoral Dissertation, University of Minnesota. Accessed April 02, 2020. http://hdl.handle.net/11299/177131.

MLA Handbook (7th Edition):

Marck, Julien. “A Nonlinear Dynamical Model of Borehole Spiraling.” 2015. Web. 02 Apr 2020.

Vancouver:

Marck J. A Nonlinear Dynamical Model of Borehole Spiraling. [Internet] [Doctoral dissertation]. University of Minnesota; 2015. [cited 2020 Apr 02]. Available from: http://hdl.handle.net/11299/177131.

Council of Science Editors:

Marck J. A Nonlinear Dynamical Model of Borehole Spiraling. [Doctoral Dissertation]. University of Minnesota; 2015. Available from: http://hdl.handle.net/11299/177131

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