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You searched for subject:(Electronic Gate Delay Measurement). Showing records 1 – 30 of 38391 total matches.

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Indian Institute of Science

1. Das, Bishnu Prasad. Random Local Delay Variability : On-chip Measurement And Modeling.

Degree: 2009, Indian Institute of Science

 This thesis focuses on random local delay variability measurement and its modeling. It explains a circuit technique to measure the individual logic gate delay in… (more)

Subjects/Keywords: Electronic Gates - Design; On-chip Management And Construction; Electronic Gate Delay - Modeling; Random Local Delay Variation; On-chip Gate Delay Measurement; Process Voltage And Temperature Gate Delay Model; Electronic Gate Delay - Measurement; Statistical Static Timing Analysis (SSTA); Gate Delay Variability Measurement; Delay Variability; On-chip Measurement; Gate Delay Models; Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Das, B. P. (2009). Random Local Delay Variability : On-chip Measurement And Modeling. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1008

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Das, Bishnu Prasad. “Random Local Delay Variability : On-chip Measurement And Modeling.” 2009. Thesis, Indian Institute of Science. Accessed April 06, 2020. http://hdl.handle.net/2005/1008.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Das, Bishnu Prasad. “Random Local Delay Variability : On-chip Measurement And Modeling.” 2009. Web. 06 Apr 2020.

Vancouver:

Das BP. Random Local Delay Variability : On-chip Measurement And Modeling. [Internet] [Thesis]. Indian Institute of Science; 2009. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/2005/1008.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Das BP. Random Local Delay Variability : On-chip Measurement And Modeling. [Thesis]. Indian Institute of Science; 2009. Available from: http://hdl.handle.net/2005/1008

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

2. Harish, B P. Process Variability-Aware Performance Modeling In 65 nm CMOS.

Degree: 2006, Indian Institute of Science

 With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all… (more)

Subjects/Keywords: Complementary Metal Oxide Semiconductors; Semiconductors; NAND Gate; Gate Delay Models; CMOS Digital Circuits; Circuit Design; Circuit Delay Performance; Circuit Delay Distribution; CMOS Designs; 65nm CMOS; Electronic Engineering

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APA (6th Edition):

Harish, B. P. (2006). Process Variability-Aware Performance Modeling In 65 nm CMOS. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1080

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Harish, B P. “Process Variability-Aware Performance Modeling In 65 nm CMOS.” 2006. Thesis, Indian Institute of Science. Accessed April 06, 2020. http://hdl.handle.net/2005/1080.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Harish, B P. “Process Variability-Aware Performance Modeling In 65 nm CMOS.” 2006. Web. 06 Apr 2020.

Vancouver:

Harish BP. Process Variability-Aware Performance Modeling In 65 nm CMOS. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/2005/1080.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Harish BP. Process Variability-Aware Performance Modeling In 65 nm CMOS. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/1080

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

3. Klabal, Petr. Měření kontrakcí izolovaných srdečních buněk v reálném čase .

Degree: 2012, Brno University of Technology

 Diplomová práce se zabývá základním popisem srdečních buněk, mechanismu jejich kontrakce a jevů, které s kontrakcí souvisí. Existují různé typy metod, které lze v dnešní… (more)

Subjects/Keywords: Srdeční buňka; kontrakce; akční napětí; metody měření; televizní signál; logický člen; řádkový synchronizační impuls; půlsnímkový synchronizační impuls; časové zpoždění; výběr řádku; simulace; Cardiac muscle cell; contractions; action potential; methods of measurement; television signal; logic gate; composite sync output; vertical sync output; time delay; row selection; simulation

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APA (6th Edition):

Klabal, P. (2012). Měření kontrakcí izolovaných srdečních buněk v reálném čase . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/12723

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Klabal, Petr. “Měření kontrakcí izolovaných srdečních buněk v reálném čase .” 2012. Thesis, Brno University of Technology. Accessed April 06, 2020. http://hdl.handle.net/11012/12723.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Klabal, Petr. “Měření kontrakcí izolovaných srdečních buněk v reálném čase .” 2012. Web. 06 Apr 2020.

Vancouver:

Klabal P. Měření kontrakcí izolovaných srdečních buněk v reálném čase . [Internet] [Thesis]. Brno University of Technology; 2012. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/11012/12723.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Klabal P. Měření kontrakcí izolovaných srdečních buněk v reálném čase . [Thesis]. Brno University of Technology; 2012. Available from: http://hdl.handle.net/11012/12723

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

4. Zafar, Muhammad Umair. Measuring the dynamic energy efficiency of FPGAs over processors.

Degree: 2016, Ryerson University

 This work investigates the dynamic energy efficiency of the parallel execution model of an FPGA and the sequential execution model of a processor, for latency-insensitive… (more)

Subjects/Keywords: Field programmable gate arrays  – Energy consumption  – Measurement; Field programmable gate arrays  – Energy consumption  – Mathematical models

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zafar, M. U. (2016). Measuring the dynamic energy efficiency of FPGAs over processors. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A5816

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zafar, Muhammad Umair. “Measuring the dynamic energy efficiency of FPGAs over processors.” 2016. Thesis, Ryerson University. Accessed April 06, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A5816.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zafar, Muhammad Umair. “Measuring the dynamic energy efficiency of FPGAs over processors.” 2016. Web. 06 Apr 2020.

Vancouver:

Zafar MU. Measuring the dynamic energy efficiency of FPGAs over processors. [Internet] [Thesis]. Ryerson University; 2016. [cited 2020 Apr 06]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5816.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zafar MU. Measuring the dynamic energy efficiency of FPGAs over processors. [Thesis]. Ryerson University; 2016. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5816

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Florida

5. Nezvadovitz, Brian. Reliable FPGA Overclocking through Cycle Time Borrowing.

Degree: 2013, University of Florida

 Field programmable gate arrays (FPGAs) are reconfigurable devices that are commonly used to accelerate many high performance computing applications, including those in signal processing, numerical… (more)

Subjects/Keywords: Design optimization; Electric potential; Field programmable gate arrays; Microprocessors; Phase shift; Pipelines; Propagation delay; Recycling; Signals; Timber; Field programmable gate arrays

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APA (6th Edition):

Nezvadovitz, B. (2013). Reliable FPGA Overclocking through Cycle Time Borrowing. (Thesis). University of Florida. Retrieved from http://ufdc.ufl.edu/AA00059588

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nezvadovitz, Brian. “Reliable FPGA Overclocking through Cycle Time Borrowing.” 2013. Thesis, University of Florida. Accessed April 06, 2020. http://ufdc.ufl.edu/AA00059588.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nezvadovitz, Brian. “Reliable FPGA Overclocking through Cycle Time Borrowing.” 2013. Web. 06 Apr 2020.

Vancouver:

Nezvadovitz B. Reliable FPGA Overclocking through Cycle Time Borrowing. [Internet] [Thesis]. University of Florida; 2013. [cited 2020 Apr 06]. Available from: http://ufdc.ufl.edu/AA00059588.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nezvadovitz B. Reliable FPGA Overclocking through Cycle Time Borrowing. [Thesis]. University of Florida; 2013. Available from: http://ufdc.ufl.edu/AA00059588

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

6. Posser, Gracieli. Dimensionamento de portas lógicas usando programação geométrica.

Degree: 2011, Universidade do Rio Grande do Sul

Neste trabalho é desenvolvida uma ferramenta de dimensionamento de portas lógicas para circuitos integrados, utilizando técnicas de otimização de problemas baseadas em Programação Geométrica (PG).… (more)

Subjects/Keywords: Gate sizing; Microeletrônica; Physical synthesis; Circuitos integrados; Sintese automatica; Geometric programming; Elmore delay model; Microelectronics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Posser, G. (2011). Dimensionamento de portas lógicas usando programação geométrica. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/29571

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Posser, Gracieli. “Dimensionamento de portas lógicas usando programação geométrica.” 2011. Thesis, Universidade do Rio Grande do Sul. Accessed April 06, 2020. http://hdl.handle.net/10183/29571.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Posser, Gracieli. “Dimensionamento de portas lógicas usando programação geométrica.” 2011. Web. 06 Apr 2020.

Vancouver:

Posser G. Dimensionamento de portas lógicas usando programação geométrica. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2011. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/10183/29571.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Posser G. Dimensionamento de portas lógicas usando programação geométrica. [Thesis]. Universidade do Rio Grande do Sul; 2011. Available from: http://hdl.handle.net/10183/29571

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

7. Johnson, Matthew Robert. Fast, accurate power measurement and optimization for microprocessor platforms.

Degree: PhD, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 Power and energy consumption have become important for all computers, but the tools used to measure and optimize power on physical hardware lag far behind… (more)

Subjects/Keywords: Power measurement; Current measurement; Energy efficiency; Software optimization; Field-Programmable Gate Array (FPGA); Power optimization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Johnson, M. R. (2015). Fast, accurate power measurement and optimization for microprocessor platforms. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78785

Chicago Manual of Style (16th Edition):

Johnson, Matthew Robert. “Fast, accurate power measurement and optimization for microprocessor platforms.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 06, 2020. http://hdl.handle.net/2142/78785.

MLA Handbook (7th Edition):

Johnson, Matthew Robert. “Fast, accurate power measurement and optimization for microprocessor platforms.” 2015. Web. 06 Apr 2020.

Vancouver:

Johnson MR. Fast, accurate power measurement and optimization for microprocessor platforms. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/2142/78785.

Council of Science Editors:

Johnson MR. Fast, accurate power measurement and optimization for microprocessor platforms. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78785


Stellenbosch University

8. Prinsloo, David Schalk Van Der Merwe. Characterisation of L-band differential low noise amplifiers.

Degree: MScEng, Electrical and Electronic Engineering, 2011, Stellenbosch University

ENGLISH ABSTRACT: This thesis addresses the complications that are encountered when characterising the performance of differential microwave LNAs. The predominant sources of noise in electronic(more)

Subjects/Keywords: Electronic engineering; Noise  – Measurement

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APA (6th Edition):

Prinsloo, D. S. V. D. M. (2011). Characterisation of L-band differential low noise amplifiers. (Masters Thesis). Stellenbosch University. Retrieved from http://hdl.handle.net/10019.1/18063

Chicago Manual of Style (16th Edition):

Prinsloo, David Schalk Van Der Merwe. “Characterisation of L-band differential low noise amplifiers.” 2011. Masters Thesis, Stellenbosch University. Accessed April 06, 2020. http://hdl.handle.net/10019.1/18063.

MLA Handbook (7th Edition):

Prinsloo, David Schalk Van Der Merwe. “Characterisation of L-band differential low noise amplifiers.” 2011. Web. 06 Apr 2020.

Vancouver:

Prinsloo DSVDM. Characterisation of L-band differential low noise amplifiers. [Internet] [Masters thesis]. Stellenbosch University; 2011. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/10019.1/18063.

Council of Science Editors:

Prinsloo DSVDM. Characterisation of L-band differential low noise amplifiers. [Masters Thesis]. Stellenbosch University; 2011. Available from: http://hdl.handle.net/10019.1/18063


Stellenbosch University

9. Ulyate, Jessica. Automated reading of high volume water meters.

Degree: Electrical and Electronic Engineering, 2011, Stellenbosch University

Thesis (MScEng (Electrical and Electronic Engineering)) – University of Stellenbosch, 2011.

ENGLISH ABSTRACT: Accurate water usage information is very important for municipalities in order to provide… (more)

Subjects/Keywords: Electronic engineering; Water usage  – Measurement

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APA (6th Edition):

Ulyate, J. (2011). Automated reading of high volume water meters. (Thesis). Stellenbosch University. Retrieved from http://hdl.handle.net/10019.1/6673

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ulyate, Jessica. “Automated reading of high volume water meters.” 2011. Thesis, Stellenbosch University. Accessed April 06, 2020. http://hdl.handle.net/10019.1/6673.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ulyate, Jessica. “Automated reading of high volume water meters.” 2011. Web. 06 Apr 2020.

Vancouver:

Ulyate J. Automated reading of high volume water meters. [Internet] [Thesis]. Stellenbosch University; 2011. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/10019.1/6673.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ulyate J. Automated reading of high volume water meters. [Thesis]. Stellenbosch University; 2011. Available from: http://hdl.handle.net/10019.1/6673

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Montana State University

10. Pandit, Pushkar Pradeep. Compressive laser ranging with embedded systems.

Degree: MS, College of Engineering, 2015, Montana State University

 Compressive sensing is a signal processing technique that has recently come to the forefront due to its ability to work around the well-known Shannon-Nyquist-Whittaker sampling… (more)

Subjects/Keywords: Compressed sensing (Telecommunication).; Distances.; Measurement.; Field programmable gate arrays.

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APA (6th Edition):

Pandit, P. P. (2015). Compressive laser ranging with embedded systems. (Masters Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/9151

Chicago Manual of Style (16th Edition):

Pandit, Pushkar Pradeep. “Compressive laser ranging with embedded systems.” 2015. Masters Thesis, Montana State University. Accessed April 06, 2020. https://scholarworks.montana.edu/xmlui/handle/1/9151.

MLA Handbook (7th Edition):

Pandit, Pushkar Pradeep. “Compressive laser ranging with embedded systems.” 2015. Web. 06 Apr 2020.

Vancouver:

Pandit PP. Compressive laser ranging with embedded systems. [Internet] [Masters thesis]. Montana State University; 2015. [cited 2020 Apr 06]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/9151.

Council of Science Editors:

Pandit PP. Compressive laser ranging with embedded systems. [Masters Thesis]. Montana State University; 2015. Available from: https://scholarworks.montana.edu/xmlui/handle/1/9151


Indian Institute of Science

11. Srivatsava, J. Compact Modeling Of Asymmetric/Independent Double Gate MOSFET.

Degree: 2012, Indian Institute of Science

 For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. In order to continue the technology… (more)

Subjects/Keywords: Asymmetric Double Gate MOSFET; Asymmetric Double Gate Transistor - Compact Modeling; Transistor Performance; Common-Gate Asymmetric Double Gate MOSFET; Independent-gate Asymmetric Double Gate MOSFET; DG MOSFET; Double Gate MOSFET; Metal Oxide Semiconductor Field Effect Transistor; Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Srivatsava, J. (2012). Compact Modeling Of Asymmetric/Independent Double Gate MOSFET. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2346

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Srivatsava, J. “Compact Modeling Of Asymmetric/Independent Double Gate MOSFET.” 2012. Thesis, Indian Institute of Science. Accessed April 06, 2020. http://hdl.handle.net/2005/2346.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Srivatsava, J. “Compact Modeling Of Asymmetric/Independent Double Gate MOSFET.” 2012. Web. 06 Apr 2020.

Vancouver:

Srivatsava J. Compact Modeling Of Asymmetric/Independent Double Gate MOSFET. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/2005/2346.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Srivatsava J. Compact Modeling Of Asymmetric/Independent Double Gate MOSFET. [Thesis]. Indian Institute of Science; 2012. Available from: http://hdl.handle.net/2005/2346

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

12. Srivatsava, J. Compact Modeling Of Asymmetric/Independent Double Gate MOSFET.

Degree: 2012, Indian Institute of Science

 For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. In order to continue the technology… (more)

Subjects/Keywords: Asymmetric Double Gate MOSFET; Asymmetric Double Gate Transistor - Compact Modeling; Transistor Performance; Common-Gate Asymmetric Double Gate MOSFET; Independent-gate Asymmetric Double Gate MOSFET; DG MOSFET; Double Gate MOSFET; Metal Oxide Semiconductor Field Effect Transistor; Electronic Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Srivatsava, J. (2012). Compact Modeling Of Asymmetric/Independent Double Gate MOSFET. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2346 ; http://etd.ncsi.iisc.ernet.in/abstracts/3017/G25480-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Srivatsava, J. “Compact Modeling Of Asymmetric/Independent Double Gate MOSFET.” 2012. Thesis, Indian Institute of Science. Accessed April 06, 2020. http://etd.iisc.ernet.in/handle/2005/2346 ; http://etd.ncsi.iisc.ernet.in/abstracts/3017/G25480-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Srivatsava, J. “Compact Modeling Of Asymmetric/Independent Double Gate MOSFET.” 2012. Web. 06 Apr 2020.

Vancouver:

Srivatsava J. Compact Modeling Of Asymmetric/Independent Double Gate MOSFET. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2020 Apr 06]. Available from: http://etd.iisc.ernet.in/handle/2005/2346 ; http://etd.ncsi.iisc.ernet.in/abstracts/3017/G25480-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Srivatsava J. Compact Modeling Of Asymmetric/Independent Double Gate MOSFET. [Thesis]. Indian Institute of Science; 2012. Available from: http://etd.iisc.ernet.in/handle/2005/2346 ; http://etd.ncsi.iisc.ernet.in/abstracts/3017/G25480-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

13. Pšenčík, Petr. Využití programovatelného hradlového pole Compact RIO pro měření vibrací .

Degree: 2012, Brno University of Technology

 Bakalářská práce se zabývá měřením vibrací na programovatelném hradlovém poli Compact RIO, pomocí měřící aplikace vytvořené v grafickém vývojovém prostředí LabVIEW. V práci jsou popsány… (more)

Subjects/Keywords: Měření vibrací; Compact RIO; FPGA; programovatelné hradlové pole; LabVIEW; Vibrations measurement; Compact RIO; FPGA; gate of programmable gate arrays; LabVIEW

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pšenčík, P. (2012). Využití programovatelného hradlového pole Compact RIO pro měření vibrací . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/17455

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pšenčík, Petr. “Využití programovatelného hradlového pole Compact RIO pro měření vibrací .” 2012. Thesis, Brno University of Technology. Accessed April 06, 2020. http://hdl.handle.net/11012/17455.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pšenčík, Petr. “Využití programovatelného hradlového pole Compact RIO pro měření vibrací .” 2012. Web. 06 Apr 2020.

Vancouver:

Pšenčík P. Využití programovatelného hradlového pole Compact RIO pro měření vibrací . [Internet] [Thesis]. Brno University of Technology; 2012. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/11012/17455.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pšenčík P. Využití programovatelného hradlového pole Compact RIO pro měření vibrací . [Thesis]. Brno University of Technology; 2012. Available from: http://hdl.handle.net/11012/17455

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Montana State University

14. Dack, Connor Aquila. Development of a smart camera system using a system on module FPGA.

Degree: College of Engineering, 2017, Montana State University

 Imaging systems can now produce more data than conventional PCs with frame grabbers can process in real-time. Moving real-time custom computation as close as possible… (more)

Subjects/Keywords: Field programmable gate arrays.; Cameras.; Optical spectroscopy.; Electronic data processing.; Algorithms.

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APA (6th Edition):

Dack, C. A. (2017). Development of a smart camera system using a system on module FPGA. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/14902

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dack, Connor Aquila. “Development of a smart camera system using a system on module FPGA.” 2017. Thesis, Montana State University. Accessed April 06, 2020. https://scholarworks.montana.edu/xmlui/handle/1/14902.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dack, Connor Aquila. “Development of a smart camera system using a system on module FPGA.” 2017. Web. 06 Apr 2020.

Vancouver:

Dack CA. Development of a smart camera system using a system on module FPGA. [Internet] [Thesis]. Montana State University; 2017. [cited 2020 Apr 06]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/14902.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dack CA. Development of a smart camera system using a system on module FPGA. [Thesis]. Montana State University; 2017. Available from: https://scholarworks.montana.edu/xmlui/handle/1/14902

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

15. Riccardi, Elisa. Spectroscopie raman des excitations électroniques du graphène : Raman spectroscopy of electronic excitations in graphene.

Degree: Docteur es, Physique, 2017, Sorbonne Paris Cité

Depuis sa découverte, les propriétés électroniques exceptionnelles du graphène ont fait l'objet d'un nombre impressionnant d'études, faisant émerger un nouveau domaine de recherche autour des… (more)

Subjects/Keywords: Dispositifs; Effet de grille; Excitations electroniques; Devices; Gate Effect; Electronic excitations

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APA (6th Edition):

Riccardi, E. (2017). Spectroscopie raman des excitations électroniques du graphène : Raman spectroscopy of electronic excitations in graphene. (Doctoral Dissertation). Sorbonne Paris Cité. Retrieved from http://www.theses.fr/2017USPCC166

Chicago Manual of Style (16th Edition):

Riccardi, Elisa. “Spectroscopie raman des excitations électroniques du graphène : Raman spectroscopy of electronic excitations in graphene.” 2017. Doctoral Dissertation, Sorbonne Paris Cité. Accessed April 06, 2020. http://www.theses.fr/2017USPCC166.

MLA Handbook (7th Edition):

Riccardi, Elisa. “Spectroscopie raman des excitations électroniques du graphène : Raman spectroscopy of electronic excitations in graphene.” 2017. Web. 06 Apr 2020.

Vancouver:

Riccardi E. Spectroscopie raman des excitations électroniques du graphène : Raman spectroscopy of electronic excitations in graphene. [Internet] [Doctoral dissertation]. Sorbonne Paris Cité; 2017. [cited 2020 Apr 06]. Available from: http://www.theses.fr/2017USPCC166.

Council of Science Editors:

Riccardi E. Spectroscopie raman des excitations électroniques du graphène : Raman spectroscopy of electronic excitations in graphene. [Doctoral Dissertation]. Sorbonne Paris Cité; 2017. Available from: http://www.theses.fr/2017USPCC166


University of Manchester

16. Yang, Xue Jiao. Supervisory wide-area control for multi-machine power system.

Degree: PhD, 2012, University of Manchester

 With the increasing demand for electrical power and the growing need for the restructuring of the power industry, electric power systems have become highly complex… (more)

Subjects/Keywords: 621.319; LQG/LTR; supervisory control; wide-area measurement system; time-delay

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APA (6th Edition):

Yang, X. J. (2012). Supervisory wide-area control for multi-machine power system. (Doctoral Dissertation). University of Manchester. Retrieved from https://www.research.manchester.ac.uk/portal/en/theses/supervisory-widearea-control-for-multimachine-power-system(6c0575f9-7b20-4751-9d67-276aaaa4c7b2).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.553433

Chicago Manual of Style (16th Edition):

Yang, Xue Jiao. “Supervisory wide-area control for multi-machine power system.” 2012. Doctoral Dissertation, University of Manchester. Accessed April 06, 2020. https://www.research.manchester.ac.uk/portal/en/theses/supervisory-widearea-control-for-multimachine-power-system(6c0575f9-7b20-4751-9d67-276aaaa4c7b2).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.553433.

MLA Handbook (7th Edition):

Yang, Xue Jiao. “Supervisory wide-area control for multi-machine power system.” 2012. Web. 06 Apr 2020.

Vancouver:

Yang XJ. Supervisory wide-area control for multi-machine power system. [Internet] [Doctoral dissertation]. University of Manchester; 2012. [cited 2020 Apr 06]. Available from: https://www.research.manchester.ac.uk/portal/en/theses/supervisory-widearea-control-for-multimachine-power-system(6c0575f9-7b20-4751-9d67-276aaaa4c7b2).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.553433.

Council of Science Editors:

Yang XJ. Supervisory wide-area control for multi-machine power system. [Doctoral Dissertation]. University of Manchester; 2012. Available from: https://www.research.manchester.ac.uk/portal/en/theses/supervisory-widearea-control-for-multimachine-power-system(6c0575f9-7b20-4751-9d67-276aaaa4c7b2).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.553433


University of Southern California

17. Cha, Byeongju. Trustworthiness of integrated circuits: a new testing framework for hardware Trojans.

Degree: PhD, Electrical Engineering, 2015, University of Southern California

 High cost differentials are causing many aspects of integrated circuit (IC) design—including IC design and fabrication, high-volume testing, and IC packaging—to increasingly move overseas. Consequently,… (more)

Subjects/Keywords: security; testing; integrated circuits; hardware Trojans; parametric test; delay measurement

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APA (6th Edition):

Cha, B. (2015). Trustworthiness of integrated circuits: a new testing framework for hardware Trojans. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/534923/rec/7621

Chicago Manual of Style (16th Edition):

Cha, Byeongju. “Trustworthiness of integrated circuits: a new testing framework for hardware Trojans.” 2015. Doctoral Dissertation, University of Southern California. Accessed April 06, 2020. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/534923/rec/7621.

MLA Handbook (7th Edition):

Cha, Byeongju. “Trustworthiness of integrated circuits: a new testing framework for hardware Trojans.” 2015. Web. 06 Apr 2020.

Vancouver:

Cha B. Trustworthiness of integrated circuits: a new testing framework for hardware Trojans. [Internet] [Doctoral dissertation]. University of Southern California; 2015. [cited 2020 Apr 06]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/534923/rec/7621.

Council of Science Editors:

Cha B. Trustworthiness of integrated circuits: a new testing framework for hardware Trojans. [Doctoral Dissertation]. University of Southern California; 2015. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/534923/rec/7621

18. Lai, Jingou. Use SNA instead of VNA to characterize indoor channel : implementing and rms theory.

Degree: Mathematics and Natural Sciences, 2010, University of Gävle

  In this report we focus on the use of an economical way on how Scalar Network Analyzer (SNA) works instead of Vector Network Analyzer… (more)

Subjects/Keywords: network analyzer; rms delay; hilbert transform; Electronic measurement and instrumentation; Elektronisk mät- och apparatteknik

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APA (6th Edition):

Lai, J. (2010). Use SNA instead of VNA to characterize indoor channel : implementing and rms theory. (Thesis). University of Gävle. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-7780

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lai, Jingou. “Use SNA instead of VNA to characterize indoor channel : implementing and rms theory.” 2010. Thesis, University of Gävle. Accessed April 06, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-7780.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lai, Jingou. “Use SNA instead of VNA to characterize indoor channel : implementing and rms theory.” 2010. Web. 06 Apr 2020.

Vancouver:

Lai J. Use SNA instead of VNA to characterize indoor channel : implementing and rms theory. [Internet] [Thesis]. University of Gävle; 2010. [cited 2020 Apr 06]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-7780.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lai J. Use SNA instead of VNA to characterize indoor channel : implementing and rms theory. [Thesis]. University of Gävle; 2010. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-7780

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

19. Xie, Shuang. VLSI Thermal Sensing and Management using Low Power Self-calibrated Delay-line Based Temperature Sensors.

Degree: PhD, 2014, University of Toronto

 The power density of microprocessor chips continues to rise due to the growing demand on microprocessor performance and technology scaling. The resulting temperature rise and… (more)

Subjects/Keywords: delay lines; digital temperature sensor; field programmable gate arrays; power management; self-calibration; thermal management; 0544

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APA (6th Edition):

Xie, S. (2014). VLSI Thermal Sensing and Management using Low Power Self-calibrated Delay-line Based Temperature Sensors. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/68366

Chicago Manual of Style (16th Edition):

Xie, Shuang. “VLSI Thermal Sensing and Management using Low Power Self-calibrated Delay-line Based Temperature Sensors.” 2014. Doctoral Dissertation, University of Toronto. Accessed April 06, 2020. http://hdl.handle.net/1807/68366.

MLA Handbook (7th Edition):

Xie, Shuang. “VLSI Thermal Sensing and Management using Low Power Self-calibrated Delay-line Based Temperature Sensors.” 2014. Web. 06 Apr 2020.

Vancouver:

Xie S. VLSI Thermal Sensing and Management using Low Power Self-calibrated Delay-line Based Temperature Sensors. [Internet] [Doctoral dissertation]. University of Toronto; 2014. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1807/68366.

Council of Science Editors:

Xie S. VLSI Thermal Sensing and Management using Low Power Self-calibrated Delay-line Based Temperature Sensors. [Doctoral Dissertation]. University of Toronto; 2014. Available from: http://hdl.handle.net/1807/68366


University of Florida

20. Orozco, Reinaldo. Demonstration Tool for Intermediate Fabrics on FPGA with Audio Effects.

Degree: 2011, University of Florida

 Intermediate fabric is a very useful and fast approach to VHDL hardware design that provides the capabilities of fast placement and routing. It provides a… (more)

Subjects/Keywords: Audio signals; Communications protocols; Delay circuits; Design analysis; Feedback circuits; FIR filters; Propagation delay; Signals; Software; Tremolo; Electric circuits; Field programmable gate arrays; VHDL (Computer hardware description language)

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APA (6th Edition):

Orozco, R. (2011). Demonstration Tool for Intermediate Fabrics on FPGA with Audio Effects. (Thesis). University of Florida. Retrieved from http://ufdc.ufl.edu/AA00057232

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Orozco, Reinaldo. “Demonstration Tool for Intermediate Fabrics on FPGA with Audio Effects.” 2011. Thesis, University of Florida. Accessed April 06, 2020. http://ufdc.ufl.edu/AA00057232.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Orozco, Reinaldo. “Demonstration Tool for Intermediate Fabrics on FPGA with Audio Effects.” 2011. Web. 06 Apr 2020.

Vancouver:

Orozco R. Demonstration Tool for Intermediate Fabrics on FPGA with Audio Effects. [Internet] [Thesis]. University of Florida; 2011. [cited 2020 Apr 06]. Available from: http://ufdc.ufl.edu/AA00057232.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Orozco R. Demonstration Tool for Intermediate Fabrics on FPGA with Audio Effects. [Thesis]. University of Florida; 2011. Available from: http://ufdc.ufl.edu/AA00057232

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Rochester

21. Wang, Chen. Real-time signal processing techniques and hardware implementation for optical metrology.

Degree: PhD, 2018, University of Rochester

 Optical metrology uses characteristics of light to perform measurements. This could be in the form of calibrating the physical size of an object, measuring the… (more)

Subjects/Keywords: Data age error; Displacement measurement; Field-programmable gate array; Interferometer; Periodic error; Straightness error

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, C. (2018). Real-time signal processing techniques and hardware implementation for optical metrology. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/33503

Chicago Manual of Style (16th Edition):

Wang, Chen. “Real-time signal processing techniques and hardware implementation for optical metrology.” 2018. Doctoral Dissertation, University of Rochester. Accessed April 06, 2020. http://hdl.handle.net/1802/33503.

MLA Handbook (7th Edition):

Wang, Chen. “Real-time signal processing techniques and hardware implementation for optical metrology.” 2018. Web. 06 Apr 2020.

Vancouver:

Wang C. Real-time signal processing techniques and hardware implementation for optical metrology. [Internet] [Doctoral dissertation]. University of Rochester; 2018. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1802/33503.

Council of Science Editors:

Wang C. Real-time signal processing techniques and hardware implementation for optical metrology. [Doctoral Dissertation]. University of Rochester; 2018. Available from: http://hdl.handle.net/1802/33503


Georgia Tech

22. Luharuka, Rajesh. An electromagnetically actuated rotary gate microvalve with bistability.

Degree: PhD, Mechanical Engineering, 2007, Georgia Tech

 Two types of rotary gate microvalves are developed for flow modulation in a microfluidic system that operates at high flow rate and/or uses particulate flow.… (more)

Subjects/Keywords: MEMS; Microfluidics; Gate microvalve; Compliant micromechanism; Bistability; Rotary; Electromagnetic actuator; Particulate flow; High flow; Permalloy; Microfabrication; Electroplating; Torque measurement; Flow characterization; Fluidic devices; Miniature electronic equipment; Valves

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APA (6th Edition):

Luharuka, R. (2007). An electromagnetically actuated rotary gate microvalve with bistability. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/22576

Chicago Manual of Style (16th Edition):

Luharuka, Rajesh. “An electromagnetically actuated rotary gate microvalve with bistability.” 2007. Doctoral Dissertation, Georgia Tech. Accessed April 06, 2020. http://hdl.handle.net/1853/22576.

MLA Handbook (7th Edition):

Luharuka, Rajesh. “An electromagnetically actuated rotary gate microvalve with bistability.” 2007. Web. 06 Apr 2020.

Vancouver:

Luharuka R. An electromagnetically actuated rotary gate microvalve with bistability. [Internet] [Doctoral dissertation]. Georgia Tech; 2007. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1853/22576.

Council of Science Editors:

Luharuka R. An electromagnetically actuated rotary gate microvalve with bistability. [Doctoral Dissertation]. Georgia Tech; 2007. Available from: http://hdl.handle.net/1853/22576


Indian Institute of Science

23. Kumar, P Rakesh. Analytical Modeling Of Quantum Thershold Voltage For Short Channel Multi Gate Silicon Nanowire Transistors.

Degree: 2009, Indian Institute of Science

 Silicon nanowire based multiple gate metal oxide field effect transistors(MG-MOSFET) appear as replacements for conventional bulk transistors in post 45nm technology nodes. In such transistors… (more)

Subjects/Keywords: Transistors; Silicon Nanowire Transistors; Quantum Threshold Voltage; Threshold Voltage Models; Transistors - Modeling; Double Gate Transistor; Cylindrical Gate Transistor; Quad Gate Transistor; Tri Gate Transistor; Cylindrical Gate All-around Transistor; Silicon Nanowire Transistor; MOSFET; Electronic Engineering

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APA (6th Edition):

Kumar, P. R. (2009). Analytical Modeling Of Quantum Thershold Voltage For Short Channel Multi Gate Silicon Nanowire Transistors. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kumar, P Rakesh. “Analytical Modeling Of Quantum Thershold Voltage For Short Channel Multi Gate Silicon Nanowire Transistors.” 2009. Thesis, Indian Institute of Science. Accessed April 06, 2020. http://hdl.handle.net/2005/969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kumar, P Rakesh. “Analytical Modeling Of Quantum Thershold Voltage For Short Channel Multi Gate Silicon Nanowire Transistors.” 2009. Web. 06 Apr 2020.

Vancouver:

Kumar PR. Analytical Modeling Of Quantum Thershold Voltage For Short Channel Multi Gate Silicon Nanowire Transistors. [Internet] [Thesis]. Indian Institute of Science; 2009. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/2005/969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kumar PR. Analytical Modeling Of Quantum Thershold Voltage For Short Channel Multi Gate Silicon Nanowire Transistors. [Thesis]. Indian Institute of Science; 2009. Available from: http://hdl.handle.net/2005/969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

24. Sharan, Neha. Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry.

Degree: 2014, Indian Institute of Science

 Compact Models are the physically based accurate mathematical description of the cir-cuit elements, which are computationally efficient enough to be incorporated in circuit simulators so… (more)

Subjects/Keywords: Metal Semiconductor Field Effect Transistors (MOSFET); Common Double Gate (CDG) MOSFETs-Compact Modeling; Electronic Circuits-Design; Transistor Circuits; MOSFETs-Core Model; Double Gate MOSFETs; Asymmetric CDG MOSFETs; Semiconductor Device Modeling; Gate Oxide Thickness Asymmetry; Gate Oxide Asymmetry; Electronic Systems Engineering

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APA (6th Edition):

Sharan, N. (2014). Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3489 ; http://etd.iisc.ernet.in/abstracts/4356/G26589-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sharan, Neha. “Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry.” 2014. Thesis, Indian Institute of Science. Accessed April 06, 2020. http://etd.iisc.ernet.in/2005/3489 ; http://etd.iisc.ernet.in/abstracts/4356/G26589-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sharan, Neha. “Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry.” 2014. Web. 06 Apr 2020.

Vancouver:

Sharan N. Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry. [Internet] [Thesis]. Indian Institute of Science; 2014. [cited 2020 Apr 06]. Available from: http://etd.iisc.ernet.in/2005/3489 ; http://etd.iisc.ernet.in/abstracts/4356/G26589-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sharan N. Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry. [Thesis]. Indian Institute of Science; 2014. Available from: http://etd.iisc.ernet.in/2005/3489 ; http://etd.iisc.ernet.in/abstracts/4356/G26589-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

25. Barton, Nathen. Prediction of phase noise and jitter in ring oscillators.

Degree: MS, Electrical and Computer Engineering, 2002, Oregon State University

 This thesis presents distinctly different methods of accurately predicting phase noise and absolute jitter in ring oscillators. The phase noise prediction methods are the commercially… (more)

Subjects/Keywords: Electronic noise  – Measurement

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APA (6th Edition):

Barton, N. (2002). Prediction of phase noise and jitter in ring oscillators. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/29635

Chicago Manual of Style (16th Edition):

Barton, Nathen. “Prediction of phase noise and jitter in ring oscillators.” 2002. Masters Thesis, Oregon State University. Accessed April 06, 2020. http://hdl.handle.net/1957/29635.

MLA Handbook (7th Edition):

Barton, Nathen. “Prediction of phase noise and jitter in ring oscillators.” 2002. Web. 06 Apr 2020.

Vancouver:

Barton N. Prediction of phase noise and jitter in ring oscillators. [Internet] [Masters thesis]. Oregon State University; 2002. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/1957/29635.

Council of Science Editors:

Barton N. Prediction of phase noise and jitter in ring oscillators. [Masters Thesis]. Oregon State University; 2002. Available from: http://hdl.handle.net/1957/29635


Stellenbosch University

26. Olivier, Marius. The conceptual design and development of novel low cost sensors for measuring the relative light emission in the pre-millisecond stages of detonating explosive charges.

Degree: MScEng, Electrical and Electronic Engineering, 2012, Stellenbosch University

 ENGLISH ABSTRACT: During the course of the CSIR’s research into the characterisation of explosive sources to devise methods of active intervention against threats, the need… (more)

Subjects/Keywords: Electronic engineering; Explosions  – Light emissions  – Measurement

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APA (6th Edition):

Olivier, M. (2012). The conceptual design and development of novel low cost sensors for measuring the relative light emission in the pre-millisecond stages of detonating explosive charges. (Masters Thesis). Stellenbosch University. Retrieved from http://hdl.handle.net/10019.1/71686

Chicago Manual of Style (16th Edition):

Olivier, Marius. “The conceptual design and development of novel low cost sensors for measuring the relative light emission in the pre-millisecond stages of detonating explosive charges.” 2012. Masters Thesis, Stellenbosch University. Accessed April 06, 2020. http://hdl.handle.net/10019.1/71686.

MLA Handbook (7th Edition):

Olivier, Marius. “The conceptual design and development of novel low cost sensors for measuring the relative light emission in the pre-millisecond stages of detonating explosive charges.” 2012. Web. 06 Apr 2020.

Vancouver:

Olivier M. The conceptual design and development of novel low cost sensors for measuring the relative light emission in the pre-millisecond stages of detonating explosive charges. [Internet] [Masters thesis]. Stellenbosch University; 2012. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/10019.1/71686.

Council of Science Editors:

Olivier M. The conceptual design and development of novel low cost sensors for measuring the relative light emission in the pre-millisecond stages of detonating explosive charges. [Masters Thesis]. Stellenbosch University; 2012. Available from: http://hdl.handle.net/10019.1/71686

27. Xie, Jiani. Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization.

Degree: PhD, Electrical Engineering and Computer Science, 2014, Syracuse University

  The modeling of an individual gate and the optimization of circuit performance has long been a critical issue in the VLSI industry. In this… (more)

Subjects/Keywords: Circuit optimization; Delay minimization; Discrete gate sizing; Gate and delay model; Power optimization; Engineering

…Discrete Gate Sizing Using Effective Local Delay Measurement and Cell Adjustment Gate sizing… …Gate Set D. Delay Cost Measurement Then considering the gate 𝑣 𝑖 on the critical path in… …sorting order . 15 Figure 2. 2. Pseudo code for Discrete Gate Sizing Algorithm with Delay… …circuit delay, layout area or power consumption, etc. Gate sizing is a flexible and powerful… …gate sizing problem for delay 2 minimization. And we may solve the power minimization… 

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APA (6th Edition):

Xie, J. (2014). Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization. (Doctoral Dissertation). Syracuse University. Retrieved from https://surface.syr.edu/etd/201

Chicago Manual of Style (16th Edition):

Xie, Jiani. “Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization.” 2014. Doctoral Dissertation, Syracuse University. Accessed April 06, 2020. https://surface.syr.edu/etd/201.

MLA Handbook (7th Edition):

Xie, Jiani. “Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization.” 2014. Web. 06 Apr 2020.

Vancouver:

Xie J. Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization. [Internet] [Doctoral dissertation]. Syracuse University; 2014. [cited 2020 Apr 06]. Available from: https://surface.syr.edu/etd/201.

Council of Science Editors:

Xie J. Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization. [Doctoral Dissertation]. Syracuse University; 2014. Available from: https://surface.syr.edu/etd/201


University of Arizona

28. Hu, Jhy-Fang, 1961-. AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY .

Degree: 1986, University of Arizona

Subjects/Keywords: Compiling (Electronic computers); Gate array circuits.

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APA (6th Edition):

Hu, Jhy-Fang, 1. (1986). AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/276948

Chicago Manual of Style (16th Edition):

Hu, Jhy-Fang, 1961-. “AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY .” 1986. Masters Thesis, University of Arizona. Accessed April 06, 2020. http://hdl.handle.net/10150/276948.

MLA Handbook (7th Edition):

Hu, Jhy-Fang, 1961-. “AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY .” 1986. Web. 06 Apr 2020.

Vancouver:

Hu, Jhy-Fang 1. AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY . [Internet] [Masters thesis]. University of Arizona; 1986. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/10150/276948.

Council of Science Editors:

Hu, Jhy-Fang 1. AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY . [Masters Thesis]. University of Arizona; 1986. Available from: http://hdl.handle.net/10150/276948


East Tennessee State University

29. Dreves, Parker A. An Investigation into the Structure of Self-Control.

Degree: PhD, Psychology, 2019, East Tennessee State University

  Self-control has been measured using a variety of methods including self-report measures, cognitive inhibition tasks, delay discounting and delay of gratification tasks, and persistence… (more)

Subjects/Keywords: self-control; impulse inhibition; delay of gratification; willpower; measurement; Other Psychology; Quantitative Psychology

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dreves, P. A. (2019). An Investigation into the Structure of Self-Control. (Doctoral Dissertation). East Tennessee State University. Retrieved from https://dc.etsu.edu/etd/3543

Chicago Manual of Style (16th Edition):

Dreves, Parker A. “An Investigation into the Structure of Self-Control.” 2019. Doctoral Dissertation, East Tennessee State University. Accessed April 06, 2020. https://dc.etsu.edu/etd/3543.

MLA Handbook (7th Edition):

Dreves, Parker A. “An Investigation into the Structure of Self-Control.” 2019. Web. 06 Apr 2020.

Vancouver:

Dreves PA. An Investigation into the Structure of Self-Control. [Internet] [Doctoral dissertation]. East Tennessee State University; 2019. [cited 2020 Apr 06]. Available from: https://dc.etsu.edu/etd/3543.

Council of Science Editors:

Dreves PA. An Investigation into the Structure of Self-Control. [Doctoral Dissertation]. East Tennessee State University; 2019. Available from: https://dc.etsu.edu/etd/3543


Brno University of Technology

30. Ingr, Michal. Geolokace stanic v síti Internet .

Degree: 2011, Brno University of Technology

 Diplomová práce se zabývá metodami geolokace stanic v síti Internet, či-li odhadem geografické polohy neznámé stanice, která je do této sítě připojena. Úvodní část práce… (more)

Subjects/Keywords: Geolokace; zpoždění; měření RTT; PlanetLab; CBG; Geolocation; delay; RTT measurement; PlanetLab; CBG

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ingr, M. (2011). Geolokace stanic v síti Internet . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/3689

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ingr, Michal. “Geolokace stanic v síti Internet .” 2011. Thesis, Brno University of Technology. Accessed April 06, 2020. http://hdl.handle.net/11012/3689.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ingr, Michal. “Geolokace stanic v síti Internet .” 2011. Web. 06 Apr 2020.

Vancouver:

Ingr M. Geolokace stanic v síti Internet . [Internet] [Thesis]. Brno University of Technology; 2011. [cited 2020 Apr 06]. Available from: http://hdl.handle.net/11012/3689.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ingr M. Geolokace stanic v síti Internet . [Thesis]. Brno University of Technology; 2011. Available from: http://hdl.handle.net/11012/3689

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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