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You searched for subject:(Electrical bug). Showing records 1 – 5 of 5 total matches.

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Iowa State University

1. Tamrawi, Ahmed. Fuzzy set and cache-based approach for bug triaging.

Degree: 2011, Iowa State University

 Software bugs are inevitable and bug fixing is an essential and costly phase during software development. Such defects are often reported in bug reports which… (more)

Subjects/Keywords: Bug Triaging; Developers' Expertise; Fuzzy Set; Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tamrawi, A. (2011). Fuzzy set and cache-based approach for bug triaging. (Thesis). Iowa State University. Retrieved from https://lib.dr.iastate.edu/etd/12230

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tamrawi, Ahmed. “Fuzzy set and cache-based approach for bug triaging.” 2011. Thesis, Iowa State University. Accessed March 06, 2021. https://lib.dr.iastate.edu/etd/12230.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tamrawi, Ahmed. “Fuzzy set and cache-based approach for bug triaging.” 2011. Web. 06 Mar 2021.

Vancouver:

Tamrawi A. Fuzzy set and cache-based approach for bug triaging. [Internet] [Thesis]. Iowa State University; 2011. [cited 2021 Mar 06]. Available from: https://lib.dr.iastate.edu/etd/12230.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tamrawi A. Fuzzy set and cache-based approach for bug triaging. [Thesis]. Iowa State University; 2011. Available from: https://lib.dr.iastate.edu/etd/12230

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


The Ohio State University

2. Thiagarajan, Deepa. EFFICIENT DETECTION OF HANG BUGS IN MOBILE APPLICATIONS.

Degree: MS, Electrical and Computer Engineering, 2016, The Ohio State University

 Mobile applications (apps) are growing tremendously in the market. Many apps are useful for our day-to-day activities. In order to survive in the market, these… (more)

Subjects/Keywords: Electrical Engineering; Computer Engineering; Android Applications, Hang Bug, Algorithm, Delay, CPU, Memory Utilization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Thiagarajan, D. (2016). EFFICIENT DETECTION OF HANG BUGS IN MOBILE APPLICATIONS. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1480534528352408

Chicago Manual of Style (16th Edition):

Thiagarajan, Deepa. “EFFICIENT DETECTION OF HANG BUGS IN MOBILE APPLICATIONS.” 2016. Masters Thesis, The Ohio State University. Accessed March 06, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=osu1480534528352408.

MLA Handbook (7th Edition):

Thiagarajan, Deepa. “EFFICIENT DETECTION OF HANG BUGS IN MOBILE APPLICATIONS.” 2016. Web. 06 Mar 2021.

Vancouver:

Thiagarajan D. EFFICIENT DETECTION OF HANG BUGS IN MOBILE APPLICATIONS. [Internet] [Masters thesis]. The Ohio State University; 2016. [cited 2021 Mar 06]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1480534528352408.

Council of Science Editors:

Thiagarajan D. EFFICIENT DETECTION OF HANG BUGS IN MOBILE APPLICATIONS. [Masters Thesis]. The Ohio State University; 2016. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1480534528352408


Oklahoma State University

3. Maskey, Kaushal. Comparison of Electrical Penetration Graph Waveforms of Squash Bug Feeding on Watermelon and Its Relatives.

Degree: Department of Entomology and Plant Pathology, 2010, Oklahoma State University

 Cucurbit yellow vine disease is caused by the bacterium Serratia marcescens, which is transmitted by the squash bug, a serious pest of cucurbit. Watermelon is… (more)

Subjects/Keywords: cucurbit yellow vine disease; electrical penetration graph; feeding behavior; serratia marcescens; squash bug; watermelon

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Maskey, K. (2010). Comparison of Electrical Penetration Graph Waveforms of Squash Bug Feeding on Watermelon and Its Relatives. (Thesis). Oklahoma State University. Retrieved from http://hdl.handle.net/11244/9001

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Maskey, Kaushal. “Comparison of Electrical Penetration Graph Waveforms of Squash Bug Feeding on Watermelon and Its Relatives.” 2010. Thesis, Oklahoma State University. Accessed March 06, 2021. http://hdl.handle.net/11244/9001.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Maskey, Kaushal. “Comparison of Electrical Penetration Graph Waveforms of Squash Bug Feeding on Watermelon and Its Relatives.” 2010. Web. 06 Mar 2021.

Vancouver:

Maskey K. Comparison of Electrical Penetration Graph Waveforms of Squash Bug Feeding on Watermelon and Its Relatives. [Internet] [Thesis]. Oklahoma State University; 2010. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/11244/9001.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Maskey K. Comparison of Electrical Penetration Graph Waveforms of Squash Bug Feeding on Watermelon and Its Relatives. [Thesis]. Oklahoma State University; 2010. Available from: http://hdl.handle.net/11244/9001

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. Svensson, Niclas. Sequence to Sequence Machine Learning for Automatic Program Repair.

Degree: Electrical Engineering and Computer Science (EECS), 2019, KTH

  Most of previous program repair approaches are only able to generate fixes for one-line bugs, including machine learning based approaches. This work aims to… (more)

Subjects/Keywords: Automatic program repair; neural machine translation; sequence to sequence; bug fix; Electrical Engineering, Electronic Engineering, Information Engineering; Elektroteknik och elektronik

…system for automatic program repair is suitable for multi-line-bug-fixing. A system was… …Poshyvanyk, “An empirical study on learning bug-fixing patches in the wild via neural machine… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Svensson, N. (2019). Sequence to Sequence Machine Learning for Automatic Program Repair. (Thesis). KTH. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-254272

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Svensson, Niclas. “Sequence to Sequence Machine Learning for Automatic Program Repair.” 2019. Thesis, KTH. Accessed March 06, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-254272.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Svensson, Niclas. “Sequence to Sequence Machine Learning for Automatic Program Repair.” 2019. Web. 06 Mar 2021.

Vancouver:

Svensson N. Sequence to Sequence Machine Learning for Automatic Program Repair. [Internet] [Thesis]. KTH; 2019. [cited 2021 Mar 06]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-254272.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Svensson N. Sequence to Sequence Machine Learning for Automatic Program Repair. [Thesis]. KTH; 2019. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-254272

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

5. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety… (more)

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

…conditions and effects are in general more difficult to pin down than the above electrical bug… …Simulation Breakpoint Trigger . . . . . . . . . . . . . 5.4 Bug Example… …Institute of Electrical and Electronics Engineers IR Intermediate Representation ISA… …with a software version generated to produce the same result, we show that logic bug… …line where a source-code bug resides. This technique also leverages cosimulation to use high… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 06, 2021. http://hdl.handle.net/2142/99294.

MLA Handbook (7th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 06 Mar 2021.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294

.