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You searched for subject:(Dynamic Biasing). Showing records 1 – 9 of 9 total matches.

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NSYSU

1. Liu, Yi-cheng. Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell.

Degree: Master, Electrical Engineering, 2009, NSYSU

 The thesis is composed of tow topics: a fully bidirectional mixed- voltage-tolerant I/O cell using a new output stage circuit and a sub-3ÃVDD wide range… (more)

Subjects/Keywords: I/O cell; Mixed-Voltage-Tolerant; Dynamic Biasing; Sub 3ÃVDD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, Y. (2009). Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Yi-cheng. “Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell.” 2009. Thesis, NSYSU. Accessed January 17, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Yi-cheng. “Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell.” 2009. Web. 17 Jan 2020.

Vancouver:

Liu Y. Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Jan 17]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu Y. Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Purdue University

2. Mohammad, Imaduddin. Integrated DC-DC boost converters using CMOS silicon on Sapphire Technology.

Degree: MS, Electrical and Computer Engineering, 2014, Purdue University

  With the recent advancements in semiconductor manufacturing towards smaller, faster and more efficient microelectronic systems, the problems of increasing leakage current and reduced breakdown… (more)

Subjects/Keywords: Applied sciences; Dc-dc boost converter; Dynamic biasing; Fully-integrated; On-chip; Stacking; Transformerless; Electrical and Computer Engineering

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APA (6th Edition):

Mohammad, I. (2014). Integrated DC-DC boost converters using CMOS silicon on Sapphire Technology. (Thesis). Purdue University. Retrieved from http://docs.lib.purdue.edu/open_access_theses/456

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mohammad, Imaduddin. “Integrated DC-DC boost converters using CMOS silicon on Sapphire Technology.” 2014. Thesis, Purdue University. Accessed January 17, 2020. http://docs.lib.purdue.edu/open_access_theses/456.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mohammad, Imaduddin. “Integrated DC-DC boost converters using CMOS silicon on Sapphire Technology.” 2014. Web. 17 Jan 2020.

Vancouver:

Mohammad I. Integrated DC-DC boost converters using CMOS silicon on Sapphire Technology. [Internet] [Thesis]. Purdue University; 2014. [cited 2020 Jan 17]. Available from: http://docs.lib.purdue.edu/open_access_theses/456.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mohammad I. Integrated DC-DC boost converters using CMOS silicon on Sapphire Technology. [Thesis]. Purdue University; 2014. Available from: http://docs.lib.purdue.edu/open_access_theses/456

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Arizona State University

3. Magod Ramakrishna, Raveesh. Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications.

Degree: Electrical Engineering, 2018, Arizona State University

Subjects/Keywords: Electrical engineering; charge-pump; Dynamic biasing; Fast transient response; Hybrid biasing; NMOS LDO; Switched capacitor pole tracking compensation

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APA (6th Edition):

Magod Ramakrishna, R. (2018). Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications. (Doctoral Dissertation). Arizona State University. Retrieved from http://repository.asu.edu/items/50579

Chicago Manual of Style (16th Edition):

Magod Ramakrishna, Raveesh. “Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications.” 2018. Doctoral Dissertation, Arizona State University. Accessed January 17, 2020. http://repository.asu.edu/items/50579.

MLA Handbook (7th Edition):

Magod Ramakrishna, Raveesh. “Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications.” 2018. Web. 17 Jan 2020.

Vancouver:

Magod Ramakrishna R. Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications. [Internet] [Doctoral dissertation]. Arizona State University; 2018. [cited 2020 Jan 17]. Available from: http://repository.asu.edu/items/50579.

Council of Science Editors:

Magod Ramakrishna R. Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications. [Doctoral Dissertation]. Arizona State University; 2018. Available from: http://repository.asu.edu/items/50579


University of New Mexico

4. El-Howayek, Georges. Communication-Theoretic Foundations for Optical Receivers Using Dynamically Biased Avalanche Photodiodes.

Degree: Electrical and Computer Engineering, 2015, University of New Mexico

  To meet the demands of the exponential growth in video, voice, data and mobile device traffic over the internet, the telecommunication industry has been… (more)

Subjects/Keywords: Communication Theory; Optical Receivers; Avalanche Photodiodes; Dynamic biasing; Branching process; Intersymbol Interference; Bit error rate; Receiver sensitivity; Gaussian distribution; Stochastic process; Dead space; Dark current and tunneling; Electrical and Computer Engineering

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APA (6th Edition):

El-Howayek, G. (2015). Communication-Theoretic Foundations for Optical Receivers Using Dynamically Biased Avalanche Photodiodes. (Doctoral Dissertation). University of New Mexico. Retrieved from http://hdl.handle.net/1928/27778

Chicago Manual of Style (16th Edition):

El-Howayek, Georges. “Communication-Theoretic Foundations for Optical Receivers Using Dynamically Biased Avalanche Photodiodes.” 2015. Doctoral Dissertation, University of New Mexico. Accessed January 17, 2020. http://hdl.handle.net/1928/27778.

MLA Handbook (7th Edition):

El-Howayek, Georges. “Communication-Theoretic Foundations for Optical Receivers Using Dynamically Biased Avalanche Photodiodes.” 2015. Web. 17 Jan 2020.

Vancouver:

El-Howayek G. Communication-Theoretic Foundations for Optical Receivers Using Dynamically Biased Avalanche Photodiodes. [Internet] [Doctoral dissertation]. University of New Mexico; 2015. [cited 2020 Jan 17]. Available from: http://hdl.handle.net/1928/27778.

Council of Science Editors:

El-Howayek G. Communication-Theoretic Foundations for Optical Receivers Using Dynamically Biased Avalanche Photodiodes. [Doctoral Dissertation]. University of New Mexico; 2015. Available from: http://hdl.handle.net/1928/27778


North Carolina State University

5. Devasthali, Vinayak Sudhakar. Application of Body Biasing and Supply Voltage Scaling Techniques for Leakage Reduction and Performance Improvements of CMOS Circuits.

Degree: MS, Electrical Engineering, 2008, North Carolina State University

 The efficiency of body biasing technique is evaluated in 90-nm process technology for regular and low threshold voltage devices. A new leakage monitor circuit for… (more)

Subjects/Keywords: body biasing; standby leakage; leakage monitor; optimum reverse bias; dynamic power; supply voltage scaling

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APA (6th Edition):

Devasthali, V. S. (2008). Application of Body Biasing and Supply Voltage Scaling Techniques for Leakage Reduction and Performance Improvements of CMOS Circuits. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/868

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Devasthali, Vinayak Sudhakar. “Application of Body Biasing and Supply Voltage Scaling Techniques for Leakage Reduction and Performance Improvements of CMOS Circuits.” 2008. Thesis, North Carolina State University. Accessed January 17, 2020. http://www.lib.ncsu.edu/resolver/1840.16/868.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Devasthali, Vinayak Sudhakar. “Application of Body Biasing and Supply Voltage Scaling Techniques for Leakage Reduction and Performance Improvements of CMOS Circuits.” 2008. Web. 17 Jan 2020.

Vancouver:

Devasthali VS. Application of Body Biasing and Supply Voltage Scaling Techniques for Leakage Reduction and Performance Improvements of CMOS Circuits. [Internet] [Thesis]. North Carolina State University; 2008. [cited 2020 Jan 17]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/868.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Devasthali VS. Application of Body Biasing and Supply Voltage Scaling Techniques for Leakage Reduction and Performance Improvements of CMOS Circuits. [Thesis]. North Carolina State University; 2008. Available from: http://www.lib.ncsu.edu/resolver/1840.16/868

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université Montpellier II

6. Akgul, Yeter. Gestion de la consommation basée sur l’adaptation dynamique de la tension, fréquence et body bias sur les systèmes sur puce en technologie FD-SOI : Power Management based on Dynamic Voltage, Frequency and Body Bias Scaling on System On Chip in FD-SOI technology.

Degree: Docteur es, Systèmes automatiques et microélectroniques, 2014, Université Montpellier II

Au-delà du nœud technologique CMOS BULK 28nm, certaines limites ont été atteintes dans l'amélioration des performances en raison notamment d'une consommation énergétique devenant trop importante.… (more)

Subjects/Keywords: Dvfs; Adaptation dynamique de Body Bias; Fd-Soi; Gestion de la consommation; Optimisation de la consommation; Sélection de Power Mode; Dynamic Voltage and Frequency Scaling; Adaptive Body Biasing; Fd-Soi; Power Management; Power Optimization; Power Mode Selection

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APA (6th Edition):

Akgul, Y. (2014). Gestion de la consommation basée sur l’adaptation dynamique de la tension, fréquence et body bias sur les systèmes sur puce en technologie FD-SOI : Power Management based on Dynamic Voltage, Frequency and Body Bias Scaling on System On Chip in FD-SOI technology. (Doctoral Dissertation). Université Montpellier II. Retrieved from http://www.theses.fr/2014MON20132

Chicago Manual of Style (16th Edition):

Akgul, Yeter. “Gestion de la consommation basée sur l’adaptation dynamique de la tension, fréquence et body bias sur les systèmes sur puce en technologie FD-SOI : Power Management based on Dynamic Voltage, Frequency and Body Bias Scaling on System On Chip in FD-SOI technology.” 2014. Doctoral Dissertation, Université Montpellier II. Accessed January 17, 2020. http://www.theses.fr/2014MON20132.

MLA Handbook (7th Edition):

Akgul, Yeter. “Gestion de la consommation basée sur l’adaptation dynamique de la tension, fréquence et body bias sur les systèmes sur puce en technologie FD-SOI : Power Management based on Dynamic Voltage, Frequency and Body Bias Scaling on System On Chip in FD-SOI technology.” 2014. Web. 17 Jan 2020.

Vancouver:

Akgul Y. Gestion de la consommation basée sur l’adaptation dynamique de la tension, fréquence et body bias sur les systèmes sur puce en technologie FD-SOI : Power Management based on Dynamic Voltage, Frequency and Body Bias Scaling on System On Chip in FD-SOI technology. [Internet] [Doctoral dissertation]. Université Montpellier II; 2014. [cited 2020 Jan 17]. Available from: http://www.theses.fr/2014MON20132.

Council of Science Editors:

Akgul Y. Gestion de la consommation basée sur l’adaptation dynamique de la tension, fréquence et body bias sur les systèmes sur puce en technologie FD-SOI : Power Management based on Dynamic Voltage, Frequency and Body Bias Scaling on System On Chip in FD-SOI technology. [Doctoral Dissertation]. Université Montpellier II; 2014. Available from: http://www.theses.fr/2014MON20132

7. Rai, Gursewak Singh. Constant Conduction Angle Biasing for Class C Monolithic RF Power Amplifiers.

Degree: MS, Electrical Engineering, 2012, Cal Poly

  In modern wireless communication systems, a base station typically serves a few hundred users within its cell coverage. To combat the near-far problem –… (more)

Subjects/Keywords: Dynamic Biasing; Constant Conduction Angle; Linearized Class C; RF Power Amplifiers; Systems and Communications

…11 3.1 Values used in simulating CCA biasing circuit for θ=120… …13 1.9 Approach to adaptive biasing used by [8]… …biasing; (b) Desired class C operation… …15 2.3 Simplified block diagram of LaCaille’s CCA biasing approach… …19 2.5 Simplified block diagram of Garber’s CCA biasing approach… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rai, G. S. (2012). Constant Conduction Angle Biasing for Class C Monolithic RF Power Amplifiers. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/872 ; 10.15368/theses.2012.190

Chicago Manual of Style (16th Edition):

Rai, Gursewak Singh. “Constant Conduction Angle Biasing for Class C Monolithic RF Power Amplifiers.” 2012. Masters Thesis, Cal Poly. Accessed January 17, 2020. https://digitalcommons.calpoly.edu/theses/872 ; 10.15368/theses.2012.190.

MLA Handbook (7th Edition):

Rai, Gursewak Singh. “Constant Conduction Angle Biasing for Class C Monolithic RF Power Amplifiers.” 2012. Web. 17 Jan 2020.

Vancouver:

Rai GS. Constant Conduction Angle Biasing for Class C Monolithic RF Power Amplifiers. [Internet] [Masters thesis]. Cal Poly; 2012. [cited 2020 Jan 17]. Available from: https://digitalcommons.calpoly.edu/theses/872 ; 10.15368/theses.2012.190.

Council of Science Editors:

Rai GS. Constant Conduction Angle Biasing for Class C Monolithic RF Power Amplifiers. [Masters Thesis]. Cal Poly; 2012. Available from: https://digitalcommons.calpoly.edu/theses/872 ; 10.15368/theses.2012.190


Kyoto University

8. Shiomi, Jun. Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits .

Degree: 2017, Kyoto University

Subjects/Keywords: Energy-efficient LSI; Low-voltage operation; Variability-aware timing modeling; Standard-Cell Memory (SCM); Dynamic Voltage and Frequency Scaling (DVFS); Adaptive Body Biasing (ABB); Minimum energy point operation

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APA (6th Edition):

Shiomi, J. (2017). Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits . (Thesis). Kyoto University. Retrieved from http://hdl.handle.net/2433/228252

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shiomi, Jun. “Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits .” 2017. Thesis, Kyoto University. Accessed January 17, 2020. http://hdl.handle.net/2433/228252.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shiomi, Jun. “Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits .” 2017. Web. 17 Jan 2020.

Vancouver:

Shiomi J. Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits . [Internet] [Thesis]. Kyoto University; 2017. [cited 2020 Jan 17]. Available from: http://hdl.handle.net/2433/228252.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shiomi J. Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits . [Thesis]. Kyoto University; 2017. Available from: http://hdl.handle.net/2433/228252

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Kyoto University / 京都大学

9. Shiomi, Jun. Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits : 低電圧集積回路の消費エネルギー最小化のための解析的性能予測とオンチップメモリ構造.

Degree: 博士(情報学), 2017, Kyoto University / 京都大学

新制・課程博士

甲第20778号

情博第658号

Subjects/Keywords: Energy-efficient LSI; Low-voltage operation; Variability-aware timing modeling; Standard-Cell Memory (SCM); Dynamic Voltage and Frequency Scaling (DVFS); Adaptive Body Biasing (ABB); Minimum energy point operation

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APA (6th Edition):

Shiomi, J. (2017). Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits : 低電圧集積回路の消費エネルギー最小化のための解析的性能予測とオンチップメモリ構造. (Thesis). Kyoto University / 京都大学. Retrieved from http://hdl.handle.net/2433/228252 ; http://dx.doi.org/10.14989/doctor.k20778

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shiomi, Jun. “Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits : 低電圧集積回路の消費エネルギー最小化のための解析的性能予測とオンチップメモリ構造.” 2017. Thesis, Kyoto University / 京都大学. Accessed January 17, 2020. http://hdl.handle.net/2433/228252 ; http://dx.doi.org/10.14989/doctor.k20778.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shiomi, Jun. “Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits : 低電圧集積回路の消費エネルギー最小化のための解析的性能予測とオンチップメモリ構造.” 2017. Web. 17 Jan 2020.

Vancouver:

Shiomi J. Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits : 低電圧集積回路の消費エネルギー最小化のための解析的性能予測とオンチップメモリ構造. [Internet] [Thesis]. Kyoto University / 京都大学; 2017. [cited 2020 Jan 17]. Available from: http://hdl.handle.net/2433/228252 ; http://dx.doi.org/10.14989/doctor.k20778.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shiomi J. Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits : 低電圧集積回路の消費エネルギー最小化のための解析的性能予測とオンチップメモリ構造. [Thesis]. Kyoto University / 京都大学; 2017. Available from: http://hdl.handle.net/2433/228252 ; http://dx.doi.org/10.14989/doctor.k20778

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.