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You searched for subject:(Discretized statistical static timing analysis SSTA ). Showing records 1 – 30 of 94126 total matches.

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University of Illinois – Urbana-Champaign

1. Chilstedt, Scott E. Architecture and CAD for carbon nanomaterial integrated circuits.

Degree: MS, 1200, 2010, University of Illinois – Urbana-Champaign

 The ITRS (International Technology Roadmap for Semiconductors) has recommended that carbon-based transistors be given further study as a potential ???Beyond CMOS??? technology. Unlike traditional devices… (more)

Subjects/Keywords: Carbon Nanotubes; Graphene Nanoribbons; Carbon Nanomaterial Transistors; Nanoelectronic Architectures; Field programmable carbon nanotube array (FPCNA); Variation-Aware CAD; Discretized statistical static timing analysis (SSTA)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chilstedt, S. E. (2010). Architecture and CAD for carbon nanomaterial integrated circuits. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/15969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chilstedt, Scott E. “Architecture and CAD for carbon nanomaterial integrated circuits.” 2010. Thesis, University of Illinois – Urbana-Champaign. Accessed April 01, 2020. http://hdl.handle.net/2142/15969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chilstedt, Scott E. “Architecture and CAD for carbon nanomaterial integrated circuits.” 2010. Web. 01 Apr 2020.

Vancouver:

Chilstedt SE. Architecture and CAD for carbon nanomaterial integrated circuits. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2010. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/2142/15969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chilstedt SE. Architecture and CAD for carbon nanomaterial integrated circuits. [Thesis]. University of Illinois – Urbana-Champaign; 2010. Available from: http://hdl.handle.net/2142/15969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

2. Kim, Hyun Sung. Statistical static timing analysis considering the impact of power supply noise in VLSI circuits.

Degree: 2009, Texas A&M University

 As semiconductor technology is scaled and voltage level is reduced, the impact of the variation in power supply has become very significant in predicting the… (more)

Subjects/Keywords: Statistical Static Timing Analysis; power supply noise

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APA (6th Edition):

Kim, H. S. (2009). Statistical static timing analysis considering the impact of power supply noise in VLSI circuits. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-1902

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kim, Hyun Sung. “Statistical static timing analysis considering the impact of power supply noise in VLSI circuits.” 2009. Thesis, Texas A&M University. Accessed April 01, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-1902.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kim, Hyun Sung. “Statistical static timing analysis considering the impact of power supply noise in VLSI circuits.” 2009. Web. 01 Apr 2020.

Vancouver:

Kim HS. Statistical static timing analysis considering the impact of power supply noise in VLSI circuits. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1902.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim HS. Statistical static timing analysis considering the impact of power supply noise in VLSI circuits. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1902

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

3. Lucas, Gregory M. Timing Analysis and Behavioral Synthesis with Process Variation.

Degree: MS, Electrical and Computer Engineering, 2009, University of Illinois – Urbana-Champaign

 The move to deep submicron processes has brought about new problems that designers must contend with in order to obtain functional circuits. Process variation has… (more)

Subjects/Keywords: process variation; high-level synthesis; behavioral synthesis; statistical static timing analysis; SSTA; multi-cycle; multi-clock

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APA (6th Edition):

Lucas, G. M. (2009). Timing Analysis and Behavioral Synthesis with Process Variation. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/11966

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lucas, Gregory M. “Timing Analysis and Behavioral Synthesis with Process Variation.” 2009. Thesis, University of Illinois – Urbana-Champaign. Accessed April 01, 2020. http://hdl.handle.net/2142/11966.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lucas, Gregory M. “Timing Analysis and Behavioral Synthesis with Process Variation.” 2009. Web. 01 Apr 2020.

Vancouver:

Lucas GM. Timing Analysis and Behavioral Synthesis with Process Variation. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2009. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/2142/11966.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lucas GM. Timing Analysis and Behavioral Synthesis with Process Variation. [Thesis]. University of Illinois – Urbana-Champaign; 2009. Available from: http://hdl.handle.net/2142/11966

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

4. Hsieh, Kai-Yang. Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 Small Delay Defect (SDD) is one kind of the signal transition delay faults. It could not be detected via traditional delay testing method because the… (more)

Subjects/Keywords: Commercial ATPG Tool; False Path; Statistical Static Timing Analysis; Timing-aware ATPG; Small Delay Defect

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APA (6th Edition):

Hsieh, K. (2013). Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629113-155339

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsieh, Kai-Yang. “Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection.” 2013. Thesis, NSYSU. Accessed April 01, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629113-155339.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsieh, Kai-Yang. “Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection.” 2013. Web. 01 Apr 2020.

Vancouver:

Hsieh K. Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Apr 01]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629113-155339.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsieh K. Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629113-155339

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

5. Das, Bishnu Prasad. Random Local Delay Variability : On-chip Measurement And Modeling.

Degree: 2009, Indian Institute of Science

 This thesis focuses on random local delay variability measurement and its modeling. It explains a circuit technique to measure the individual logic gate delay in… (more)

Subjects/Keywords: Electronic Gates - Design; On-chip Management And Construction; Electronic Gate Delay - Modeling; Random Local Delay Variation; On-chip Gate Delay Measurement; Process Voltage And Temperature Gate Delay Model; Electronic Gate Delay - Measurement; Statistical Static Timing Analysis (SSTA); Gate Delay Variability Measurement; Delay Variability; On-chip Measurement; Gate Delay Models; Electronic Engineering

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APA (6th Edition):

Das, B. P. (2009). Random Local Delay Variability : On-chip Measurement And Modeling. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1008

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Das, Bishnu Prasad. “Random Local Delay Variability : On-chip Measurement And Modeling.” 2009. Thesis, Indian Institute of Science. Accessed April 01, 2020. http://hdl.handle.net/2005/1008.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Das, Bishnu Prasad. “Random Local Delay Variability : On-chip Measurement And Modeling.” 2009. Web. 01 Apr 2020.

Vancouver:

Das BP. Random Local Delay Variability : On-chip Measurement And Modeling. [Internet] [Thesis]. Indian Institute of Science; 2009. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/2005/1008.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Das BP. Random Local Delay Variability : On-chip Measurement And Modeling. [Thesis]. Indian Institute of Science; 2009. Available from: http://hdl.handle.net/2005/1008

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

6. Pendela Venkata Ramanjuneya, Suryanarayana. Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits.

Degree: MS, Engineering : Computer Engineering, 2010, University of Cincinnati

 Much of the Semiconductor Industry’s success can be attributed to Moore’s law whichstates that the number of transistors on an integrated circuit would double approximatelyevery… (more)

Subjects/Keywords: Electrical Engineering; sta; timing; process variations; ssta; static timing analysis; standard cell

…a new class of STA called Statistical Static Timing Analysis (SSTA). Another… …Timing Analysis in particular, has led to a new paradigm called Statistical Static Timing… …Timing Analysis engine in the figure. The authors envision the usage of a Interval Valued Static… …developed in C++ which performs interval valued static timing analysis that can guide the… …of future work in Chapter 6. 14 Chapter 2 Static Timing Analysis Static Timing Analysis… 

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APA (6th Edition):

Pendela Venkata Ramanjuneya, S. (2010). Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324

Chicago Manual of Style (16th Edition):

Pendela Venkata Ramanjuneya, Suryanarayana. “Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits.” 2010. Masters Thesis, University of Cincinnati. Accessed April 01, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324.

MLA Handbook (7th Edition):

Pendela Venkata Ramanjuneya, Suryanarayana. “Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits.” 2010. Web. 01 Apr 2020.

Vancouver:

Pendela Venkata Ramanjuneya S. Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits. [Internet] [Masters thesis]. University of Cincinnati; 2010. [cited 2020 Apr 01]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324.

Council of Science Editors:

Pendela Venkata Ramanjuneya S. Techniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits. [Masters Thesis]. University of Cincinnati; 2010. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1268426324


Delft University of Technology

7. Nigam, A. Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:.

Degree: 2010, Delft University of Technology

 As we are moving toward nanometre technology, the variability in the circuit parameters and operating environment (Process, Voltage and Temperature (PVT)) are increasing, causing uncertainty… (more)

Subjects/Keywords: STA; SSTA; digital circuit; timing analysis; EDA; PVT; variation; Monte Carlo; 45nm; methodology; simulation; MODERN

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APA (6th Edition):

Nigam, A. (2010). Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:6d56368c-a3c4-4e5d-8234-ef70a7f26b78

Chicago Manual of Style (16th Edition):

Nigam, A. “Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:.” 2010. Masters Thesis, Delft University of Technology. Accessed April 01, 2020. http://resolver.tudelft.nl/uuid:6d56368c-a3c4-4e5d-8234-ef70a7f26b78.

MLA Handbook (7th Edition):

Nigam, A. “Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:.” 2010. Web. 01 Apr 2020.

Vancouver:

Nigam A. Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:. [Internet] [Masters thesis]. Delft University of Technology; 2010. [cited 2020 Apr 01]. Available from: http://resolver.tudelft.nl/uuid:6d56368c-a3c4-4e5d-8234-ef70a7f26b78.

Council of Science Editors:

Nigam A. Standard Cell Behavior Analysis and Waveform Set Model for Statistical Static Timing Analysis:. [Masters Thesis]. Delft University of Technology; 2010. Available from: http://resolver.tudelft.nl/uuid:6d56368c-a3c4-4e5d-8234-ef70a7f26b78


University of Ottawa

8. Fu, Jingyi J.Y. Delay Analysis of Digital Circuits Using Prony's Method .

Degree: 2011, University of Ottawa

 This thesis describes possible applications of Prony's method in timing analysis of digital circuits. Such applications include predicting the future shape of the waveform in… (more)

Subjects/Keywords: Prony's method; Timing Analysis; Obreshokov; numerical method; Dynamic Timing Analysis (DTA); Static Timing Analysis (STA)

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APA (6th Edition):

Fu, J. J. Y. (2011). Delay Analysis of Digital Circuits Using Prony's Method . (Thesis). University of Ottawa. Retrieved from http://hdl.handle.net/10393/20125

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fu, Jingyi J Y. “Delay Analysis of Digital Circuits Using Prony's Method .” 2011. Thesis, University of Ottawa. Accessed April 01, 2020. http://hdl.handle.net/10393/20125.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fu, Jingyi J Y. “Delay Analysis of Digital Circuits Using Prony's Method .” 2011. Web. 01 Apr 2020.

Vancouver:

Fu JJY. Delay Analysis of Digital Circuits Using Prony's Method . [Internet] [Thesis]. University of Ottawa; 2011. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10393/20125.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fu JJY. Delay Analysis of Digital Circuits Using Prony's Method . [Thesis]. University of Ottawa; 2011. Available from: http://hdl.handle.net/10393/20125

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

9. Shriram, Vignesh. Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits.

Degree: M.S.E.E., Electrical/Computer Engineering, 2019, University of Minnesota

 Coupling capacitance is becoming increasingly problematic at the more advanced technology nodes and affects the timing and sign-off timeline of integrated circuits (ICs). As the… (more)

Subjects/Keywords: coupling capacitance; static timing analysis; VLSI

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APA (6th Edition):

Shriram, V. (2019). Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits. (Masters Thesis). University of Minnesota. Retrieved from http://hdl.handle.net/11299/206136

Chicago Manual of Style (16th Edition):

Shriram, Vignesh. “Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits.” 2019. Masters Thesis, University of Minnesota. Accessed April 01, 2020. http://hdl.handle.net/11299/206136.

MLA Handbook (7th Edition):

Shriram, Vignesh. “Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits.” 2019. Web. 01 Apr 2020.

Vancouver:

Shriram V. Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits. [Internet] [Masters thesis]. University of Minnesota; 2019. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/11299/206136.

Council of Science Editors:

Shriram V. Early Estimation Of The Impact Of Delay Due To Coupling Capacitance In VSLI Circuits. [Masters Thesis]. University of Minnesota; 2019. Available from: http://hdl.handle.net/11299/206136

10. Shen, Yiren. Parallel Acceleration for Timing Analysis and Optimization of Adaptive Integrated Circuits.

Degree: 2016, Texas A&M University

 Adaptive circuit design is a power-efficient approach to handle variations. Compared to conventional circuits, its implementation is more complicated especially when we deal with the… (more)

Subjects/Keywords: parallel acceleration; adaptive circuits; statistical static timing analysis

…variations more effectively, statistical static timing analysis (SSTA) was proposed and… …variations especially the spatial correlation. II-D. Statistical Static Timing Analysis The SSTA… …Acceleration for PCA-Based Statistical Static Timing Analysis” by Y. Shen and J. Hu, 2015. In… …also fundamental to provide assurance for design timing closure. Static Timing Analysis (… …static timing analysis with PCA (Principal Component Analysis). It is demonstrated in… 

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APA (6th Edition):

Shen, Y. (2016). Parallel Acceleration for Timing Analysis and Optimization of Adaptive Integrated Circuits. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/156792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shen, Yiren. “Parallel Acceleration for Timing Analysis and Optimization of Adaptive Integrated Circuits.” 2016. Thesis, Texas A&M University. Accessed April 01, 2020. http://hdl.handle.net/1969.1/156792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shen, Yiren. “Parallel Acceleration for Timing Analysis and Optimization of Adaptive Integrated Circuits.” 2016. Web. 01 Apr 2020.

Vancouver:

Shen Y. Parallel Acceleration for Timing Analysis and Optimization of Adaptive Integrated Circuits. [Internet] [Thesis]. Texas A&M University; 2016. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1969.1/156792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shen Y. Parallel Acceleration for Timing Analysis and Optimization of Adaptive Integrated Circuits. [Thesis]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/156792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Zheng, X.Y. Implementing and evaluating a simplified transistor model for timing analysis of integrated circuits:.

Degree: 2012, Delft University of Technology

Static Timing Analysis (STA) is one approach to verify the timing of a digital circuit. The currently used Gate Level Model (GLM) has limitations on… (more)

Subjects/Keywords: Static Timing Analysis; Verilog-AMS; transistor level model; spectre; polynomial curve fitting; statistical timing analysis

Statistical Timing Analysis 5.1 The sensitivity of the transistor model… …Relative time points error of NOR2X2 compared with BSIM4 . statistical timing analysis on 7… …statistical timing analysis for 7 stages inverter chain . . . . . . . . . . . 47 49 5.4 xiii 51… …56 xiv 1 Introduction Static Timing Analysis (STA) is an approach to… …simple structure of the model enables statistical timing analysis for digital circuits at the… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zheng, X. Y. (2012). Implementing and evaluating a simplified transistor model for timing analysis of integrated circuits:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:84ff0f8e-ec0a-4b77-8fa9-9df7eaef6b60

Chicago Manual of Style (16th Edition):

Zheng, X Y. “Implementing and evaluating a simplified transistor model for timing analysis of integrated circuits:.” 2012. Masters Thesis, Delft University of Technology. Accessed April 01, 2020. http://resolver.tudelft.nl/uuid:84ff0f8e-ec0a-4b77-8fa9-9df7eaef6b60.

MLA Handbook (7th Edition):

Zheng, X Y. “Implementing and evaluating a simplified transistor model for timing analysis of integrated circuits:.” 2012. Web. 01 Apr 2020.

Vancouver:

Zheng XY. Implementing and evaluating a simplified transistor model for timing analysis of integrated circuits:. [Internet] [Masters thesis]. Delft University of Technology; 2012. [cited 2020 Apr 01]. Available from: http://resolver.tudelft.nl/uuid:84ff0f8e-ec0a-4b77-8fa9-9df7eaef6b60.

Council of Science Editors:

Zheng XY. Implementing and evaluating a simplified transistor model for timing analysis of integrated circuits:. [Masters Thesis]. Delft University of Technology; 2012. Available from: http://resolver.tudelft.nl/uuid:84ff0f8e-ec0a-4b77-8fa9-9df7eaef6b60


NSYSU

12. Ko, Xue-Da. Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 With the improvement of semiconductor manufacturing processes, the power consumption of the integrated circuit(IC) is growing rapidly. Therefore, the power consumption reduction of IC is… (more)

Subjects/Keywords: Static Timing Analysis; Level Converter; Critical Path; Multiple-Supply Voltage

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APA (6th Edition):

Ko, X. (2013). Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ko, Xue-Da. “Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology.” 2013. Thesis, NSYSU. Accessed April 01, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ko, Xue-Da. “Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology.” 2013. Web. 01 Apr 2020.

Vancouver:

Ko X. Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Apr 01]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ko X. Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625113-170420

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Case Western Reserve University

13. Krishnamurthy, Sivasubramaniam T. STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS.

Degree: MSs (Engineering), Computer Engineering, 2008, Case Western Reserve University

 As designers build complex digital circuits with ever diminishing device sizes, there is a need to obtain fast circuits with low hardware overhead. Critical path… (more)

Subjects/Keywords: Static Timing Analysis; Partitioning; Heuristics; Microprocessors; Digital Logic; VLSI

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APA (6th Edition):

Krishnamurthy, S. T. (2008). STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS. (Masters Thesis). Case Western Reserve University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=case1201299462

Chicago Manual of Style (16th Edition):

Krishnamurthy, Sivasubramaniam T. “STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS.” 2008. Masters Thesis, Case Western Reserve University. Accessed April 01, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=case1201299462.

MLA Handbook (7th Edition):

Krishnamurthy, Sivasubramaniam T. “STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS.” 2008. Web. 01 Apr 2020.

Vancouver:

Krishnamurthy ST. STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS. [Internet] [Masters thesis]. Case Western Reserve University; 2008. [cited 2020 Apr 01]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1201299462.

Council of Science Editors:

Krishnamurthy ST. STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS. [Masters Thesis]. Case Western Reserve University; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1201299462

14. Tsiampas, Michail. Timing analysis and power integrity of integrated circuits in technologies below 60nm.

Degree: 2019, University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας

 Technology Process continues to evolve, scaling down transistor sizes aiming to decrease power supply nominal voltages as the easiest way to lower the power footprint.… (more)

Subjects/Keywords: Ανάλυση ισχύος; Ανάλυση χρονισμού; Πτώση τάσης; Στατική ανάλυση χρονισμού; Δυναμική ανάλυση χρονισμού; Μηχανή στατιστικής πρόβλεψης; Θεωρία ακραίων τιμών; Γραμμικός αναλυτής; Γραμμές μεταφοράς; Power integrity; Timing analysis; Voltage - drop; Statistical prediction engine; Static timing analysis; Statistical prediction engine; Extreme value theory; Linear solver; Transmission lines; Bivariate joint process variation

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APA (6th Edition):

Tsiampas, M. (2019). Timing analysis and power integrity of integrated circuits in technologies below 60nm. (Thesis). University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας. Retrieved from http://hdl.handle.net/10442/hedi/45356

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tsiampas, Michail. “Timing analysis and power integrity of integrated circuits in technologies below 60nm.” 2019. Thesis, University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας. Accessed April 01, 2020. http://hdl.handle.net/10442/hedi/45356.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tsiampas, Michail. “Timing analysis and power integrity of integrated circuits in technologies below 60nm.” 2019. Web. 01 Apr 2020.

Vancouver:

Tsiampas M. Timing analysis and power integrity of integrated circuits in technologies below 60nm. [Internet] [Thesis]. University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας; 2019. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10442/hedi/45356.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsiampas M. Timing analysis and power integrity of integrated circuits in technologies below 60nm. [Thesis]. University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας; 2019. Available from: http://hdl.handle.net/10442/hedi/45356

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

15. Liu, Qunzeng. Statistical analysis techniques for logic and memory circuits.

Degree: PhD, Electrical Engineering, 2010, University of Minnesota

 Process variations have become increasingly important as feature sizes enter the sub- 100nm regime and continue to shrink. Both logic and memory circuits have seen… (more)

Subjects/Keywords: Embedded DRAM; Post-silicon optimization; SSTA; Statistical analysis; Electrical Engineering

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APA (6th Edition):

Liu, Q. (2010). Statistical analysis techniques for logic and memory circuits. (Doctoral Dissertation). University of Minnesota. Retrieved from http://purl.umn.edu/95019

Chicago Manual of Style (16th Edition):

Liu, Qunzeng. “Statistical analysis techniques for logic and memory circuits.” 2010. Doctoral Dissertation, University of Minnesota. Accessed April 01, 2020. http://purl.umn.edu/95019.

MLA Handbook (7th Edition):

Liu, Qunzeng. “Statistical analysis techniques for logic and memory circuits.” 2010. Web. 01 Apr 2020.

Vancouver:

Liu Q. Statistical analysis techniques for logic and memory circuits. [Internet] [Doctoral dissertation]. University of Minnesota; 2010. [cited 2020 Apr 01]. Available from: http://purl.umn.edu/95019.

Council of Science Editors:

Liu Q. Statistical analysis techniques for logic and memory circuits. [Doctoral Dissertation]. University of Minnesota; 2010. Available from: http://purl.umn.edu/95019


Texas A&M University

16. Feng, Zhuo. Modeling and Analysis of Large-Scale On-Chip Interconnects.

Degree: 2010, Texas A&M University

 As IC technologies scale to the nanometer regime, efficient and accurate modeling and analysis of VLSI systems with billions of transistors and interconnects becomes increasingly… (more)

Subjects/Keywords: process variation; statistical circuit modeling and analysis; model order reduction; statistical parameter dimension reduction; reduced rank regression; design-dependent interconnect corner extraction; statistical static timing analysis; power grid analysis; circuit simulation; general-purpose computation on graphics processing unit; GPU; massively parallel computing; multigrid; CUDA programming language; multi-core programming

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APA (6th Edition):

Feng, Z. (2010). Modeling and Analysis of Large-Scale On-Chip Interconnects. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7142

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Feng, Zhuo. “Modeling and Analysis of Large-Scale On-Chip Interconnects.” 2010. Thesis, Texas A&M University. Accessed April 01, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7142.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Feng, Zhuo. “Modeling and Analysis of Large-Scale On-Chip Interconnects.” 2010. Web. 01 Apr 2020.

Vancouver:

Feng Z. Modeling and Analysis of Large-Scale On-Chip Interconnects. [Internet] [Thesis]. Texas A&M University; 2010. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7142.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Feng Z. Modeling and Analysis of Large-Scale On-Chip Interconnects. [Thesis]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7142

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Gaspar, Nuno Miguel Pires. Timing analysis: from predictions to certificates.

Degree: 2010, RCAAP

 In real-time systems timing properties must be satisfied in order to guarantee that deadlines will be met. In this context, the calculation of theworst-case execution… (more)

Subjects/Keywords: Timing analysis; Worst-case execution time; Static analysis; Fixpoint computation; Abstract interpretation; Abstraction-carrying code

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APA (6th Edition):

Gaspar, N. M. P. (2010). Timing analysis: from predictions to certificates. (Thesis). RCAAP. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:ubibliorum.ubi.pt:10400.6/3764

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gaspar, Nuno Miguel Pires. “Timing analysis: from predictions to certificates.” 2010. Thesis, RCAAP. Accessed April 01, 2020. http://www.rcaap.pt/detail.jsp?id=oai:ubibliorum.ubi.pt:10400.6/3764.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gaspar, Nuno Miguel Pires. “Timing analysis: from predictions to certificates.” 2010. Web. 01 Apr 2020.

Vancouver:

Gaspar NMP. Timing analysis: from predictions to certificates. [Internet] [Thesis]. RCAAP; 2010. [cited 2020 Apr 01]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:ubibliorum.ubi.pt:10400.6/3764.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gaspar NMP. Timing analysis: from predictions to certificates. [Thesis]. RCAAP; 2010. Available from: http://www.rcaap.pt/detail.jsp?id=oai:ubibliorum.ubi.pt:10400.6/3764

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. Kang, Sang Yeol. Providing Static Timing Anlaysis Support for an ARM7 Processor Platform.

Degree: MS, Computer Engineering, 2008, North Carolina State University

 Scratchpad memory provides faster speed but smaller capacity than other memories do in embedded systems. It provides a visibly heterogeneous memory hierarchy rather than abstracting… (more)

Subjects/Keywords: Static Timing Analysis; WCET; BCET

…ABSTRACT KANG, SANG YEOL. Providing Static Timing Analysis Support for an ARM7 Processor… …program’s timing information. Based on the WCET and BCET estimated by static timing analysis, the… …unstructured code are also identified, which make static timing analysis more difficult. A control… …In addition, the static timing analysis framework of this study is implemented by the tool… …execution times. Providing Static Timing Analysis Support for an ARM7 Processor Platform by Sang… 

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APA (6th Edition):

Kang, S. Y. (2008). Providing Static Timing Anlaysis Support for an ARM7 Processor Platform. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/1546

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kang, Sang Yeol. “Providing Static Timing Anlaysis Support for an ARM7 Processor Platform.” 2008. Thesis, North Carolina State University. Accessed April 01, 2020. http://www.lib.ncsu.edu/resolver/1840.16/1546.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kang, Sang Yeol. “Providing Static Timing Anlaysis Support for an ARM7 Processor Platform.” 2008. Web. 01 Apr 2020.

Vancouver:

Kang SY. Providing Static Timing Anlaysis Support for an ARM7 Processor Platform. [Internet] [Thesis]. North Carolina State University; 2008. [cited 2020 Apr 01]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1546.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kang SY. Providing Static Timing Anlaysis Support for an ARM7 Processor Platform. [Thesis]. North Carolina State University; 2008. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1546

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Southern California

19. Joshi, Prasad. Static timing analysis of GasP.

Degree: MS, Electrical Engineering, 2008, University of Southern California

 The 6-4 GasP family of asynchronous circuits has been sought for its potential advantages of ultra-high performance and low power especially in the processor and… (more)

Subjects/Keywords: GasP; static timing analysis; asynchronous; STA

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APA (6th Edition):

Joshi, P. (2008). Static timing analysis of GasP. (Masters Thesis). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/128888/rec/6045

Chicago Manual of Style (16th Edition):

Joshi, Prasad. “Static timing analysis of GasP.” 2008. Masters Thesis, University of Southern California. Accessed April 01, 2020. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/128888/rec/6045.

MLA Handbook (7th Edition):

Joshi, Prasad. “Static timing analysis of GasP.” 2008. Web. 01 Apr 2020.

Vancouver:

Joshi P. Static timing analysis of GasP. [Internet] [Masters thesis]. University of Southern California; 2008. [cited 2020 Apr 01]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/128888/rec/6045.

Council of Science Editors:

Joshi P. Static timing analysis of GasP. [Masters Thesis]. University of Southern California; 2008. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/128888/rec/6045

20. Rogachev, Artem. Evaluating the effect of process variation on silicon and graphene nano-ribbon based circuits.

Degree: MS, 1200, 2012, University of Illinois – Urbana-Champaign

 With technology scaling, the variability of device parameters continues to increase. Both performance and power consumption are quite sensitive to process parameters (PP) such as… (more)

Subjects/Keywords: Compact Modeling; Graphene Nano Ribbons; Statistical Static Timing Analysis; Process Variations; Thermal

statistical static timing analysis (SSTA) and the MC simulation. Lu characterized the… …CHAPTER 2 TEMPERATURE-AWARE STATISTICAL STATIC TIMING ANALYSIS This work was a joint effort with… …temperature during timing analysis, most of the existing SSTA works do not take this into… …and supply variations during timing analysis. The authors of [8] obtain the… …first calculating the statistical thermal profile and then performing statistical timing… 

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APA (6th Edition):

Rogachev, A. (2012). Evaluating the effect of process variation on silicon and graphene nano-ribbon based circuits. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/32079

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rogachev, Artem. “Evaluating the effect of process variation on silicon and graphene nano-ribbon based circuits.” 2012. Thesis, University of Illinois – Urbana-Champaign. Accessed April 01, 2020. http://hdl.handle.net/2142/32079.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rogachev, Artem. “Evaluating the effect of process variation on silicon and graphene nano-ribbon based circuits.” 2012. Web. 01 Apr 2020.

Vancouver:

Rogachev A. Evaluating the effect of process variation on silicon and graphene nano-ribbon based circuits. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2012. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/2142/32079.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rogachev A. Evaluating the effect of process variation on silicon and graphene nano-ribbon based circuits. [Thesis]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/32079

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Aftabjahani, Seyed-Abdollah. Compact variation-aware standard cells for statistical static timing analysis.

Degree: PhD, Electrical and Computer Engineering, 2011, Georgia Tech

 This dissertation reports on a new methodology to characterize and simulate a standard cell library to be used for statistical static timing analysis. A compact… (more)

Subjects/Keywords: Variation-aware standard cell modeling; Process and environmental variation; Variation-aware waveform modeling; Statistical static timing analysis; Static timing analysis; Integrated circuits; Microelectronics; Standard cells

…Exchange Format SSM Symetric Standardized Model SSTA Statistical Static Timing Analysis STA… …variation, we need to perform statistical static timing analysis (SSTA) at corners that… …library to be used for statistical static timing analysis. A compact variation-aware timing… …summary of the main contributions of this work to the statistical static timing analysis: (… …statistical static timing analysis authored by Dr. David Blaauw et al. [1] and Dr… 

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APA (6th Edition):

Aftabjahani, S. (2011). Compact variation-aware standard cells for statistical static timing analysis. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/41129

Chicago Manual of Style (16th Edition):

Aftabjahani, Seyed-Abdollah. “Compact variation-aware standard cells for statistical static timing analysis.” 2011. Doctoral Dissertation, Georgia Tech. Accessed April 01, 2020. http://hdl.handle.net/1853/41129.

MLA Handbook (7th Edition):

Aftabjahani, Seyed-Abdollah. “Compact variation-aware standard cells for statistical static timing analysis.” 2011. Web. 01 Apr 2020.

Vancouver:

Aftabjahani S. Compact variation-aware standard cells for statistical static timing analysis. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1853/41129.

Council of Science Editors:

Aftabjahani S. Compact variation-aware standard cells for statistical static timing analysis. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/41129


University of Southern California

22. Hatami, Safar. Gate delay modeling and static timing analysis in ASIC designs considering process variations.

Degree: PhD, Electrical Engineering, 2011, University of Southern California

Static timing analysis (STA) is a key tool used for the design, optimization, and final sign-off of VLSI (Very Large Scale Integration) circuits. The down… (more)

Subjects/Keywords: VLSI; CSM; Statistical Timing Analysis; Current Source Modeling; Process Variation; Principal Component Analysis; PCA

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APA (6th Edition):

Hatami, S. (2011). Gate delay modeling and static timing analysis in ASIC designs considering process variations. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/658415/rec/2964

Chicago Manual of Style (16th Edition):

Hatami, Safar. “Gate delay modeling and static timing analysis in ASIC designs considering process variations.” 2011. Doctoral Dissertation, University of Southern California. Accessed April 01, 2020. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/658415/rec/2964.

MLA Handbook (7th Edition):

Hatami, Safar. “Gate delay modeling and static timing analysis in ASIC designs considering process variations.” 2011. Web. 01 Apr 2020.

Vancouver:

Hatami S. Gate delay modeling and static timing analysis in ASIC designs considering process variations. [Internet] [Doctoral dissertation]. University of Southern California; 2011. [cited 2020 Apr 01]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/658415/rec/2964.

Council of Science Editors:

Hatami S. Gate delay modeling and static timing analysis in ASIC designs considering process variations. [Doctoral Dissertation]. University of Southern California; 2011. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/658415/rec/2964


University of Cincinnati

23. WANG, CHIH-KUAN. AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER.

Degree: MS, Engineering : Computer Engineering, 2006, University of Cincinnati

 This thesis presents an iterative, crosstalk aware timing analyzer. Parameters such as slew rate, voltage supply, coupling capacitance, and load capacitance are shown to affect… (more)

Subjects/Keywords: crosstalk; capacitive crosstalk; dual-vdd; timing analysis; static timing analysis

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APA (6th Edition):

WANG, C. (2006). AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159253235

Chicago Manual of Style (16th Edition):

WANG, CHIH-KUAN. “AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER.” 2006. Masters Thesis, University of Cincinnati. Accessed April 01, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159253235.

MLA Handbook (7th Edition):

WANG, CHIH-KUAN. “AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER.” 2006. Web. 01 Apr 2020.

Vancouver:

WANG C. AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER. [Internet] [Masters thesis]. University of Cincinnati; 2006. [cited 2020 Apr 01]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159253235.

Council of Science Editors:

WANG C. AN ITERATIVE CROSSTALK AWARE TIMING ANALYZER. [Masters Thesis]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1159253235


NSYSU

24. Lin, Wen-yuan. The Maximize Asset Value for Optimal Decision-making.

Degree: PhD, Finance, 2014, NSYSU

 This dissertation addresses two topics on strategy, namely optimal capital structure and mortgage risk premium setting, and the optimal sale timing for developers. In Chapter… (more)

Subjects/Keywords: real option; comparative statistical analysis; optimal sale timing; mortgage risk premiums; loan-to-value

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APA (6th Edition):

Lin, W. (2014). The Maximize Asset Value for Optimal Decision-making. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-102749

Chicago Manual of Style (16th Edition):

Lin, Wen-yuan. “The Maximize Asset Value for Optimal Decision-making.” 2014. Doctoral Dissertation, NSYSU. Accessed April 01, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-102749.

MLA Handbook (7th Edition):

Lin, Wen-yuan. “The Maximize Asset Value for Optimal Decision-making.” 2014. Web. 01 Apr 2020.

Vancouver:

Lin W. The Maximize Asset Value for Optimal Decision-making. [Internet] [Doctoral dissertation]. NSYSU; 2014. [cited 2020 Apr 01]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-102749.

Council of Science Editors:

Lin W. The Maximize Asset Value for Optimal Decision-making. [Doctoral Dissertation]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0614114-102749


University of Michigan

25. Chopra, Kaviraj. Statistical Performance Analysis Optimization of Digital Circuits.

Degree: PhD, Computer Science & Engineering, 2008, University of Michigan

 Aggressive device scaling has made it imperative to account for process variations in the design flow. A robust model of process variations is an essential… (more)

Subjects/Keywords: Statistical Timing Analysis; Computer Science; Engineering

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APA (6th Edition):

Chopra, K. (2008). Statistical Performance Analysis Optimization of Digital Circuits. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/60747

Chicago Manual of Style (16th Edition):

Chopra, Kaviraj. “Statistical Performance Analysis Optimization of Digital Circuits.” 2008. Doctoral Dissertation, University of Michigan. Accessed April 01, 2020. http://hdl.handle.net/2027.42/60747.

MLA Handbook (7th Edition):

Chopra, Kaviraj. “Statistical Performance Analysis Optimization of Digital Circuits.” 2008. Web. 01 Apr 2020.

Vancouver:

Chopra K. Statistical Performance Analysis Optimization of Digital Circuits. [Internet] [Doctoral dissertation]. University of Michigan; 2008. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/2027.42/60747.

Council of Science Editors:

Chopra K. Statistical Performance Analysis Optimization of Digital Circuits. [Doctoral Dissertation]. University of Michigan; 2008. Available from: http://hdl.handle.net/2027.42/60747


University of Michigan

26. Thazhathu Veetil, Vineeth. Efficient Monte Carlo Based Methods for Variability Aware Analysis and Optimization of Digital Circuits.

Degree: PhD, Electrical Engineering, 2010, University of Michigan

 Process variability is of increasing concern in modern nanometer-scale CMOS. The suitability of Monte Carlo based algorithms for efficient analysis and optimization of digital circuits… (more)

Subjects/Keywords: Statistical Timing Analysis; Process Variability; Digital Circuits; Leakage Power; Monte Carlo; Electrical Engineering; Engineering

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APA (6th Edition):

Thazhathu Veetil, V. (2010). Efficient Monte Carlo Based Methods for Variability Aware Analysis and Optimization of Digital Circuits. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/78936

Chicago Manual of Style (16th Edition):

Thazhathu Veetil, Vineeth. “Efficient Monte Carlo Based Methods for Variability Aware Analysis and Optimization of Digital Circuits.” 2010. Doctoral Dissertation, University of Michigan. Accessed April 01, 2020. http://hdl.handle.net/2027.42/78936.

MLA Handbook (7th Edition):

Thazhathu Veetil, Vineeth. “Efficient Monte Carlo Based Methods for Variability Aware Analysis and Optimization of Digital Circuits.” 2010. Web. 01 Apr 2020.

Vancouver:

Thazhathu Veetil V. Efficient Monte Carlo Based Methods for Variability Aware Analysis and Optimization of Digital Circuits. [Internet] [Doctoral dissertation]. University of Michigan; 2010. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/2027.42/78936.

Council of Science Editors:

Thazhathu Veetil V. Efficient Monte Carlo Based Methods for Variability Aware Analysis and Optimization of Digital Circuits. [Doctoral Dissertation]. University of Michigan; 2010. Available from: http://hdl.handle.net/2027.42/78936


North Carolina State University

27. Ramaprasad, Harini. Analytical Bounding Data Cache Behavior for Real-Time Systems.

Degree: PhD, Computer Science, 2008, North Carolina State University

 This dissertation presents data cache analysis techniques that make it feasible to predict data cache behavior and to bound the worst-case execution time for a… (more)

Subjects/Keywords: WCET; data cache; static timing analysis; real-time

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ramaprasad, H. (2008). Analytical Bounding Data Cache Behavior for Real-Time Systems. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/4583

Chicago Manual of Style (16th Edition):

Ramaprasad, Harini. “Analytical Bounding Data Cache Behavior for Real-Time Systems.” 2008. Doctoral Dissertation, North Carolina State University. Accessed April 01, 2020. http://www.lib.ncsu.edu/resolver/1840.16/4583.

MLA Handbook (7th Edition):

Ramaprasad, Harini. “Analytical Bounding Data Cache Behavior for Real-Time Systems.” 2008. Web. 01 Apr 2020.

Vancouver:

Ramaprasad H. Analytical Bounding Data Cache Behavior for Real-Time Systems. [Internet] [Doctoral dissertation]. North Carolina State University; 2008. [cited 2020 Apr 01]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/4583.

Council of Science Editors:

Ramaprasad H. Analytical Bounding Data Cache Behavior for Real-Time Systems. [Doctoral Dissertation]. North Carolina State University; 2008. Available from: http://www.lib.ncsu.edu/resolver/1840.16/4583


North Carolina State University

28. Patil, Kaustubh Sambhaji. Compositional Static Cache Analysis Using Module-level Abstraction.

Degree: MS, Computer Science, 2003, North Carolina State University

Static cache analysis is utilized for timing analysis to derive worst-case execution time of a program. Such analysis is constrained by the requirement of an… (more)

Subjects/Keywords: compositional approach; timing analysis; static cache simulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Patil, K. S. (2003). Compositional Static Cache Analysis Using Module-level Abstraction. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/1445

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Patil, Kaustubh Sambhaji. “Compositional Static Cache Analysis Using Module-level Abstraction.” 2003. Thesis, North Carolina State University. Accessed April 01, 2020. http://www.lib.ncsu.edu/resolver/1840.16/1445.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Patil, Kaustubh Sambhaji. “Compositional Static Cache Analysis Using Module-level Abstraction.” 2003. Web. 01 Apr 2020.

Vancouver:

Patil KS. Compositional Static Cache Analysis Using Module-level Abstraction. [Internet] [Thesis]. North Carolina State University; 2003. [cited 2020 Apr 01]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1445.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Patil KS. Compositional Static Cache Analysis Using Module-level Abstraction. [Thesis]. North Carolina State University; 2003. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1445

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

29. Machado, Lucas. KL-cut based remapping.

Degree: 2013, Universidade do Rio Grande do Sul

This work introduces the concept of k-cuts and kl-cuts on top of a mapped circuit in a netlist representation. Such new approach is derived from… (more)

Subjects/Keywords: Digital circuits; Microeletrônica; Logic synthesis; Circuitos digitais; Technology mapping; Cut enumeration; Static timing analysis; Remapping; Lithography

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Machado, L. (2013). KL-cut based remapping. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/116138

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Machado, Lucas. “KL-cut based remapping.” 2013. Thesis, Universidade do Rio Grande do Sul. Accessed April 01, 2020. http://hdl.handle.net/10183/116138.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Machado, Lucas. “KL-cut based remapping.” 2013. Web. 01 Apr 2020.

Vancouver:

Machado L. KL-cut based remapping. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2013. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10183/116138.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Machado L. KL-cut based remapping. [Thesis]. Universidade do Rio Grande do Sul; 2013. Available from: http://hdl.handle.net/10183/116138

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

30. Choi, Munkang. Modeling of Deterministic Within-Die Variation in Timing Analysis, Leakage current Analysis, and Delay Fault Diagnosis.

Degree: PhD, Electrical and Computer Engineering, 2007, Georgia Tech

 As semiconductor technology advances into the nano-scale era and more functional blocks are added into systems on chip (SoC), the interface between circuit design and… (more)

Subjects/Keywords: DFM; Lithography; CMP; Within-die variation; Static timing analysis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Choi, M. (2007). Modeling of Deterministic Within-Die Variation in Timing Analysis, Leakage current Analysis, and Delay Fault Diagnosis. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/14544

Chicago Manual of Style (16th Edition):

Choi, Munkang. “Modeling of Deterministic Within-Die Variation in Timing Analysis, Leakage current Analysis, and Delay Fault Diagnosis.” 2007. Doctoral Dissertation, Georgia Tech. Accessed April 01, 2020. http://hdl.handle.net/1853/14544.

MLA Handbook (7th Edition):

Choi, Munkang. “Modeling of Deterministic Within-Die Variation in Timing Analysis, Leakage current Analysis, and Delay Fault Diagnosis.” 2007. Web. 01 Apr 2020.

Vancouver:

Choi M. Modeling of Deterministic Within-Die Variation in Timing Analysis, Leakage current Analysis, and Delay Fault Diagnosis. [Internet] [Doctoral dissertation]. Georgia Tech; 2007. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1853/14544.

Council of Science Editors:

Choi M. Modeling of Deterministic Within-Die Variation in Timing Analysis, Leakage current Analysis, and Delay Fault Diagnosis. [Doctoral Dissertation]. Georgia Tech; 2007. Available from: http://hdl.handle.net/1853/14544

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