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Indian Institute of Science

1.
Gopalakrishnan, K S.
Study On DC-Link Capacitor Current In A Three-Level Neutral-Point *Clamped* Inverter.

Degree: 2013, Indian Institute of Science

URL: http://etd.iisc.ernet.in/handle/2005/2628 ; http://etd.ncsi.iisc.ernet.in/abstracts/3382/G25997-Abs.pdf

Three-level diode-clamped inverter is being widely used these days. Extensive research has been carried out on pulse width modulation (PWM) strategies for a three-level inverter. The most widely used PWM strategies are sine-triangle pulse width modulation (SPWM) and centered space vector pulse width modulation (CSVPWM). The influence of these PWM strategies on the DC-link capacitor current and voltage ripple is studied in this thesis.
The sizing of the DC capacitor depends on value of the maximum RMS current flowing through it. In this work, an analytical expression for capacitor RMS current is derived as a function of operating conditions like modulation index, power factor angle of the load and peak load current. The worst case current stress on the capacitor is evaluated using the analytical expression. The capacitor RMS current is found to be the same in SPWM and CSVPWM schemes. The analytical expression is validated through simulations and experiments on a 3kVA MOSFET based three-level inverter.
Harmonic analysis of the capacitor current is helpful in better evaluation of capacitor power loss. Therefore, harmonic analysis of the capacitor current is carried out, using the techniques of geometric wall model and double Fourier integral for SPWM and CSVPWM schemes. The theoretical predictions are validated through experiments.
The capacitor RMS current is divided into low-frequency RMS current (where low frequency component is defined as a component whose frequency is less than half the switching frequency) and high-frequency RMS current. The capacitor voltage ripple is estimated analytically for SPWM and CSVPWM schemes, using the low-frequency and high-frequency capacitor RMS current. The voltage ripples due to SPWM and CSVPWM schemes are compared. It is found that the voltage ripple with SPWM is higher than that with CSVPWM. A simplified method to estimate the capacitor power loss, without the requirement of FFT analysis of capacitor current, is proposed. The results from this simplified method agree reasonably well with the results from the detailed method.
A space vector based modulation scheme is proposed, which reduces the capacitor RMS current at high power factor angles. However, the proposed method leads to higher total harmonic distortion (THD) than CSVPWM. Simulation and experimental results, comparing CSVPWM and the proposed PWM, are presented.
*Advisors/Committee Members: Narayanan, G.*

Subjects/Keywords: Voltage Source Inverters; Electrolytic Capacitors; Capacitor Current; Electric Inverters; Pulse Width Modulation (PWM); Dc-Link Capacitor Current; DC Electrolytic Capacitor; Space-Vector Pulse Width Modulation; Capacitor Power Loss; Capacitor Voltage Ripple; Capacitor RMS (Root Mean Square) Current; Centered Space Vector Pulse Width Modulation (CSVPWM); Diode Clamped Inverters; Sine-triangle Pulse Width Modulation (SPWM); RMS Current; Three-Level Diode-Clamped Inverters; Diode-clamped VSI; Power Electronics

Record Details Similar Records

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Gopalakrishnan, K. S. (2013). Study On DC-Link Capacitor Current In A Three-Level Neutral-Point Clamped Inverter. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2628 ; http://etd.ncsi.iisc.ernet.in/abstracts/3382/G25997-Abs.pdf

Note: this citation may be lacking information needed for this citation format:

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Gopalakrishnan, K S. “Study On DC-Link Capacitor Current In A Three-Level Neutral-Point Clamped Inverter.” 2013. Thesis, Indian Institute of Science. Accessed December 08, 2019. http://etd.iisc.ernet.in/handle/2005/2628 ; http://etd.ncsi.iisc.ernet.in/abstracts/3382/G25997-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Gopalakrishnan, K S. “Study On DC-Link Capacitor Current In A Three-Level Neutral-Point Clamped Inverter.” 2013. Web. 08 Dec 2019.

Vancouver:

Gopalakrishnan KS. Study On DC-Link Capacitor Current In A Three-Level Neutral-Point Clamped Inverter. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2019 Dec 08]. Available from: http://etd.iisc.ernet.in/handle/2005/2628 ; http://etd.ncsi.iisc.ernet.in/abstracts/3382/G25997-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gopalakrishnan KS. Study On DC-Link Capacitor Current In A Three-Level Neutral-Point Clamped Inverter. [Thesis]. Indian Institute of Science; 2013. Available from: http://etd.iisc.ernet.in/handle/2005/2628 ; http://etd.ncsi.iisc.ernet.in/abstracts/3382/G25997-Abs.pdf

Not specified: Masters Thesis or Doctoral Dissertation

Indian Institute of Science

2.
Gopalakrishnan, K S.
Study On DC-Link Capacitor Current In A Three-Level Neutral-Point *Clamped* Inverter.

Degree: 2013, Indian Institute of Science

URL: http://hdl.handle.net/2005/2628

Three-level diode-clamped inverter is being widely used these days. Extensive research has been carried out on pulse width modulation (PWM) strategies for a three-level inverter. The most widely used PWM strategies are sine-triangle pulse width modulation (SPWM) and centered space vector pulse width modulation (CSVPWM). The influence of these PWM strategies on the DC-link capacitor current and voltage ripple is studied in this thesis.
The sizing of the DC capacitor depends on value of the maximum RMS current flowing through it. In this work, an analytical expression for capacitor RMS current is derived as a function of operating conditions like modulation index, power factor angle of the load and peak load current. The worst case current stress on the capacitor is evaluated using the analytical expression. The capacitor RMS current is found to be the same in SPWM and CSVPWM schemes. The analytical expression is validated through simulations and experiments on a 3kVA MOSFET based three-level inverter.
Harmonic analysis of the capacitor current is helpful in better evaluation of capacitor power loss. Therefore, harmonic analysis of the capacitor current is carried out, using the techniques of geometric wall model and double Fourier integral for SPWM and CSVPWM schemes. The theoretical predictions are validated through experiments.
The capacitor RMS current is divided into low-frequency RMS current (where low frequency component is defined as a component whose frequency is less than half the switching frequency) and high-frequency RMS current. The capacitor voltage ripple is estimated analytically for SPWM and CSVPWM schemes, using the low-frequency and high-frequency capacitor RMS current. The voltage ripples due to SPWM and CSVPWM schemes are compared. It is found that the voltage ripple with SPWM is higher than that with CSVPWM. A simplified method to estimate the capacitor power loss, without the requirement of FFT analysis of capacitor current, is proposed. The results from this simplified method agree reasonably well with the results from the detailed method.
A space vector based modulation scheme is proposed, which reduces the capacitor RMS current at high power factor angles. However, the proposed method leads to higher total harmonic distortion (THD) than CSVPWM. Simulation and experimental results, comparing CSVPWM and the proposed PWM, are presented.
*Advisors/Committee Members: Narayanan, G.*

Subjects/Keywords: Voltage Source Inverters; Electrolytic Capacitors; Capacitor Current; Electric Inverters; Pulse Width Modulation (PWM); Dc-Link Capacitor Current; DC Electrolytic Capacitor; Space-Vector Pulse Width Modulation; Capacitor Power Loss; Capacitor Voltage Ripple; Capacitor RMS (Root Mean Square) Current; Centered Space Vector Pulse Width Modulation (CSVPWM); Diode Clamped Inverters; Sine-triangle Pulse Width Modulation (SPWM); RMS Current; Three-Level Diode-Clamped Inverters; Diode-clamped VSI; Power Electronics

Record Details Similar Records

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Gopalakrishnan, K. S. (2013). Study On DC-Link Capacitor Current In A Three-Level Neutral-Point Clamped Inverter. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2628

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Gopalakrishnan, K S. “Study On DC-Link Capacitor Current In A Three-Level Neutral-Point Clamped Inverter.” 2013. Thesis, Indian Institute of Science. Accessed December 08, 2019. http://hdl.handle.net/2005/2628.

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Gopalakrishnan, K S. “Study On DC-Link Capacitor Current In A Three-Level Neutral-Point Clamped Inverter.” 2013. Web. 08 Dec 2019.

Vancouver:

Gopalakrishnan KS. Study On DC-Link Capacitor Current In A Three-Level Neutral-Point Clamped Inverter. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2019 Dec 08]. Available from: http://hdl.handle.net/2005/2628.

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gopalakrishnan KS. Study On DC-Link Capacitor Current In A Three-Level Neutral-Point Clamped Inverter. [Thesis]. Indian Institute of Science; 2013. Available from: http://hdl.handle.net/2005/2628

Not specified: Masters Thesis or Doctoral Dissertation

Indian Institute of Science

3. Pappu, Roshan Kumar. Studies on Single DC Link Fed Multilevel Inverter Topologies by Cascading Flying Capacitor and Floating Capacitor Fed H-Bridges.

Degree: 2014, Indian Institute of Science

URL: http://hdl.handle.net/2005/3189

Use of multilevel inverters are inevitable in medium and high voltage drives. This is due to the fact that the multilevel inverters can produce voltages in smaller steps which will reduce the harmonic content and result in more sinusoidal voltages and currents as compared to voltages and currents from two-level inverters. Due to the device limitations, use of two-level inverters is not possible in medium and high voltage drive applications. Though multiple devices can be connected both in series and parallel to achieve two-level operation, the output voltages still suﬀer from high harmonic content. Multilevel inverters have multiple DC voltage levels with switches that enable one of the voltage steps to be applied to the load. Due to decrease in step size during each switching instant, output voltages and currents of the multilevel inverters have considerably less harmonic content. As the number of levels increase, the switching step reduces thereby the harmonic content also reduces drastically.
Due to their advantages, multilevel inverters have gained lot of acceptance in the industry even at lower voltages. The three main conﬁgurations that have gained popularity are the neutral point clamped converter, the ﬂying capacitor converter and the cascaded H-bridge converter. Each converter has its own set of advantages and disadvantages. Based on the requirements of various applications, it is possible to fabricate hybrid multilevel topologies that are combinations of the three basic topologies. Researchers around the world have proposed several such converters for diverse applications so as to suit particular requirements like modularity, ease of control, improved reliability, fault tolerant capability etc. The present thesis explores multilevel converters with single DC link to be used for motor drive and grid connected applications.
A novel ﬁve-level inverter topology formed by cascading a ﬂoating capacitor H-bridge module to a regular three-level ﬂying capacitor inverter has been explored in chapter 2. The three-level ﬂying capacitor inverter can generate pole voltages of 0, VDC /2 and VDC . By cascading it with another ﬂoating capacitor H-bridge of voltage magnitude VDC /4, pole voltages of 0, VDC /4, VDC/2, 3VDC /4 and VDC . Each of these pole voltage levels can have one or more switching combinations. However each switching combination has a unique eﬀect on the state of the two capacitor voltages. By switching through redundant switching combinations for the same pole voltage, the two capacitors present in each phase can be balanced. The proposed topology also has an advantage that if one of the devices in the H-bridge fails, the topology can still be operated as a regular three-level ﬂying capacitor inverter that can supply full load at rated power by bypassing the faulty H-bridge. This fault tolerant operation of the converter will enable it to be used in applications like traction and marine drives where high reliability is needed. The proposed converter needs a single DC link. All the required voltage levels…
*Advisors/Committee Members: Gopakumar, K.*

Subjects/Keywords: Electric Drives; High Voltage Drives; Multilevel Inverters; Multilevel Inverter Topology; Voltage Source Inverters; Pulse Width Modulation; Space Vector Width Modulation; Flying Capacitor Multilevel Inverters; Floating Capacitor Multilevel Inverters; Induction Motor Drives; Electric Inverters; Capacitors; Cascaded H-Bridges; Diode Clamped Multilevel Inverters; Power Converters; Space Vector PWM; Flying Capacitor Inverter; Cascaded H-Bridge; Electronic Systems Engineering

Record Details Similar Records

❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Pappu, R. K. (2014). Studies on Single DC Link Fed Multilevel Inverter Topologies by Cascading Flying Capacitor and Floating Capacitor Fed H-Bridges. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/3189

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Pappu, Roshan Kumar. “Studies on Single DC Link Fed Multilevel Inverter Topologies by Cascading Flying Capacitor and Floating Capacitor Fed H-Bridges.” 2014. Thesis, Indian Institute of Science. Accessed December 08, 2019. http://hdl.handle.net/2005/3189.

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Pappu, Roshan Kumar. “Studies on Single DC Link Fed Multilevel Inverter Topologies by Cascading Flying Capacitor and Floating Capacitor Fed H-Bridges.” 2014. Web. 08 Dec 2019.

Vancouver:

Pappu RK. Studies on Single DC Link Fed Multilevel Inverter Topologies by Cascading Flying Capacitor and Floating Capacitor Fed H-Bridges. [Internet] [Thesis]. Indian Institute of Science; 2014. [cited 2019 Dec 08]. Available from: http://hdl.handle.net/2005/3189.

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pappu RK. Studies on Single DC Link Fed Multilevel Inverter Topologies by Cascading Flying Capacitor and Floating Capacitor Fed H-Bridges. [Thesis]. Indian Institute of Science; 2014. Available from: http://hdl.handle.net/2005/3189

Not specified: Masters Thesis or Doctoral Dissertation