Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(Digital Integrated Circuits). Showing records 1 – 30 of 180 total matches.

[1] [2] [3] [4] [5] [6]

Search Limiters

Last 2 Years | English Only

Degrees

Levels

Country

▼ Search Limiters


Columbia University

1. Kim, Seongjong. Variation-Tolerant and Voltage-Scalable Integrated Circuits Design.

Degree: 2016, Columbia University

 Ultra-low-voltage (ULV) operation where the supply voltage of the digital computing hardware is scaled down to the level near or below transistor threshold voltage (e.g.… (more)

Subjects/Keywords: Integrated circuits – Design and construction; Electrical engineering; Digital integrated circuits; Digital integrated circuits – Design and construction; Integrated circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kim, S. (2016). Variation-Tolerant and Voltage-Scalable Integrated Circuits Design. (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/D8TM7BPF

Chicago Manual of Style (16th Edition):

Kim, Seongjong. “Variation-Tolerant and Voltage-Scalable Integrated Circuits Design.” 2016. Doctoral Dissertation, Columbia University. Accessed May 30, 2020. https://doi.org/10.7916/D8TM7BPF.

MLA Handbook (7th Edition):

Kim, Seongjong. “Variation-Tolerant and Voltage-Scalable Integrated Circuits Design.” 2016. Web. 30 May 2020.

Vancouver:

Kim S. Variation-Tolerant and Voltage-Scalable Integrated Circuits Design. [Internet] [Doctoral dissertation]. Columbia University; 2016. [cited 2020 May 30]. Available from: https://doi.org/10.7916/D8TM7BPF.

Council of Science Editors:

Kim S. Variation-Tolerant and Voltage-Scalable Integrated Circuits Design. [Doctoral Dissertation]. Columbia University; 2016. Available from: https://doi.org/10.7916/D8TM7BPF


University of Pretoria

2. Reddy, Reeshen. Spurious free dynamic range enhancement of high-speed integrated digital to analogue converters using bicmos technology.

Degree: MEng, Electrical, Electronic and Computer Engineering, 2015, University of Pretoria

 High-speed digital to analogue converters (DAC), which are optimised for large bandwidth signal synthesis applications, are a fundamental building block and enabling technology in industrial… (more)

Subjects/Keywords: Microelectronic; Digital-analogue conversion; BiCMOS integrated circuits; Dynamic range; Analogue-digital integrated circuits; Mixed analogue digital integrated circuits; UCTD

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Reddy, R. (2015). Spurious free dynamic range enhancement of high-speed integrated digital to analogue converters using bicmos technology. (Masters Thesis). University of Pretoria. Retrieved from http://hdl.handle.net/2263/48947

Chicago Manual of Style (16th Edition):

Reddy, Reeshen. “Spurious free dynamic range enhancement of high-speed integrated digital to analogue converters using bicmos technology.” 2015. Masters Thesis, University of Pretoria. Accessed May 30, 2020. http://hdl.handle.net/2263/48947.

MLA Handbook (7th Edition):

Reddy, Reeshen. “Spurious free dynamic range enhancement of high-speed integrated digital to analogue converters using bicmos technology.” 2015. Web. 30 May 2020.

Vancouver:

Reddy R. Spurious free dynamic range enhancement of high-speed integrated digital to analogue converters using bicmos technology. [Internet] [Masters thesis]. University of Pretoria; 2015. [cited 2020 May 30]. Available from: http://hdl.handle.net/2263/48947.

Council of Science Editors:

Reddy R. Spurious free dynamic range enhancement of high-speed integrated digital to analogue converters using bicmos technology. [Masters Thesis]. University of Pretoria; 2015. Available from: http://hdl.handle.net/2263/48947


University of Waterloo

3. Emtenan, Ariq. MachineFlow: A Web Tool to Adaptively Select EDA Tool Parameters for Digital ICs Using Statistical Learning.

Degree: 2016, University of Waterloo

Digital integrated circuits (ICs) are the driving force behind computing, communication and entertainment in today’s world. More powerful and energy efficient ICs continue to be… (more)

Subjects/Keywords: Digital integrated circuits; physical design; statistical learning

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Emtenan, A. (2016). MachineFlow: A Web Tool to Adaptively Select EDA Tool Parameters for Digital ICs Using Statistical Learning. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/11027

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Emtenan, Ariq. “MachineFlow: A Web Tool to Adaptively Select EDA Tool Parameters for Digital ICs Using Statistical Learning.” 2016. Thesis, University of Waterloo. Accessed May 30, 2020. http://hdl.handle.net/10012/11027.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Emtenan, Ariq. “MachineFlow: A Web Tool to Adaptively Select EDA Tool Parameters for Digital ICs Using Statistical Learning.” 2016. Web. 30 May 2020.

Vancouver:

Emtenan A. MachineFlow: A Web Tool to Adaptively Select EDA Tool Parameters for Digital ICs Using Statistical Learning. [Internet] [Thesis]. University of Waterloo; 2016. [cited 2020 May 30]. Available from: http://hdl.handle.net/10012/11027.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Emtenan A. MachineFlow: A Web Tool to Adaptively Select EDA Tool Parameters for Digital ICs Using Statistical Learning. [Thesis]. University of Waterloo; 2016. Available from: http://hdl.handle.net/10012/11027

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Limerick

4. Indino, Ivano. An open source platform and EDA tool framework to enable scan test power analysis testing.

Degree: 2017, University of Limerick

 Ivano Indino Scan testing has been the preferred method used for testing large digital integrated circuits for many decades and many electronic design automation (EDA)… (more)

Subjects/Keywords: scan testing; digital integrated circuits; OpenPiton project

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Indino, I. (2017). An open source platform and EDA tool framework to enable scan test power analysis testing. (Thesis). University of Limerick. Retrieved from http://hdl.handle.net/10344/6572

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Indino, Ivano. “An open source platform and EDA tool framework to enable scan test power analysis testing.” 2017. Thesis, University of Limerick. Accessed May 30, 2020. http://hdl.handle.net/10344/6572.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Indino, Ivano. “An open source platform and EDA tool framework to enable scan test power analysis testing.” 2017. Web. 30 May 2020.

Vancouver:

Indino I. An open source platform and EDA tool framework to enable scan test power analysis testing. [Internet] [Thesis]. University of Limerick; 2017. [cited 2020 May 30]. Available from: http://hdl.handle.net/10344/6572.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Indino I. An open source platform and EDA tool framework to enable scan test power analysis testing. [Thesis]. University of Limerick; 2017. Available from: http://hdl.handle.net/10344/6572

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Victoria

5. Byrne, Rodrigue. A high-level language and CAD environment for BIST embedding.

Degree: Department of Computer Science, 2018, University of Victoria

 The reliable construction of VLSI integrated circuits (ICs) requires that the ICs be tested after fabrication. An alternative to performing external testing is to create… (more)

Subjects/Keywords: Integrated circuits; Embedding theorems; Digital electronics; Computers; Circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Byrne, R. (2018). A high-level language and CAD environment for BIST embedding. (Thesis). University of Victoria. Retrieved from https://dspace.library.uvic.ca//handle/1828/9680

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Byrne, Rodrigue. “A high-level language and CAD environment for BIST embedding.” 2018. Thesis, University of Victoria. Accessed May 30, 2020. https://dspace.library.uvic.ca//handle/1828/9680.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Byrne, Rodrigue. “A high-level language and CAD environment for BIST embedding.” 2018. Web. 30 May 2020.

Vancouver:

Byrne R. A high-level language and CAD environment for BIST embedding. [Internet] [Thesis]. University of Victoria; 2018. [cited 2020 May 30]. Available from: https://dspace.library.uvic.ca//handle/1828/9680.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Byrne R. A high-level language and CAD environment for BIST embedding. [Thesis]. University of Victoria; 2018. Available from: https://dspace.library.uvic.ca//handle/1828/9680

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

6. Mettala Gilla, Swetha. Silicon Compilation and Test for Dataflow Implementations in GasP and Click.

Degree: PhD, Electrical and Computer Engineering, 2018, Portland State University

  Many modern computer systems are distributed over space. Well-known examples are the Internet of Things and IBM's TrueNorth for deep learning applications. At the… (more)

Subjects/Keywords: Data flow computing; Electrical engineering; Integrated circuits; Asynchronous circuits; Digital Circuits; Electrical and Computer Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mettala Gilla, S. (2018). Silicon Compilation and Test for Dataflow Implementations in GasP and Click. (Doctoral Dissertation). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/4237

Chicago Manual of Style (16th Edition):

Mettala Gilla, Swetha. “Silicon Compilation and Test for Dataflow Implementations in GasP and Click.” 2018. Doctoral Dissertation, Portland State University. Accessed May 30, 2020. https://pdxscholar.library.pdx.edu/open_access_etds/4237.

MLA Handbook (7th Edition):

Mettala Gilla, Swetha. “Silicon Compilation and Test for Dataflow Implementations in GasP and Click.” 2018. Web. 30 May 2020.

Vancouver:

Mettala Gilla S. Silicon Compilation and Test for Dataflow Implementations in GasP and Click. [Internet] [Doctoral dissertation]. Portland State University; 2018. [cited 2020 May 30]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/4237.

Council of Science Editors:

Mettala Gilla S. Silicon Compilation and Test for Dataflow Implementations in GasP and Click. [Doctoral Dissertation]. Portland State University; 2018. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/4237


University of Waterloo

7. Nabavi, Morteza. Subthreshold SRAM Design for Energy Efficient Applications in Nanometric CMOS Technologies.

Degree: 2018, University of Waterloo

 Embedded SRAM circuits are vital components in a modern system on chip (SOC) that can occupy up to 90% of the total area. Therefore, SRAM… (more)

Subjects/Keywords: Subthreshold; SRAM; Memories; Very Large Integrated Circuits (VLSI); Digital Circuits; Low Power; Low Energy

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nabavi, M. (2018). Subthreshold SRAM Design for Energy Efficient Applications in Nanometric CMOS Technologies. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/12931

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nabavi, Morteza. “Subthreshold SRAM Design for Energy Efficient Applications in Nanometric CMOS Technologies.” 2018. Thesis, University of Waterloo. Accessed May 30, 2020. http://hdl.handle.net/10012/12931.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nabavi, Morteza. “Subthreshold SRAM Design for Energy Efficient Applications in Nanometric CMOS Technologies.” 2018. Web. 30 May 2020.

Vancouver:

Nabavi M. Subthreshold SRAM Design for Energy Efficient Applications in Nanometric CMOS Technologies. [Internet] [Thesis]. University of Waterloo; 2018. [cited 2020 May 30]. Available from: http://hdl.handle.net/10012/12931.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nabavi M. Subthreshold SRAM Design for Energy Efficient Applications in Nanometric CMOS Technologies. [Thesis]. University of Waterloo; 2018. Available from: http://hdl.handle.net/10012/12931

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Carnegie Mellon University

8. Liu, Shaolong. SAR ADCs Design and Calibration in Nano-scaled Technologies.

Degree: 2017, Carnegie Mellon University

 The rapid progress of scaling and integration of modern complimentary metal oxide semiconductor (CMOS) technology motivates the replacement of traditional analog signal processing by digital(more)

Subjects/Keywords: ADC; analog-to-digital converter; Calibration; Integrated circuits; Low power; Offset

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, S. (2017). SAR ADCs Design and Calibration in Nano-scaled Technologies. (Thesis). Carnegie Mellon University. Retrieved from http://repository.cmu.edu/dissertations/1073

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Shaolong. “SAR ADCs Design and Calibration in Nano-scaled Technologies.” 2017. Thesis, Carnegie Mellon University. Accessed May 30, 2020. http://repository.cmu.edu/dissertations/1073.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Shaolong. “SAR ADCs Design and Calibration in Nano-scaled Technologies.” 2017. Web. 30 May 2020.

Vancouver:

Liu S. SAR ADCs Design and Calibration in Nano-scaled Technologies. [Internet] [Thesis]. Carnegie Mellon University; 2017. [cited 2020 May 30]. Available from: http://repository.cmu.edu/dissertations/1073.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu S. SAR ADCs Design and Calibration in Nano-scaled Technologies. [Thesis]. Carnegie Mellon University; 2017. Available from: http://repository.cmu.edu/dissertations/1073

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Columbia University

9. Chen, Yu. Digital Signal Processing with Signal-Derived Timing: Analysis and Implementation.

Degree: 2017, Columbia University

 This work investigates two different digital signal processing (DSP) approaches that rely on signal-derived timing: continuous-time (CT) DSP and variable-rate DSP. Both approaches enable designs… (more)

Subjects/Keywords: Integrated circuits; Signal processing – Digital techniques; Continuous-time filters; Electrical engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, Y. (2017). Digital Signal Processing with Signal-Derived Timing: Analysis and Implementation. (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/D8PR81KW

Chicago Manual of Style (16th Edition):

Chen, Yu. “Digital Signal Processing with Signal-Derived Timing: Analysis and Implementation.” 2017. Doctoral Dissertation, Columbia University. Accessed May 30, 2020. https://doi.org/10.7916/D8PR81KW.

MLA Handbook (7th Edition):

Chen, Yu. “Digital Signal Processing with Signal-Derived Timing: Analysis and Implementation.” 2017. Web. 30 May 2020.

Vancouver:

Chen Y. Digital Signal Processing with Signal-Derived Timing: Analysis and Implementation. [Internet] [Doctoral dissertation]. Columbia University; 2017. [cited 2020 May 30]. Available from: https://doi.org/10.7916/D8PR81KW.

Council of Science Editors:

Chen Y. Digital Signal Processing with Signal-Derived Timing: Analysis and Implementation. [Doctoral Dissertation]. Columbia University; 2017. Available from: https://doi.org/10.7916/D8PR81KW


Northeastern University

10. Cho, Geunho. Modeling undeposited CNTs for high performance design and the evaluation of reliable CNTFET circuits.

Degree: PhD, Department of Electrical and Computer Engineering, 2012, Northeastern University

 The Carbon NanoTube Field Effect Transistor (CNTFET) is one of the most promising emerging technologies to extend and complement silicon MOSFET; this is due to… (more)

Subjects/Keywords: Carbon NanoTube Field Effect Transistorcircuits; integrated circuit; Computer Engineering; Digital Circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cho, G. (2012). Modeling undeposited CNTs for high performance design and the evaluation of reliable CNTFET circuits. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20002840

Chicago Manual of Style (16th Edition):

Cho, Geunho. “Modeling undeposited CNTs for high performance design and the evaluation of reliable CNTFET circuits.” 2012. Doctoral Dissertation, Northeastern University. Accessed May 30, 2020. http://hdl.handle.net/2047/d20002840.

MLA Handbook (7th Edition):

Cho, Geunho. “Modeling undeposited CNTs for high performance design and the evaluation of reliable CNTFET circuits.” 2012. Web. 30 May 2020.

Vancouver:

Cho G. Modeling undeposited CNTs for high performance design and the evaluation of reliable CNTFET circuits. [Internet] [Doctoral dissertation]. Northeastern University; 2012. [cited 2020 May 30]. Available from: http://hdl.handle.net/2047/d20002840.

Council of Science Editors:

Cho G. Modeling undeposited CNTs for high performance design and the evaluation of reliable CNTFET circuits. [Doctoral Dissertation]. Northeastern University; 2012. Available from: http://hdl.handle.net/2047/d20002840


University of Arizona

11. Patel, Mayank Raman. HARDWARE COMPILER DRIVEN HEURISTIC SEARCH FOR DIGITAL IC TEST SEQUENCES.

Degree: 1985, University of Arizona

Subjects/Keywords: Digital integrated circuits  – Testing.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Patel, M. R. (1985). HARDWARE COMPILER DRIVEN HEURISTIC SEARCH FOR DIGITAL IC TEST SEQUENCES. (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/275246

Chicago Manual of Style (16th Edition):

Patel, Mayank Raman. “HARDWARE COMPILER DRIVEN HEURISTIC SEARCH FOR DIGITAL IC TEST SEQUENCES. ” 1985. Masters Thesis, University of Arizona. Accessed May 30, 2020. http://hdl.handle.net/10150/275246.

MLA Handbook (7th Edition):

Patel, Mayank Raman. “HARDWARE COMPILER DRIVEN HEURISTIC SEARCH FOR DIGITAL IC TEST SEQUENCES. ” 1985. Web. 30 May 2020.

Vancouver:

Patel MR. HARDWARE COMPILER DRIVEN HEURISTIC SEARCH FOR DIGITAL IC TEST SEQUENCES. [Internet] [Masters thesis]. University of Arizona; 1985. [cited 2020 May 30]. Available from: http://hdl.handle.net/10150/275246.

Council of Science Editors:

Patel MR. HARDWARE COMPILER DRIVEN HEURISTIC SEARCH FOR DIGITAL IC TEST SEQUENCES. [Masters Thesis]. University of Arizona; 1985. Available from: http://hdl.handle.net/10150/275246


Queens University

12. Stewart, David. Digitally Assisted Radio-Frequency Integrated Circuits .

Degree: Electrical and Computer Engineering, 2013, Queens University

 In this thesis, three radio frequency integrated circuits (RFICs) were digitally assisted for varying signal power, frequency or both. Performance paramters were 'optimized' in the… (more)

Subjects/Keywords: Microwave; RF; Integrated Circuits; Digital Assist; Electrical Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Stewart, D. (2013). Digitally Assisted Radio-Frequency Integrated Circuits . (Thesis). Queens University. Retrieved from http://hdl.handle.net/1974/8135

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Stewart, David. “Digitally Assisted Radio-Frequency Integrated Circuits .” 2013. Thesis, Queens University. Accessed May 30, 2020. http://hdl.handle.net/1974/8135.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Stewart, David. “Digitally Assisted Radio-Frequency Integrated Circuits .” 2013. Web. 30 May 2020.

Vancouver:

Stewart D. Digitally Assisted Radio-Frequency Integrated Circuits . [Internet] [Thesis]. Queens University; 2013. [cited 2020 May 30]. Available from: http://hdl.handle.net/1974/8135.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Stewart D. Digitally Assisted Radio-Frequency Integrated Circuits . [Thesis]. Queens University; 2013. Available from: http://hdl.handle.net/1974/8135

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Queens University

13. Aytimur, Cenk. Design and Implementation of a Programmable Digital Pseudo-Random Bit Generator for Applications in Noise Radar .

Degree: Electrical and Computer Engineering, 2013, Queens University

 Noise radar systems have become more prevalent over the past couple of decades due to their superior performance over conventional continuous-wave and pulsed-wave radar systems… (more)

Subjects/Keywords: Pseudo-Random Bit Generator; Digital Systems; Noise Radar; Integrated Circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Aytimur, C. (2013). Design and Implementation of a Programmable Digital Pseudo-Random Bit Generator for Applications in Noise Radar . (Thesis). Queens University. Retrieved from http://hdl.handle.net/1974/8447

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Aytimur, Cenk. “Design and Implementation of a Programmable Digital Pseudo-Random Bit Generator for Applications in Noise Radar .” 2013. Thesis, Queens University. Accessed May 30, 2020. http://hdl.handle.net/1974/8447.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Aytimur, Cenk. “Design and Implementation of a Programmable Digital Pseudo-Random Bit Generator for Applications in Noise Radar .” 2013. Web. 30 May 2020.

Vancouver:

Aytimur C. Design and Implementation of a Programmable Digital Pseudo-Random Bit Generator for Applications in Noise Radar . [Internet] [Thesis]. Queens University; 2013. [cited 2020 May 30]. Available from: http://hdl.handle.net/1974/8447.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Aytimur C. Design and Implementation of a Programmable Digital Pseudo-Random Bit Generator for Applications in Noise Radar . [Thesis]. Queens University; 2013. Available from: http://hdl.handle.net/1974/8447

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Portland State University

14. Bilagi, Vedanth. Experimental Study Of Fault Cones And Fault Aliasing.

Degree: MS(M.S.) in Electrical and Computer Engineering, Electrical and Computer Engineering, 2012, Portland State University

  The test of digital integrated circuits compares the test pattern results for the device under test (DUT) to the expected test pattern results of… (more)

Subjects/Keywords: Fault aliasing; Fault cones; Triple modular redundancy; Digital integrated circuits  – Testing; Integrated circuits  – Fault tolerance; Redundancy (Engineering); Electrical and Computer Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bilagi, V. (2012). Experimental Study Of Fault Cones And Fault Aliasing. (Masters Thesis). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/64

Chicago Manual of Style (16th Edition):

Bilagi, Vedanth. “Experimental Study Of Fault Cones And Fault Aliasing.” 2012. Masters Thesis, Portland State University. Accessed May 30, 2020. https://pdxscholar.library.pdx.edu/open_access_etds/64.

MLA Handbook (7th Edition):

Bilagi, Vedanth. “Experimental Study Of Fault Cones And Fault Aliasing.” 2012. Web. 30 May 2020.

Vancouver:

Bilagi V. Experimental Study Of Fault Cones And Fault Aliasing. [Internet] [Masters thesis]. Portland State University; 2012. [cited 2020 May 30]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/64.

Council of Science Editors:

Bilagi V. Experimental Study Of Fault Cones And Fault Aliasing. [Masters Thesis]. Portland State University; 2012. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/64


Texas Tech University

15. Randhawa, Preet Singh. Digital logic testing and verification using ordered binary decision diagrams.

Degree: 1995, Texas Tech University

 Computer-Aided Design has become a major part of design and testing of digital circuits. Since CAD systems use Boolean expressions extensively for testing and verifying… (more)

Subjects/Keywords: Computer-aided design; Digital integrated circuits; Integrated circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Randhawa, P. S. (1995). Digital logic testing and verification using ordered binary decision diagrams. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/16048

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Randhawa, Preet Singh. “Digital logic testing and verification using ordered binary decision diagrams.” 1995. Thesis, Texas Tech University. Accessed May 30, 2020. http://hdl.handle.net/2346/16048.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Randhawa, Preet Singh. “Digital logic testing and verification using ordered binary decision diagrams.” 1995. Web. 30 May 2020.

Vancouver:

Randhawa PS. Digital logic testing and verification using ordered binary decision diagrams. [Internet] [Thesis]. Texas Tech University; 1995. [cited 2020 May 30]. Available from: http://hdl.handle.net/2346/16048.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Randhawa PS. Digital logic testing and verification using ordered binary decision diagrams. [Thesis]. Texas Tech University; 1995. Available from: http://hdl.handle.net/2346/16048

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

16. Parekh, Parth. All-digital ΔΣ time-to-digital converter with bi-directional gated delay line time integrator.

Degree: 2017, Ryerson University

 This report presents a low-power time integrator and its applications in an all-digital first-order ΔΣ time-to-digital converter (TDC). Time-to-Digital Converter (TDC) that map a time… (more)

Subjects/Keywords: Metal oxide semiconductors, Complementary.; Signal processing  – Digital techniques.; Analog-to-digital converters.; Integrated circuits.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Parekh, P. (2017). All-digital ΔΣ time-to-digital converter with bi-directional gated delay line time integrator. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A6877

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Parekh, Parth. “All-digital ΔΣ time-to-digital converter with bi-directional gated delay line time integrator.” 2017. Thesis, Ryerson University. Accessed May 30, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A6877.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Parekh, Parth. “All-digital ΔΣ time-to-digital converter with bi-directional gated delay line time integrator.” 2017. Web. 30 May 2020.

Vancouver:

Parekh P. All-digital ΔΣ time-to-digital converter with bi-directional gated delay line time integrator. [Internet] [Thesis]. Ryerson University; 2017. [cited 2020 May 30]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6877.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Parekh P. All-digital ΔΣ time-to-digital converter with bi-directional gated delay line time integrator. [Thesis]. Ryerson University; 2017. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6877

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Portland State University

17. Park, Hoon. Formal Modeling and Verification of Delay-Insensitive Circuits.

Degree: PhD, Electrical and Computer Engineering, 2015, Portland State University

  Einstein's relativity theory tells us that the notion of simultaneity can only be approximated for events distributed over space. As a result, the use… (more)

Subjects/Keywords: Asynchronous circuits  – Design and construction; Integrated circuits  – Very large scale integration  – Design and construction; Digital Circuits; Electrical and Computer Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Park, H. (2015). Formal Modeling and Verification of Delay-Insensitive Circuits. (Doctoral Dissertation). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/2639

Chicago Manual of Style (16th Edition):

Park, Hoon. “Formal Modeling and Verification of Delay-Insensitive Circuits.” 2015. Doctoral Dissertation, Portland State University. Accessed May 30, 2020. https://pdxscholar.library.pdx.edu/open_access_etds/2639.

MLA Handbook (7th Edition):

Park, Hoon. “Formal Modeling and Verification of Delay-Insensitive Circuits.” 2015. Web. 30 May 2020.

Vancouver:

Park H. Formal Modeling and Verification of Delay-Insensitive Circuits. [Internet] [Doctoral dissertation]. Portland State University; 2015. [cited 2020 May 30]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/2639.

Council of Science Editors:

Park H. Formal Modeling and Verification of Delay-Insensitive Circuits. [Doctoral Dissertation]. Portland State University; 2015. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/2639


University of Oulu

18. Korhonen, E. (Esa). On-chip testing of A/D and D/A converters:static linearity testing without statistically known stimulus.

Degree: 2010, University of Oulu

 Abstract The static linearity testing of analog-to-digital and digital-to-analog converters (ADCs and DACs) has traditionally required test instruments with higher linearity and resolution than that… (more)

Subjects/Keywords: algorithms; analog-digital conversion; built-in testing; digital-analog conversion; manufacturing testing; mixed analog-digital integrated circuits; self-testing

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Korhonen, E. (. (2010). On-chip testing of A/D and D/A converters:static linearity testing without statistically known stimulus. (Doctoral Dissertation). University of Oulu. Retrieved from http://urn.fi/urn:isbn:9789514263064

Chicago Manual of Style (16th Edition):

Korhonen, E (Esa). “On-chip testing of A/D and D/A converters:static linearity testing without statistically known stimulus.” 2010. Doctoral Dissertation, University of Oulu. Accessed May 30, 2020. http://urn.fi/urn:isbn:9789514263064.

MLA Handbook (7th Edition):

Korhonen, E (Esa). “On-chip testing of A/D and D/A converters:static linearity testing without statistically known stimulus.” 2010. Web. 30 May 2020.

Vancouver:

Korhonen E(. On-chip testing of A/D and D/A converters:static linearity testing without statistically known stimulus. [Internet] [Doctoral dissertation]. University of Oulu; 2010. [cited 2020 May 30]. Available from: http://urn.fi/urn:isbn:9789514263064.

Council of Science Editors:

Korhonen E(. On-chip testing of A/D and D/A converters:static linearity testing without statistically known stimulus. [Doctoral Dissertation]. University of Oulu; 2010. Available from: http://urn.fi/urn:isbn:9789514263064


Texas A&M University

19. Mukherjee, Parijat. Detection and Diagnosis of Out-of-Specification Failures in Mixed-Signal Circuits.

Degree: 2014, Texas A&M University

 Verifying whether a circuit meets its intended specifications, as well as diagnosing the circuits that do not, is indispensable at every stage of integrated circuit… (more)

Subjects/Keywords: Model checking; Integrated circuit testing; Integrated circuit yield; Yield estimation; Circuit optimization; Statistical analysis; Sampling methods; Monte carlo methods; Machine learning; Analog circuits; Mixed analog digital integrated circuits

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mukherjee, P. (2014). Detection and Diagnosis of Out-of-Specification Failures in Mixed-Signal Circuits. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/154004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mukherjee, Parijat. “Detection and Diagnosis of Out-of-Specification Failures in Mixed-Signal Circuits.” 2014. Thesis, Texas A&M University. Accessed May 30, 2020. http://hdl.handle.net/1969.1/154004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mukherjee, Parijat. “Detection and Diagnosis of Out-of-Specification Failures in Mixed-Signal Circuits.” 2014. Web. 30 May 2020.

Vancouver:

Mukherjee P. Detection and Diagnosis of Out-of-Specification Failures in Mixed-Signal Circuits. [Internet] [Thesis]. Texas A&M University; 2014. [cited 2020 May 30]. Available from: http://hdl.handle.net/1969.1/154004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mukherjee P. Detection and Diagnosis of Out-of-Specification Failures in Mixed-Signal Circuits. [Thesis]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/154004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Northeastern University

20. Zhu, Haiyang. Design techniques to improve noise and linearity of data converters.

Degree: PhD, Department of Electrical and Computer Engineering, 2016, Northeastern University

 The data converters including analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) act as interfaces between a DSP-based system and the physical analog world. They are… (more)

Subjects/Keywords: data converter; integrated circuit; linearity; noise; Analog-to-digital converters; Design and construction; Digital-to-analog converters; Design and construction; Switched capacitor circuits; Amplifiers (Electronics); Integrated circuits; Electronic noise

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhu, H. (2016). Design techniques to improve noise and linearity of data converters. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/D20214142

Chicago Manual of Style (16th Edition):

Zhu, Haiyang. “Design techniques to improve noise and linearity of data converters.” 2016. Doctoral Dissertation, Northeastern University. Accessed May 30, 2020. http://hdl.handle.net/2047/D20214142.

MLA Handbook (7th Edition):

Zhu, Haiyang. “Design techniques to improve noise and linearity of data converters.” 2016. Web. 30 May 2020.

Vancouver:

Zhu H. Design techniques to improve noise and linearity of data converters. [Internet] [Doctoral dissertation]. Northeastern University; 2016. [cited 2020 May 30]. Available from: http://hdl.handle.net/2047/D20214142.

Council of Science Editors:

Zhu H. Design techniques to improve noise and linearity of data converters. [Doctoral Dissertation]. Northeastern University; 2016. Available from: http://hdl.handle.net/2047/D20214142


Ryerson University

21. Pourdowlat, Pirouz. A hardware based technique to reduce the timing complexity of number factoring problem.

Degree: 2006, Ryerson University

 Most digital circuits which have been developed to implement algorithms, can benefit from an increase in clock speed, but do not completely map the problem… (more)

Subjects/Keywords: Digital integrated circuits  – Design and construction.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pourdowlat, P. (2006). A hardware based technique to reduce the timing complexity of number factoring problem. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A5177

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pourdowlat, Pirouz. “A hardware based technique to reduce the timing complexity of number factoring problem.” 2006. Thesis, Ryerson University. Accessed May 30, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A5177.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pourdowlat, Pirouz. “A hardware based technique to reduce the timing complexity of number factoring problem.” 2006. Web. 30 May 2020.

Vancouver:

Pourdowlat P. A hardware based technique to reduce the timing complexity of number factoring problem. [Internet] [Thesis]. Ryerson University; 2006. [cited 2020 May 30]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5177.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pourdowlat P. A hardware based technique to reduce the timing complexity of number factoring problem. [Thesis]. Ryerson University; 2006. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5177

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

22. Luong, Vincent. Implementation of Space Vector Pulse Width Modulation on System on Programmable Chip.

Degree: 2010, Ryerson University

 For years, DSP has been the dominant tool in implementing gate switching for power inverter. It is a powerful and reliable technology in carrying out… (more)

Subjects/Keywords: Electric current converters  – Design and construction; Embedded computer systems  – Testing.; Digital integrated circuits.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Luong, V. (2010). Implementation of Space Vector Pulse Width Modulation on System on Programmable Chip. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A6708

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Luong, Vincent. “Implementation of Space Vector Pulse Width Modulation on System on Programmable Chip.” 2010. Thesis, Ryerson University. Accessed May 30, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A6708.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Luong, Vincent. “Implementation of Space Vector Pulse Width Modulation on System on Programmable Chip.” 2010. Web. 30 May 2020.

Vancouver:

Luong V. Implementation of Space Vector Pulse Width Modulation on System on Programmable Chip. [Internet] [Thesis]. Ryerson University; 2010. [cited 2020 May 30]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6708.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Luong V. Implementation of Space Vector Pulse Width Modulation on System on Programmable Chip. [Thesis]. Ryerson University; 2010. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6708

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Columbia University

23. da Silva Cerqueira, Joao Pedro. Ultra-Low Leakage, Energy-Efficient Digital Integrated Circuit and System Design.

Degree: 2019, Columbia University

 The advances of the complementary metal-oxide-semiconductor (CMOS) technology manufacturing and design over the years have enabled a diverse range of applications across the power consumption,… (more)

Subjects/Keywords: Electrical engineering; Computer engineering; Computer science; Energy consumption; Digital integrated circuits – Design and construction

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

da Silva Cerqueira, J. P. (2019). Ultra-Low Leakage, Energy-Efficient Digital Integrated Circuit and System Design. (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/d8-2wxf-m411

Chicago Manual of Style (16th Edition):

da Silva Cerqueira, Joao Pedro. “Ultra-Low Leakage, Energy-Efficient Digital Integrated Circuit and System Design.” 2019. Doctoral Dissertation, Columbia University. Accessed May 30, 2020. https://doi.org/10.7916/d8-2wxf-m411.

MLA Handbook (7th Edition):

da Silva Cerqueira, Joao Pedro. “Ultra-Low Leakage, Energy-Efficient Digital Integrated Circuit and System Design.” 2019. Web. 30 May 2020.

Vancouver:

da Silva Cerqueira JP. Ultra-Low Leakage, Energy-Efficient Digital Integrated Circuit and System Design. [Internet] [Doctoral dissertation]. Columbia University; 2019. [cited 2020 May 30]. Available from: https://doi.org/10.7916/d8-2wxf-m411.

Council of Science Editors:

da Silva Cerqueira JP. Ultra-Low Leakage, Energy-Efficient Digital Integrated Circuit and System Design. [Doctoral Dissertation]. Columbia University; 2019. Available from: https://doi.org/10.7916/d8-2wxf-m411


University of Arizona

24. Burt, Roger William, 1932-. Optimum design and error analysis of digital integrators .

Degree: 1963, University of Arizona

Subjects/Keywords: Digital integrated circuits  – Design and construction.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Burt, Roger William, 1. (1963). Optimum design and error analysis of digital integrators . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/319721

Chicago Manual of Style (16th Edition):

Burt, Roger William, 1932-. “Optimum design and error analysis of digital integrators .” 1963. Masters Thesis, University of Arizona. Accessed May 30, 2020. http://hdl.handle.net/10150/319721.

MLA Handbook (7th Edition):

Burt, Roger William, 1932-. “Optimum design and error analysis of digital integrators .” 1963. Web. 30 May 2020.

Vancouver:

Burt, Roger William 1. Optimum design and error analysis of digital integrators . [Internet] [Masters thesis]. University of Arizona; 1963. [cited 2020 May 30]. Available from: http://hdl.handle.net/10150/319721.

Council of Science Editors:

Burt, Roger William 1. Optimum design and error analysis of digital integrators . [Masters Thesis]. University of Arizona; 1963. Available from: http://hdl.handle.net/10150/319721


University of Arkansas

25. Roark, Justin Thomas. Analysis of Parameter Tuning on Energy Efficiency in Asynchronous Circuits.

Degree: MSCmpE, 2013, University of Arkansas

  Power and energy consumption are the primary concern of the digital integrated circuit (IC) industry. Asynchronous logic, in the past several years, has increased… (more)

Subjects/Keywords: Applied sciences; asynchronous circuits; Energy efficiency; Integrated circuits; Multi-threshold null convention logic; Null convention logic; Digital Circuits; VLSI and Circuits, Embedded and Hardware Systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Roark, J. T. (2013). Analysis of Parameter Tuning on Energy Efficiency in Asynchronous Circuits. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/862

Chicago Manual of Style (16th Edition):

Roark, Justin Thomas. “Analysis of Parameter Tuning on Energy Efficiency in Asynchronous Circuits.” 2013. Masters Thesis, University of Arkansas. Accessed May 30, 2020. https://scholarworks.uark.edu/etd/862.

MLA Handbook (7th Edition):

Roark, Justin Thomas. “Analysis of Parameter Tuning on Energy Efficiency in Asynchronous Circuits.” 2013. Web. 30 May 2020.

Vancouver:

Roark JT. Analysis of Parameter Tuning on Energy Efficiency in Asynchronous Circuits. [Internet] [Masters thesis]. University of Arkansas; 2013. [cited 2020 May 30]. Available from: https://scholarworks.uark.edu/etd/862.

Council of Science Editors:

Roark JT. Analysis of Parameter Tuning on Energy Efficiency in Asynchronous Circuits. [Masters Thesis]. University of Arkansas; 2013. Available from: https://scholarworks.uark.edu/etd/862


Delft University of Technology

26. Mahmoud, K.E.M. Non-Linear A/D Converters for Integrated Silicon Smart Sensors.

Degree: 1994, Delft University of Technology

Subjects/Keywords: analogue-digital conversion; bipolar integrated circuits; integrated smart sensors

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mahmoud, K. E. M. (1994). Non-Linear A/D Converters for Integrated Silicon Smart Sensors. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:4e51048c-9520-4f46-992b-5260dee0ee01 ; urn:NBN:nl:ui:24-uuid:4e51048c-9520-4f46-992b-5260dee0ee01 ; urn:NBN:nl:ui:24-uuid:4e51048c-9520-4f46-992b-5260dee0ee01 ; http://resolver.tudelft.nl/uuid:4e51048c-9520-4f46-992b-5260dee0ee01

Chicago Manual of Style (16th Edition):

Mahmoud, K E M. “Non-Linear A/D Converters for Integrated Silicon Smart Sensors.” 1994. Doctoral Dissertation, Delft University of Technology. Accessed May 30, 2020. http://resolver.tudelft.nl/uuid:4e51048c-9520-4f46-992b-5260dee0ee01 ; urn:NBN:nl:ui:24-uuid:4e51048c-9520-4f46-992b-5260dee0ee01 ; urn:NBN:nl:ui:24-uuid:4e51048c-9520-4f46-992b-5260dee0ee01 ; http://resolver.tudelft.nl/uuid:4e51048c-9520-4f46-992b-5260dee0ee01.

MLA Handbook (7th Edition):

Mahmoud, K E M. “Non-Linear A/D Converters for Integrated Silicon Smart Sensors.” 1994. Web. 30 May 2020.

Vancouver:

Mahmoud KEM. Non-Linear A/D Converters for Integrated Silicon Smart Sensors. [Internet] [Doctoral dissertation]. Delft University of Technology; 1994. [cited 2020 May 30]. Available from: http://resolver.tudelft.nl/uuid:4e51048c-9520-4f46-992b-5260dee0ee01 ; urn:NBN:nl:ui:24-uuid:4e51048c-9520-4f46-992b-5260dee0ee01 ; urn:NBN:nl:ui:24-uuid:4e51048c-9520-4f46-992b-5260dee0ee01 ; http://resolver.tudelft.nl/uuid:4e51048c-9520-4f46-992b-5260dee0ee01.

Council of Science Editors:

Mahmoud KEM. Non-Linear A/D Converters for Integrated Silicon Smart Sensors. [Doctoral Dissertation]. Delft University of Technology; 1994. Available from: http://resolver.tudelft.nl/uuid:4e51048c-9520-4f46-992b-5260dee0ee01 ; urn:NBN:nl:ui:24-uuid:4e51048c-9520-4f46-992b-5260dee0ee01 ; urn:NBN:nl:ui:24-uuid:4e51048c-9520-4f46-992b-5260dee0ee01 ; http://resolver.tudelft.nl/uuid:4e51048c-9520-4f46-992b-5260dee0ee01


Texas Tech University

27. Yilmaz, Abdullah. Switched-current analog-to-digital conversion techniques.

Degree: Electrical and Computer Engineering, 1995, Texas Tech University

Subjects/Keywords: Integrated circuits; Analog-to-digital converters; Digital electronics

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yilmaz, A. (1995). Switched-current analog-to-digital conversion techniques. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/21922

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yilmaz, Abdullah. “Switched-current analog-to-digital conversion techniques.” 1995. Thesis, Texas Tech University. Accessed May 30, 2020. http://hdl.handle.net/2346/21922.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yilmaz, Abdullah. “Switched-current analog-to-digital conversion techniques.” 1995. Web. 30 May 2020.

Vancouver:

Yilmaz A. Switched-current analog-to-digital conversion techniques. [Internet] [Thesis]. Texas Tech University; 1995. [cited 2020 May 30]. Available from: http://hdl.handle.net/2346/21922.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yilmaz A. Switched-current analog-to-digital conversion techniques. [Thesis]. Texas Tech University; 1995. Available from: http://hdl.handle.net/2346/21922

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of North Texas

28. Battina, Brahmasree. An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design.

Degree: 2014, University of North Texas

Integrated Circuits (ICs) have a broad range of applications in healthcare, military, consumer electronics etc. The acronym VLSI stands for Very Large Scale Integration and… (more)

Subjects/Keywords: interactive framework; digital logic design; VLSR Design; integrated circuits; Digital integrated circuits  – Design and construction  – Study and teaching.; Integrated circuits  – Very large scale integration  – Design and construction  – Study and teaching.; Logic design  – Study and teaching.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Battina, B. (2014). An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc799495/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Battina, Brahmasree. “An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design.” 2014. Thesis, University of North Texas. Accessed May 30, 2020. https://digital.library.unt.edu/ark:/67531/metadc799495/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Battina, Brahmasree. “An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design.” 2014. Web. 30 May 2020.

Vancouver:

Battina B. An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design. [Internet] [Thesis]. University of North Texas; 2014. [cited 2020 May 30]. Available from: https://digital.library.unt.edu/ark:/67531/metadc799495/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Battina B. An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design. [Thesis]. University of North Texas; 2014. Available from: https://digital.library.unt.edu/ark:/67531/metadc799495/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

29. Lim, Charles. Digital integrated circuit design : "ASIC implementation of an adaptive digital predistorter for lasers on ROF.

Degree: 2006, Ryerson University

 Radio over fiber has become one of the most useful technologies for providing extended coverage of wireless communications services. ROF uses analog fiber optic links… (more)

Subjects/Keywords: Digital integrated circuits  – Design and construction; Application-specific integrated circuits  – Design and construction

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lim, C. (2006). Digital integrated circuit design : "ASIC implementation of an adaptive digital predistorter for lasers on ROF. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A5162

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lim, Charles. “Digital integrated circuit design : "ASIC implementation of an adaptive digital predistorter for lasers on ROF.” 2006. Thesis, Ryerson University. Accessed May 30, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A5162.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lim, Charles. “Digital integrated circuit design : "ASIC implementation of an adaptive digital predistorter for lasers on ROF.” 2006. Web. 30 May 2020.

Vancouver:

Lim C. Digital integrated circuit design : "ASIC implementation of an adaptive digital predistorter for lasers on ROF. [Internet] [Thesis]. Ryerson University; 2006. [cited 2020 May 30]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5162.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lim C. Digital integrated circuit design : "ASIC implementation of an adaptive digital predistorter for lasers on ROF. [Thesis]. Ryerson University; 2006. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5162

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

30. Teng, Ying. Low Power Resonant Rotary Global Clock Distribution Network Design.

Degree: 2014, Drexel University

Along with the increasing complexity of the modern very large scale integrated (VLSI) circuit design, the power consumption of the clock distribution network in digital(more)

Subjects/Keywords: Electrical engineering; Integrated circuits – Large scale integration; Digital integrated circuits

…distribution network in digital integrated circuits is continuously increasing. In terms of power and… …recovery circuits to convert the sinusoid signals to digital levels in order to be used as the… …16 2.8 Recover circuits for standing wave oscillators… …scale integrated (VLSI) circuit design, the power consumption of the clock… …performance synchronous VLSI circuits. This dissertation work aims to develop the global clock… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Teng, Y. (2014). Low Power Resonant Rotary Global Clock Distribution Network Design. (Thesis). Drexel University. Retrieved from http://hdl.handle.net/1860/4573

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Teng, Ying. “Low Power Resonant Rotary Global Clock Distribution Network Design.” 2014. Thesis, Drexel University. Accessed May 30, 2020. http://hdl.handle.net/1860/4573.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Teng, Ying. “Low Power Resonant Rotary Global Clock Distribution Network Design.” 2014. Web. 30 May 2020.

Vancouver:

Teng Y. Low Power Resonant Rotary Global Clock Distribution Network Design. [Internet] [Thesis]. Drexel University; 2014. [cited 2020 May 30]. Available from: http://hdl.handle.net/1860/4573.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Teng Y. Low Power Resonant Rotary Global Clock Distribution Network Design. [Thesis]. Drexel University; 2014. Available from: http://hdl.handle.net/1860/4573

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2] [3] [4] [5] [6]

.