subject:(Detection latency)

Virginia Tech

1. Schroeder, Betsy. Finding Typhoid Mary: Identifying Latent Carriers of Salmonella enterica serovar Typhimurium.

Degree: PhD, Biomedical and Veterinary Sciences, 2020, Virginia Tech

► Salmonella enterica serovar Typhimurium (S. Typhimurium) is an important human pathogen. Determining the true number of cases of salmonellosis is made more difficult because of… (more)

Subjects/Keywords: Salmonella; latency; detection

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APA (6^th Edition):

Schroeder, B. (2020). Finding Typhoid Mary: Identifying Latent Carriers of Salmonella enterica serovar Typhimurium. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/99979

Chicago Manual of Style (16^th Edition):

Schroeder, Betsy. “Finding Typhoid Mary: Identifying Latent Carriers of Salmonella enterica serovar Typhimurium.” 2020. Doctoral Dissertation, Virginia Tech. Accessed March 02, 2021. http://hdl.handle.net/10919/99979.

MLA Handbook (7^th Edition):

Schroeder, Betsy. “Finding Typhoid Mary: Identifying Latent Carriers of Salmonella enterica serovar Typhimurium.” 2020. Web. 02 Mar 2021.

Vancouver:

Schroeder B. Finding Typhoid Mary: Identifying Latent Carriers of Salmonella enterica serovar Typhimurium. [Internet] [Doctoral dissertation]. Virginia Tech; 2020. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/10919/99979.

Council of Science Editors:

Schroeder B. Finding Typhoid Mary: Identifying Latent Carriers of Salmonella enterica serovar Typhimurium. [Doctoral Dissertation]. Virginia Tech; 2020. Available from: http://hdl.handle.net/10919/99979

University of Waikato

2. Mungro, Meenakshee. Rating the Significance of Detected Network Events .

Degree: 2014, University of Waikato

URL: http://hdl.handle.net/10289/8808

► Existing anomaly detection systems do not reliably produce accurate severity ratings for detected network events, which results in network operators wasting a large amount of… (more)

Subjects/Keywords: Data fusion; Anomaly detection; Network latency

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APA (6^th Edition):

Mungro, M. (2014). Rating the Significance of Detected Network Events . (Masters Thesis). University of Waikato. Retrieved from http://hdl.handle.net/10289/8808

Chicago Manual of Style (16^th Edition):

Mungro, Meenakshee. “Rating the Significance of Detected Network Events .” 2014. Masters Thesis, University of Waikato. Accessed March 02, 2021. http://hdl.handle.net/10289/8808.

MLA Handbook (7^th Edition):

Mungro, Meenakshee. “Rating the Significance of Detected Network Events .” 2014. Web. 02 Mar 2021.

Vancouver:

Mungro M. Rating the Significance of Detected Network Events . [Internet] [Masters thesis]. University of Waikato; 2014. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/10289/8808.

Council of Science Editors:

Mungro M. Rating the Significance of Detected Network Events . [Masters Thesis]. University of Waikato; 2014. Available from: http://hdl.handle.net/10289/8808

University of Washington

3. Wu, Yifan. Improvement of Vibration and End-to-End Latency for Optical Motion Detection System in Magnetic Resonance Imaging.

Degree: 2017, University of Washington

URL: http://hdl.handle.net/1773/39950

► This dissertation presents improvements to both software and hardware for a marker-less optical motion detection system used in magnetic resonance imaging. Multiple devices have been… (more)

▼ This dissertation presents improvements to both software and hardware for a marker-less optical motion detection system used in magnetic resonance imaging. Multiple devices have been developed to eliminate artifacts in MRI caused by patient movement, as motion is a common cause of artifact. Most developed devices require attaching pieces to a subject’s body; however, our optical motion detection system is attachment-free. Previously, we successfully reduced imaging artifacts retrospectively using carotid artery MR data. We used gathered motion data to determine beginning and ending times of the movement, then discarded the corresponding k-space lines within the movement duration to eliminate artifacts. Now we would like to push this process from retrospective correction to real time. However, the camera and laser mounting vibration, as well as the system time delay variation, generate inaccuracies which make it difficult to find the exact k-space lines to be removed. To make the artifact-eliminating process more efficient, we reduced the overall end-to-end latency from 110ms  21ms to 100ms  12ms by coding the motion processing program in Python with OpenCV library. We also designed a new laser and camera holder using 3D printing with PLA for better stability. The noise and drift in both x and y directions are decreased with the new holder compared to the previous setup. The same result for decrease in vibration was seen during phantom scanning with T1-weighted (TR = 100ms) gradient echo (GRE) and with T1-weighted turbo spin-echo (TSE) quadruple inversion-recovery (QIR) (TR = 800ms) sequence. Furthermore, the 3D printed holder decreases the overall assembly time required to set up the system. Overall, the new design of the system reduces the event-to-display latency, the latency variation, the hardware vibration, and the assembly time. The new design improves the old design and provides a path to pursue prospective optical motion correction. Advisors/Committee Members: Yuan, Chun (advisor).

Subjects/Keywords: 3D Printing; Delay; Latency; Motion Detection; MRI; Vibration; Biomedical engineering; Mechanical engineering; Medical imaging; Bioengineering

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APA (6^th Edition):

Wu, Y. (2017). Improvement of Vibration and End-to-End Latency for Optical Motion Detection System in Magnetic Resonance Imaging. (Thesis). University of Washington. Retrieved from http://hdl.handle.net/1773/39950

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wu, Yifan. “Improvement of Vibration and End-to-End Latency for Optical Motion Detection System in Magnetic Resonance Imaging.” 2017. Thesis, University of Washington. Accessed March 02, 2021. http://hdl.handle.net/1773/39950.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wu, Yifan. “Improvement of Vibration and End-to-End Latency for Optical Motion Detection System in Magnetic Resonance Imaging.” 2017. Web. 02 Mar 2021.

Vancouver:

Wu Y. Improvement of Vibration and End-to-End Latency for Optical Motion Detection System in Magnetic Resonance Imaging. [Internet] [Thesis]. University of Washington; 2017. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/1773/39950.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu Y. Improvement of Vibration and End-to-End Latency for Optical Motion Detection System in Magnetic Resonance Imaging. [Thesis]. University of Washington; 2017. Available from: http://hdl.handle.net/1773/39950

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Arkansas

4. Akingeneye, Israel Zairi. Low Latency Intrusion Detection in Smart Grids.

Degree: PhD, 2018, University of Arkansas

URL: https://scholarworks.uark.edu/etd/2740

► The transformation of traditional power grids into smart grids has seen more new technologies such as communication networks and smart meters (sensors) being integrated… (more)

Subjects/Keywords: Cybersecurity; Low Latency Detection; Power System; Smart Grid; Information Security; VLSI and Circuits, Embedded and Hardware Systems

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APA (6^th Edition):

Akingeneye, I. Z. (2018). Low Latency Intrusion Detection in Smart Grids. (Doctoral Dissertation). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/2740

Chicago Manual of Style (16^th Edition):

Akingeneye, Israel Zairi. “Low Latency Intrusion Detection in Smart Grids.” 2018. Doctoral Dissertation, University of Arkansas. Accessed March 02, 2021. https://scholarworks.uark.edu/etd/2740.

MLA Handbook (7^th Edition):

Akingeneye, Israel Zairi. “Low Latency Intrusion Detection in Smart Grids.” 2018. Web. 02 Mar 2021.

Vancouver:

Akingeneye IZ. Low Latency Intrusion Detection in Smart Grids. [Internet] [Doctoral dissertation]. University of Arkansas; 2018. [cited 2021 Mar 02]. Available from: https://scholarworks.uark.edu/etd/2740.

Council of Science Editors:

Akingeneye IZ. Low Latency Intrusion Detection in Smart Grids. [Doctoral Dissertation]. University of Arkansas; 2018. Available from: https://scholarworks.uark.edu/etd/2740

University of Georgia

5. Zheng, Nibiao. Mathematical studies of persistence and cost effectiveness of active case finding of tuberculosis.

Degree: 2014, University of Georgia

URL: http://hdl.handle.net/10724/30277

► Tuberculosis (TB) has been a human infectious disease for a long time. Yet, there are currently 2 billion persons infected with TB in the world.… (more)

Subjects/Keywords: Tuberculosis; HIV; Persistence; Latency; Active Case Finding (ACF); Passive Case Finding (PCF); TB Detection; Cost-effectiveness; Mathematical model; Modeling

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APA (6^th Edition):

Zheng, N. (2014). Mathematical studies of persistence and cost effectiveness of active case finding of tuberculosis. (Thesis). University of Georgia. Retrieved from http://hdl.handle.net/10724/30277

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Zheng, Nibiao. “Mathematical studies of persistence and cost effectiveness of active case finding of tuberculosis.” 2014. Thesis, University of Georgia. Accessed March 02, 2021. http://hdl.handle.net/10724/30277.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Zheng, Nibiao. “Mathematical studies of persistence and cost effectiveness of active case finding of tuberculosis.” 2014. Web. 02 Mar 2021.

Vancouver:

Zheng N. Mathematical studies of persistence and cost effectiveness of active case finding of tuberculosis. [Internet] [Thesis]. University of Georgia; 2014. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/10724/30277.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zheng N. Mathematical studies of persistence and cost effectiveness of active case finding of tuberculosis. [Thesis]. University of Georgia; 2014. Available from: http://hdl.handle.net/10724/30277

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Universidade do Rio Grande do Sul

6. Ferreira, Ronaldo Rodrigues. The transactional HW/SW stack for fault tolerant embedded computing.

Degree: 2015, Universidade do Rio Grande do Sul

URL: http://hdl.handle.net/10183/114607

►

Fault tolerance implementation in embedded systems is challenging because the physical constraints of area occupation, power dissipation, and energy consumption of these systems. The need… (more)

▼

Fault tolerance implementation in embedded systems is challenging because the physical constraints of area occupation, power dissipation, and energy consumption of these systems. The need for optimizing these three physical constraints while doing computation within the available performance goals and real-time deadlines creates a conundrum that is hard to solve. Classical fault tolerance solutions such as triple and dual modular redundancy are not feasible due to their high power overhead or lack of efficient and deterministic error recovery. Existing techniques, although some of them reduce the power and area overhead, incur heavy perfor- mance penalties and most of the time do not assume a feasible fault model. This dissertation introduces the Transactional HW/SW Stack, or simply Stack, to effi- ciently manage the area, power, fault coverage, and performance conundrum. The Stack introduces a new compilation strategy that assembles programs into Transac- tional Basic Blocks, together with a novel microprocessor, the TransactiOnal Basic Block Architecture (ToBBA), which provides fine-grained error detection and deter- ministic error rollback and elimination using the Transactional Basic Blocks (TBBs) both as a container for errors and as a small unit of data checkpointing. Two so- lutions to sustain the TBB semantics in hardware are introduced: software- and hardware-based. Stack’s area, power, performance, and coverage were evaluated using ToBBA’s hardware implementation model. The Stack attains an error correc- tion coverage of 99.35% with 2.05 power overhead within an area overhead of 2.65. The Stack also presents a performance overhead of 1.33 or 1.54, depending on the hardware model adopted to support the TBB.

O desafio de implementar tolerância a falhas em sistemas embarcados advém das restrições físicas de ocupação de área, dissipação de potência e consumo de energia desses sistemas. A necessidade de otimizar essas três restrições de projeto concomitante à computação dentro dos requisitos de desempenho e de tempo-real cria um problema difícil de ser resolvido. Soluções clássicas de tolerância a falhas tais como redundância modular dupla e tripla não são factíveis devido ao alto custo em potência e a falta de um mecanismo para se recuperar erros. Apesar de algumas técnicas existentes reduzirem o overhead de potência e área, essas incorrem em alta degradação de desempenho e muitas vezes assumem um modelo de falhas que não é factível. Essa tese introduz a Pilha de HW/SW Transacional, ou simplesmente Pilha, para gerenciar de maneira eficiente as restrições de área, potência, cobertura de falhas e desempenho. A Pilha introduz uma nova estratégia de compilação que organiza os programas em Blocos Básicos Transacionais (BBT), juntamente com um novo processador, a Arquitetura de Blocos Básicos Transacionais (ABBT), a qual provê detecção e recuperação de erros de grão fino e determinística ao usar o BBT como um contâiner de erros e como unidade de checkpointing. Duas soluções para prover a semântica de execução do…

Advisors/Committee Members: Carro, Luigi.

Subjects/Keywords: Compiler design; Microeletrônica; Coverage; Sistemas embarcados; Tolerancia : Falhas; Error detection; Error recovery; Fault injection; Hardening by design; Latency; LLVM; Modular redundancy; Register file; Rollback; Single event effects; Soft error

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APA (6^th Edition):

Ferreira, R. R. (2015). The transactional HW/SW stack for fault tolerant embedded computing. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/114607

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Ferreira, Ronaldo Rodrigues. “The transactional HW/SW stack for fault tolerant embedded computing.” 2015. Thesis, Universidade do Rio Grande do Sul. Accessed March 02, 2021. http://hdl.handle.net/10183/114607.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Ferreira, Ronaldo Rodrigues. “The transactional HW/SW stack for fault tolerant embedded computing.” 2015. Web. 02 Mar 2021.

Vancouver:

Ferreira RR. The transactional HW/SW stack for fault tolerant embedded computing. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2015. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/10183/114607.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ferreira RR. The transactional HW/SW stack for fault tolerant embedded computing. [Thesis]. Universidade do Rio Grande do Sul; 2015. Available from: http://hdl.handle.net/10183/114607

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Toronto

7. Kayili, Levent. Abnormal Group Delay and Detection Latency in the Presence of Noise for Communication Systems.

Degree: 2010, University of Toronto

URL: http://hdl.handle.net/1807/24255

►

Although it has been well established that abnormal group delay is a real physical phenomenon and is not in violation of Einstein causality, there has… (more)

Subjects/Keywords: electrical engineering; Einstein causality; causality; communication systems; abnormal group delay; abnormal group velocity; superluminal group delay; superluminal group velocity; time-varying error probability; signal latency; detection system; detection latency; pulse advancement; spatially extended systems; negative group delay; negative group velocity; spatially negligible systems; microwave circuits; microelectronic interconnects; channel; relativistic causality; electromagnetic; dispersion; physics; signals; 0544

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APA (6^th Edition):

Kayili, L. (2010). Abnormal Group Delay and Detection Latency in the Presence of Noise for Communication Systems. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/24255

Chicago Manual of Style (16^th Edition):

Kayili, Levent. “Abnormal Group Delay and Detection Latency in the Presence of Noise for Communication Systems.” 2010. Masters Thesis, University of Toronto. Accessed March 02, 2021. http://hdl.handle.net/1807/24255.

MLA Handbook (7^th Edition):

Kayili, Levent. “Abnormal Group Delay and Detection Latency in the Presence of Noise for Communication Systems.” 2010. Web. 02 Mar 2021.

Vancouver:

Kayili L. Abnormal Group Delay and Detection Latency in the Presence of Noise for Communication Systems. [Internet] [Masters thesis]. University of Toronto; 2010. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/1807/24255.

Council of Science Editors:

Kayili L. Abnormal Group Delay and Detection Latency in the Presence of Noise for Communication Systems. [Masters Thesis]. University of Toronto; 2010. Available from: http://hdl.handle.net/1807/24255

Universiteit Hasselt

8. OPDENAKKER, John. Collision Detection in CVEs.

Degree: 2005, Universiteit Hasselt

URL: http://hdl.handle.net/1942/1168

► Collaborative Virtual Environments (CVE's) zijn drie-dimensionale grafische werelden die er voor zorgen dat verscheidene geografisch verspreide gebruikers met elkaar kunnen communiceren door middel van een… (more)

Subjects/Keywords: Collision detection; polygonale modellen; broad phase collision detection; bounding volumes; binaire subruimtes; narrow phase collision detection; convexe objecten; polygon soups; MDK2; CVE; TCP; UDP; peer-to-peer; P2P; client-server topologie; broadcasting; multicasting; latency problemen; dead reckoning; implementatie; main loop; render loop

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APA (6^th Edition):

OPDENAKKER, J. (2005). Collision Detection in CVEs. (Thesis). Universiteit Hasselt. Retrieved from http://hdl.handle.net/1942/1168

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

OPDENAKKER, John. “Collision Detection in CVEs.” 2005. Thesis, Universiteit Hasselt. Accessed March 02, 2021. http://hdl.handle.net/1942/1168.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

OPDENAKKER, John. “Collision Detection in CVEs.” 2005. Web. 02 Mar 2021.

Vancouver:

OPDENAKKER J. Collision Detection in CVEs. [Internet] [Thesis]. Universiteit Hasselt; 2005. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/1942/1168.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

OPDENAKKER J. Collision Detection in CVEs. [Thesis]. Universiteit Hasselt; 2005. Available from: http://hdl.handle.net/1942/1168

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

9. Adams, Markus. Entwicklung eines Simulationsprogrammes für das Myon-Pretrigger-System des HERA-B-Experimentes und Untersuchungen zum Systemverhalten.

Degree: 2001, Universität Dortmund

URL: http://hdl.handle.net/2003/2366

►

Das HERA-B Experiment am Deutschen Elektronen-Synchrotron (DESY) in Hamburg wurde aufgebaut, um die CP-Verletzung im System der neutralen B-Mesonen zu untersuchen. Für diese und weitere… (more)

Subjects/Keywords: acceptance; Akzeptanz; efficiency; Effizienz; HERA-B; latency; Latenzzeit; multiplicity veto system; Multiplizitäts-Veto-System; muon detection; muon pretrigger; Myon; Myon-Pretrigger; performance study; Simulation; Trigger; Untersuchungen zum Systemverhalten; 530

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APA (6^th Edition):

Adams, M. (2001). Entwicklung eines Simulationsprogrammes für das Myon-Pretrigger-System des HERA-B-Experimentes und Untersuchungen zum Systemverhalten. (Thesis). Universität Dortmund. Retrieved from http://hdl.handle.net/2003/2366

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Adams, Markus. “Entwicklung eines Simulationsprogrammes für das Myon-Pretrigger-System des HERA-B-Experimentes und Untersuchungen zum Systemverhalten.” 2001. Thesis, Universität Dortmund. Accessed March 02, 2021. http://hdl.handle.net/2003/2366.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Adams, Markus. “Entwicklung eines Simulationsprogrammes für das Myon-Pretrigger-System des HERA-B-Experimentes und Untersuchungen zum Systemverhalten.” 2001. Web. 02 Mar 2021.

Vancouver:

Adams M. Entwicklung eines Simulationsprogrammes für das Myon-Pretrigger-System des HERA-B-Experimentes und Untersuchungen zum Systemverhalten. [Internet] [Thesis]. Universität Dortmund; 2001. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/2003/2366.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Adams M. Entwicklung eines Simulationsprogrammes für das Myon-Pretrigger-System des HERA-B-Experimentes und Untersuchungen zum Systemverhalten. [Thesis]. Universität Dortmund; 2001. Available from: http://hdl.handle.net/2003/2366

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

10. Adams, Markus. Entwicklung eines Simulationsprogrammes für das Myon-Pretrigger-System des HERA-B-Experimentes und Untersuchungen zum Systemverhalten.

Degree: 2002, Technische Universität Dortmund

URL: http://dx.doi.org/10.17877/DE290R-4991

► The HERA-B experiment was built up at the Deutsches Elektronen-Synchrotron (DESY) in Hamburg to study CP violation in the neutral B meson system. For this… (more)

Subjects/Keywords: acceptance; efficiency; latency; multiplicity veto system; muon detection; muon pretrigger; performance study; Akzeptanz; Effizienz; HERA-B; Latenzzeit; Multiplizitäts-Veto-System; Myon; Myon-Pretrigger; Simulation; Trigger; Untersuchungen zum Systemverhalten; 530

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APA (6^th Edition):

Adams, M. (2002). Entwicklung eines Simulationsprogrammes für das Myon-Pretrigger-System des HERA-B-Experimentes und Untersuchungen zum Systemverhalten. (Doctoral Dissertation). Technische Universität Dortmund. Retrieved from http://dx.doi.org/10.17877/DE290R-4991

Chicago Manual of Style (16^th Edition):

Adams, Markus. “Entwicklung eines Simulationsprogrammes für das Myon-Pretrigger-System des HERA-B-Experimentes und Untersuchungen zum Systemverhalten.” 2002. Doctoral Dissertation, Technische Universität Dortmund. Accessed March 02, 2021. http://dx.doi.org/10.17877/DE290R-4991.

MLA Handbook (7^th Edition):

Adams, Markus. “Entwicklung eines Simulationsprogrammes für das Myon-Pretrigger-System des HERA-B-Experimentes und Untersuchungen zum Systemverhalten.” 2002. Web. 02 Mar 2021.

Vancouver:

Adams M. Entwicklung eines Simulationsprogrammes für das Myon-Pretrigger-System des HERA-B-Experimentes und Untersuchungen zum Systemverhalten. [Internet] [Doctoral dissertation]. Technische Universität Dortmund; 2002. [cited 2021 Mar 02]. Available from: http://dx.doi.org/10.17877/DE290R-4991.

Council of Science Editors:

Adams M. Entwicklung eines Simulationsprogrammes für das Myon-Pretrigger-System des HERA-B-Experimentes und Untersuchungen zum Systemverhalten. [Doctoral Dissertation]. Technische Universität Dortmund; 2002. Available from: http://dx.doi.org/10.17877/DE290R-4991

11. Campbell, Keith A. Low-cost error detection through high-level synthesis.

Degree: MS, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/89068

► System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling and complexity has resulted in a… (more)

▼ System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling and complexity has resulted in a variety of reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters worse, as we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware accelerators in SoCs. Thus the challenge is to design complex, custom hardware that is efficient, but also correct and reliable. High-level synthesis shows promise to address the problem of complex hardware design by providing a bridge from the high-productivity software domain to the hardware design process. Much research has been done on high-level synthesis efficiency optimizations. This thesis shows that high-level synthesis also has the power to address validation and reliability challenges through two solutions. One solution for circuit reliability is modulo-3 shadow datapaths: performing lightweight shadow computations in modulo-3 space for each main computation. We leverage the binding and scheduling flexibility of high-level synthesis to detect control errors through diverse binding and minimize area cost through intelligent checkpoint scheduling and modulo-3 reducer sharing. We introduce logic and dataflow optimizations to further reduce cost. We evaluated our technique with 12 high-level synthesis benchmarks from the arithmetic-oriented PolyBench benchmark suite using FPGA emulated netlist-level error injection. We observe coverages of 99.1% for stuck-at faults, 99.5% for soft errors, and 99.6% for timing errors with a 25.7% area cost and negligible performance impact. Leveraging a mean error detection latency of 12.75 cycles (4150x faster than end result check) for soft errors, we also explore a rollback recovery method with an additional area cost of 28.0%, observing a 175x increase in reliability against soft errors. Another solution for rapid post-silicon validation of accelerator designs is Hybrid Quick Error Detection (H-QED): inserting signature generation logic in a hardware design to create a heavily compressed signature stream that captures the internal behavior of the design at a fine temporal and spatial granularity for comparison with a reference set of signatures generated by high-level simulation to detect bugs. Using H-QED, we demonstrate an improvement in error detection latency (time elapsed from when a bug is activated to when it manifests as an observable failure) of two orders of magnitude and a threefold improvement in bug coverage compared to traditional post-silicon validation techniques. H-QED also uncovered previously unknown bugs in the CHStone benchmark suite, which is widely used by the HLS community. H-QED incurs less than 10% area overhead for the accelerator it validates with negligible performance impact, and we also introduce techniques to minimize any possible intrusiveness introduced by H-QED. Advisors/Committee Members: Chen, Deming (advisor).

Subjects/Keywords: High-level synthesis; Automation; error detection; scheduling; binding; compiler transformation; compiler optimization; pipelining; modulo arithmetic; logic optimization; state machine; datapath, control logic; shadow logic; low cost; high performance; electrical bugs; Aliasing; stuck-at faults; soft errors; timing errors; checkpointing; rollback; recovery; post-silicon validation; Accelerators; system on a chip; signature generation; execution signatures; execution hashing; logic bugs; nondeterministic bugs; masked errors; circuit reliability; hot spots; wear out; silent data corruption; observability; detection latency; mixed datapath; diversity; checkpoint corruption; error injection; error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); hybrid hardware/software; execution tracing; address conversion; undefined behavior; High-Level Synthesis (HLS) engine bugs; detection coverage

…by two cycles, adding two cycles of error detection latency in exchange for reduced area… …Instability CED Concurrent Error Detection CHStone C-based High-level Synthesis benchmark suite… …Error Detection, detecting errors by fine-grained duplication RISC Reduced Instruction Set… …Quick Error Detection (H-QED): Accelerator Validation and Debug using High-Level… …can make it into the physical design. Some of those bugs evade detection in post-silicon…

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APA (6^th Edition):

Campbell, K. A. (2015). Low-cost error detection through high-level synthesis. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/89068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Campbell, Keith A. “Low-cost error detection through high-level synthesis.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed March 02, 2021. http://hdl.handle.net/2142/89068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Campbell, Keith A. “Low-cost error detection through high-level synthesis.” 2015. Web. 02 Mar 2021.

Vancouver:

Campbell KA. Low-cost error detection through high-level synthesis. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/2142/89068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Campbell KA. Low-cost error detection through high-level synthesis. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/89068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

12. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/99294

► System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety… (more)

▼ System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety of reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters worse, as we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware accelerators in SoCs. Thus the challenge is to design complex, custom hardware that is efficient, but also correct and reliable. High-level synthesis shows promise to address the problem of complex hardware design by providing a bridge from the high-productivity software domain to the hardware design process. Much research has been done on high-level synthesis efficiency optimizations. This dissertation shows that high-level synthesis also has the power to address validation and reliability challenges through three automated solutions targeting three key stages in the hardware design and use cycle: pre-silicon debugging, post-silicon validation, and post-deployment error detection. Our solution for rapid pre-silicon debugging of accelerator designs is hybrid tracing: comparing a datapath-level trace of hardware execution with a reference software implementation at a fine temporal and spatial granularity to detect logic bugs. An integrated backtrace process delivers source-code meaning to the hardware designer, pinpointing the location of bug activation and providing a strong hint for potential bug fixes. Experimental results show that we are able to detect and aid in localization of logic bugs from both C/C++ specifications as well as the high-level synthesis engine itself. A variation of this solution tailored for rapid post-silicon validation of accelerator designs is hybrid hashing: inserting signature generation logic in a hardware design to create a heavily compressed signature stream that captures the internal behavior of the design at a fine temporal and spatial granularity for comparison with a reference set of signatures generated by high-level simulation to detect bugs. Using hybrid hashing, we demonstrate an improvement in error detection latency (time elapsed from when a bug is activated to when it manifests as an observable failure) of two orders of magnitude and a threefold improvement in bug coverage compared to traditional post-silicon validation techniques. Hybrid hashing also uncovered previously unknown bugs in the CHStone benchmark suite, which is widely used by the HLS community. Hybrid hashing incurs less than 10% area overhead for the accelerator it validates with negligible performance impact, and we also introduce techniques to minimize any possible intrusiveness introduced by hybrid hashing. Finally, our solution for post-deployment error detection is modulo-3 shadow datapaths: performing lightweight shadow computations in modulo-3 space for each main computation. We leverage the binding and scheduling… Advisors/Committee Members: Chen, Deming (advisor), Chen, Deming (Committee Chair), Hwu, Wen-Mei W (committee member), Wong, Martin D F (committee member), Kim, Nam Sung (committee member).

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

…Change Order EDDI Error Detection by Duplicated Instructions EDL Error Detection Latency ix… …12 12 14 17 CHAPTER 3 RELATED WORK . . 3.1 Hybrid Quick Error Detection 3.2 Modulo Shadow… …19 19 21 23 CHAPTER 4 HYBRID QUICK ERROR DETECTION 4.1 Basic Principles… …Real-time Error Detection . . . . . . . 6.5 Experimental Results . . . . . . . . . . vii… …Instability CDFG Control and DataFlow Graph CED Concurrent Error Detection CHStone C-based…

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Record Details Similar Records Cite « Share

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16^th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 02, 2021. http://hdl.handle.net/2142/99294.

MLA Handbook (7^th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 02 Mar 2021.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 02]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294

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