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You searched for subject:(Design of CML toggle flip flop). Showing records 1 – 30 of 224554 total matches.

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Arizona State University

1. Matush, Bradley. An Innovative Radiation Hardened By Design Flip-Flop.

Degree: MS, Electrical Engineering, 2010, Arizona State University

 Radiation hardening by design (RHBD) has become a necessary practice when creating circuits to operate within radiated environments. While employing RHBD techniques has tradeoffs between… (more)

Subjects/Keywords: Electrical Engineering; Flip-Flop; Radiation Hardened By Design; Sequential Circuits

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APA (6th Edition):

Matush, B. (2010). An Innovative Radiation Hardened By Design Flip-Flop. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/8782

Chicago Manual of Style (16th Edition):

Matush, Bradley. “An Innovative Radiation Hardened By Design Flip-Flop.” 2010. Masters Thesis, Arizona State University. Accessed May 29, 2017. http://repository.asu.edu/items/8782.

MLA Handbook (7th Edition):

Matush, Bradley. “An Innovative Radiation Hardened By Design Flip-Flop.” 2010. Web. 29 May 2017.

Vancouver:

Matush B. An Innovative Radiation Hardened By Design Flip-Flop. [Internet] [Masters thesis]. Arizona State University; 2010. [cited 2017 May 29]. Available from: http://repository.asu.edu/items/8782.

Council of Science Editors:

Matush B. An Innovative Radiation Hardened By Design Flip-Flop. [Masters Thesis]. Arizona State University; 2010. Available from: http://repository.asu.edu/items/8782


Université Catholique de Louvain

2. Bernard, Sébastien. Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm FDSOI technology for ultra-wide voltage range and ultra-low power circuits.

Degree: 2014, Université Catholique de Louvain

The explosion market of the mobile application and the paradigm of the Internet of Things lead to a huge demand for energy-efficient systems. To overcome… (more)

Subjects/Keywords: CMOS Digital Circuits; Standard-Cell Design; FDSOI; UWVR; Pulsed Flip-Flop; Low-Voltage; Delay Generator; Register file

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APA (6th Edition):

Bernard, S. (2014). Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm FDSOI technology for ultra-wide voltage range and ultra-low power circuits. (Thesis). Université Catholique de Louvain. Retrieved from http://hdl.handle.net/2078.1/153437

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bernard, Sébastien. “Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm FDSOI technology for ultra-wide voltage range and ultra-low power circuits.” 2014. Thesis, Université Catholique de Louvain. Accessed May 29, 2017. http://hdl.handle.net/2078.1/153437.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bernard, Sébastien. “Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm FDSOI technology for ultra-wide voltage range and ultra-low power circuits.” 2014. Web. 29 May 2017.

Vancouver:

Bernard S. Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm FDSOI technology for ultra-wide voltage range and ultra-low power circuits. [Internet] [Thesis]. Université Catholique de Louvain; 2014. [cited 2017 May 29]. Available from: http://hdl.handle.net/2078.1/153437.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bernard S. Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm FDSOI technology for ultra-wide voltage range and ultra-low power circuits. [Thesis]. Université Catholique de Louvain; 2014. Available from: http://hdl.handle.net/2078.1/153437

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Notre Dame

3. Kristy Marie DiVittorio. Phospholipid Flip-Flop and Molecular Transport Across Biomembranes.

Degree: PhD, Chemistry and Biochemistry, 2007, University of Notre Dame

  This dissertation describes the ability of four classes of synthetic small molecules to promote the transport of anions across biomembranes without disturbing membrane integrity.… (more)

Subjects/Keywords: scramblase; biomembranes; translocation; phospholipid; Flip-flop

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APA (6th Edition):

DiVittorio, K. M. (2007). Phospholipid Flip-Flop and Molecular Transport Across Biomembranes. (Doctoral Dissertation). University of Notre Dame. Retrieved from https://curate.nd.edu/concern/etds/4x51hh65q0p

Chicago Manual of Style (16th Edition):

DiVittorio, Kristy Marie. “Phospholipid Flip-Flop and Molecular Transport Across Biomembranes.” 2007. Doctoral Dissertation, University of Notre Dame. Accessed May 29, 2017. https://curate.nd.edu/concern/etds/4x51hh65q0p.

MLA Handbook (7th Edition):

DiVittorio, Kristy Marie. “Phospholipid Flip-Flop and Molecular Transport Across Biomembranes.” 2007. Web. 29 May 2017.

Vancouver:

DiVittorio KM. Phospholipid Flip-Flop and Molecular Transport Across Biomembranes. [Internet] [Doctoral dissertation]. University of Notre Dame; 2007. [cited 2017 May 29]. Available from: https://curate.nd.edu/concern/etds/4x51hh65q0p.

Council of Science Editors:

DiVittorio KM. Phospholipid Flip-Flop and Molecular Transport Across Biomembranes. [Doctoral Dissertation]. University of Notre Dame; 2007. Available from: https://curate.nd.edu/concern/etds/4x51hh65q0p

4. Uznanski, Slawosz. Monte-Carlo simulation and contribution to understanding of Single-Event-Upset (SEU) mechanisms in CMOS technologies down to 20nm technological node : Simulation numérique de l'écoulement de gaz raréfiés sur la base des équations cinétiques modèles.

Degree: Docteur es, Micro et nanoélectronique, 2011, Autran, Jean-Luc (thesis director)

L’augmentation de la densité et la réduction de la tension d’alimentation des circuits intégrés rend la contribution des effets singuliers induits par les radiations majoritaire… (more)

Subjects/Keywords: Evénements Singulier; Aléa logiques; Rhbd; Cmos; Sram; Flip-Flop; SEE; SER; SEU; RHBD; Monte-Carlo; CMOS technology; SRAM; Flip-Flop

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APA (6th Edition):

Uznanski, S. (2011). Monte-Carlo simulation and contribution to understanding of Single-Event-Upset (SEU) mechanisms in CMOS technologies down to 20nm technological node : Simulation numérique de l'écoulement de gaz raréfiés sur la base des équations cinétiques modèles. (Thesis). Autran, Jean-Luc (thesis director). Retrieved from http://www.theses.fr/fr/2011AIX10222

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Uznanski, Slawosz. “Monte-Carlo simulation and contribution to understanding of Single-Event-Upset (SEU) mechanisms in CMOS technologies down to 20nm technological node : Simulation numérique de l'écoulement de gaz raréfiés sur la base des équations cinétiques modèles.” 2011. Thesis, Autran, Jean-Luc (thesis director). Accessed May 29, 2017. http://www.theses.fr/fr/2011AIX10222.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Uznanski, Slawosz. “Monte-Carlo simulation and contribution to understanding of Single-Event-Upset (SEU) mechanisms in CMOS technologies down to 20nm technological node : Simulation numérique de l'écoulement de gaz raréfiés sur la base des équations cinétiques modèles.” 2011. Web. 29 May 2017.

Vancouver:

Uznanski S. Monte-Carlo simulation and contribution to understanding of Single-Event-Upset (SEU) mechanisms in CMOS technologies down to 20nm technological node : Simulation numérique de l'écoulement de gaz raréfiés sur la base des équations cinétiques modèles. [Internet] [Thesis]. Autran, Jean-Luc (thesis director); 2011. [cited 2017 May 29]. Available from: http://www.theses.fr/fr/2011AIX10222.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Uznanski S. Monte-Carlo simulation and contribution to understanding of Single-Event-Upset (SEU) mechanisms in CMOS technologies down to 20nm technological node : Simulation numérique de l'écoulement de gaz raréfiés sur la base des équations cinétiques modèles. [Thesis]. Autran, Jean-Luc (thesis director); 2011. Available from: http://www.theses.fr/fr/2011AIX10222

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Oregon

5. Lindsay, Theodore. Functional Circuitry Controlling the Selection of Behavioral Primitives in Caenorhabditis elegans.

Degree: 2012, University of Oregon

 One central question of neuroscience asks how a neural system can generate the diversity of complex behaviors needed to meet the range of possible demands… (more)

Subjects/Keywords: Brownian; C. elegans; Circuit; Command Neuron; flip-flop; Optogenetics

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APA (6th Edition):

Lindsay, T. (2012). Functional Circuitry Controlling the Selection of Behavioral Primitives in Caenorhabditis elegans. (Thesis). University of Oregon. Retrieved from http://hdl.handle.net/1794/12560

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lindsay, Theodore. “Functional Circuitry Controlling the Selection of Behavioral Primitives in Caenorhabditis elegans.” 2012. Thesis, University of Oregon. Accessed May 29, 2017. http://hdl.handle.net/1794/12560.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lindsay, Theodore. “Functional Circuitry Controlling the Selection of Behavioral Primitives in Caenorhabditis elegans.” 2012. Web. 29 May 2017.

Vancouver:

Lindsay T. Functional Circuitry Controlling the Selection of Behavioral Primitives in Caenorhabditis elegans. [Internet] [Thesis]. University of Oregon; 2012. [cited 2017 May 29]. Available from: http://hdl.handle.net/1794/12560.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lindsay T. Functional Circuitry Controlling the Selection of Behavioral Primitives in Caenorhabditis elegans. [Thesis]. University of Oregon; 2012. Available from: http://hdl.handle.net/1794/12560

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Notre Dame

6. Christopher C. Forbes. Supramolecular Chemistry of Amide Containing Molecules.

Degree: PhD, Chemistry and Biochemistry, 2005, University of Notre Dame

  Amide-based synthetic molecules have been prepared and examined in four separate research projects which investigate conformational isomerization, anion binding, phospholipid translocation and rotaxane formation.… (more)

Subjects/Keywords: squaraine; Rotaxane; phospholipid flip flop

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APA (6th Edition):

Forbes, C. C. (2005). Supramolecular Chemistry of Amide Containing Molecules. (Doctoral Dissertation). University of Notre Dame. Retrieved from https://curate.nd.edu/concern/etds/6q182j64r5m

Chicago Manual of Style (16th Edition):

Forbes, Christopher C.. “Supramolecular Chemistry of Amide Containing Molecules.” 2005. Doctoral Dissertation, University of Notre Dame. Accessed May 29, 2017. https://curate.nd.edu/concern/etds/6q182j64r5m.

MLA Handbook (7th Edition):

Forbes, Christopher C.. “Supramolecular Chemistry of Amide Containing Molecules.” 2005. Web. 29 May 2017.

Vancouver:

Forbes CC. Supramolecular Chemistry of Amide Containing Molecules. [Internet] [Doctoral dissertation]. University of Notre Dame; 2005. [cited 2017 May 29]. Available from: https://curate.nd.edu/concern/etds/6q182j64r5m.

Council of Science Editors:

Forbes CC. Supramolecular Chemistry of Amide Containing Molecules. [Doctoral Dissertation]. University of Notre Dame; 2005. Available from: https://curate.nd.edu/concern/etds/6q182j64r5m


Vanderbilt University

7. Wang, Xiaowen. A clock-gated, double edge-triggered flip-flop implemented with transmission gates.

Degree: MS, Electrical Engineering, 2011, Vanderbilt University

 Power is a critical issue in digital system design, especially with the emphasis on the portability of electronic devices. However, decreasing power does not necessarily… (more)

Subjects/Keywords: Lowpower; Flip-Flop; Double edge-triggered; Clock-gating

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APA (6th Edition):

Wang, X. (2011). A clock-gated, double edge-triggered flip-flop implemented with transmission gates. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03282011-102121/ ;

Chicago Manual of Style (16th Edition):

Wang, Xiaowen. “A clock-gated, double edge-triggered flip-flop implemented with transmission gates.” 2011. Masters Thesis, Vanderbilt University. Accessed May 29, 2017. http://etd.library.vanderbilt.edu/available/etd-03282011-102121/ ;.

MLA Handbook (7th Edition):

Wang, Xiaowen. “A clock-gated, double edge-triggered flip-flop implemented with transmission gates.” 2011. Web. 29 May 2017.

Vancouver:

Wang X. A clock-gated, double edge-triggered flip-flop implemented with transmission gates. [Internet] [Masters thesis]. Vanderbilt University; 2011. [cited 2017 May 29]. Available from: http://etd.library.vanderbilt.edu/available/etd-03282011-102121/ ;.

Council of Science Editors:

Wang X. A clock-gated, double edge-triggered flip-flop implemented with transmission gates. [Masters Thesis]. Vanderbilt University; 2011. Available from: http://etd.library.vanderbilt.edu/available/etd-03282011-102121/ ;


Vanderbilt University

8. Kay, William Hunter. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.

Degree: MS, Electrical Engineering, 2015, Vanderbilt University

 The scaling of CMOS technology has brought about the increased susceptibility of circuits to single-event (SE) effects. Electronic systems operating in space often face extreme… (more)

Subjects/Keywords: flip flop; 20 nm; single event; SET; SEE; SEU

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APA (6th Edition):

Kay, W. H. (2015). Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;

Chicago Manual of Style (16th Edition):

Kay, William Hunter. “Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.” 2015. Masters Thesis, Vanderbilt University. Accessed May 29, 2017. http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;.

MLA Handbook (7th Edition):

Kay, William Hunter. “Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.” 2015. Web. 29 May 2017.

Vancouver:

Kay WH. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. [Internet] [Masters thesis]. Vanderbilt University; 2015. [cited 2017 May 29]. Available from: http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;.

Council of Science Editors:

Kay WH. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. [Masters Thesis]. Vanderbilt University; 2015. Available from: http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;


Vanderbilt University

9. Gaspard, Nelson Joseph III. Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS.

Degree: PhD, Electrical Engineering, 2017, Vanderbilt University

 Alpha, heavy-ion, neutron, and proton experimental results from 130-nm to 28-nm technology nodes are establish single-event upset cross section trends in soft and hardened flip-flop(more)

Subjects/Keywords: single event upset; CMOS; flip-flop; soft error

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APA (6th Edition):

Gaspard, N. J. I. (2017). Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03162017-144405/ ;

Chicago Manual of Style (16th Edition):

Gaspard, Nelson Joseph III. “Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS.” 2017. Doctoral Dissertation, Vanderbilt University. Accessed May 29, 2017. http://etd.library.vanderbilt.edu/available/etd-03162017-144405/ ;.

MLA Handbook (7th Edition):

Gaspard, Nelson Joseph III. “Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS.” 2017. Web. 29 May 2017.

Vancouver:

Gaspard NJI. Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS. [Internet] [Doctoral dissertation]. Vanderbilt University; 2017. [cited 2017 May 29]. Available from: http://etd.library.vanderbilt.edu/available/etd-03162017-144405/ ;.

Council of Science Editors:

Gaspard NJI. Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS. [Doctoral Dissertation]. Vanderbilt University; 2017. Available from: http://etd.library.vanderbilt.edu/available/etd-03162017-144405/ ;

10. Solé, Ricard V. Modelling Lipid Competition Dynamics in Heterogeneous Protocell Populations .

Degree: 2014, Euskal Herriko Unibertsitatea / Universidad del País Vasco

 Recent experimental work in the field of synthetic protocell biology has shown that prebiotic vesicles are able to 'steal' lipids from each other. This phenomenon… (more)

Subjects/Keywords: stochastic simulations; flip-flop; vesicles; acid; reproduction; membranes; systems

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APA (6th Edition):

Solé, R. V. (2014). Modelling Lipid Competition Dynamics in Heterogeneous Protocell Populations . (Thesis). Euskal Herriko Unibertsitatea / Universidad del País Vasco. Retrieved from http://hdl.handle.net/10810/16415

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Solé, Ricard V. “Modelling Lipid Competition Dynamics in Heterogeneous Protocell Populations .” 2014. Thesis, Euskal Herriko Unibertsitatea / Universidad del País Vasco. Accessed May 29, 2017. http://hdl.handle.net/10810/16415.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Solé, Ricard V. “Modelling Lipid Competition Dynamics in Heterogeneous Protocell Populations .” 2014. Web. 29 May 2017.

Vancouver:

Solé RV. Modelling Lipid Competition Dynamics in Heterogeneous Protocell Populations . [Internet] [Thesis]. Euskal Herriko Unibertsitatea / Universidad del País Vasco; 2014. [cited 2017 May 29]. Available from: http://hdl.handle.net/10810/16415.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Solé RV. Modelling Lipid Competition Dynamics in Heterogeneous Protocell Populations . [Thesis]. Euskal Herriko Unibertsitatea / Universidad del País Vasco; 2014. Available from: http://hdl.handle.net/10810/16415

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Urcelay, Elena. Human Endogenous Retrovirus HERV-Fc1 Association with Multiple Sclerosis Susceptibility: A Meta-Analysis .

Degree: 2014, Euskal Herriko Unibertsitatea / Universidad del País Vasco

 Background: Human endogenous retroviruses (HERVs) are repetitive sequences derived from ancestral germ-line infections by exogenous retroviruses and different HERV families have been integrated in the… (more)

Subjects/Keywords: epstein-barr-virus; risk-factors; flip-flop; expression; linkcage

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APA (6th Edition):

Urcelay, E. (2014). Human Endogenous Retrovirus HERV-Fc1 Association with Multiple Sclerosis Susceptibility: A Meta-Analysis . (Thesis). Euskal Herriko Unibertsitatea / Universidad del País Vasco. Retrieved from http://hdl.handle.net/10810/17363

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Urcelay, Elena. “Human Endogenous Retrovirus HERV-Fc1 Association with Multiple Sclerosis Susceptibility: A Meta-Analysis .” 2014. Thesis, Euskal Herriko Unibertsitatea / Universidad del País Vasco. Accessed May 29, 2017. http://hdl.handle.net/10810/17363.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Urcelay, Elena. “Human Endogenous Retrovirus HERV-Fc1 Association with Multiple Sclerosis Susceptibility: A Meta-Analysis .” 2014. Web. 29 May 2017.

Vancouver:

Urcelay E. Human Endogenous Retrovirus HERV-Fc1 Association with Multiple Sclerosis Susceptibility: A Meta-Analysis . [Internet] [Thesis]. Euskal Herriko Unibertsitatea / Universidad del País Vasco; 2014. [cited 2017 May 29]. Available from: http://hdl.handle.net/10810/17363.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Urcelay E. Human Endogenous Retrovirus HERV-Fc1 Association with Multiple Sclerosis Susceptibility: A Meta-Analysis . [Thesis]. Euskal Herriko Unibertsitatea / Universidad del País Vasco; 2014. Available from: http://hdl.handle.net/10810/17363

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

12. Fontaine, Robert Alexander. Investigation of 10-bit SAR ADC using flip-flip bypass circuit.

Degree: Electrical and Computer Engineering, 2013, University of Texas – Austin

 The Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is power efficient and operates at moderate resolution. However, the conversion speed is limited by… (more)

Subjects/Keywords: SAR; Successive Approximation Register; ADC; Flip-flop bypass

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APA (6th Edition):

Fontaine, R. A. (2013). Investigation of 10-bit SAR ADC using flip-flip bypass circuit. (Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/24011

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fontaine, Robert Alexander. “Investigation of 10-bit SAR ADC using flip-flip bypass circuit.” 2013. Thesis, University of Texas – Austin. Accessed May 29, 2017. http://hdl.handle.net/2152/24011.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fontaine, Robert Alexander. “Investigation of 10-bit SAR ADC using flip-flip bypass circuit.” 2013. Web. 29 May 2017.

Vancouver:

Fontaine RA. Investigation of 10-bit SAR ADC using flip-flip bypass circuit. [Internet] [Thesis]. University of Texas – Austin; 2013. [cited 2017 May 29]. Available from: http://hdl.handle.net/2152/24011.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fontaine RA. Investigation of 10-bit SAR ADC using flip-flip bypass circuit. [Thesis]. University of Texas – Austin; 2013. Available from: http://hdl.handle.net/2152/24011

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. Bernard, Sébastien. Bascules à impulsion robustes en technologie 28nm FDSOI pour circuits numériques basse consommation à très large gamme de tension d'alimentation : Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm fdsoi technology for ultrawide voltage range and ultra-low power circuits.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2014, Bol, David (thesis director)

Avec l'explosion du marché des applications portables et le paradigme de l'Internet des objets, la demande pour les circuits à très haute efficacité énergétique ne… (more)

Subjects/Keywords: Bascule; Numérique; FDSOI; Énergétique; Efficacité; Flip-flop; Digital; FDSOI; Energy; Efficiency; 620

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APA (6th Edition):

Bernard, S. (2014). Bascules à impulsion robustes en technologie 28nm FDSOI pour circuits numériques basse consommation à très large gamme de tension d'alimentation : Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm fdsoi technology for ultrawide voltage range and ultra-low power circuits. (Thesis). Bol, David (thesis director). Retrieved from http://www.theses.fr/fr/2014GRENT071

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bernard, Sébastien. “Bascules à impulsion robustes en technologie 28nm FDSOI pour circuits numériques basse consommation à très large gamme de tension d'alimentation : Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm fdsoi technology for ultrawide voltage range and ultra-low power circuits.” 2014. Thesis, Bol, David (thesis director). Accessed May 29, 2017. http://www.theses.fr/fr/2014GRENT071.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bernard, Sébastien. “Bascules à impulsion robustes en technologie 28nm FDSOI pour circuits numériques basse consommation à très large gamme de tension d'alimentation : Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm fdsoi technology for ultrawide voltage range and ultra-low power circuits.” 2014. Web. 29 May 2017.

Vancouver:

Bernard S. Bascules à impulsion robustes en technologie 28nm FDSOI pour circuits numériques basse consommation à très large gamme de tension d'alimentation : Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm fdsoi technology for ultrawide voltage range and ultra-low power circuits. [Internet] [Thesis]. Bol, David (thesis director); 2014. [cited 2017 May 29]. Available from: http://www.theses.fr/fr/2014GRENT071.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bernard S. Bascules à impulsion robustes en technologie 28nm FDSOI pour circuits numériques basse consommation à très large gamme de tension d'alimentation : Robust and energy-efficient explicit pulse-triggered flip-flops in 28nm fdsoi technology for ultrawide voltage range and ultra-low power circuits. [Thesis]. Bol, David (thesis director); 2014. Available from: http://www.theses.fr/fr/2014GRENT071

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Saskatchewan

14. [No author]. Single Event Effect Hardening Designs in 65nm CMOS Bulk Technology .

Degree: 2017, University of Saskatchewan

 Radiation from terrestrial and space environments is a great danger to integrated circuits (ICs). A single particle from a radiation environment strikes semiconductor materials resulting… (more)

Subjects/Keywords: Single Event Effect; Radiation Resistance; Digital Circuits; Dynamic Logic; Flip-flop; CMOS Static Logic

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

author], [. (2017). Single Event Effect Hardening Designs in 65nm CMOS Bulk Technology . (Thesis). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/7705

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

author], [No. “Single Event Effect Hardening Designs in 65nm CMOS Bulk Technology .” 2017. Thesis, University of Saskatchewan. Accessed May 29, 2017. http://hdl.handle.net/10388/7705.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

author], [No. “Single Event Effect Hardening Designs in 65nm CMOS Bulk Technology .” 2017. Web. 29 May 2017.

Vancouver:

author] [. Single Event Effect Hardening Designs in 65nm CMOS Bulk Technology . [Internet] [Thesis]. University of Saskatchewan; 2017. [cited 2017 May 29]. Available from: http://hdl.handle.net/10388/7705.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. Single Event Effect Hardening Designs in 65nm CMOS Bulk Technology . [Thesis]. University of Saskatchewan; 2017. Available from: http://hdl.handle.net/10388/7705

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

15. Swiecicki, Jean-Marie. Étude des mécanismes d'internalisation des peptides pénétrants. : Towards the Internalization Mechanisms of Cell Penetrating Peptides.

Degree: Docteur es, Chimie, 2014, Burlinat, Fabienne (thesis director)

Les peptides pénétrants (CPP) se caractérisent par deux propriétés : ils pénètrent dans l'espace intracellulaire et favorisent l'internalisation de cargaisons moléculaires auxquelles ils sont associés.… (more)

Subjects/Keywords: Peptide pénétrant; Lipopeptide; Vésicule; Phospholipide; Flip-Flop; Extinction de fluorescence; Cell penetrating peptides; Phospholipids; 540

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Swiecicki, J. (2014). Étude des mécanismes d'internalisation des peptides pénétrants. : Towards the Internalization Mechanisms of Cell Penetrating Peptides. (Thesis). Burlinat, Fabienne (thesis director). Retrieved from http://www.theses.fr/fr/2014PA066474

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Swiecicki, Jean-Marie. “Étude des mécanismes d'internalisation des peptides pénétrants. : Towards the Internalization Mechanisms of Cell Penetrating Peptides.” 2014. Thesis, Burlinat, Fabienne (thesis director). Accessed May 29, 2017. http://www.theses.fr/fr/2014PA066474.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Swiecicki, Jean-Marie. “Étude des mécanismes d'internalisation des peptides pénétrants. : Towards the Internalization Mechanisms of Cell Penetrating Peptides.” 2014. Web. 29 May 2017.

Vancouver:

Swiecicki J. Étude des mécanismes d'internalisation des peptides pénétrants. : Towards the Internalization Mechanisms of Cell Penetrating Peptides. [Internet] [Thesis]. Burlinat, Fabienne (thesis director); 2014. [cited 2017 May 29]. Available from: http://www.theses.fr/fr/2014PA066474.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Swiecicki J. Étude des mécanismes d'internalisation des peptides pénétrants. : Towards the Internalization Mechanisms of Cell Penetrating Peptides. [Thesis]. Burlinat, Fabienne (thesis director); 2014. Available from: http://www.theses.fr/fr/2014PA066474

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universiteit Utrecht

16. Halter, D. Transport and Translocation of Glucosylceramide.

Degree: 2007, Universiteit Utrecht

 Glycosphingolipids (GSL) are important determinants of the functional organization of cellular membranes. They are controlled by the spatial organization of their metabolism and by specificity… (more)

Subjects/Keywords: Scheikunde; glucosylceramide; glycosphingolipid; GLTP; V-ATPase; ABC transporter; flip-flop; transmembrane translocation; transport

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Halter, D. (2007). Transport and Translocation of Glucosylceramide. (Doctoral Dissertation). Universiteit Utrecht. Retrieved from http://dspace.library.uu.nl:8080/handle/1874/22788

Chicago Manual of Style (16th Edition):

Halter, D. “Transport and Translocation of Glucosylceramide.” 2007. Doctoral Dissertation, Universiteit Utrecht. Accessed May 29, 2017. http://dspace.library.uu.nl:8080/handle/1874/22788.

MLA Handbook (7th Edition):

Halter, D. “Transport and Translocation of Glucosylceramide.” 2007. Web. 29 May 2017.

Vancouver:

Halter D. Transport and Translocation of Glucosylceramide. [Internet] [Doctoral dissertation]. Universiteit Utrecht; 2007. [cited 2017 May 29]. Available from: http://dspace.library.uu.nl:8080/handle/1874/22788.

Council of Science Editors:

Halter D. Transport and Translocation of Glucosylceramide. [Doctoral Dissertation]. Universiteit Utrecht; 2007. Available from: http://dspace.library.uu.nl:8080/handle/1874/22788


Vanderbilt University

17. Kou, Lingbo. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.

Degree: MS, Electrical Engineering, 2014, Vanderbilt University

 Power consumption has become a major concern of integrated circuit (IC) design. Reducing the supply voltage to the near-threshold region is one method to reduce… (more)

Subjects/Keywords: flip-flop; radiation-induced soft errors; sram; near-threshold voltage; critical charge; process variations; reliability

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APA (6th Edition):

Kou, L. (2014). Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;

Chicago Manual of Style (16th Edition):

Kou, Lingbo. “Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.” 2014. Masters Thesis, Vanderbilt University. Accessed May 29, 2017. http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;.

MLA Handbook (7th Edition):

Kou, Lingbo. “Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.” 2014. Web. 29 May 2017.

Vancouver:

Kou L. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. [Internet] [Masters thesis]. Vanderbilt University; 2014. [cited 2017 May 29]. Available from: http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;.

Council of Science Editors:

Kou L. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. [Masters Thesis]. Vanderbilt University; 2014. Available from: http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;

18. Elsharkasy, Wael Mahmoud. Low Power Reliable Design using Pulsed Latch Circuits.

Degree: Electrical and Computer Engineering, 2017, University of California – Irvine

 System-on-Chip (SoC) faced lots of challenges over the past decade. With nowadays applications centered around Internet-of-Everything (IoE), these challenges are expected to be more critical.… (more)

Subjects/Keywords: Electrical engineering; Computer engineering; Flip-Flop; Low Power; Pulsed Latch; Register File; Reliability; Sequential Element

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APA (6th Edition):

Elsharkasy, W. M. (2017). Low Power Reliable Design using Pulsed Latch Circuits. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/5ss2z430

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Elsharkasy, Wael Mahmoud. “Low Power Reliable Design using Pulsed Latch Circuits.” 2017. Thesis, University of California – Irvine. Accessed May 29, 2017. http://www.escholarship.org/uc/item/5ss2z430.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Elsharkasy, Wael Mahmoud. “Low Power Reliable Design using Pulsed Latch Circuits.” 2017. Web. 29 May 2017.

Vancouver:

Elsharkasy WM. Low Power Reliable Design using Pulsed Latch Circuits. [Internet] [Thesis]. University of California – Irvine; 2017. [cited 2017 May 29]. Available from: http://www.escholarship.org/uc/item/5ss2z430.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Elsharkasy WM. Low Power Reliable Design using Pulsed Latch Circuits. [Thesis]. University of California – Irvine; 2017. Available from: http://www.escholarship.org/uc/item/5ss2z430

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Southern California

19. Choubey, Amit. Shock-induced poration, cholesterol flip-flop and small interfering RNA transfection in a phospholipid membrane: multimillion atom, microsecond molecular dynamics simulations.

Degree: PhD, Physics, 2014, University of Southern California

 Biological cell membranes provide mechanical stability to cells and understanding their structure, dynamics and mechanics are important biophysics problems. Experiments coupled with computational methods such… (more)

Subjects/Keywords: molecular dynamics; DPPC bilayer; nanobubble collapse; shock; poration; cholesterol flip-flop; siRNA

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APA (6th Edition):

Choubey, A. (2014). Shock-induced poration, cholesterol flip-flop and small interfering RNA transfection in a phospholipid membrane: multimillion atom, microsecond molecular dynamics simulations. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/363504/rec/5808

Chicago Manual of Style (16th Edition):

Choubey, Amit. “Shock-induced poration, cholesterol flip-flop and small interfering RNA transfection in a phospholipid membrane: multimillion atom, microsecond molecular dynamics simulations.” 2014. Doctoral Dissertation, University of Southern California. Accessed May 29, 2017. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/363504/rec/5808.

MLA Handbook (7th Edition):

Choubey, Amit. “Shock-induced poration, cholesterol flip-flop and small interfering RNA transfection in a phospholipid membrane: multimillion atom, microsecond molecular dynamics simulations.” 2014. Web. 29 May 2017.

Vancouver:

Choubey A. Shock-induced poration, cholesterol flip-flop and small interfering RNA transfection in a phospholipid membrane: multimillion atom, microsecond molecular dynamics simulations. [Internet] [Doctoral dissertation]. University of Southern California; 2014. [cited 2017 May 29]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/363504/rec/5808.

Council of Science Editors:

Choubey A. Shock-induced poration, cholesterol flip-flop and small interfering RNA transfection in a phospholipid membrane: multimillion atom, microsecond molecular dynamics simulations. [Doctoral Dissertation]. University of Southern California; 2014. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/363504/rec/5808


Arizona State University

20. Shambhulingaiah, Sandeep. Methodical Design Approaches to Multiple Node Collection Robustness for Flip-Flop Soft Error MItigation.

Degree: Doctoral, Dissertation Electrical Engineering, 2015, Arizona State University

Subjects/Keywords: Electrical engineering; Flip-flop; Methodology; Multi node charge collection; Radiation hardening by design; Single Event Transient (SET); Single Event Upset (SEU)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shambhulingaiah, S. (2015). Methodical Design Approaches to Multiple Node Collection Robustness for Flip-Flop Soft Error MItigation. (Doctoral Dissertation). Arizona State University. Retrieved from http://repository.asu.edu/items/29650

Chicago Manual of Style (16th Edition):

Shambhulingaiah, Sandeep. “Methodical Design Approaches to Multiple Node Collection Robustness for Flip-Flop Soft Error MItigation.” 2015. Doctoral Dissertation, Arizona State University. Accessed May 29, 2017. http://repository.asu.edu/items/29650.

MLA Handbook (7th Edition):

Shambhulingaiah, Sandeep. “Methodical Design Approaches to Multiple Node Collection Robustness for Flip-Flop Soft Error MItigation.” 2015. Web. 29 May 2017.

Vancouver:

Shambhulingaiah S. Methodical Design Approaches to Multiple Node Collection Robustness for Flip-Flop Soft Error MItigation. [Internet] [Doctoral dissertation]. Arizona State University; 2015. [cited 2017 May 29]. Available from: http://repository.asu.edu/items/29650.

Council of Science Editors:

Shambhulingaiah S. Methodical Design Approaches to Multiple Node Collection Robustness for Flip-Flop Soft Error MItigation. [Doctoral Dissertation]. Arizona State University; 2015. Available from: http://repository.asu.edu/items/29650

21. Kim, Yejoong. Robust Circuit Design for Low-Voltage VLSI.

Degree: PhD, Electrical Engineering, 2015, University of Michigan

 Voltage scaling is an effective way to reduce the overall power consumption, but the major challenges in low voltage operations include performance degradation and reliability… (more)

Subjects/Keywords: Low-Voltage; VLSI; Level Converter; SRAM; Flip-Flop; Robust Circuit Design; Electrical Engineering; Engineering

…advantages of the 7T. The next key component is the clocked sequential element, called a flip-flop… …because of its importance in digital circuits, numerous flip-flop designs have been investigated… …harness for flip-flop timing characterization. Rep- 7 resentative timing parameters of flip… …to demonstrate the benefit of the new flip-flop introduced in Chapter 4. Finally, in… …example, both of POWER7TM and SPARC T4 processors have more than 2 million flip-flops, taking up… 

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APA (6th Edition):

Kim, Y. (2015). Robust Circuit Design for Low-Voltage VLSI. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/111525

Chicago Manual of Style (16th Edition):

Kim, Yejoong. “Robust Circuit Design for Low-Voltage VLSI.” 2015. Doctoral Dissertation, University of Michigan. Accessed May 29, 2017. http://hdl.handle.net/2027.42/111525.

MLA Handbook (7th Edition):

Kim, Yejoong. “Robust Circuit Design for Low-Voltage VLSI.” 2015. Web. 29 May 2017.

Vancouver:

Kim Y. Robust Circuit Design for Low-Voltage VLSI. [Internet] [Doctoral dissertation]. University of Michigan; 2015. [cited 2017 May 29]. Available from: http://hdl.handle.net/2027.42/111525.

Council of Science Editors:

Kim Y. Robust Circuit Design for Low-Voltage VLSI. [Doctoral Dissertation]. University of Michigan; 2015. Available from: http://hdl.handle.net/2027.42/111525

22. Wang, Haibin. STUDY OF SINGLE-EVENT EFFECTS ON DIGITAL SYSTEMS.

Degree: PhD, Electrical Engineering, 2015, University of Saskatchewan

 Microelectronic devices and systems have been extensively utilized in a variety of radiation environments, ranging from the low-earth orbit to the ground level. A high-energy… (more)

Subjects/Keywords: Single event effects; Charge sharing; nano technology; flip-flop; Radiation Hardening By Design

…x28;b) block diagram of each flip-flop design in the shift register chain… …through the use of simulations and experimental data.  RHBD flip-flop designs: In digital… …which distributes the global clock signal all over the flip-flop chains. All of these shift… …130 7.3.1 Operating Principles of the Proposed Design… …31 Figure III-1. The structure of the TDICE design [16]; two feedback transistors… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, H. (2015). STUDY OF SINGLE-EVENT EFFECTS ON DIGITAL SYSTEMS. (Doctoral Dissertation). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/ETD-2015-08-2101

Chicago Manual of Style (16th Edition):

Wang, Haibin. “STUDY OF SINGLE-EVENT EFFECTS ON DIGITAL SYSTEMS.” 2015. Doctoral Dissertation, University of Saskatchewan. Accessed May 29, 2017. http://hdl.handle.net/10388/ETD-2015-08-2101.

MLA Handbook (7th Edition):

Wang, Haibin. “STUDY OF SINGLE-EVENT EFFECTS ON DIGITAL SYSTEMS.” 2015. Web. 29 May 2017.

Vancouver:

Wang H. STUDY OF SINGLE-EVENT EFFECTS ON DIGITAL SYSTEMS. [Internet] [Doctoral dissertation]. University of Saskatchewan; 2015. [cited 2017 May 29]. Available from: http://hdl.handle.net/10388/ETD-2015-08-2101.

Council of Science Editors:

Wang H. STUDY OF SINGLE-EVENT EFFECTS ON DIGITAL SYSTEMS. [Doctoral Dissertation]. University of Saskatchewan; 2015. Available from: http://hdl.handle.net/10388/ETD-2015-08-2101

23. Khan, Muhammad Imran. Logic Gates Switching Harmonics.

Degree: 2010, Chalmers University of Technology

 This report deals with the study of spectrum generation from logic circuits, in order to better understand how to suppress the generation of high harmonics,… (more)

Subjects/Keywords: BSIM transistor Model; Cadence Spectre; PowerPC 603 Master-Slave Latch; modified C²MOS Latch; hybrid-latch flip flop (HLFF)

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APA (6th Edition):

Khan, M. I. (2010). Logic Gates Switching Harmonics. (Thesis). Chalmers University of Technology. Retrieved from http://studentarbeten.chalmers.se/publication/125612-logic-gates-switching-harmonics

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Khan, Muhammad Imran. “Logic Gates Switching Harmonics.” 2010. Thesis, Chalmers University of Technology. Accessed May 29, 2017. http://studentarbeten.chalmers.se/publication/125612-logic-gates-switching-harmonics.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Khan, Muhammad Imran. “Logic Gates Switching Harmonics.” 2010. Web. 29 May 2017.

Vancouver:

Khan MI. Logic Gates Switching Harmonics. [Internet] [Thesis]. Chalmers University of Technology; 2010. [cited 2017 May 29]. Available from: http://studentarbeten.chalmers.se/publication/125612-logic-gates-switching-harmonics.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Khan MI. Logic Gates Switching Harmonics. [Thesis]. Chalmers University of Technology; 2010. Available from: http://studentarbeten.chalmers.se/publication/125612-logic-gates-switching-harmonics

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. Neuberger, Gustavo. Protecting digital circuits against hold time violations due to process variations.

Degree: 2007, Universidade do Rio Grande do Sul

Com o desenvolvimento da tecnologia CMOS, os circuitos estão ficando cada vez mais sujeitos a variabilidade no processo de fabricação. Variações estatísticas de processo são… (more)

Subjects/Keywords: Process variability; Microeletronica; Hold time violations; Circuitos integrados; On-chip testing; Clock skew; Flip-flop characterization; Race immunity; Microelectronics

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APA (6th Edition):

Neuberger, G. (2007). Protecting digital circuits against hold time violations due to process variations. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/12924

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Neuberger, Gustavo. “Protecting digital circuits against hold time violations due to process variations.” 2007. Thesis, Universidade do Rio Grande do Sul. Accessed May 29, 2017. http://hdl.handle.net/10183/12924.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Neuberger, Gustavo. “Protecting digital circuits against hold time violations due to process variations.” 2007. Web. 29 May 2017.

Vancouver:

Neuberger G. Protecting digital circuits against hold time violations due to process variations. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2007. [cited 2017 May 29]. Available from: http://hdl.handle.net/10183/12924.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Neuberger G. Protecting digital circuits against hold time violations due to process variations. [Thesis]. Universidade do Rio Grande do Sul; 2007. Available from: http://hdl.handle.net/10183/12924

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

25. Pearson, Robert. PMOS digital structures.

Degree: 1986, Rochester Institute of Technology

  A majority of new integrated circuit designs are being fabricated in CMOS technology which uses both pMOSFETs and nMOSFETS. The nMOSFETS have been well… (more)

Subjects/Keywords: Fabrication; Flip-flop; Integrated circuit; pMOS; pMOSFET; RS

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APA (6th Edition):

Pearson, R. (1986). PMOS digital structures. (Thesis). Rochester Institute of Technology. Retrieved from http://scholarworks.rit.edu/theses/4088

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pearson, Robert. “PMOS digital structures.” 1986. Thesis, Rochester Institute of Technology. Accessed May 29, 2017. http://scholarworks.rit.edu/theses/4088.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pearson, Robert. “PMOS digital structures.” 1986. Web. 29 May 2017.

Vancouver:

Pearson R. PMOS digital structures. [Internet] [Thesis]. Rochester Institute of Technology; 1986. [cited 2017 May 29]. Available from: http://scholarworks.rit.edu/theses/4088.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pearson R. PMOS digital structures. [Thesis]. Rochester Institute of Technology; 1986. Available from: http://scholarworks.rit.edu/theses/4088

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Arizona State University

26. Gujja, Aditya. Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft-Error Mitigation.

Degree: Masters, Thesis Electrical Engineering, 2015, Arizona State University

 An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both single event upsets (SEU) and single event transients (SET) with reduced… (more)

Subjects/Keywords: Electrical engineering; Flip-Flop; multiple node charge collection; single event transient; single event upset; temporal hardening; triple mode redundancy

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gujja, A. (2015). Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft-Error Mitigation. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/36471

Chicago Manual of Style (16th Edition):

Gujja, Aditya. “Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft-Error Mitigation.” 2015. Masters Thesis, Arizona State University. Accessed May 29, 2017. http://repository.asu.edu/items/36471.

MLA Handbook (7th Edition):

Gujja, Aditya. “Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft-Error Mitigation.” 2015. Web. 29 May 2017.

Vancouver:

Gujja A. Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft-Error Mitigation. [Internet] [Masters thesis]. Arizona State University; 2015. [cited 2017 May 29]. Available from: http://repository.asu.edu/items/36471.

Council of Science Editors:

Gujja A. Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft-Error Mitigation. [Masters Thesis]. Arizona State University; 2015. Available from: http://repository.asu.edu/items/36471


University of Missouri – Columbia

27. Glantz, Mark, 1983-. Negative political advertising and the charge of inconsistency: the rhetoric of "flip-flop" arguments.

Degree: 2010, University of Missouri – Columbia

 This dissertation performs a rhetorical analysis of televised presidential campaign advertisements that accuse rival candidates of being inconsistent or otherwise "flip-flopping." The verbal, visual, and… (more)

Subjects/Keywords: flip-flop commercials; flip-flopping in politics; Advertising, Political; Communication in politics; Mass media  – Political aspects; Mass media  – Moral and ethical aspects; Negativism; Political campaigns

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Glantz, Mark, 1. (2010). Negative political advertising and the charge of inconsistency: the rhetoric of "flip-flop" arguments. (Thesis). University of Missouri – Columbia. Retrieved from http://hdl.handle.net/10355/8344

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Glantz, Mark, 1983-. “Negative political advertising and the charge of inconsistency: the rhetoric of "flip-flop" arguments.” 2010. Thesis, University of Missouri – Columbia. Accessed May 29, 2017. http://hdl.handle.net/10355/8344.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Glantz, Mark, 1983-. “Negative political advertising and the charge of inconsistency: the rhetoric of "flip-flop" arguments.” 2010. Web. 29 May 2017.

Vancouver:

Glantz, Mark 1. Negative political advertising and the charge of inconsistency: the rhetoric of "flip-flop" arguments. [Internet] [Thesis]. University of Missouri – Columbia; 2010. [cited 2017 May 29]. Available from: http://hdl.handle.net/10355/8344.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Glantz, Mark 1. Negative political advertising and the charge of inconsistency: the rhetoric of "flip-flop" arguments. [Thesis]. University of Missouri – Columbia; 2010. Available from: http://hdl.handle.net/10355/8344

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

28. CHANDRASEKARAN RAJASEKARAN. The development of building block circuits for high-speed decimation filters.

Degree: 2006, National University of Singapore

Subjects/Keywords: CMOS; Differential logic; Decimation filter; Full adder; Flip-Flop; RF digitization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

RAJASEKARAN, C. (2006). The development of building block circuits for high-speed decimation filters. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/15333 ; http://scholarbank.nus.edu.sg/bitstream/10635%2F15333/1/bitstream ; http://scholarbank.nus.edu.sg/bitstream/10635%2F15333/2/bitstream

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

RAJASEKARAN, CHANDRASEKARAN. “The development of building block circuits for high-speed decimation filters.” 2006. Thesis, National University of Singapore. Accessed May 29, 2017. http://scholarbank.nus.edu.sg/handle/10635/15333 ; http://scholarbank.nus.edu.sg/bitstream/10635%2F15333/1/bitstream ; http://scholarbank.nus.edu.sg/bitstream/10635%2F15333/2/bitstream.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

RAJASEKARAN, CHANDRASEKARAN. “The development of building block circuits for high-speed decimation filters.” 2006. Web. 29 May 2017.

Vancouver:

RAJASEKARAN C. The development of building block circuits for high-speed decimation filters. [Internet] [Thesis]. National University of Singapore; 2006. [cited 2017 May 29]. Available from: http://scholarbank.nus.edu.sg/handle/10635/15333 ; http://scholarbank.nus.edu.sg/bitstream/10635%2F15333/1/bitstream ; http://scholarbank.nus.edu.sg/bitstream/10635%2F15333/2/bitstream.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

RAJASEKARAN C. The development of building block circuits for high-speed decimation filters. [Thesis]. National University of Singapore; 2006. Available from: http://scholarbank.nus.edu.sg/handle/10635/15333 ; http://scholarbank.nus.edu.sg/bitstream/10635%2F15333/1/bitstream ; http://scholarbank.nus.edu.sg/bitstream/10635%2F15333/2/bitstream

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Kumar, Sushil. Radiation Hardened Pulse Based D Flip Flop Design.

Degree: MS, Electrical Engineering, 2014, Arizona State University

 ABSTRACT The D flip flop acts as a sequencing element while designing any pipelined system. Radiation Hardening by Design (RHBD) allows hardened circuits to be… (more)

Subjects/Keywords: Electrical engineering; ciruits; D Flip Flop; pulse; Radiation hardened

…Fig. 1.3), also called the setup node of the flip flop. Similarly after the rising edge… …afterclock rising edge for which data should be constant. During the rising edge of flip-flop, new… …violation can be solved by adding delays between the stages of the flip flop and must be done… …during the design phase of the chip. 1.3. Principle of pulse clock based flip-flops The… …65 viii Chapter 1 INTRODUCTION The flip flop (FF) is the most widely used… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kumar, S. (2014). Radiation Hardened Pulse Based D Flip Flop Design. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/24764

Chicago Manual of Style (16th Edition):

Kumar, Sushil. “Radiation Hardened Pulse Based D Flip Flop Design.” 2014. Masters Thesis, Arizona State University. Accessed May 29, 2017. http://repository.asu.edu/items/24764.

MLA Handbook (7th Edition):

Kumar, Sushil. “Radiation Hardened Pulse Based D Flip Flop Design.” 2014. Web. 29 May 2017.

Vancouver:

Kumar S. Radiation Hardened Pulse Based D Flip Flop Design. [Internet] [Masters thesis]. Arizona State University; 2014. [cited 2017 May 29]. Available from: http://repository.asu.edu/items/24764.

Council of Science Editors:

Kumar S. Radiation Hardened Pulse Based D Flip Flop Design. [Masters Thesis]. Arizona State University; 2014. Available from: http://repository.asu.edu/items/24764


University of Southern California

30. Ghasemazar, Mohammad. Variation-aware circuit and chip level power optimization in digital VLSI systems.

Degree: PhD, Electrical Engineering, 2011, University of Southern California

 In today’s IC design, one of the key challenges is the increase in power consumption of the circuit which in turn shortens the service time… (more)

Subjects/Keywords: power optimization; circuit and chip-level techniques; soft-edge flip flop; soft pipeline; Chip Multiprocessors; dynamic power and thermal management; hierarchical power management; dynamic voltage and frequency scaling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ghasemazar, M. (2011). Variation-aware circuit and chip level power optimization in digital VLSI systems. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/211848/rec/7763

Chicago Manual of Style (16th Edition):

Ghasemazar, Mohammad. “Variation-aware circuit and chip level power optimization in digital VLSI systems.” 2011. Doctoral Dissertation, University of Southern California. Accessed May 29, 2017. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/211848/rec/7763.

MLA Handbook (7th Edition):

Ghasemazar, Mohammad. “Variation-aware circuit and chip level power optimization in digital VLSI systems.” 2011. Web. 29 May 2017.

Vancouver:

Ghasemazar M. Variation-aware circuit and chip level power optimization in digital VLSI systems. [Internet] [Doctoral dissertation]. University of Southern California; 2011. [cited 2017 May 29]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/211848/rec/7763.

Council of Science Editors:

Ghasemazar M. Variation-aware circuit and chip level power optimization in digital VLSI systems. [Doctoral Dissertation]. University of Southern California; 2011. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/211848/rec/7763

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