Open Access Theses and Dissertations

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You searched for subject:(Delay set analysis). Showing records 1 – 3 of 3 total matches.

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Georgia State University

1. Yan, Mingyuan. Data Aggregation Scheduling in Wireless Networks.

Degree: PhD, Computer Science, 2015, Georgia State University

URL: https://scholarworks.gsu.edu/cs_diss/100 

Data aggregation is one of the most essential data gathering operations in wireless networks. It is an efficient strategy to alleviate energy consumption and reduce medium access contention. In this dissertation, the data aggregation scheduling problem in different wireless networks is investigated. Since Wireless Sensor Networks (WSNs) are one of the most important types of wireless networks and data aggregation plays a vital role in WSNs, the minimum latency data aggregation scheduling problem for multi-regional queries in WSNs is first studied. A scheduling algorithm is proposed with comprehensive theoretical and simulation analysis regarding time efficiency. Second, with the increasing popularity of Cognitive Radio Networks (CRNs), data aggregation scheduling in CRNs is studied. Considering the precious spectrum opportunity in CRNs, a routing hierarchy, which allows a secondary user to seek a transmission opportunity among a group of receivers, is introduced. Several scheduling algorithms are proposed for both the Unit Disk Graph (UDG) interference model and the Physical Interference Model (PhIM), followed by performance evaluation through simulations. Third, the data aggregation scheduling problem in wireless networks with cognitive radio capability is investigated. Under the defined network model, besides a default working spectrum, users can access extra available spectrum through a cognitive radio. The problem is formalized as an Integer Linear Programming (ILP) problem and solved through an optimization method in the beginning. The simulation results show that the ILP based method has a good performance. However, it is difficult to evaluate the solution theoretically. A heuristic scheduling algorithm with guaranteed latency bound is presented in our further investigation. Finally, we investigate how to make use of cognitive radio capability to accelerate data aggregation in probabilistic wireless networks with lossy links. A two-phase scheduling algorithm is proposed, and the effectiveness of the algorithm is verified through both theoretical analysis and numerical simulations. Advisors/Committee Members: Dr. Yingshu Li, Dr. Zhipeng Cai, Dr. Raj Sunderraman, Dr. Anu Bourgeois, Dr. Xin Qi.

Subjects/Keywords: Data aggregation; Scheduling; Connected dominate set; Delay analysis; Wireless sensor network; Cognitive radio network; Probabilistic wireless networks

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yan, M. (2015). Data Aggregation Scheduling in Wireless Networks. (Doctoral Dissertation). Georgia State University. Retrieved from https://scholarworks.gsu.edu/cs_diss/100

Chicago Manual of Style (16th Edition):

Yan, Mingyuan. “Data Aggregation Scheduling in Wireless Networks.” 2015. Doctoral Dissertation, Georgia State University. Accessed March 04, 2021. https://scholarworks.gsu.edu/cs_diss/100.

MLA Handbook (7th Edition):

Yan, Mingyuan. “Data Aggregation Scheduling in Wireless Networks.” 2015. Web. 04 Mar 2021.

Vancouver:

Yan M. Data Aggregation Scheduling in Wireless Networks. [Internet] [Doctoral dissertation]. Georgia State University; 2015. [cited 2021 Mar 04]. Available from: https://scholarworks.gsu.edu/cs_diss/100.

Council of Science Editors:

Yan M. Data Aggregation Scheduling in Wireless Networks. [Doctoral Dissertation]. Georgia State University; 2015. Available from: https://scholarworks.gsu.edu/cs_diss/100


University of Texas – Austin

2. Srinivasa Murthy, Karthik, 1983-. A proposed memory consistency model for Chapel.

Degree: MA, Computer Sciences, 2010, University of Texas – Austin

URL: http://hdl.handle.net/2152/ETD-UT-2010-08-1990 

A memory consistency model for a language defines the order of memory operations performed by each thread in a parallel execution. Such a constraint is necessary to prevent the compiler and hardware optimizations from reordering certain memory operations, since such reordering might lead to unintuitive results. In this thesis, we propose a memory consistency model for Chapel, a parallel programming language from Cray Inc. Our memory model for Chapel is based on the idea of multiresolution and aims to provide a migration path from a program that is easy to reason about to a program that has better performance efficiency. Our model allows a programmer to write a parallel program with sequential consistency semantics, and then migrate to a performance-oriented version by increasingly changing different parts of the program to follow relaxed semantics. Sequential semantics helps in reasoning about the correctness of the parallel program and is provided by the strict sequential consistency model in our proposed memory model. The performance-oriented versions can be obtained either by using the compiler sequential consistency model, which maintains the sequential semantics, or by the relaxed consistency model, which maintains consistency only at global synchronization points. Our proposed memory model for Chapel thus combines strict sequential consistency model, compiler sequential consistency model and relaxed consistency model. We analyze the performance of the three consistency models by implementing three applications: Barnes-Hut, FFT and Random-Access in Chapel, and the hybrid model of MPI and Pthread. We conclude the following: The strict sequential consistency model is the best model to determine algorithmic errors in the applications, though it leads to the worst performance; the relaxed consistency model gives the best performance among the three models, but relies on the programmer to enforce synchronization correctly; the performance of the compiler sequential model depends on accuracy of the dependence analysis performed by the compiler; the relative performance of the consistency models across Chapel and the hybrid programming model of MPI and Pthread are the same. This shows that our model is not tightly bound to Chapel and can be applied on other programming models/languages. Advisors/Committee Members: Lin, Yun Calvin (advisor), Chamberlain, Brad (committee member).

Subjects/Keywords: Chapel; Memory models; Sequential consistency; Delay set analysis; Parallel programming language

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Srinivasa Murthy, Karthik, 1. (2010). A proposed memory consistency model for Chapel. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2010-08-1990

Chicago Manual of Style (16th Edition):

Srinivasa Murthy, Karthik, 1983-. “A proposed memory consistency model for Chapel.” 2010. Masters Thesis, University of Texas – Austin. Accessed March 04, 2021. http://hdl.handle.net/2152/ETD-UT-2010-08-1990.

MLA Handbook (7th Edition):

Srinivasa Murthy, Karthik, 1983-. “A proposed memory consistency model for Chapel.” 2010. Web. 04 Mar 2021.

Vancouver:

Srinivasa Murthy, Karthik 1. A proposed memory consistency model for Chapel. [Internet] [Masters thesis]. University of Texas – Austin; 2010. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2152/ETD-UT-2010-08-1990.

Council of Science Editors:

Srinivasa Murthy, Karthik 1. A proposed memory consistency model for Chapel. [Masters Thesis]. University of Texas – Austin; 2010. Available from: http://hdl.handle.net/2152/ETD-UT-2010-08-1990

3. Barceló Adrover, Salvador. An advanced Framework for efficient IC optimization based on analytical models engine.

Degree: Departament de Física, 2013, Universitat de les Illes Balears

URL: http://hdl.handle.net/10803/128968 

Based on the challenges arising as a result of technology scaling, this thesis develops and evaluates a complete framework for SET propagation sensitivity. The framework comprises a number of processing tools capable of handling circuits with high complexity in an efficient way. Various SET propagation metrics have been proposed considering the impact of logic, electric and combined logic-electric masking. Such metrics provide a valuable vehicle to grade either in-circuit regions being more susceptible of propagating SETs toward the circuit outputs or circuit outputs more susceptible to produce SET. A quite efficient and customizable true path finding algorithm with a specific logic system has been constructed and its efficacy demonstrated on large benchmark circuits. It has been shown that the delay of a path depends on the sensitization vectors applied to the gates within the path. In some cases, this variation is comparable to the one caused by process parameters variations. Advisors/Committee Members: [email protected] (authoremail), true (authoremailshow), Segura Fuster, Jaume (director), true (authorsendemail).

Subjects/Keywords: SET, SEE, Soft-Errors, Timing Analysis, EDA, Critical Path, Algorithms, Delay Fault Testing, Test, Circuit Design, Delay Modeling, Capacitance modeling; Tecnologia electrònica; 53; 537

…4 Chapter 2: Timing analysis and SET propagation… …focused on developing specific SET propagation analysis tools, when integrating such components… …about timing analysis and SET propagation through a combinational circuit, and some… …work and the future work. 4 Chapter 2: Timing analysis and SET propagation This chapter… …Chapter 2: Timing analysis and SET propagation Circuit synthesis is performed according to… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Barceló Adrover, S. (2013). An advanced Framework for efficient IC optimization based on analytical models engine. (Thesis). Universitat de les Illes Balears. Retrieved from http://hdl.handle.net/10803/128968

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Barceló Adrover, Salvador. “An advanced Framework for efficient IC optimization based on analytical models engine.” 2013. Thesis, Universitat de les Illes Balears. Accessed March 04, 2021. http://hdl.handle.net/10803/128968.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Barceló Adrover, Salvador. “An advanced Framework for efficient IC optimization based on analytical models engine.” 2013. Web. 04 Mar 2021.

Vancouver:

Barceló Adrover S. An advanced Framework for efficient IC optimization based on analytical models engine. [Internet] [Thesis]. Universitat de les Illes Balears; 2013. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10803/128968.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Barceló Adrover S. An advanced Framework for efficient IC optimization based on analytical models engine. [Thesis]. Universitat de les Illes Balears; 2013. Available from: http://hdl.handle.net/10803/128968

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.