Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(Dataflow Architecture). Showing records 1 – 20 of 20 total matches.

Search Limiters

Last 2 Years | English Only

No search limiters apply to these results.

▼ Search Limiters


Indian Institute of Science

1. Varadarajan, Keshavan. A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution.

Degree: 2012, Indian Institute of Science

 A Coarse-Grained Reconfigurable Architecture (CGRA) is a processing platform which constitutes an interconnection of coarse-grained computation units (viz. Function Units (FUs), Arithmetic Logic Units (ALUs)).… (more)

Subjects/Keywords: Coarse Grained Computation; Reconfigurable Architectures; Macro Dataflow Execution; Coarse Grained Reconfigurable Architecture; Macro-Dataflow Orchestration; Microarchitectural Optimizations; Reconfigurable Fabric; Coarse-Grained Reconfigurable Architecture (CGRA); Macro Dataflow Execution; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Varadarajan, K. (2012). A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2302

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Varadarajan, Keshavan. “A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution.” 2012. Thesis, Indian Institute of Science. Accessed December 13, 2019. http://hdl.handle.net/2005/2302.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Varadarajan, Keshavan. “A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution.” 2012. Web. 13 Dec 2019.

Vancouver:

Varadarajan K. A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2019 Dec 13]. Available from: http://hdl.handle.net/2005/2302.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Varadarajan K. A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution. [Thesis]. Indian Institute of Science; 2012. Available from: http://hdl.handle.net/2005/2302

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

2. Varadarajan, Keshavan. A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution.

Degree: 2012, Indian Institute of Science

 A Coarse-Grained Reconfigurable Architecture (CGRA) is a processing platform which constitutes an interconnection of coarse-grained computation units (viz. Function Units (FUs), Arithmetic Logic Units (ALUs)).… (more)

Subjects/Keywords: Coarse Grained Computation; Reconfigurable Architectures; Macro Dataflow Execution; Coarse Grained Reconfigurable Architecture; Macro-Dataflow Orchestration; Microarchitectural Optimizations; Reconfigurable Fabric; Coarse-Grained Reconfigurable Architecture (CGRA); Macro Dataflow Execution; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Varadarajan, K. (2012). A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2302 ; http://etd.ncsi.iisc.ernet.in/abstracts/2962/G25467-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Varadarajan, Keshavan. “A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution.” 2012. Thesis, Indian Institute of Science. Accessed December 13, 2019. http://etd.iisc.ernet.in/handle/2005/2302 ; http://etd.ncsi.iisc.ernet.in/abstracts/2962/G25467-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Varadarajan, Keshavan. “A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution.” 2012. Web. 13 Dec 2019.

Vancouver:

Varadarajan K. A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2019 Dec 13]. Available from: http://etd.iisc.ernet.in/handle/2005/2302 ; http://etd.ncsi.iisc.ernet.in/abstracts/2962/G25467-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Varadarajan K. A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution. [Thesis]. Indian Institute of Science; 2012. Available from: http://etd.iisc.ernet.in/handle/2005/2302 ; http://etd.ncsi.iisc.ernet.in/abstracts/2962/G25467-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Utah

3. Vo, Huy T. Designing a parallel dataflow architecture for streaming large-scale visualization on heterogeneous platforms.

Degree: PhD, School of Computing, 2011, University of Utah

Dataflow pipeline models are widely used in visualization systems. Despite recent advancements in parallel architecture, most systems still support only a single CPU or a… (more)

Subjects/Keywords: Dataflow architecture; Heterogeneous platforms; Multi-CPU; Multi-GPU; Parallel execution

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vo, H. T. (2011). Designing a parallel dataflow architecture for streaming large-scale visualization on heterogeneous platforms. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/342/rec/656

Chicago Manual of Style (16th Edition):

Vo, Huy T. “Designing a parallel dataflow architecture for streaming large-scale visualization on heterogeneous platforms.” 2011. Doctoral Dissertation, University of Utah. Accessed December 13, 2019. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/342/rec/656.

MLA Handbook (7th Edition):

Vo, Huy T. “Designing a parallel dataflow architecture for streaming large-scale visualization on heterogeneous platforms.” 2011. Web. 13 Dec 2019.

Vancouver:

Vo HT. Designing a parallel dataflow architecture for streaming large-scale visualization on heterogeneous platforms. [Internet] [Doctoral dissertation]. University of Utah; 2011. [cited 2019 Dec 13]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/342/rec/656.

Council of Science Editors:

Vo HT. Designing a parallel dataflow architecture for streaming large-scale visualization on heterogeneous platforms. [Doctoral Dissertation]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/342/rec/656


Virginia Tech

4. Mandlekar, Anup Shrikant. An Application Framework for a Power-Aware Processor Architecture.

Degree: MS, Electrical and Computer Engineering, 2012, Virginia Tech

 The instruction-set based general purpose processors are not energy-efficient for event-driven applications. The E-textiles group at Virginia Tech proposed a novel data-flow processor architecture design… (more)

Subjects/Keywords: Low Power Flash Memory Cells; Model Driven Engineering; Simulink; Dataflow Architecture

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mandlekar, A. S. (2012). An Application Framework for a Power-Aware Processor Architecture. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34484

Chicago Manual of Style (16th Edition):

Mandlekar, Anup Shrikant. “An Application Framework for a Power-Aware Processor Architecture.” 2012. Masters Thesis, Virginia Tech. Accessed December 13, 2019. http://hdl.handle.net/10919/34484.

MLA Handbook (7th Edition):

Mandlekar, Anup Shrikant. “An Application Framework for a Power-Aware Processor Architecture.” 2012. Web. 13 Dec 2019.

Vancouver:

Mandlekar AS. An Application Framework for a Power-Aware Processor Architecture. [Internet] [Masters thesis]. Virginia Tech; 2012. [cited 2019 Dec 13]. Available from: http://hdl.handle.net/10919/34484.

Council of Science Editors:

Mandlekar AS. An Application Framework for a Power-Aware Processor Architecture. [Masters Thesis]. Virginia Tech; 2012. Available from: http://hdl.handle.net/10919/34484

5. Ngo, Dinh Thanh. Runtime mapping of dynamic dataflow applications on heterogeneous multiprocessor platforms : Déploiement à la volée d'appllications flot de données dynamiques sur plateforme multiprocesseurs hétérogène.

Degree: Docteur es, Stic, 2015, Lorient

La complexité et le nombre toujours plus grandissant des applications, notamment les standards vidéo, nécessite d’étudier des méthodes et outils pour leur déploiement sur des… (more)

Subjects/Keywords: Architecture multiprocesseurs; Flot de données; Multi-Processors Systeme on Chips; Dataflow; 004.35

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ngo, D. T. (2015). Runtime mapping of dynamic dataflow applications on heterogeneous multiprocessor platforms : Déploiement à la volée d'appllications flot de données dynamiques sur plateforme multiprocesseurs hétérogène. (Doctoral Dissertation). Lorient. Retrieved from http://www.theses.fr/2015LORIS371

Chicago Manual of Style (16th Edition):

Ngo, Dinh Thanh. “Runtime mapping of dynamic dataflow applications on heterogeneous multiprocessor platforms : Déploiement à la volée d'appllications flot de données dynamiques sur plateforme multiprocesseurs hétérogène.” 2015. Doctoral Dissertation, Lorient. Accessed December 13, 2019. http://www.theses.fr/2015LORIS371.

MLA Handbook (7th Edition):

Ngo, Dinh Thanh. “Runtime mapping of dynamic dataflow applications on heterogeneous multiprocessor platforms : Déploiement à la volée d'appllications flot de données dynamiques sur plateforme multiprocesseurs hétérogène.” 2015. Web. 13 Dec 2019.

Vancouver:

Ngo DT. Runtime mapping of dynamic dataflow applications on heterogeneous multiprocessor platforms : Déploiement à la volée d'appllications flot de données dynamiques sur plateforme multiprocesseurs hétérogène. [Internet] [Doctoral dissertation]. Lorient; 2015. [cited 2019 Dec 13]. Available from: http://www.theses.fr/2015LORIS371.

Council of Science Editors:

Ngo DT. Runtime mapping of dynamic dataflow applications on heterogeneous multiprocessor platforms : Déploiement à la volée d'appllications flot de données dynamiques sur plateforme multiprocesseurs hétérogène. [Doctoral Dissertation]. Lorient; 2015. Available from: http://www.theses.fr/2015LORIS371

6. Li, Feng. Compiling for a multithreaded dataflow architecture : algorithms, tools, and experience : Compilation pour une architecture multi-thread à flot de données : algorithmes, outils et retour d'expérience.

Degree: Docteur es, Informatique, 2014, Université Pierre et Marie Curie – Paris VI

Quelque-soit le multiprocesseur et son architecture, la facilité de leur programmation demeure une difficulté majeure. Une croyance bien installée est que l’exploitation correcte et efficace… (more)

Subjects/Keywords: Flot de données; Parallélisation; Multiprocesseur; Architecture; Partitionnement d'un programme; Dataflow; Multiprocessors; 004

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, F. (2014). Compiling for a multithreaded dataflow architecture : algorithms, tools, and experience : Compilation pour une architecture multi-thread à flot de données : algorithmes, outils et retour d'expérience. (Doctoral Dissertation). Université Pierre et Marie Curie – Paris VI. Retrieved from http://www.theses.fr/2014PA066102

Chicago Manual of Style (16th Edition):

Li, Feng. “Compiling for a multithreaded dataflow architecture : algorithms, tools, and experience : Compilation pour une architecture multi-thread à flot de données : algorithmes, outils et retour d'expérience.” 2014. Doctoral Dissertation, Université Pierre et Marie Curie – Paris VI. Accessed December 13, 2019. http://www.theses.fr/2014PA066102.

MLA Handbook (7th Edition):

Li, Feng. “Compiling for a multithreaded dataflow architecture : algorithms, tools, and experience : Compilation pour une architecture multi-thread à flot de données : algorithmes, outils et retour d'expérience.” 2014. Web. 13 Dec 2019.

Vancouver:

Li F. Compiling for a multithreaded dataflow architecture : algorithms, tools, and experience : Compilation pour une architecture multi-thread à flot de données : algorithmes, outils et retour d'expérience. [Internet] [Doctoral dissertation]. Université Pierre et Marie Curie – Paris VI; 2014. [cited 2019 Dec 13]. Available from: http://www.theses.fr/2014PA066102.

Council of Science Editors:

Li F. Compiling for a multithreaded dataflow architecture : algorithms, tools, and experience : Compilation pour une architecture multi-thread à flot de données : algorithmes, outils et retour d'expérience. [Doctoral Dissertation]. Université Pierre et Marie Curie – Paris VI; 2014. Available from: http://www.theses.fr/2014PA066102


Indian Institute of Science

7. Satrawala, Amar Nath. RETHROTTLE : Execution Throttling In The REDEFINE SoC Architecture.

Degree: 2009, Indian Institute of Science

 REDEFINE is a reconfigurable SoC architecture that provides a unique platform for high performance and low power computing by exploiting the synergistic interaction between coarse… (more)

Subjects/Keywords: SoC Architecture; Computer Architecture; Semiconductor-on-Chip Architecture; Dataflow Models; Throttling; Computer Simulation; REDEFINE Architecture; Computer Architecture - Modeling; Hybrid Computer Simulation; Von Neumann Architecture; Coarse Grain; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Satrawala, A. N. (2009). RETHROTTLE : Execution Throttling In The REDEFINE SoC Architecture. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1017

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Satrawala, Amar Nath. “RETHROTTLE : Execution Throttling In The REDEFINE SoC Architecture.” 2009. Thesis, Indian Institute of Science. Accessed December 13, 2019. http://hdl.handle.net/2005/1017.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Satrawala, Amar Nath. “RETHROTTLE : Execution Throttling In The REDEFINE SoC Architecture.” 2009. Web. 13 Dec 2019.

Vancouver:

Satrawala AN. RETHROTTLE : Execution Throttling In The REDEFINE SoC Architecture. [Internet] [Thesis]. Indian Institute of Science; 2009. [cited 2019 Dec 13]. Available from: http://hdl.handle.net/2005/1017.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Satrawala AN. RETHROTTLE : Execution Throttling In The REDEFINE SoC Architecture. [Thesis]. Indian Institute of Science; 2009. Available from: http://hdl.handle.net/2005/1017

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universitat Pompeu Fabra

8. Arumí Albó, Pau. Real-time multimedia on off-the-shelf operating systems: from timeliness dataflow models to pattern languages.

Degree: Departament de Tecnologies de la Informació i les Comunicacions, 2009, Universitat Pompeu Fabra

 Software-based multimedia systems that deal with real-time audio, video and graphics processing are pervasive today, not only in desktop workstations but also in ultra-light devices… (more)

Subjects/Keywords: design pattern languages; time-triggered synchronous dataflow; multimedia systems; real-time operating system; callback architecture; static scheduling; dataflow; actor-oriented design; 62

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Arumí Albó, P. (2009). Real-time multimedia on off-the-shelf operating systems: from timeliness dataflow models to pattern languages. (Thesis). Universitat Pompeu Fabra. Retrieved from http://hdl.handle.net/10803/7558

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Arumí Albó, Pau. “Real-time multimedia on off-the-shelf operating systems: from timeliness dataflow models to pattern languages.” 2009. Thesis, Universitat Pompeu Fabra. Accessed December 13, 2019. http://hdl.handle.net/10803/7558.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Arumí Albó, Pau. “Real-time multimedia on off-the-shelf operating systems: from timeliness dataflow models to pattern languages.” 2009. Web. 13 Dec 2019.

Vancouver:

Arumí Albó P. Real-time multimedia on off-the-shelf operating systems: from timeliness dataflow models to pattern languages. [Internet] [Thesis]. Universitat Pompeu Fabra; 2009. [cited 2019 Dec 13]. Available from: http://hdl.handle.net/10803/7558.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Arumí Albó P. Real-time multimedia on off-the-shelf operating systems: from timeliness dataflow models to pattern languages. [Thesis]. Universitat Pompeu Fabra; 2009. Available from: http://hdl.handle.net/10803/7558

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

9. Astolfi, Vitor Fiorotto. ChipCflow - em hardware dinamicamente reconfigurável.

Degree: Mestrado, Ciências de Computação e Matemática Computacional, 2009, University of São Paulo

Nos últimos anos, houve um grande avanço na computação reconfigurável, em particular em hardware que emprega Field-Programmable Gate Arrays. Porém, esse aumento de capacidade e… (more)

Subjects/Keywords: Arquitetura a fluxo de dados; Computação reconfigurável; Dataflow architecture; Dynamic partial reconfiguration; FPGA; FPGA; Reconfigurable computing; Reconfiguração parcial dinâmica; Virtex; Virtex

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Astolfi, V. F. (2009). ChipCflow - em hardware dinamicamente reconfigurável. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/55/55134/tde-05032010-203142/ ;

Chicago Manual of Style (16th Edition):

Astolfi, Vitor Fiorotto. “ChipCflow - em hardware dinamicamente reconfigurável.” 2009. Masters Thesis, University of São Paulo. Accessed December 13, 2019. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-05032010-203142/ ;.

MLA Handbook (7th Edition):

Astolfi, Vitor Fiorotto. “ChipCflow - em hardware dinamicamente reconfigurável.” 2009. Web. 13 Dec 2019.

Vancouver:

Astolfi VF. ChipCflow - em hardware dinamicamente reconfigurável. [Internet] [Masters thesis]. University of São Paulo; 2009. [cited 2019 Dec 13]. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-05032010-203142/ ;.

Council of Science Editors:

Astolfi VF. ChipCflow - em hardware dinamicamente reconfigurável. [Masters Thesis]. University of São Paulo; 2009. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-05032010-203142/ ;


Penn State University

10. Lim, Joford T. PROGRAM ALLOCATION AND IMPLEMENTATION OF CACHE IN A DATAFLOW ENVIRONMENT.

Degree: PhD, Computer Science and Engineering, 2001, Penn State University

 The success of multithreaded systems depends on how quickly context switching between threads can be achieved. Fast context switch is only possible if threads are… (more)

Subjects/Keywords: dataflow; program allocation; loop scheduling; computer architecture; cache

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lim, J. T. (2001). PROGRAM ALLOCATION AND IMPLEMENTATION OF CACHE IN A DATAFLOW ENVIRONMENT. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/5885

Chicago Manual of Style (16th Edition):

Lim, Joford T. “PROGRAM ALLOCATION AND IMPLEMENTATION OF CACHE IN A DATAFLOW ENVIRONMENT.” 2001. Doctoral Dissertation, Penn State University. Accessed December 13, 2019. https://etda.libraries.psu.edu/catalog/5885.

MLA Handbook (7th Edition):

Lim, Joford T. “PROGRAM ALLOCATION AND IMPLEMENTATION OF CACHE IN A DATAFLOW ENVIRONMENT.” 2001. Web. 13 Dec 2019.

Vancouver:

Lim JT. PROGRAM ALLOCATION AND IMPLEMENTATION OF CACHE IN A DATAFLOW ENVIRONMENT. [Internet] [Doctoral dissertation]. Penn State University; 2001. [cited 2019 Dec 13]. Available from: https://etda.libraries.psu.edu/catalog/5885.

Council of Science Editors:

Lim JT. PROGRAM ALLOCATION AND IMPLEMENTATION OF CACHE IN A DATAFLOW ENVIRONMENT. [Doctoral Dissertation]. Penn State University; 2001. Available from: https://etda.libraries.psu.edu/catalog/5885


Virginia Tech

11. Guo, Jinghong. Distributed, Modular, Open Control Architecture for Power Conversion Systems.

Degree: PhD, Electrical and Computer Engineering, 2005, Virginia Tech

 Due to close coupling to hardware and lack of software engineering technologies, the control software in digitally controlled power conversion systems is difficult to design… (more)

Subjects/Keywords: PEBB; real-time system; open control architecture; dataflow

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Guo, J. (2005). Distributed, Modular, Open Control Architecture for Power Conversion Systems. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/27900

Chicago Manual of Style (16th Edition):

Guo, Jinghong. “Distributed, Modular, Open Control Architecture for Power Conversion Systems.” 2005. Doctoral Dissertation, Virginia Tech. Accessed December 13, 2019. http://hdl.handle.net/10919/27900.

MLA Handbook (7th Edition):

Guo, Jinghong. “Distributed, Modular, Open Control Architecture for Power Conversion Systems.” 2005. Web. 13 Dec 2019.

Vancouver:

Guo J. Distributed, Modular, Open Control Architecture for Power Conversion Systems. [Internet] [Doctoral dissertation]. Virginia Tech; 2005. [cited 2019 Dec 13]. Available from: http://hdl.handle.net/10919/27900.

Council of Science Editors:

Guo J. Distributed, Modular, Open Control Architecture for Power Conversion Systems. [Doctoral Dissertation]. Virginia Tech; 2005. Available from: http://hdl.handle.net/10919/27900


University of North Texas

12. Shelor, Charles F. Dataflow Processing in Memory Achieves Significant Energy Efficiency.

Degree: 2018, University of North Texas

 The large difference between processor CPU cycle time and memory access time, often referred to as the memory wall, severely limits the performance of streaming… (more)

Subjects/Keywords: Computer architecture; dataflow; processing in memory; coarse grain reconfigurable logic; energy efficient; 3D memory; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shelor, C. F. (2018). Dataflow Processing in Memory Achieves Significant Energy Efficiency. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc1248478/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shelor, Charles F. “Dataflow Processing in Memory Achieves Significant Energy Efficiency.” 2018. Thesis, University of North Texas. Accessed December 13, 2019. https://digital.library.unt.edu/ark:/67531/metadc1248478/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shelor, Charles F. “Dataflow Processing in Memory Achieves Significant Energy Efficiency.” 2018. Web. 13 Dec 2019.

Vancouver:

Shelor CF. Dataflow Processing in Memory Achieves Significant Energy Efficiency. [Internet] [Thesis]. University of North Texas; 2018. [cited 2019 Dec 13]. Available from: https://digital.library.unt.edu/ark:/67531/metadc1248478/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shelor CF. Dataflow Processing in Memory Achieves Significant Energy Efficiency. [Thesis]. University of North Texas; 2018. Available from: https://digital.library.unt.edu/ark:/67531/metadc1248478/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. Cavenaghi, Marcos Antônio. Implementação de um simulador para a arquitetura de dados Wolf.

Degree: Mestrado, Física Aplicada, 1992, University of São Paulo

Esse trabalho apresenta a Proto-Arquitetura a fluxo de dados WOLF e trata da implementação de um simulador simplificado dirigido a eventos para essa arquitetura. O… (more)

Subjects/Keywords: Arquitetura Fluxo de Dados; Dataflow architecture; Simulação; Simulation; Wolf; Wolf

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cavenaghi, M. A. (1992). Implementação de um simulador para a arquitetura de dados Wolf. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/54/54132/tde-08062009-102639/ ;

Chicago Manual of Style (16th Edition):

Cavenaghi, Marcos Antônio. “Implementação de um simulador para a arquitetura de dados Wolf.” 1992. Masters Thesis, University of São Paulo. Accessed December 13, 2019. http://www.teses.usp.br/teses/disponiveis/54/54132/tde-08062009-102639/ ;.

MLA Handbook (7th Edition):

Cavenaghi, Marcos Antônio. “Implementação de um simulador para a arquitetura de dados Wolf.” 1992. Web. 13 Dec 2019.

Vancouver:

Cavenaghi MA. Implementação de um simulador para a arquitetura de dados Wolf. [Internet] [Masters thesis]. University of São Paulo; 1992. [cited 2019 Dec 13]. Available from: http://www.teses.usp.br/teses/disponiveis/54/54132/tde-08062009-102639/ ;.

Council of Science Editors:

Cavenaghi MA. Implementação de um simulador para a arquitetura de dados Wolf. [Masters Thesis]. University of São Paulo; 1992. Available from: http://www.teses.usp.br/teses/disponiveis/54/54132/tde-08062009-102639/ ;

14. Lopes, Joelmir José. ChipCflow - uma ferramenta para execução de algoritmos utilizando o modelo a fluxo de dados dinâmico em hardware reconfigurável.

Degree: PhD, Ciências de Computação e Matemática Computacional, 2012, University of São Paulo

Devido à complexidade das aplicações, a demanda crescente por sistemas que usam milhões de transistores e hardware complexo; tem sido desenvolvidas ferramentas que convertem C… (more)

Subjects/Keywords: Arquiteturas a fluxo de dados dinâmicas; Asynchronous implementation model in FPGA; Dynamic dataflow architecture; Modelo de implementação assíncrona em FPGA; Parallel systems; Sistemas paralelos

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lopes, J. J. (2012). ChipCflow - uma ferramenta para execução de algoritmos utilizando o modelo a fluxo de dados dinâmico em hardware reconfigurável. (Doctoral Dissertation). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/55/55134/tde-05122012-154304/ ;

Chicago Manual of Style (16th Edition):

Lopes, Joelmir José. “ChipCflow - uma ferramenta para execução de algoritmos utilizando o modelo a fluxo de dados dinâmico em hardware reconfigurável.” 2012. Doctoral Dissertation, University of São Paulo. Accessed December 13, 2019. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-05122012-154304/ ;.

MLA Handbook (7th Edition):

Lopes, Joelmir José. “ChipCflow - uma ferramenta para execução de algoritmos utilizando o modelo a fluxo de dados dinâmico em hardware reconfigurável.” 2012. Web. 13 Dec 2019.

Vancouver:

Lopes JJ. ChipCflow - uma ferramenta para execução de algoritmos utilizando o modelo a fluxo de dados dinâmico em hardware reconfigurável. [Internet] [Doctoral dissertation]. University of São Paulo; 2012. [cited 2019 Dec 13]. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-05122012-154304/ ;.

Council of Science Editors:

Lopes JJ. ChipCflow - uma ferramenta para execução de algoritmos utilizando o modelo a fluxo de dados dinâmico em hardware reconfigurável. [Doctoral Dissertation]. University of São Paulo; 2012. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-05122012-154304/ ;

15. Cavenaghi, Marcos Antônio. Implementação e estudo da arquitetura a fluxo de dados Wolf.

Degree: PhD, Física Aplicada, 1997, University of São Paulo

Esse trabalho apresenta a arquitetura a fluxo de dados Wolf. Essa arquitetura foi proposta considerando-se alguns problemas conhecidos em execução de código em arquiteturas a… (more)

Subjects/Keywords: Arquitetura Fluxo de dados; Dataflow architecture; Simulação; Simulation; Wolf; Wolf

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cavenaghi, M. A. (1997). Implementação e estudo da arquitetura a fluxo de dados Wolf. (Doctoral Dissertation). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/76/76132/tde-01062009-111139/ ;

Chicago Manual of Style (16th Edition):

Cavenaghi, Marcos Antônio. “Implementação e estudo da arquitetura a fluxo de dados Wolf.” 1997. Doctoral Dissertation, University of São Paulo. Accessed December 13, 2019. http://www.teses.usp.br/teses/disponiveis/76/76132/tde-01062009-111139/ ;.

MLA Handbook (7th Edition):

Cavenaghi, Marcos Antônio. “Implementação e estudo da arquitetura a fluxo de dados Wolf.” 1997. Web. 13 Dec 2019.

Vancouver:

Cavenaghi MA. Implementação e estudo da arquitetura a fluxo de dados Wolf. [Internet] [Doctoral dissertation]. University of São Paulo; 1997. [cited 2019 Dec 13]. Available from: http://www.teses.usp.br/teses/disponiveis/76/76132/tde-01062009-111139/ ;.

Council of Science Editors:

Cavenaghi MA. Implementação e estudo da arquitetura a fluxo de dados Wolf. [Doctoral Dissertation]. University of São Paulo; 1997. Available from: http://www.teses.usp.br/teses/disponiveis/76/76132/tde-01062009-111139/ ;


New Jersey Institute of Technology

16. Sathe, Anish Arvind. Configurable computer systems can support dataflow computing.

Degree: MSin Electrical Engineering - (M.S.), Electrical and Computer Engineering, 2003, New Jersey Institute of Technology

  This work presents a practical implementation of a uni-processor system design. This design, named D2-CPU, satisfies the pure <i>data-driven</i> paradigm, which is a radical… (more)

Subjects/Keywords: Computer architecture; Dataflow computing; Data driven paradigm; Electrical and Electronics

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sathe, A. A. (2003). Configurable computer systems can support dataflow computing. (Thesis). New Jersey Institute of Technology. Retrieved from https://digitalcommons.njit.edu/theses/530

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sathe, Anish Arvind. “Configurable computer systems can support dataflow computing.” 2003. Thesis, New Jersey Institute of Technology. Accessed December 13, 2019. https://digitalcommons.njit.edu/theses/530.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sathe, Anish Arvind. “Configurable computer systems can support dataflow computing.” 2003. Web. 13 Dec 2019.

Vancouver:

Sathe AA. Configurable computer systems can support dataflow computing. [Internet] [Thesis]. New Jersey Institute of Technology; 2003. [cited 2019 Dec 13]. Available from: https://digitalcommons.njit.edu/theses/530.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sathe AA. Configurable computer systems can support dataflow computing. [Thesis]. New Jersey Institute of Technology; 2003. Available from: https://digitalcommons.njit.edu/theses/530

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

17. Alle, Mythri. Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm.

Degree: 2012, Indian Institute of Science

 Coarse-Grained Reconfigurable Architectures(CGRAs) can be employed for accelerating computational workloads that demand both flexibility and performance. CGRAs comprise a set of computation elements interconnected using… (more)

Subjects/Keywords: Coarse-Grained Reconfigurable Architecture (CGRA); Reconfigurable Fabric; Dataflow Execution; Compilers (Computer Programs); Computer Architecture; Reconfigurable Architectures; Coarse-Grained Reconfigurable Architectures (CGRAs); Run Time Reconfigurable Platform; Runtime Reconfigurable Platform; Runtime Reconfigurable Hardware; Coarse Grained Computation; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Alle, M. (2012). Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2453

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Alle, Mythri. “Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm.” 2012. Thesis, Indian Institute of Science. Accessed December 13, 2019. http://hdl.handle.net/2005/2453.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Alle, Mythri. “Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm.” 2012. Web. 13 Dec 2019.

Vancouver:

Alle M. Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2019 Dec 13]. Available from: http://hdl.handle.net/2005/2453.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Alle M. Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm. [Thesis]. Indian Institute of Science; 2012. Available from: http://hdl.handle.net/2005/2453

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

18. Alle, Mythri. Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm.

Degree: 2012, Indian Institute of Science

 Coarse-Grained Reconfigurable Architectures(CGRAs) can be employed for accelerating computational workloads that demand both flexibility and performance. CGRAs comprise a set of computation elements interconnected using… (more)

Subjects/Keywords: Coarse-Grained Reconfigurable Architecture (CGRA); Reconfigurable Fabric; Dataflow Execution; Compilers (Computer Programs); Computer Architecture; Reconfigurable Architectures; Coarse-Grained Reconfigurable Architectures (CGRAs); Run Time Reconfigurable Platform; Runtime Reconfigurable Platform; Runtime Reconfigurable Hardware; Coarse Grained Computation; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Alle, M. (2012). Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2453 ; http://etd.ncsi.iisc.ernet.in/abstracts/3167/G25487-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Alle, Mythri. “Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm.” 2012. Thesis, Indian Institute of Science. Accessed December 13, 2019. http://etd.iisc.ernet.in/handle/2005/2453 ; http://etd.ncsi.iisc.ernet.in/abstracts/3167/G25487-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Alle, Mythri. “Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm.” 2012. Web. 13 Dec 2019.

Vancouver:

Alle M. Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2019 Dec 13]. Available from: http://etd.iisc.ernet.in/handle/2005/2453 ; http://etd.ncsi.iisc.ernet.in/abstracts/3167/G25487-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Alle M. Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm. [Thesis]. Indian Institute of Science; 2012. Available from: http://etd.iisc.ernet.in/handle/2005/2453 ; http://etd.ncsi.iisc.ernet.in/abstracts/3167/G25487-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Lowell, Nicholas Stephen. Model-based Software Design Tools for the Cell Processor.

Degree: MS, Electrical Engineering, 2009, Vanderbilt University

 This thesis presents a multi-core architecture, the Cell processor, and an updated model-based tool suite named the Signal Processing Platform (SPP) that supports development of… (more)

Subjects/Keywords: domain specific modeling language; automatic target recognition; model-based design; multi-core architecture; dataflow modeling; code generation; cell processor

…the language. I have adopted the Cell Broadband Engine Architecture (or, Cell)—the… …multi-core architecture resulting from the collaborative efforts of IBM, Sony, and Toshiba—and… …the Cell architecture. Chapter four introduces the SPP tool chain—the modeling language… …cores. The architecture may require the cores to share as much as cache, memory, and busses… …source. shows different possible core architecture designs. Figure 1. Different Processor… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lowell, N. S. (2009). Model-based Software Design Tools for the Cell Processor. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu//available/etd-03302009-113308/ ;

Chicago Manual of Style (16th Edition):

Lowell, Nicholas Stephen. “Model-based Software Design Tools for the Cell Processor.” 2009. Masters Thesis, Vanderbilt University. Accessed December 13, 2019. http://etd.library.vanderbilt.edu//available/etd-03302009-113308/ ;.

MLA Handbook (7th Edition):

Lowell, Nicholas Stephen. “Model-based Software Design Tools for the Cell Processor.” 2009. Web. 13 Dec 2019.

Vancouver:

Lowell NS. Model-based Software Design Tools for the Cell Processor. [Internet] [Masters thesis]. Vanderbilt University; 2009. [cited 2019 Dec 13]. Available from: http://etd.library.vanderbilt.edu//available/etd-03302009-113308/ ;.

Council of Science Editors:

Lowell NS. Model-based Software Design Tools for the Cell Processor. [Masters Thesis]. Vanderbilt University; 2009. Available from: http://etd.library.vanderbilt.edu//available/etd-03302009-113308/ ;


Virginia Tech

20. Menon, Suraj S. Supporting Distributed Fault Tolerance In A Real-Time Micro-Kernel.

Degree: MS, Computer Science, 2006, Virginia Tech

 Research into modular approaches for constructing power electronics control systems has provided a number of benefits, as well as new opportunities. Control systems composed of… (more)

Subjects/Keywords: fault tolerance; fault-tolerant real-time offline scheduling; power electronics control system; dual ring fault tolerant protocol; power electronics; power converter; fault tolerance; fault tolerant micro-kernel; dataflow architecture; real-time; offline; precedence constraints

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Menon, S. S. (2006). Supporting Distributed Fault Tolerance In A Real-Time Micro-Kernel. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/35463

Chicago Manual of Style (16th Edition):

Menon, Suraj S. “Supporting Distributed Fault Tolerance In A Real-Time Micro-Kernel.” 2006. Masters Thesis, Virginia Tech. Accessed December 13, 2019. http://hdl.handle.net/10919/35463.

MLA Handbook (7th Edition):

Menon, Suraj S. “Supporting Distributed Fault Tolerance In A Real-Time Micro-Kernel.” 2006. Web. 13 Dec 2019.

Vancouver:

Menon SS. Supporting Distributed Fault Tolerance In A Real-Time Micro-Kernel. [Internet] [Masters thesis]. Virginia Tech; 2006. [cited 2019 Dec 13]. Available from: http://hdl.handle.net/10919/35463.

Council of Science Editors:

Menon SS. Supporting Distributed Fault Tolerance In A Real-Time Micro-Kernel. [Masters Thesis]. Virginia Tech; 2006. Available from: http://hdl.handle.net/10919/35463

.