subject:(DVFS)

1. Zahaf, Houssam-Eddine. Energy efficient scheduling of parallel real-time tasks on heterogeneous multicore systems : Minimisation de la consommation d'énergie pour des taches temps-réels parallèles sur des architectures multicoeurs hétérogènes.

Degree: Docteur es, Informatique, 2016, Université Lille I – Sciences et Technologies

URL: http://www.theses.fr/2016LIL10100

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Les systèmes cyber-physiques (CPS) et d’Internet des objets génèrent un volume et une variété des données sans précédant. Le temps que ces données parcourent le… (more)

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Les systèmes cyber-physiques (CPS) et d’Internet des objets génèrent un volume et une variété des données sans précédant. Le temps que ces données parcourent le réseau dans son chemin vers le cloud, la possibilité de réagir à un événement critique pourrait être tardive. Pour résoudre ce problème, les traitements de données nécessitant une réponse rapide sont faits à proximité d’où les données sont collectées. Ainsi, seuls les résultats du pré-traitement sont envoyées au cloud et la réaction pourrai être déclenché suffisamment rapide pour préserver l’intégrité du système. Ce modèle de calcul est connu comme Fog Computing. Un large spectre d’applications de CPS ont des contraintes temporelle et peuvent être facilement parallélisées en distribuant les calculs sur différents sous-ensembles de données en même temps. Ceci peut permettre d’obtenir un temps de réponse plus court et un temps de creux plus large. Ainsi, on peut réduire la fréquence du processeur et/ou éteindre des parties du processeur afin de réduire la consommation d’énergie. Dans cette thèse, nous nous concentrons sur le problème d'ordonnancement d’un ensemble de taches temps-réels parallèles sur des architectures multi-coeurs dans l’objectif de réduire la consommation d’énergie en respectant toutes les contraintes temporelles. Nous proposons ainsi plusieurs modèles de tâches et des testes d'ordonnançabilité pour résoudre le problème d’allocation des threads aux processeurs. Nous proposons aussi des méthodes qui permettent de sélectionner les fréquences et les états des processeurs. Les modèles proposés peuvent être implantés comme des directives dans la même logique que OpenMP.

Cyber physical systems (CPS) and Internet of Objects (IoT) are generating an unprecedented volume and variety of data that needs to be collected and stored on the cloud before being processed. By the time the data makes its way to the cloud for analysis, the opportunity to trigger a reply might be late. One approach to solve this problem is to analyze the most time-sensitive data at the network edge, close to where it is generated. Thus, only the pre-processed results are sent to the cloud. This computation model is know as *Fog Computing* or *Edge computing*. Critical CPS applications using the fog computing model may have real-time constraints because results must be delivered in a pre-determined time window. Furthermore, in many relevant applications of CPS, the processing can be parallelized by applying the same processing on different sub-sets of data at the same time by the mean parallel programming techniques. This allow to achieve a shorter response time, and then, a larger slack time, which can be used to reduce energy consumption. In this thesis we focus on the problem of scheduling a set of parallel tasks on multicore processors, with the goal of reducing the energy consumption while all deadlines are met. We propose several realistic task models on architectures with identical and heterogeneous cores, and we develop algorithms for allocating threads to processors,…

Advisors/Committee Members: Olejnik, Richard (thesis director), Benyamina, Abou el hassan (thesis director).

Subjects/Keywords: DVFS- DPM; 004.33

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Zahaf, H. (2016). Energy efficient scheduling of parallel real-time tasks on heterogeneous multicore systems : Minimisation de la consommation d'énergie pour des taches temps-réels parallèles sur des architectures multicoeurs hétérogènes. (Doctoral Dissertation). Université Lille I – Sciences et Technologies. Retrieved from http://www.theses.fr/2016LIL10100

Chicago Manual of Style (16^th Edition):

Zahaf, Houssam-Eddine. “Energy efficient scheduling of parallel real-time tasks on heterogeneous multicore systems : Minimisation de la consommation d'énergie pour des taches temps-réels parallèles sur des architectures multicoeurs hétérogènes.” 2016. Doctoral Dissertation, Université Lille I – Sciences et Technologies. Accessed February 27, 2021. http://www.theses.fr/2016LIL10100.

MLA Handbook (7^th Edition):

Zahaf, Houssam-Eddine. “Energy efficient scheduling of parallel real-time tasks on heterogeneous multicore systems : Minimisation de la consommation d'énergie pour des taches temps-réels parallèles sur des architectures multicoeurs hétérogènes.” 2016. Web. 27 Feb 2021.

Vancouver:

Zahaf H. Energy efficient scheduling of parallel real-time tasks on heterogeneous multicore systems : Minimisation de la consommation d'énergie pour des taches temps-réels parallèles sur des architectures multicoeurs hétérogènes. [Internet] [Doctoral dissertation]. Université Lille I – Sciences et Technologies; 2016. [cited 2021 Feb 27]. Available from: http://www.theses.fr/2016LIL10100.

Council of Science Editors:

Zahaf H. Energy efficient scheduling of parallel real-time tasks on heterogeneous multicore systems : Minimisation de la consommation d'énergie pour des taches temps-réels parallèles sur des architectures multicoeurs hétérogènes. [Doctoral Dissertation]. Université Lille I – Sciences et Technologies; 2016. Available from: http://www.theses.fr/2016LIL10100

Texas A&M University

2. Won, Jae Yeon. Dynamic Voltage and Frequency Scaling Techniques for Chip Multiprocessor Designs.

Degree: PhD, Computer Engineering, 2015, Texas A&M University

URL: http://hdl.handle.net/1969.1/155587

► Due to chip power density limitations as well as the recent breakdown of Dennard's Scalingover the past decade, performance growth in microprocessor design has largely… (more)

▼ Due to chip power density limitations as well as the recent breakdown of Dennard's Scalingover the past decade, performance growth in microprocessor design has largely been driven by core scaling. These trends have led to Chip Multi- Processor(CMP) designs, currently with tens of cores, and expected to grow to the thousands in the pursuit of exascale computing. The more complicated CMP design is more leading power consumption relatively in computer architecture. The increased power consumption generates thermal issues, and so performance degradation. Therefore, it is certain that power efficient algorithm in CMP and main memory are essential. For the power efficiency, we focus on dynamic voltage/frequency scaling (DVFS) techniques for CMP and main memory. In the first work, we focus on the "uncore", consisting of an on-chip communication fabric and shared LLC in CMP. The uncore now occupies as much as 30% of the overall die area, which is not negligible in CMP design, but has rarely researched. We find there are predictable patterns in uncore utility which point towards the potential of a proactive approach to uncore power management. In this work, we utilize artificial intelligence principles to proactively leverage uncore utility pattern prediction via an Artificial Neural Network (ANN). Even though the uncore takes non-negligible portion of CMP power consumption, processor cores still exist as major power consumers. For core DVFS, We explore a novel approach with the potential to achieve synergistic energy-savings and performance gain in chip multiprocessors (CMPs). In current designs, performance must typically be traded-off to achieve energy savings or, conversely, performance gains come with significant energy overhead. Resources shared by processor cores, such as on-chip interconnect and shared memory, play an increasingly critical role in determining the overall CMP performance. Our key observation is that per-core DVFS can be used as a client regulation mechanism for the shared resources. Based on this observation, we propose a new DVFS technique inspired by TCP Vegas, a congestion control protocol from the IP-networking domain. In addition to uncore in CMP, main memory is also critical shared resource in total system. As uncore is critical resource for CMP performance while occupying critical portion of total CMP energy consumed, main memory is also critical for total performance and accounts for large fraction of total energy consumption. Most conventional approaches focused on utilization of cores and memory only for memory power management. We found, however, the uncore plays an important role of total system performance and its utilization must be considered as well for memory power management. From the observation, we propose shared resource utilization aware power management technique for main memory. Our technique chooses low V/F level of memory for some congested case in uncore, and so derives negligible performance degradation while saving more energy by the low V/F level. We also proposed… Advisors/Committee Members: Hu, Jiang (advisor), Gratz, Paul V (advisor), Xie, Le (committee member), Stoleru, Radu (committee member).

Subjects/Keywords: power management; DVFS; CMP; resource

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Won, J. Y. (2015). Dynamic Voltage and Frequency Scaling Techniques for Chip Multiprocessor Designs. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/155587

Chicago Manual of Style (16^th Edition):

Won, Jae Yeon. “Dynamic Voltage and Frequency Scaling Techniques for Chip Multiprocessor Designs.” 2015. Doctoral Dissertation, Texas A&M University. Accessed February 27, 2021. http://hdl.handle.net/1969.1/155587.

MLA Handbook (7^th Edition):

Won, Jae Yeon. “Dynamic Voltage and Frequency Scaling Techniques for Chip Multiprocessor Designs.” 2015. Web. 27 Feb 2021.

Vancouver:

Won JY. Dynamic Voltage and Frequency Scaling Techniques for Chip Multiprocessor Designs. [Internet] [Doctoral dissertation]. Texas A&M University; 2015. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/1969.1/155587.

Council of Science Editors:

Won JY. Dynamic Voltage and Frequency Scaling Techniques for Chip Multiprocessor Designs. [Doctoral Dissertation]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/155587

University of Minnesota

3. Satapathy, Saroj. A Revolving Reference Odometer Circuit for BTI-Induced Frequency Fluctuation Measurements under Fast DVFS Transients and Reconfigurable Feed Forward MUX PUF Design.

Degree: M.S.E.E., Electrical Engineering, 2014, University of Minnesota

URL: http://hdl.handle.net/11299/183283

► The frequency shift due to fast Bias Temperature Instability (BTI) related fast Dynamic Voltage and Frequency Scaled (DVFS) stress-recovery effects were measured using a high… (more)

Subjects/Keywords: BTI; DVFS; Odometer; PUF; reference; revolving

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Satapathy, S. (2014). A Revolving Reference Odometer Circuit for BTI-Induced Frequency Fluctuation Measurements under Fast DVFS Transients and Reconfigurable Feed Forward MUX PUF Design. (Masters Thesis). University of Minnesota. Retrieved from http://hdl.handle.net/11299/183283

Chicago Manual of Style (16^th Edition):

Satapathy, Saroj. “A Revolving Reference Odometer Circuit for BTI-Induced Frequency Fluctuation Measurements under Fast DVFS Transients and Reconfigurable Feed Forward MUX PUF Design.” 2014. Masters Thesis, University of Minnesota. Accessed February 27, 2021. http://hdl.handle.net/11299/183283.

MLA Handbook (7^th Edition):

Satapathy, Saroj. “A Revolving Reference Odometer Circuit for BTI-Induced Frequency Fluctuation Measurements under Fast DVFS Transients and Reconfigurable Feed Forward MUX PUF Design.” 2014. Web. 27 Feb 2021.

Vancouver:

Satapathy S. A Revolving Reference Odometer Circuit for BTI-Induced Frequency Fluctuation Measurements under Fast DVFS Transients and Reconfigurable Feed Forward MUX PUF Design. [Internet] [Masters thesis]. University of Minnesota; 2014. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/11299/183283.

Council of Science Editors:

Satapathy S. A Revolving Reference Odometer Circuit for BTI-Induced Frequency Fluctuation Measurements under Fast DVFS Transients and Reconfigurable Feed Forward MUX PUF Design. [Masters Thesis]. University of Minnesota; 2014. Available from: http://hdl.handle.net/11299/183283

University of Arizona

4. Gajaria, Dhruv Mayur. DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors .

Degree: 2019, University of Arizona

URL: http://hdl.handle.net/10150/633246

► Spin-transfer torque RAMs (STT-RAMs) have been studied as a promising alternative to SRAMs in emerging caches and main memories due to their low leakage power… (more)

▼ Spin-transfer torque RAMs (STT-RAMs) have been studied as a promising alternative to SRAMs in emerging caches and main memories due to their low leakage power and high density. However, STT-RAMs, also have drawbacks of high dynamic write energy and long write latency. Relaxing the retention time of the non-volatile STT-RAM has been widely studied as a way to reduce STT-RAM's write energy and latency. However, since different applications may require different retention times, STT-RAM retention times must be critically explored to satisfy various applications' needs. This process can be challenging due to exploration overhead, and exacerbated by the fact that STT-RAM caches are emerging and are not readily available for design time exploration. This work explores using known statistics (e.g., SRAM statistics) to predict the appropriate STT-RAM retention times, in order to minimize exploration overhead. We propose an STT-RAM Cache Retention Time (SCART) model, which utilizes machine learning to enable design time or runtime prediction of best STT-RAM retention times for latency or energy optimization. Furthermore, we analyze the impacts of dynamic voltage and frequency scaling (DVFS) – a common optimization in modern processors – on STT-RAM L1 cache design. Our analysis reveals that, apart from the fact that different applications may require different retention times, the clock frequency, which is typically ignored in most STT-RAM studies, may also significantly impact applications' retention time needs. Based on our findings, we propose an asymmetric-retention core (ARC) design for multicore architectures. ARC features retention time heterogeneity to specialize STT-RAM retention times to applications' needs. We also propose a runtime prediction model to determine the best core on which to run an application, based on the applications' characteristics, their retention time requirements, and available DVFS settings. Results reveal that the proposed approach can reduce the average cache energy by 39.21% and overall processor energy by 13.66%, compared to an SRAM-based system, and by 20.19% and 7.66%, respectively, compared to a homogeneous STT-RAM cache design. Advisors/Committee Members: Adegbija, Tosiron (advisor), Lysecky, Roman (committeemember), Akoglu, Ali (committeemember).

Subjects/Keywords: Caches; DVFS; Multi-Core Processors; STT-RAM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Gajaria, D. M. (2019). DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/633246

Chicago Manual of Style (16^th Edition):

Gajaria, Dhruv Mayur. “DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors .” 2019. Masters Thesis, University of Arizona. Accessed February 27, 2021. http://hdl.handle.net/10150/633246.

MLA Handbook (7^th Edition):

Gajaria, Dhruv Mayur. “DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors .” 2019. Web. 27 Feb 2021.

Vancouver:

Gajaria DM. DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors . [Internet] [Masters thesis]. University of Arizona; 2019. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/10150/633246.

Council of Science Editors:

Gajaria DM. DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors . [Masters Thesis]. University of Arizona; 2019. Available from: http://hdl.handle.net/10150/633246

5. Heinrich, Franz. Modélisation, prédiction et optimisation de la consommation énergétique d'applications MPI à l'aide de SimGrid : Modeling, Prediction and Optimization of Energy Consumption of MPI Applications using SimGrid.

Degree: Docteur es, Informatique, 2019, Grenoble Alpes

URL: http://www.theses.fr/2019GREAM018

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Les changements technologiques dans la communauté du calcul hauteperformance (HPC) sont importants, en particulier dans le secteurdu parallélisme massif avec plusieurs milliers de cœurs de… (more)

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Les changements technologiques dans la communauté du calcul hauteperformance (HPC) sont importants, en particulier dans le secteurdu parallélisme massif avec plusieurs milliers de cœurs de calcul sur unGPU unique ou accélérateur, et aussi des nouveaux réseaux complexes.La consommation d’énergie de ces machines continuera de croître dans les années à venir,faisant de l’énergie l’un des principaux facteurs de coût.Cela explique pourquoi même la métrique classique"flop / s", généralement utilisé pour évaluer les applications HPC etles machines, est progressivement remplacé par une métrique centré surl’énergie en "flop / watt".Une approche pour prédire la consommation d'énergie se fait parsimulation, cependant, une prédiction précise de la performance estcruciale pour estimer l’énergie. Dans cette thèse, nouscontribuons à la prédiction de performance et d'énergie des architectures HPC.Nous proposons un modèle énergétique qui a été implémenté dans unsimulateur open source, sg. Nous validons ce modèle avec soin eten le comparant systématiquement avec des expériences réelles.Nous utilisons cette contribution pour évaluer les projetsexistants et nous proposons de nouveaux governors DVFS spécialementconçus pour le contexte HPC.

The High-Performance Computing (HPC) community is currently undergoingdisruptive technology changes in almost all fields, including a switch towardsmassive parallelism with several thousand compute cores on a single GPU oraccelerator and new, complex networks. Powering a massively parallel machinebecomesThe energy consumption of these machines will continue to grow in the future,making energy one of the principal cost factors of machine ownership. This explainswhy even the classic metric "flop/s", generally used to evaluate HPC applicationsand machines, is widely regarded as to be replaced by an energy-centric metric"flop/watt".One approach to predict energy consumption is through simulation, however, a pre-cise performance prediction is crucial to estimate the energy faithfully. In this thesis,we contribute to the performance and energy prediction of HPC architectures. Wepropose an energy model which we have implemented in the open source SimGridsimulator. We validate this model by carefully and systematically comparing itwith real experiments. We leverage this contribution to both evaluate existingand propose new DVFS governors that are part*icularly designed to suit the HPCcontext.

Advisors/Committee Members: Legrand, Arnaud (thesis director).

Subjects/Keywords: Performance; Dvfs; Hpc; Prédiction; Energie; Simulation; Performance; Dvfs; Hpc; Energy; Simulation; Prédiction; 004

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Heinrich, F. (2019). Modélisation, prédiction et optimisation de la consommation énergétique d'applications MPI à l'aide de SimGrid : Modeling, Prediction and Optimization of Energy Consumption of MPI Applications using SimGrid. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2019GREAM018

Chicago Manual of Style (16^th Edition):

Heinrich, Franz. “Modélisation, prédiction et optimisation de la consommation énergétique d'applications MPI à l'aide de SimGrid : Modeling, Prediction and Optimization of Energy Consumption of MPI Applications using SimGrid.” 2019. Doctoral Dissertation, Grenoble Alpes. Accessed February 27, 2021. http://www.theses.fr/2019GREAM018.

MLA Handbook (7^th Edition):

Heinrich, Franz. “Modélisation, prédiction et optimisation de la consommation énergétique d'applications MPI à l'aide de SimGrid : Modeling, Prediction and Optimization of Energy Consumption of MPI Applications using SimGrid.” 2019. Web. 27 Feb 2021.

Vancouver:

Heinrich F. Modélisation, prédiction et optimisation de la consommation énergétique d'applications MPI à l'aide de SimGrid : Modeling, Prediction and Optimization of Energy Consumption of MPI Applications using SimGrid. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2019. [cited 2021 Feb 27]. Available from: http://www.theses.fr/2019GREAM018.

Council of Science Editors:

Heinrich F. Modélisation, prédiction et optimisation de la consommation énergétique d'applications MPI à l'aide de SimGrid : Modeling, Prediction and Optimization of Energy Consumption of MPI Applications using SimGrid. [Doctoral Dissertation]. Grenoble Alpes; 2019. Available from: http://www.theses.fr/2019GREAM018

Universidade do Rio Grande do Sul

6. Millani, Luís Felipe Garlet. Uma metodologia de avaliação de desempenho para identificar as melhore regiões paralelas para reduzir o consumo de energia.

Degree: 2015, Universidade do Rio Grande do Sul

URL: http://hdl.handle.net/10183/131874

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Due to energy limitations imposed to supercomputers, parallel applications developed for High Performance Computers (HPC) are currently being investigated with energy efficiency metrics. The idea… (more)

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Due to energy limitations imposed to supercomputers, parallel applications developed for High Performance Computers (HPC) are currently being investigated with energy efficiency metrics. The idea is to reduce the energy footprint of these applications. While some energy reduction strategies consider the application as a whole, certain strategies adjust the core frequency only for certain regions of the parallel code. Load balancing or blocking communication phases could be used as opportunities for energy reduction, for instance. The efficiency analysis of such strategies is usually carried out with traditional methodologies derived from the performance analysis domain. It is clear that a finer grain methodology, where the energy reduction is evaluated per each code region and frequency configuration, could potentially lead to a better understanding of how energy consumption can be reduced for a particular algorithm implementation. To get this, the main challenges are: (a) the detection of such, possibly parallel, code regions and the large number of them; (b) which frequency should be adopted for that region (to reduce energy consumption without too much penalty for the runtime); and (c) the cost to dynamically adjust core frequency. The work described in this dissertation presents a performance analysis methodology to find the best parallel region candidates to reduce energy consumption. The proposal is three folded: (a) a clever design of experiments based on screening, especially important when a large number of parallel regions is detected in the applications; (b) a traditional energy and performance evaluation on the regions that were considered as good candidates for energy reduction; and (c) a Pareto-based analysis showing how hard is to obtain energy gains in optimized codes. In (c), we also show other trade-offs between performance loss and energy gains that might be of interest of the application developer. Our approach is validated against three HPC application codes: Graph500; Breadth-First Search, and Delaunay Refinement.

Devido as limitações de consumo energético impostas a supercomputadores, métricas de eficiência energética estão sendo usadas para analisar aplicações paralelas desenvolvidas para computadores de alto desempenho. O objetivo é a redução do custo energético dessas aplicações. Algumas estratégias de redução de consumo energética consideram a aplicação como um todo, outras reduzem ajustam a frequência dos núcleos apenas em certas regiões do código paralelo. Fases de balanceamento de carga ou de comunicação bloqueante podem ser oportunas para redução do consumo energético. A análise de eficiência dessas estratégias é geralmente realizada com metodologias tradicionais derivadas do domínio de análise de desempenho. Uma metodologia de grão mais fino, onde a redução de energia é avaliada para cada região de código e frequência pode lever a um melhor entendimento de como o consumo energético pode ser minimizado para uma determinada implementação. Para tal, os principais desafios são: (a) a…

Advisors/Committee Members: Maillard, Nicolas Bruno.

Subjects/Keywords: Methodology; Supercomputadores; Energy; Processamento paralelo; HPC; DVFS; Multicore; Performance; OpenMP

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APA (6^th Edition):

Millani, L. F. G. (2015). Uma metodologia de avaliação de desempenho para identificar as melhore regiões paralelas para reduzir o consumo de energia. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/131874

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Millani, Luís Felipe Garlet. “Uma metodologia de avaliação de desempenho para identificar as melhore regiões paralelas para reduzir o consumo de energia.” 2015. Thesis, Universidade do Rio Grande do Sul. Accessed February 27, 2021. http://hdl.handle.net/10183/131874.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Millani, Luís Felipe Garlet. “Uma metodologia de avaliação de desempenho para identificar as melhore regiões paralelas para reduzir o consumo de energia.” 2015. Web. 27 Feb 2021.

Vancouver:

Millani LFG. Uma metodologia de avaliação de desempenho para identificar as melhore regiões paralelas para reduzir o consumo de energia. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2015. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/10183/131874.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Millani LFG. Uma metodologia de avaliação de desempenho para identificar as melhore regiões paralelas para reduzir o consumo de energia. [Thesis]. Universidade do Rio Grande do Sul; 2015. Available from: http://hdl.handle.net/10183/131874

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

7. BARRETO NETO, Antônio Correia de Sá. gDFS: Um Mecanismo de Otimização Para Redução de Consumo de Energia em Smartphones Através de Uma Estratégia Baseada em Grupos de Aplicações .

Degree: 2014, Universidade Federal de Pernambuco

URL: http://repositorio.ufpe.br/handle/123456789/10961

► Houve, nos últimos anos, um aumento bastante significativo do uso de smartphones. No final de 2011, havia 6 bilhões de assinantes, de acordo com a… (more)

Subjects/Keywords: Android; DVFS; CPUFreq; Consumo de energia; Chaveamento de frequência; Otimização energética

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

BARRETO NETO, A. C. d. S. (2014). gDFS: Um Mecanismo de Otimização Para Redução de Consumo de Energia em Smartphones Através de Uma Estratégia Baseada em Grupos de Aplicações . (Thesis). Universidade Federal de Pernambuco. Retrieved from http://repositorio.ufpe.br/handle/123456789/10961

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

BARRETO NETO, Antônio Correia de Sá. “gDFS: Um Mecanismo de Otimização Para Redução de Consumo de Energia em Smartphones Através de Uma Estratégia Baseada em Grupos de Aplicações .” 2014. Thesis, Universidade Federal de Pernambuco. Accessed February 27, 2021. http://repositorio.ufpe.br/handle/123456789/10961.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

BARRETO NETO, Antônio Correia de Sá. “gDFS: Um Mecanismo de Otimização Para Redução de Consumo de Energia em Smartphones Através de Uma Estratégia Baseada em Grupos de Aplicações .” 2014. Web. 27 Feb 2021.

Vancouver:

BARRETO NETO ACdS. gDFS: Um Mecanismo de Otimização Para Redução de Consumo de Energia em Smartphones Através de Uma Estratégia Baseada em Grupos de Aplicações . [Internet] [Thesis]. Universidade Federal de Pernambuco; 2014. [cited 2021 Feb 27]. Available from: http://repositorio.ufpe.br/handle/123456789/10961.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

BARRETO NETO ACdS. gDFS: Um Mecanismo de Otimização Para Redução de Consumo de Energia em Smartphones Através de Uma Estratégia Baseada em Grupos de Aplicações . [Thesis]. Universidade Federal de Pernambuco; 2014. Available from: http://repositorio.ufpe.br/handle/123456789/10961

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of California – Irvine

8. Lin, Sonny. Android Application Level CPU DVFS Tuning.

Degree: Computer Science, 2014, University of California – Irvine

URL: http://www.escholarship.org/uc/item/6c32f1v2

► Battery life and performance are two important aspects for smart phone devices. The Android platform runs on top of the Linux kernel. The Linux kernel… (more)

Subjects/Keywords: Computer science; Android; CPU DVFS; Rooted; Screen; Tuning; Utilization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lin, S. (2014). Android Application Level CPU DVFS Tuning. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/6c32f1v2

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lin, Sonny. “Android Application Level CPU DVFS Tuning.” 2014. Thesis, University of California – Irvine. Accessed February 27, 2021. http://www.escholarship.org/uc/item/6c32f1v2.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lin, Sonny. “Android Application Level CPU DVFS Tuning.” 2014. Web. 27 Feb 2021.

Vancouver:

Lin S. Android Application Level CPU DVFS Tuning. [Internet] [Thesis]. University of California – Irvine; 2014. [cited 2021 Feb 27]. Available from: http://www.escholarship.org/uc/item/6c32f1v2.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin S. Android Application Level CPU DVFS Tuning. [Thesis]. University of California – Irvine; 2014. Available from: http://www.escholarship.org/uc/item/6c32f1v2

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Texas A&M University

9. Xu, Tong. Circuit and System Level Design Optimization for Power Delivery And Management.

Degree: PhD, Computer Engineering, 2014, Texas A&M University

URL: http://hdl.handle.net/1969.1/154126

► As the VLSI technology scales to the nanometer scale, power consumption has become a critical design concern of VLSI circuits. Power gating and dynamic voltage… (more)

▼ As the VLSI technology scales to the nanometer scale, power consumption has become a critical design concern of VLSI circuits. Power gating and dynamic voltage and frequency scaling (DVFS) are two effective power management techniques that are widely utilized in modern chip designs. Various design challenges merge with these power management techniques in nanometer VLSI circuits. For example, power gating introduces unique power integrity issues and trade-offs between switching noise and rush current noise. Assuring power integrity and achieving power efficiency are two highly intertwined design challenges. In addition, these trade-offs significantly vary with the supply voltage. It is difficult to use conventional power-gated power delivery networks (PDNs) to fully meet the involved conflicting design constraints while maximizing power saving and minimizing supply noise. The DVFS controller and the DC-DC power converter are two highly intertwining enablers for DVFS-based systems. However, traditional DVFS techniques treat the design optimizations of the two as separate tasks, giving rise to sub-optimal designs. To address the above research challenges, we propose several circuit and system level design optimization techniques in this dissertation. For power-gated PDN designs, we propose systemic decoupling capacitor (decap) optimization strategies that optimally trade-off between power integrity and leakage saving. First, new global decap and re-routable decap design concepts are proposed to relax the tight interaction between power integrity and leakage power saving of power-gated PDN at a single supply voltage level. Furthermore, we propose to leverage re-routable decaps to provide flexible decap allocation structures to better suit multiple supply voltage levels. The proposed strategies are implemented in an automatic design flow for choosing optimal amount of local decaps, global decaps and re-routable decaps. The proposed techniques significantly increase leakage saving without jeopardizing power integrity. The flexible decap allocations enabled by re-routable decaps lead to optimal design trade-offs for PDNs operating with two supply voltage levels. To improve the effectiveness of DVFS, we analyze the drawbacks of circuit-level only and policy-level only optimizations and the promising opportunities resulted from the cross-layer co-optimization of the DC-DC converter and online learning based DVFS polices. We present a cross-layer approach that optimizes transition time, area, energy overhead of the DC-DC converter along with key parameters of an online learning DVFS controller. We systematically evaluate the benefits of the proposed co-optimization strategy based on several processor architectures, namely single and dual-core processors and processors with DVFS and power gating. Our results indicate that the co-optimization can introduce noticeable additional energy saving without significant performance degradation. Advisors/Committee Members: Li, Peng (advisor), Gratz, Paul V. (committee member), Mahapatra, Rabi N. (committee member), Datta, Aniruddha (committee member).

Subjects/Keywords: power management; power delivery network; power gating; DVFS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Xu, T. (2014). Circuit and System Level Design Optimization for Power Delivery And Management. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/154126

Chicago Manual of Style (16^th Edition):

Xu, Tong. “Circuit and System Level Design Optimization for Power Delivery And Management.” 2014. Doctoral Dissertation, Texas A&M University. Accessed February 27, 2021. http://hdl.handle.net/1969.1/154126.

MLA Handbook (7^th Edition):

Xu, Tong. “Circuit and System Level Design Optimization for Power Delivery And Management.” 2014. Web. 27 Feb 2021.

Vancouver:

Xu T. Circuit and System Level Design Optimization for Power Delivery And Management. [Internet] [Doctoral dissertation]. Texas A&M University; 2014. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/1969.1/154126.

Council of Science Editors:

Xu T. Circuit and System Level Design Optimization for Power Delivery And Management. [Doctoral Dissertation]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/154126

North Carolina State University

10. Lim, Min Yeol. Improving Power and Performance Efficiency in Parallel and Distributed Computing Systems.

Degree: PhD, Computer Science, 2009, North Carolina State University

URL: http://www.lib.ncsu.edu/resolver/1840.16/5662

► For decades, high-performance computing systems have focused on increasing maximum performance at any cost. A consequence of the devotion towards boosting performance significantly increases power… (more)

▼ For decades, high-performance computing systems have focused on increasing maximum performance at any cost. A consequence of the devotion towards boosting performance significantly increases power consumption. The most powerful supercomputers require up to 10 megawatts of peak power Ã¢â‚¬â€œ enough to sustain a city of 40,000. However, some of that power may be wasted with little or no performance gain, because applications do not require peak performance all the time. Therefore, improving power and performance efficiency becomes one of the primary concerns in parallel and distributed computing. Our goal is to build a runtime system that can understand power-performance tradeoffs and balance power consumption and performance penalty adaptively. In this thesis, we make the following contributions. First, we develop a MPI runtime system that can dynamically balance power and performance tradeoffs in MPI applications. Our system dynamically identifies power saving opportunities without prior knowledge about system behaviors and then determines the best p-state to improve the power and performance efficiency. The system is entirely transparent to MPI applications with no user intervention. Second, we develop a method for determining minimum energy consumption in voltage and frequency scaling systems for a given time delay. Our approach helps to better analyze the performance of a specific DVFS algorithm in terms of balancing power and performance. Third, we develop a power prediction model that can correlate power and performance data on a chip multiprocessor machine. Our model shows that the power consumption can be estimated by hardware performance counters with reasonable accuracy in various execution environments. Given the prediction model, one can make a runtime decision of balancing power and performance tradeoffs on a chip-multiprocessor machine without delay for actual power measurements. Last, we develop an algorithm to save power by dynamically migrating virtual machines and placing them onto fewer physical machines depending on workloads. Our scheme uses a two-level, adaptive buffering scheme which reserves processing capacity. It is designed to adapt the buffer sizes to workloads in order to balance performance violations and energy savings by reducing the amount of energy wasted on the buffers. Our simulation framework justifies our study of the energy benefits and the performance effects of the algorithm along with studies of its sensitivity to various parameters. Advisors/Committee Members: Dr. George N. Rouskas, Committee Member (advisor), Dr. Gregory T. Byrd, Committee Member (advisor), Dr. Xiaosong Ma, Committee Member (advisor), Dr. Robert J. Fowler, Committee Member (advisor), Dr. Vincent W. Freeh, Committee Chair (advisor).

Subjects/Keywords: Virtualization; DVFS; Power aware computing; Parallel and distributed system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lim, M. Y. (2009). Improving Power and Performance Efficiency in Parallel and Distributed Computing Systems. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/5662

Chicago Manual of Style (16^th Edition):

Lim, Min Yeol. “Improving Power and Performance Efficiency in Parallel and Distributed Computing Systems.” 2009. Doctoral Dissertation, North Carolina State University. Accessed February 27, 2021. http://www.lib.ncsu.edu/resolver/1840.16/5662.

MLA Handbook (7^th Edition):

Lim, Min Yeol. “Improving Power and Performance Efficiency in Parallel and Distributed Computing Systems.” 2009. Web. 27 Feb 2021.

Vancouver:

Lim MY. Improving Power and Performance Efficiency in Parallel and Distributed Computing Systems. [Internet] [Doctoral dissertation]. North Carolina State University; 2009. [cited 2021 Feb 27]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/5662.

Council of Science Editors:

Lim MY. Improving Power and Performance Efficiency in Parallel and Distributed Computing Systems. [Doctoral Dissertation]. North Carolina State University; 2009. Available from: http://www.lib.ncsu.edu/resolver/1840.16/5662

Washington State University

11. [No author]. Wireless NoC and Voltage Frequency Island Co-Design for Energy-Efficient Manycore Platforms .

Degree: 2016, Washington State University

URL: http://hdl.handle.net/2376/12099

► Multiple Voltage Frequency Island (VFI)-based designs present a scalable power management strategy for manycore chips. However, the overall communication backbone, which relies predominantly on Networks-on-Chip… (more)

▼ Multiple Voltage Frequency Island (VFI)-based designs present a scalable power management strategy for manycore chips. However, the overall communication backbone, which relies predominantly on Networks-on-Chip (NoCs), dictates the achievable performance. Emerging paradigms, such as the small-world wireless NoC (WiNoC), can be utilized to help improve the performance of manycore chips over traditional NoCs. The achievable energy savings in a VFI-enabled manycore system depends on the control mechanism for V/F tuning. A simple control module can statically tune the voltage/frequency (V/F) of each VFI to the average workload requirements of the application. This allows large energy savings while ensuring that the system is able to accomplish its task within the specified time-frame. However, most applications have time-varying workload requirements. VFI-based designs can take advantage of this time-varying nature through dynamic V/F allocation of each VFI. When dynamically adjusting the V/F of the VFIs, the state of the system must be partially or fully known; this involves the transfer of information from the cores to the V/F control module. Here, the WiNoC's higher bandwidth and low-latency communication is well-suited for efficient dynamic VFI (DVFI) control. Due to the variations within each VFI cluster, the selection of a single V/F that suits all cores within a VFI is a crucial and difficult problem. In this dissertation, we demonstrate that Machine Learning (ML) techniques can learn accurate DVFI control policies to improve the energy-efficiency of manycore systems. This DVFI control policy jointly predicts the V/F assignment for all VFIs by leveraging the structural relationships between them. In this dissertation, we demonstrate how the emerging WiNoC architecture is able to complement and enhance VFI-partitioned systems. By implementing a VFI-aware WiNoC, the penalties associated with inter-VFI communication are mitigated, DVFI control knowledge can be transmitted more efficiently, and the performance of the system can be significantly improved. Also, we have demonstrated control mechanisms that allow us, in conjunction with the VFI-aware WiNoC architecture, to achieve significant energy savings with practically no performance penalty. This opens up a new of class of co-design approaches that can make WiNoCs the communication technology of choice for future manycore platforms. Advisors/Committee Members: Pande, Partha P (advisor), Marculescu, Radu (advisor).

Subjects/Keywords: Computer engineering; DVFS; Machine Learning; NoC; VFI; WiNoC

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APA (6^th Edition):

author], [. (2016). Wireless NoC and Voltage Frequency Island Co-Design for Energy-Efficient Manycore Platforms . (Thesis). Washington State University. Retrieved from http://hdl.handle.net/2376/12099

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

author], [No. “Wireless NoC and Voltage Frequency Island Co-Design for Energy-Efficient Manycore Platforms .” 2016. Thesis, Washington State University. Accessed February 27, 2021. http://hdl.handle.net/2376/12099.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

author], [No. “Wireless NoC and Voltage Frequency Island Co-Design for Energy-Efficient Manycore Platforms .” 2016. Web. 27 Feb 2021.

Vancouver:

author] [. Wireless NoC and Voltage Frequency Island Co-Design for Energy-Efficient Manycore Platforms . [Internet] [Thesis]. Washington State University; 2016. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/2376/12099.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. Wireless NoC and Voltage Frequency Island Co-Design for Energy-Efficient Manycore Platforms . [Thesis]. Washington State University; 2016. Available from: http://hdl.handle.net/2376/12099

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

George Mason University

12. Li, Xin. GreenVideo: A Framework for Energy-Efficient Video Streaming to Handheld Devices .

Degree: 2013, George Mason University

URL: http://hdl.handle.net/1920/8469

► With the exponentially growing smartphone market, more and more people desire to have a multipurpose handheld device that not only supports voice communication and text… (more)

Subjects/Keywords: mobile video streaming; handheld devices; 3G/4G; Codec; DVFS; display adaptation

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APA (6^th Edition):

Li, X. (2013). GreenVideo: A Framework for Energy-Efficient Video Streaming to Handheld Devices . (Thesis). George Mason University. Retrieved from http://hdl.handle.net/1920/8469

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Li, Xin. “GreenVideo: A Framework for Energy-Efficient Video Streaming to Handheld Devices .” 2013. Thesis, George Mason University. Accessed February 27, 2021. http://hdl.handle.net/1920/8469.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Li, Xin. “GreenVideo: A Framework for Energy-Efficient Video Streaming to Handheld Devices .” 2013. Web. 27 Feb 2021.

Vancouver:

Li X. GreenVideo: A Framework for Energy-Efficient Video Streaming to Handheld Devices . [Internet] [Thesis]. George Mason University; 2013. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/1920/8469.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li X. GreenVideo: A Framework for Energy-Efficient Video Streaming to Handheld Devices . [Thesis]. George Mason University; 2013. Available from: http://hdl.handle.net/1920/8469

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. Janzén, Johan. Evaluation of Energy-Optimizing Scheduling Algorithms for Streaming Computations on Massively Parallel Multicore Architectures.

Degree: The Institute of Technology, 2014, Linköping UniversityLinköping University

URL: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-111385

► This thesis describes an environment to evaluate and compare static schedulers for real pipelined streaming applications on massively parallel architectures, such as Intel Single… (more)

Subjects/Keywords: Intel SCC; DVFS; Task based programming; Static scheduling; Energy efficiency; Multicore

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APA (6^th Edition):

Janzén, J. (2014). Evaluation of Energy-Optimizing Scheduling Algorithms for Streaming Computations on Massively Parallel Multicore Architectures. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-111385

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Janzén, Johan. “Evaluation of Energy-Optimizing Scheduling Algorithms for Streaming Computations on Massively Parallel Multicore Architectures.” 2014. Thesis, Linköping UniversityLinköping University. Accessed February 27, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-111385.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Janzén, Johan. “Evaluation of Energy-Optimizing Scheduling Algorithms for Streaming Computations on Massively Parallel Multicore Architectures.” 2014. Web. 27 Feb 2021.

Vancouver:

Janzén J. Evaluation of Energy-Optimizing Scheduling Algorithms for Streaming Computations on Massively Parallel Multicore Architectures. [Internet] [Thesis]. Linköping UniversityLinköping University; 2014. [cited 2021 Feb 27]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-111385.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Janzén J. Evaluation of Energy-Optimizing Scheduling Algorithms for Streaming Computations on Massively Parallel Multicore Architectures. [Thesis]. Linköping UniversityLinköping University; 2014. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-111385

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Edinburgh

14. Mohd Tadza, Noor Zahrinah Binti. Energy efficient design of an adaptive switching algorithm for the iterative-MIMO receiver.

Degree: PhD, 2015, University of Edinburgh

URL: http://hdl.handle.net/1842/11711

► An efficient design dedicated for iterative-multiple-input multiple-output (MIMO) receiver systems is now imperative in our world since data demands are increasing tremendously in wireless networks.… (more)

▼ An efficient design dedicated for iterative-multiple-input multiple-output (MIMO) receiver systems is now imperative in our world since data demands are increasing tremendously in wireless networks. This puts a massive burden on the signal processing power especially in small receiver systems where power sources are often shared or limited. This thesis proposes an attractive solution to both the wireless signal processing and the architectural implementation design sides of the problem. A novel algorithm, dubbed the Adaptive Switching Algorithm, is proven to not only save more than a third of the energy consumption in the algorithmic design, but is also able to achieve an energy reduction of more than 50% in terms of processing power when the design is mapped onto state-of-the-art programmable hardware. Simulations are based in MatlabTM using the Monte Carlo approach, where multiple additive white Gaussian noise (AWGN) and Rayleigh fading channels for both fast and slow fading environments were investigated. The software selects the appropriate detection algorithm depending on the current channel conditions. The design for the hardware is based on the latest field programmable gate arrays (FPGA) hardware from Xilinx R , specifically the Virtex-5 and Virtex-7 chipsets. They were chosen during the experimental phase to verify the results in order to examine trends for energy consumption in the proposed algorithm design. Savings come from dynamic allocation of the hardware resources by implementing power minimization techniques depending on the processing requirements of the system. Having demonstrated the feasibility of the algorithm in controlled environments, realistic channel conditions were simulated using spatially correlated MIMO channels to test the algorithm’s readiness for real-world deployment. The proposed algorithm is placed in both the MIMO detector and the iterative-decoder blocks of the receiver. When the final full receiver design setup is implemented, it shows that the key to energy saving lies in the fact that both software and hardware components of the Adaptive Switching Algorithm adopt adaptivity in the respective designs. The detector saves energy by selecting suitable detection schemes while the decoder provides adaptivity by limiting the number of decoding iterations, both of which are updated in real-time. The overall receiver can achieve more than 70% energy savings in comparison to state-of-the-art iterative-MIMO receivers and thus it can be concluded that this level of ‘intelligence’ is an important direction towards a more efficient iterative-MIMO receiver designs in the future.

Subjects/Keywords: 621.384; iterative-MIMO; turbo; FPGA; power savings; DVFS; sleep mode; parallelization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Mohd Tadza, N. Z. B. (2015). Energy efficient design of an adaptive switching algorithm for the iterative-MIMO receiver. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/11711

Chicago Manual of Style (16^th Edition):

Mohd Tadza, Noor Zahrinah Binti. “Energy efficient design of an adaptive switching algorithm for the iterative-MIMO receiver.” 2015. Doctoral Dissertation, University of Edinburgh. Accessed February 27, 2021. http://hdl.handle.net/1842/11711.

MLA Handbook (7^th Edition):

Mohd Tadza, Noor Zahrinah Binti. “Energy efficient design of an adaptive switching algorithm for the iterative-MIMO receiver.” 2015. Web. 27 Feb 2021.

Vancouver:

Mohd Tadza NZB. Energy efficient design of an adaptive switching algorithm for the iterative-MIMO receiver. [Internet] [Doctoral dissertation]. University of Edinburgh; 2015. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/1842/11711.

Council of Science Editors:

Mohd Tadza NZB. Energy efficient design of an adaptive switching algorithm for the iterative-MIMO receiver. [Doctoral Dissertation]. University of Edinburgh; 2015. Available from: http://hdl.handle.net/1842/11711

University of Georgia

15. Ho, Chiahsun. Reducing scheduling overheads in multi-processors real-time systems.

Degree: 2014, University of Georgia

URL: http://hdl.handle.net/10724/28757

► In real-time systems, it is required to complete all work on a timely basis. There are mainly two types of real time systems: hard real-time… (more)

Subjects/Keywords: Real-Time System; Reducing scheduling overhead; Multiprocessor real-time scheduling; DVFS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Ho, C. (2014). Reducing scheduling overheads in multi-processors real-time systems. (Thesis). University of Georgia. Retrieved from http://hdl.handle.net/10724/28757

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Ho, Chiahsun. “Reducing scheduling overheads in multi-processors real-time systems.” 2014. Thesis, University of Georgia. Accessed February 27, 2021. http://hdl.handle.net/10724/28757.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Ho, Chiahsun. “Reducing scheduling overheads in multi-processors real-time systems.” 2014. Web. 27 Feb 2021.

Vancouver:

Ho C. Reducing scheduling overheads in multi-processors real-time systems. [Internet] [Thesis]. University of Georgia; 2014. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/10724/28757.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ho C. Reducing scheduling overheads in multi-processors real-time systems. [Thesis]. University of Georgia; 2014. Available from: http://hdl.handle.net/10724/28757

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of New South Wales

16. Carroll, Aaron. Understanding and reducing smartphone energy consumption.

Degree: Computer Science & Engineering, 2017, University of New South Wales

URL: http://handle.unsw.edu.au/1959.4/58018 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:45287/SOURCE02?view=true

► Modern smartphones are increasingly performant and feature-rich, but because they are battery powered, remain highly power-constrained. Energy management is the art and science of maximising… (more)

▼ Modern smartphones are increasingly performant and feature-rich, but because they are battery powered, remain highly power-constrained. Energy management is the art and science of maximising battery lifetime, and effectively doing so requires a solid understanding of how a devices uses energy to inform policy and algorithms backed by accurate data. This work addresses each of these issues.First, we present a detailed power analysis of two smartphones, the Openmoko Freerunner and the Samsung Galaxy S III. We measure power consumption by direct instrumentation at the circuit level by interposing on the power supplies of the individual components, including CPU, RAM, display, GPU, wireless radios, camera, GPS, storage, audio, and environmental sensors. With this instrumentation in place, we produce breakdowns of how energy is distributed under micro-benchmarks and realistic usage scenarios. We also measure two other devices at the whole-system level to validate our earlier results, and to draw conclusions about how smartphone power consumption is changing over time. Additional to the results presented, we also describe a methodology for instrumenting commercial mass-market off-the-shelf devices.Based on these measurements we observe that peak CPU energy consumption is increasing due to the advent of multi-core processors in the mobile segment. Thus, effective power management of these will be important for battery life on future mobile devices. Such multi-core processors add a new dimension, the number cores active, to the spectrum of available energy management mechanisms.In the second part of this work we investigate how this mechanism, which we call core offlining, interacts with the well-established technique of dynamic voltage and frequency scaling (DVFS) for minimising power consumption. We find surprising differences in the characteristics of contemporaneous smartphones, specifically in the importance of static power, which we show to be a critical factor in minimising energy consumption. We design and implement medusa, a policy that exploits our findings to integrate core offlining with DVFS in the Linux kernel. We show that despite its simplicity, medusa obtains energy savings that are at least as good as, and often better than, the algorithms that ship on the studied phones, and that it approaches the optimal static algorithm. Advisors/Committee Members: Heiser, Gernot, Computer Science & Engineering, Faculty of Engineering, UNSW.

Subjects/Keywords: Operating systems; Power management; Energy management; Multi-core; DVFS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Carroll, A. (2017). Understanding and reducing smartphone energy consumption. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/58018 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:45287/SOURCE02?view=true

Chicago Manual of Style (16^th Edition):

Carroll, Aaron. “Understanding and reducing smartphone energy consumption.” 2017. Doctoral Dissertation, University of New South Wales. Accessed February 27, 2021. http://handle.unsw.edu.au/1959.4/58018 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:45287/SOURCE02?view=true.

MLA Handbook (7^th Edition):

Carroll, Aaron. “Understanding and reducing smartphone energy consumption.” 2017. Web. 27 Feb 2021.

Vancouver:

Carroll A. Understanding and reducing smartphone energy consumption. [Internet] [Doctoral dissertation]. University of New South Wales; 2017. [cited 2021 Feb 27]. Available from: http://handle.unsw.edu.au/1959.4/58018 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:45287/SOURCE02?view=true.

Council of Science Editors:

Carroll A. Understanding and reducing smartphone energy consumption. [Doctoral Dissertation]. University of New South Wales; 2017. Available from: http://handle.unsw.edu.au/1959.4/58018 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:45287/SOURCE02?view=true

Texas State University – San Marcos

17. Mahajan, Divya. Energy efficiency analysis and optimization of relational and NoSQL databases.

Degree: MS, Computer Science, 2016, Texas State University – San Marcos

URL: https://digital.library.txstate.edu/handle/10877/6963

► As big data becomes the norm of various industrial applications, the complexity of database workloads and database system design has increased significantly. To address these… (more)

▼ As big data becomes the norm of various industrial applications, the complexity of database workloads and database system design has increased significantly. To address these challenges, conventional relational databases have been constantly improved and NoSQL databases such as MongoDB and Cassandra have been proposed and implemented to compete with SQL databases. In addition to traditional metrics such as response time, throughput, and capacity, modern database systems are posing higher requirements on energy efficiency due to the large volume of data that need to be stored, queried, updated, and analyzed. While decades of research in the database and data processing communities has produced a wealth of literature that optimize for performance, research on optimizations for energy efficiency has been historically overlooked and only very few studies have investigated the energy efficiency of database systems. To the best our knowledge, currently no comprehensive studies analyze the impact of query optimizations on performance and energy efficiency across both SQL and NoSQL databases. In fact, the energy behavior of many basic database operations (e.g. insertion, deletion, searching, update, indexing, etc) remains largely unknown due to the lack of accurate power measurement methodologies for various databases and queries. In this thesis, we developed a tool that can accurately measure the real-time power consumption of queries running on both SQL and NoSQL databases and investigated a series of query optimization techniques for improving the energy-efficiency of both Relational Databases and NoSQL Parallel databases. We used both widely acceptable benchmarks (e.g. Yahoo! Cloud Server Benchmark) and customized datasets (converted from 100GB of Twitter data) in our experiments to evaluate the effectiveness of optimization techniques. We performed cross database analysis on SQL based database (MySQL) and NoSQL based databases (MongoDB and Cassandra) to compare their performance and energy efficiency. Additionally, we studied a variety of optimization techniques that can improve energy efficiency without compromising performance on the databases derived from the Twitter data. Using these techniques, we were able to achieve significant energy savings without performance degradation. Advisors/Committee Members: Zong, Ziliang (advisor), Lu, Yijuan (committee member), Yang, Guowei (committee member).

Subjects/Keywords: Energy efficiency; Optimization; Relational databases; NoSQL; MongoDB; DVFS; Cassandra; MySQL

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Mahajan, D. (2016). Energy efficiency analysis and optimization of relational and NoSQL databases. (Masters Thesis). Texas State University – San Marcos. Retrieved from https://digital.library.txstate.edu/handle/10877/6963

Chicago Manual of Style (16^th Edition):

Mahajan, Divya. “Energy efficiency analysis and optimization of relational and NoSQL databases.” 2016. Masters Thesis, Texas State University – San Marcos. Accessed February 27, 2021. https://digital.library.txstate.edu/handle/10877/6963.

MLA Handbook (7^th Edition):

Mahajan, Divya. “Energy efficiency analysis and optimization of relational and NoSQL databases.” 2016. Web. 27 Feb 2021.

Vancouver:

Mahajan D. Energy efficiency analysis and optimization of relational and NoSQL databases. [Internet] [Masters thesis]. Texas State University – San Marcos; 2016. [cited 2021 Feb 27]. Available from: https://digital.library.txstate.edu/handle/10877/6963.

Council of Science Editors:

Mahajan D. Energy efficiency analysis and optimization of relational and NoSQL databases. [Masters Thesis]. Texas State University – San Marcos; 2016. Available from: https://digital.library.txstate.edu/handle/10877/6963

King Abdullah University of Science and Technology

18. Ahmad, Enas M. Energy Efficient Smartphones: Minimizing the Energy Consumption of Smartphone GPUs using DVFS Governors.

Degree: Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division, 2013, King Abdullah University of Science and Technology

URL: http://hdl.handle.net/10754/292322

► Modern smartphones are being designed with increasing processing power, memory capacity, network communication, and graphics performance. Although all of these features are enriching and expanding… (more)

Subjects/Keywords: smart phone; energy; GPU; DVFS; Linux CPUFRQ; scaling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Ahmad, E. M. (2013). Energy Efficient Smartphones: Minimizing the Energy Consumption of Smartphone GPUs using DVFS Governors. (Thesis). King Abdullah University of Science and Technology. Retrieved from http://hdl.handle.net/10754/292322

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Ahmad, Enas M. “Energy Efficient Smartphones: Minimizing the Energy Consumption of Smartphone GPUs using DVFS Governors.” 2013. Thesis, King Abdullah University of Science and Technology. Accessed February 27, 2021. http://hdl.handle.net/10754/292322.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Ahmad, Enas M. “Energy Efficient Smartphones: Minimizing the Energy Consumption of Smartphone GPUs using DVFS Governors.” 2013. Web. 27 Feb 2021.

Vancouver:

Ahmad EM. Energy Efficient Smartphones: Minimizing the Energy Consumption of Smartphone GPUs using DVFS Governors. [Internet] [Thesis]. King Abdullah University of Science and Technology; 2013. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/10754/292322.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ahmad EM. Energy Efficient Smartphones: Minimizing the Energy Consumption of Smartphone GPUs using DVFS Governors. [Thesis]. King Abdullah University of Science and Technology; 2013. Available from: http://hdl.handle.net/10754/292322

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Aupy, Guillaume. Resilient and energy-efficient scheduling algorithms at scale : Algorithmes d'ordonnancement fiables et efficaces énergétiquement à l'échelle.

Degree: Docteur es, Informatique, 2014, Lyon, École normale supérieure

URL: http://www.theses.fr/2014ENSL0928

►

Dans cette thèse, j'ai considéré d'un point de vue théorique deux problèmes importants pour les futures plateformes dîtes Exascales : les restrictions liées à leur… (more)

▼

Dans cette thèse, j'ai considéré d'un point de vue théorique deux problèmes importants pour les futures plateformes dîtes Exascales : les restrictions liées à leur fiabilité ainsi que les contraintes énergétiques. En première partie de cette thèse, je me suis intéressé à l'étude de placements optimal de ces checkpoints dans un but de minimisation de temps total d'exécution. En particulier, j'ai considéré les checkpoints périodiques et coordonnés. J'ai considéré des prédicteurs de fautes capables de prévoir, de manière imparfaite, les fautes arrivant sur la plateforme. Dans ce contexte, j'ai conçu des algorithmes efficaces pour résoudre mes problèmes. Dans un deuxième temps, j'ai considéré des fautes silencieuses. Ces fautes ne peuvent être détectées qu'uniquement par un système de vérification.Dans le cas où une de ces fautes est détectée, l'utilisateur doit retourner au point de sauvegarde le plus récent qui n'a pas été affecté par cette faute, si un tel point existe ! Dans ce contexte, j'ai à nouveau proposé des algorithmes optimaux au premier ordre, mixant points de sauvegarde et points de vérification. Dans la seconde partie de cette thèse, j'ai considéré des problèmes énergétiques liés à ces mêmes plateformes. Ces problèmes critiques doivent être reliés aux problèmes de fiabilité de la partie précédente. Dans ce contexte, j'ai couplé des techniques de baisse de consommation énergétique à des techniques d'augmentation de fiabilité comme la reexécution, la réplication ainsi que le checkpoint. Pour ces différents problèmes, j'ai pu fournir des algorithmes dont l'efficacité a été montrée soit au travers de simulations, soit grâce à des preuves mathématiques.

This thesis deals with two issues for future Exascale platforms, namelyresilience and energy.In the first part of this thesis, we focus on the optimal placement ofperiodic coordinated checkpoints to minimize execution time.We consider fault predictors, a software used by system administratorsthat tries to predict (through the study of passed events) where andwhen faults will strike. In this context, we propose efficientalgorithms, and give a first-order optimal formula for the amount ofwork that should be done between two checkpoints.We then focus on silent data corruption errors. Contrarily to fail-stopfailures, such latent errors cannot be detected immediately, and amechanism to detect them must be provided. We compute the optimal periodin order to minimize the waste.In the second part of the thesis we address the energy consumptionchallenge.The speed scaling technique consists in diminishing the voltage of theprocessor, hence diminishing its execution speed. Unfortunately, it waspointed out that DVFS increases the probability of failures. In thiscontext, we consider the speed scaling technique coupled withreliability-increasing techniques such as re-execution, replication orcheckpointing. For these different problems, we propose variousalgorithms whose efficiency is shown either through thoroughsimulations, or approximation results relatively to the…

Advisors/Committee Members: Benoit, Anne (thesis director).

Subjects/Keywords: Fiabilité; Énergie; Checkpointing; Prédiction; Silent errors; Dvfs; Théorie; Algorithmes; Ordonnancement; Exascale; Reliability; Energy; Checkpointing; Prediction; Silent errors; Dvfs; Theory; Algorithms; Scheduling; Exascale

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Aupy, G. (2014). Resilient and energy-efficient scheduling algorithms at scale : Algorithmes d'ordonnancement fiables et efficaces énergétiquement à l'échelle. (Doctoral Dissertation). Lyon, École normale supérieure. Retrieved from http://www.theses.fr/2014ENSL0928

Chicago Manual of Style (16^th Edition):

Aupy, Guillaume. “Resilient and energy-efficient scheduling algorithms at scale : Algorithmes d'ordonnancement fiables et efficaces énergétiquement à l'échelle.” 2014. Doctoral Dissertation, Lyon, École normale supérieure. Accessed February 27, 2021. http://www.theses.fr/2014ENSL0928.

MLA Handbook (7^th Edition):

Aupy, Guillaume. “Resilient and energy-efficient scheduling algorithms at scale : Algorithmes d'ordonnancement fiables et efficaces énergétiquement à l'échelle.” 2014. Web. 27 Feb 2021.

Vancouver:

Aupy G. Resilient and energy-efficient scheduling algorithms at scale : Algorithmes d'ordonnancement fiables et efficaces énergétiquement à l'échelle. [Internet] [Doctoral dissertation]. Lyon, École normale supérieure; 2014. [cited 2021 Feb 27]. Available from: http://www.theses.fr/2014ENSL0928.

Council of Science Editors:

Aupy G. Resilient and energy-efficient scheduling algorithms at scale : Algorithmes d'ordonnancement fiables et efficaces énergétiquement à l'échelle. [Doctoral Dissertation]. Lyon, École normale supérieure; 2014. Available from: http://www.theses.fr/2014ENSL0928

Université Montpellier II

20. Mansouri, Imen. Contrôle distribué pour les systèmes multi-cœurs auto-adaptatifs : Distributed Control for Self-adaptatif Multi-Core Architectures.

Degree: Docteur es, SYAM - Systèmes Automatiques et Microélectroniques, 2011, Université Montpellier II

URL: http://www.theses.fr/2011MON20087

►

Les architectures régulières intégrant plusieurs cœurs de traitement sont davantage utilisées dans les systèmes embarqués. Dans cette thèse, on s'intéresse aux mécanismes d'optimisation d'énergie dans… (more)

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Les architectures régulières intégrant plusieurs cœurs de traitement sont davantage utilisées dans les systèmes embarqués. Dans cette thèse, on s'intéresse aux mécanismes d'optimisation d'énergie dans des architectures avec une dimension étendue; pour faire face aux problèmes de variabilité technologique et aux changements du contexte applicatif, le processus d'optimisation se déroule en temps réel. Des capteurs in-situ détectent le degré de dégradation du circuit. Quant a la variabilité applicative, des moniteurs d'activité sont insérés sur un niveau architectural pour estimer la charge de travail engendrée par l'application en cours et la consommation qui en découle. Nous avons développé une méthode systématique pour l'intégration de ces capteurs avec un moindre coût en surface. Leurs sorties alimentent un processus d'optimisation basé sur la théorie de consensus et dupliqué dans chaque cœur. Ce contrôle vise à fixer la meilleure configuration locale à chaque cœur permettant d'optimiser la consommation globale du système tout en respectant les contraintes temps réel de l'application en cours. Ce schéma opère d'une manière complètement distribuée afin de garantir la scalabilité de notre solution, et donc sa faisabilité, compte tenu de la complexité des circuits actuels et futurs.

Regular architectures embedding several processing elements are increasingly used in embedded systems. They require careful design to avoid high power consumption and to improve their flexibility. This thesis work deals with optimization mechanisms of large scale architectures; to meet variability issues, optimization is processed at run-time. The target design implements in-situ features to collect physical information about its yield and to monitor application workload and generated consumption. As for workload monitoring, we use activity counters connected at architecture level to a set of critical signals. We developed an automated method to optimally place these features with a minimal area overhead. The collected information are used further jointly with a power model to estimate the dissipated power and then driven appropriate optimization process. Optimal frequency for each core is set by means of a distributed controller based on consensus theory. The resulting settings aim to reduce the whole system power while fulfilling application constraints. The scheme needs to be fully distributed to garantee the control scalability, and so feasibility, as the number of cores scales.

Advisors/Committee Members: Torres, Lionel (thesis director).

Subjects/Keywords: Architecture multi-cœurs reconfigurable; Contrôle dynamique; Capteurs d'activité; Théorie de consensus; Dvfs; Reconfigurable Multi-Core architecture; Dynamic control; Activity sensors; Consensus theory; Dvfs

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Mansouri, I. (2011). Contrôle distribué pour les systèmes multi-cœurs auto-adaptatifs : Distributed Control for Self-adaptatif Multi-Core Architectures. (Doctoral Dissertation). Université Montpellier II. Retrieved from http://www.theses.fr/2011MON20087

Chicago Manual of Style (16^th Edition):

Mansouri, Imen. “Contrôle distribué pour les systèmes multi-cœurs auto-adaptatifs : Distributed Control for Self-adaptatif Multi-Core Architectures.” 2011. Doctoral Dissertation, Université Montpellier II. Accessed February 27, 2021. http://www.theses.fr/2011MON20087.

MLA Handbook (7^th Edition):

Mansouri, Imen. “Contrôle distribué pour les systèmes multi-cœurs auto-adaptatifs : Distributed Control for Self-adaptatif Multi-Core Architectures.” 2011. Web. 27 Feb 2021.

Vancouver:

Mansouri I. Contrôle distribué pour les systèmes multi-cœurs auto-adaptatifs : Distributed Control for Self-adaptatif Multi-Core Architectures. [Internet] [Doctoral dissertation]. Université Montpellier II; 2011. [cited 2021 Feb 27]. Available from: http://www.theses.fr/2011MON20087.

Council of Science Editors:

Mansouri I. Contrôle distribué pour les systèmes multi-cœurs auto-adaptatifs : Distributed Control for Self-adaptatif Multi-Core Architectures. [Doctoral Dissertation]. Université Montpellier II; 2011. Available from: http://www.theses.fr/2011MON20087

21. Pinheiro, Diego Quintana. Inserção de Código DVFS-Aware em Sistemas de tempo real críticos.

Degree: 2015, Universidade Federal do Amazonas

URL: http://tede.ufam.edu.br/handle/tede/5248

►

Desempenho e consumo de energia são variáveis diretamente proporcionais. Para aumentar o desempenho, é necessário também aumentar o número de instruções por segundo a serem… (more)

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Desempenho e consumo de energia são variáveis diretamente proporcionais. Para aumentar o desempenho, é necessário também aumentar o número de instruções por segundo a serem executadas, ou seja, alterar a frequência do processador. Quanto maior for este valor, também será o consumo de energia. Do mesmo modo, reduzir o consumo de energia implica diminuir o número de instruções a serem executadas e, logo, o desempenho. Explorar a relação entre desempenho e consumo de energia é a ideia base da técnica de escalonamento dinâmico de tensão e frequência DVFS (do inglês Dynamic Voltage and Frequency Scaling). Em sistemas de tempo real críticos, aplicar a técnica DVFS não é uma tarefa trivial. Estes sistemas associam a execução de uma tarefa a um limite temporal, de modo que, se este valor não for respeitado, devido à redução do desempenho, falhas graves podem ocorrer ao sistema. Assim, esta dissertação tem como objetivo unir duas abordagens da técnica DVFS em sistemas de tempo real críticos: uma intra e outra inter-tarefas. A abordagem intra-tarefa procura analisar o fluxo de execução de uma tarefa e identificar pontos onde é possível inserir instruções para troca de frequência e tensão, quando a execução de uma tarefa se distanciar do pior caso. Já a abordagem inter-tarefas, é responsável por: analisar o tempo de espera na execução de uma tarefa devido às interferências (preempções, compartilhamento de recursos), verificar a escalonabilidade do sistema e determinar um conjunto de frequências iniciais ótimas em ambientes de múltiplas tarefas. O resultado deste estudo é a geração de um novo código com funcionalidade igual ao de entrada, porém com instruções de troca de frequência e tensão, consideradas as interferências que uma tarefa possa sofrer. Além disso, resultados experimentais mostram como não só foi possível reduzir o consumo de energia, mas também respeitar os limites temporais das tarefas em questão.

Performance and energy consumption are directly related. To increase performance, the number of instructions per second to be executed must also be increased, in other words, processor frequency must be changed. The higher this value is, higher energy consumption also has to be. Likewise, by decreasing the number of instructions to be executed, energy consumption and performance are also reduced. So, exploring performance and energy relation is the key idea behind Dynamic Voltage and Frequency Scaling – DVFS, technique. Applying DVFS in real time systems is not a trivial task. These system’s tasks are bounded to timing constraints in such a way that, if decreasing performance does not guarantee constraints, the system may totally fail. Thus, this work aims to gather two DVFS approaches in real time systems: intra and inter-tasks. The intra-task analyzes execution flow of a task and identify where the new instructions can be inserted to change supply voltage and frequency when the worst case path is not followed. On the other hand, the inter-task approach analyzes how long a task…

Advisors/Committee Members: Barreto, Raimundo da Silva, 20070128200, http://lattes.cnpq.br/1132672107627968.

Subjects/Keywords: Sistemas Embarcados; Sistemas de Tempo Real, Baixo Consumo de Energia; DVFS Intra-Tarefa; Transformação de Código; DVFS Inter-Tarefa; CIÊNCIAS EXATAS E DA TERRA: CIÊNCIA DA COMPUTAÇÃO

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Pinheiro, D. Q. (2015). Inserção de Código DVFS-Aware em Sistemas de tempo real críticos. (Masters Thesis). Universidade Federal do Amazonas. Retrieved from http://tede.ufam.edu.br/handle/tede/5248

Chicago Manual of Style (16^th Edition):

Pinheiro, Diego Quintana. “Inserção de Código DVFS-Aware em Sistemas de tempo real críticos.” 2015. Masters Thesis, Universidade Federal do Amazonas. Accessed February 27, 2021. http://tede.ufam.edu.br/handle/tede/5248.

MLA Handbook (7^th Edition):

Pinheiro, Diego Quintana. “Inserção de Código DVFS-Aware em Sistemas de tempo real críticos.” 2015. Web. 27 Feb 2021.

Vancouver:

Pinheiro DQ. Inserção de Código DVFS-Aware em Sistemas de tempo real críticos. [Internet] [Masters thesis]. Universidade Federal do Amazonas; 2015. [cited 2021 Feb 27]. Available from: http://tede.ufam.edu.br/handle/tede/5248.

Council of Science Editors:

Pinheiro DQ. Inserção de Código DVFS-Aware em Sistemas de tempo real críticos. [Masters Thesis]. Universidade Federal do Amazonas; 2015. Available from: http://tede.ufam.edu.br/handle/tede/5248

NSYSU

22. Yeh, Jia-huei. An Adaptive Fuzzy Proportional-Integral Predictor for Power Management of 3D Graphics System-On-Chip.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802110-133640

► As time goes by rapid development of 3D graphics technique and 3C portable product output, 3D graphics have been widely applied to handheld devices, such… (more)

▼ As time goes by rapid development of 3D graphics technique and 3C portable product output, 3D graphics have been widely applied to handheld devices, such as notebooks, PDAs, and smart cellular phones. Generally, to process 3D graphics applications in mobile devices, processor needs strong capability of handling large computational-intensive workloads. Complex computation consumes a great quantity of electric power. But the lifetime of handheld device battery is limited. Therefore, the cost, to satisfy this demand, will be shortening the supply time of device battery. Moreover, Mooreâ law said that the number of transistors in a chip is double in every eighteen months. But these days the advance in manufacturing batteries still cannot get up with the advance in developing processors. In addition, the improvement of chip size has led to more small, supply voltage of kernel processor in portable device. Considering system efficiency and battery lifetime simultaneously increase the difficulty of designing power management scheme. So, how to manage power effectively has become one of the important key for designing handheld products. For 3D graphics system, dynamic voltage and frequency scaling (DVFS) is one of good solutions to implement power management policy. DVFS needs an efficient online prediction method to predict the workload of frames and then appropriately adjust voltage and frequency for saving energy consumption. Consequently, a lot of related papers have proposed different prediction policy to predict the executing workload of 3D graphics system. For instance, the existing prediction policies include signature-based[1], history-based[3] and proportion-integral-derivative (PID)[14] methods, but most of designers put power management in software, i.e. processors. This solution not only slows power management to get the information about executing time of graphic processing unit (GPU), but also increases the operating overhead of CPU in handheld system. In this paper, we propose a power management workload prediction scheme with a framework of using proportion-integral (PI) controller to be a master controller and fuzzy controller to be a slave controller, and then implement it into hardware circuit. Taking advantage of fuzzy conception in fuzzy controller is to adjust the proportional parameter in PI controller, the shortage of traditional PI controller that demands on complicated try-and-error method to look for a good proportional and integral parameters can be avoided so that the adaption and forecasting accuracy can be improved. Besides, Uniform Window-size Predictor 1 (UW1) is also implemented as an assistant manner. Using UW1 predictor appropriately can improve the prediction trend to catch up with the trend of real workload. Experimental results show that our predictor improves prediction accuracy about 3.8% on average and saves about 0.02% more energy compared with PI predictor[18]. Circuit area and power consumption only increases 6.8% percent and 1.4% compared with PI predictor. Besides, we also… Advisors/Committee Members: Chuen-Yau Chen (chair), Ko-Chi Kuo (chair), Shen-Fu Hsiao (chair), Lih-Yang Wang (chair), Shiann-Rong Kuang (committee member).

Subjects/Keywords: Power Management; Dynamic Voltage Frequency Scaling(DVFS); Proportional- Integral Controller; Fuzzy Controller

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Yeh, J. (2010). An Adaptive Fuzzy Proportional-Integral Predictor for Power Management of 3D Graphics System-On-Chip. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802110-133640

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Yeh, Jia-huei. “An Adaptive Fuzzy Proportional-Integral Predictor for Power Management of 3D Graphics System-On-Chip.” 2010. Thesis, NSYSU. Accessed February 27, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802110-133640.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Yeh, Jia-huei. “An Adaptive Fuzzy Proportional-Integral Predictor for Power Management of 3D Graphics System-On-Chip.” 2010. Web. 27 Feb 2021.

Vancouver:

Yeh J. An Adaptive Fuzzy Proportional-Integral Predictor for Power Management of 3D Graphics System-On-Chip. [Internet] [Thesis]. NSYSU; 2010. [cited 2021 Feb 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802110-133640.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yeh J. An Adaptive Fuzzy Proportional-Integral Predictor for Power Management of 3D Graphics System-On-Chip. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802110-133640

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Cornell University

23. Torng, Christopher. Software, Architecture, and VLSI Co-Design for Fine-Grain Voltage and Frequency Scaling.

Degree: PhD, Electrical and Computer Engineering, 2019, Cornell University

URL: http://hdl.handle.net/1813/69995

► As emerging domains demand higher performance under stringent constraints on power and energy, computer architects are increasingly relying on a combination of parallelization and specialization… (more)

▼ As emerging domains demand higher performance under stringent constraints on power and energy, computer architects are increasingly relying on a combination of parallelization and specialization to improve both performance and energy efficiency. However, the combination of parallelism and specialization is also steadily increasing on-chip asymmetry in the form of spatial heterogeneity and temporal variation, which poses key challenges in the form of widely varying utilization in space (i.e., across different components) and in time (i.e., used at different times across varying performance levels). Fine-grain on-chip asymmetry requires analogously fine-grain power-control techniques in order to power (or not power) different components to different levels at just the right times to significantly reduce waste. At the same time, traditional walls of abstraction have broken down, allowing a cross-stack co-design approach across software, architecture, and VLSI to provide new, previously inaccessible information to precisely control new hardware mechanisms. This thesis explores novel fine-grain voltage and frequency scaling techniques to improve both performance and energy efficiency with software, architecture, and VLSI co-design. First, I explore architecture-circuit co-design and leverage recent work on fully integrated voltage regulation to enable realistic fine-grain voltage and frequency scaling for homogeneous systems of little cores at microsecond timescales. Second, I broaden the scope to heterogeneous systems of big and little cores and specialize for productive software task-based parallel runtimes. Third, I investigate much finer-grain asymmetry that can be exploited within coarse-grain reconfigurable arrays, which have recently attracted significant interest due to their flexibility and potential for reducing data movement energy. Finally, I describe my work on four silicon prototypes including a mixed-signal test chip and three digital ASIC test chips that support different aspects of my thesis. Throughout my thesis, I take a software, architecture, and VLSI co-design approach and focus on exploiting information newly exposed across layers of abstraction. I leverage a vertically integrated research methodology spanning across applications, runtimes, architecture, cycle-level modeling, RTL, VLSI CAD tools, SPICE-level modeling, and silicon prototyping to evaluate the potential benefit of fine-grain voltage and frequency scaling techniques. Advisors/Committee Members: Batten, Christopher (chair), Apsel, Alyssa B. (committee member), Manohar, Rajit (committee member).

Subjects/Keywords: computer architecture; fine-grain dvfs; heterogeneous computing; integrated voltage regulation; reconfigurable architectures; work-stealing runtimes

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Torng, C. (2019). Software, Architecture, and VLSI Co-Design for Fine-Grain Voltage and Frequency Scaling. (Doctoral Dissertation). Cornell University. Retrieved from http://hdl.handle.net/1813/69995

Chicago Manual of Style (16^th Edition):

Torng, Christopher. “Software, Architecture, and VLSI Co-Design for Fine-Grain Voltage and Frequency Scaling.” 2019. Doctoral Dissertation, Cornell University. Accessed February 27, 2021. http://hdl.handle.net/1813/69995.

MLA Handbook (7^th Edition):

Torng, Christopher. “Software, Architecture, and VLSI Co-Design for Fine-Grain Voltage and Frequency Scaling.” 2019. Web. 27 Feb 2021.

Vancouver:

Torng C. Software, Architecture, and VLSI Co-Design for Fine-Grain Voltage and Frequency Scaling. [Internet] [Doctoral dissertation]. Cornell University; 2019. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/1813/69995.

Council of Science Editors:

Torng C. Software, Architecture, and VLSI Co-Design for Fine-Grain Voltage and Frequency Scaling. [Doctoral Dissertation]. Cornell University; 2019. Available from: http://hdl.handle.net/1813/69995

Penn State University

24. Bily, Paul Lawrence. Implementation and Evaluation of a Software-based Power Virtualization Technique.

Degree: 2013, Penn State University

URL: https://submit-etda.libraries.psu.edu/catalog/17630

► As data centers grow in size and popularity, managing utilization of resources like power becomes increasingly important due to rising costs. Effective power management remains… (more)

Subjects/Keywords: power; energy; virtualization; virtualize; management; data center; datacenter; DVFS; UPS; PDU; hierarchy; lottery scheduling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Bily, P. L. (2013). Implementation and Evaluation of a Software-based Power Virtualization Technique. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/17630

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Bily, Paul Lawrence. “Implementation and Evaluation of a Software-based Power Virtualization Technique.” 2013. Thesis, Penn State University. Accessed February 27, 2021. https://submit-etda.libraries.psu.edu/catalog/17630.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Bily, Paul Lawrence. “Implementation and Evaluation of a Software-based Power Virtualization Technique.” 2013. Web. 27 Feb 2021.

Vancouver:

Bily PL. Implementation and Evaluation of a Software-based Power Virtualization Technique. [Internet] [Thesis]. Penn State University; 2013. [cited 2021 Feb 27]. Available from: https://submit-etda.libraries.psu.edu/catalog/17630.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bily PL. Implementation and Evaluation of a Software-based Power Virtualization Technique. [Thesis]. Penn State University; 2013. Available from: https://submit-etda.libraries.psu.edu/catalog/17630

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. Ghorbani Moghaddam, Milad. Dynamic Lifetime Reliability and Energy Management for Network-on-Chip based Chip Multiprocessors.

Degree: 2018, Marquette University

URL: https://epublications.marquette.edu/dissertations_mu/834

► In this dissertation, we study dynamic reliability management (DRM) and dynamic energy management (DEM) techniques for network-on-chip (NoC) based chip multiprocessors (CMPs). In the first… (more)

▼ In this dissertation, we study dynamic reliability management (DRM) and dynamic energy management (DEM) techniques for network-on-chip (NoC) based chip multiprocessors (CMPs). In the first part, the proposed DRM algorithm takes both the computational and the communication components of the CMP into consideration and combines thread migration and dynamic voltage and frequency scaling (DVFS) as the two primary techniques to change the CMP operation. The goal is to increase the lifetime reliability of the overall system to the desired target with minimal performance degradation. The simulation results on a variety of benchmarks on 16 and 64 core NoC based CMP architectures demonstrate that lifetime reliability can be improved by 100% for an average performance penalty of 7.7% and 8.7% for the two CMP architectures. In the second part of this dissertation, we first propose novel algorithms that employ Kalman filtering and long short term memory (LSTM) for workload prediction. These predictions are then used as the basis on which voltage/frequency (V/F) pairs are selected for each core by an effective dynamic voltage and frequency scaling algorithm whose objective is to reduce energy consumption but without degrading performance beyond the user set threshold. Secondly, we investigate the use of deep neural network (DNN) models for energy optimization under performance constraints in CMPs. The proposed algorithm is implemented in three phases. The first phase collects the training data by employing Kalman filtering for workload prediction and an efficient heuristic algorithm based on DVFS. The second phase represents the training process of the DNN model and in the last phase, the DNN model is used to directly identify V/F pairs that can achieve lower energy consumption without performance degradation beyond the acceptable threshold set by the user. Simulation results on 16 and 64 core NoC based architectures demonstrate that the proposed approach can achieve up to 55% energy reduction for 10% performance degradation constraints. Simulation experiments compare the proposed algorithm against existing approaches based on reinforcement learning and Kalman filtering and show that the proposed DNN technique provides average improvements in energy-delay-product (EDP) of 6.3% and 6% for the 16 core architecture and of 7.4% and 5.5% for the 64 core architecture. Advisors/Committee Members: Ababei, Cristinel, Povinelli, Richard, Medeiros, Henry.

Subjects/Keywords: Chip Multiprocessors; Deep Neural Networks; DVFS; Dynamic energy management; Dynamic reliability management; Kalman filtering; Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Ghorbani Moghaddam, M. (2018). Dynamic Lifetime Reliability and Energy Management for Network-on-Chip based Chip Multiprocessors. (Thesis). Marquette University. Retrieved from https://epublications.marquette.edu/dissertations_mu/834

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Ghorbani Moghaddam, Milad. “Dynamic Lifetime Reliability and Energy Management for Network-on-Chip based Chip Multiprocessors.” 2018. Thesis, Marquette University. Accessed February 27, 2021. https://epublications.marquette.edu/dissertations_mu/834.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Ghorbani Moghaddam, Milad. “Dynamic Lifetime Reliability and Energy Management for Network-on-Chip based Chip Multiprocessors.” 2018. Web. 27 Feb 2021.

Vancouver:

Ghorbani Moghaddam M. Dynamic Lifetime Reliability and Energy Management for Network-on-Chip based Chip Multiprocessors. [Internet] [Thesis]. Marquette University; 2018. [cited 2021 Feb 27]. Available from: https://epublications.marquette.edu/dissertations_mu/834.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ghorbani Moghaddam M. Dynamic Lifetime Reliability and Energy Management for Network-on-Chip based Chip Multiprocessors. [Thesis]. Marquette University; 2018. Available from: https://epublications.marquette.edu/dissertations_mu/834

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

26. Joao, José Alberto. Bottleneck identification and acceleration in multithreaded applications.

Degree: PhD, Computer Engineering, 2014, University of Texas – Austin

URL: http://hdl.handle.net/2152/28383

► When parallel applications do not fully utilize the cores that are available to them they are missing the opportunity to have better performance. Sometimes threads… (more)

Subjects/Keywords: Multithreaded applications; Bottlenecks; Critical sections; Barriers; Multicore; Asymmetric CMP; Heterogeneous CMP; DVFS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Joao, J. A. (2014). Bottleneck identification and acceleration in multithreaded applications. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/28383

Chicago Manual of Style (16^th Edition):

Joao, José Alberto. “Bottleneck identification and acceleration in multithreaded applications.” 2014. Doctoral Dissertation, University of Texas – Austin. Accessed February 27, 2021. http://hdl.handle.net/2152/28383.

MLA Handbook (7^th Edition):

Joao, José Alberto. “Bottleneck identification and acceleration in multithreaded applications.” 2014. Web. 27 Feb 2021.

Vancouver:

Joao JA. Bottleneck identification and acceleration in multithreaded applications. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2014. [cited 2021 Feb 27]. Available from: http://hdl.handle.net/2152/28383.

Council of Science Editors:

Joao JA. Bottleneck identification and acceleration in multithreaded applications. [Doctoral Dissertation]. University of Texas – Austin; 2014. Available from: http://hdl.handle.net/2152/28383

Utah State University

27. Arunachalam, Srinath. An online wear state monitoring methodology for off-the-shelf embedded processors.

Degree: MS, Electrical and Computer Engineering, 2015, Utah State University

URL: https://digitalcommons.usu.edu/etd/4552

► The continued scaling of transistors has led to an exponential increase in on-chip power density, which has resulted in increasing temperature. In turn, the… (more)

Subjects/Keywords: DVFS; Embedded system; NBTI; Off-the-shelf Reliability; Wear state; Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Arunachalam, S. (2015). An online wear state monitoring methodology for off-the-shelf embedded processors. (Masters Thesis). Utah State University. Retrieved from https://digitalcommons.usu.edu/etd/4552

Chicago Manual of Style (16^th Edition):

Arunachalam, Srinath. “An online wear state monitoring methodology for off-the-shelf embedded processors.” 2015. Masters Thesis, Utah State University. Accessed February 27, 2021. https://digitalcommons.usu.edu/etd/4552.

MLA Handbook (7^th Edition):

Arunachalam, Srinath. “An online wear state monitoring methodology for off-the-shelf embedded processors.” 2015. Web. 27 Feb 2021.

Vancouver:

Arunachalam S. An online wear state monitoring methodology for off-the-shelf embedded processors. [Internet] [Masters thesis]. Utah State University; 2015. [cited 2021 Feb 27]. Available from: https://digitalcommons.usu.edu/etd/4552.

Council of Science Editors:

Arunachalam S. An online wear state monitoring methodology for off-the-shelf embedded processors. [Masters Thesis]. Utah State University; 2015. Available from: https://digitalcommons.usu.edu/etd/4552

The Ohio State University

28. Bao, Wenlei. Compiler Techniques for Transformation Verification, Energy Efficiency and Cache Modeling.

Degree: PhD, Computer Science and Engineering, 2018, The Ohio State University

URL: http://rave.ohiolink.edu/etdc/view?acc_num=osu1524073563586939

► Performance has been the focus of computer systems for decades, from past Moore law to current parallel computers. Compiler optimizations are used to improve performance… (more)

▼ Performance has been the focus of computer systems for decades, from past Moore law to current parallel computers. Compiler optimizations are used to improve performance by generating code to utilize hardware (e.g. cache)component efficiently. However, modern systems such as large scale system require not only performance but also resilience and energy efficiency. Increasing concern of system resilience and energy efficiency has been shown in both industry and academia.Errors within applications, especially those escape from detection and resulting in silent data corruption, are extremely problematic. Thus, in order to improve the resilience of applications, error detection and vulnerability characterization techniques are an important step towards fault tolerant applications.Compiler transformations, which restructure programs to improve performance by leveraging data locality and parallelism, are often complex and possibly involve bugs that leads to errors in transformed programs. Thus it is essential to guarantee the correctness, however, current approaches suffers from various problems such as transformations supported or space complexity etc. This dissertation presents a novel approach that performs dynamic verification by inserting lightweight checker codes to detect errors of transformations. The errors are exposed by the execution of checker-inserted transformed program if exist.Energy efficiency is of increasingly importance in scenarios ranging from battery-operated devices to data centers striving for lower energy costs. Dynamic voltage and frequency scaling (DVFS) adapts CPU power consumption by modifying processor frequency to improve energy efficiency. Typical DVFS approaches involve default strategies such as reacting to the CPU runtime load to adapt frequency, which have inherent limitations because of processor-specific and application-specific effects. This dissertation developed a novel compile-time characterization to select frequency and number of CPU cores to use, which providing significant additional benefits over the runtime approach.Cache memory, as one of the most fundamental components of modern processors, has a significant impact on the performance of current computer systems. Compiler optimizations on efficient use of cache to reduce data movement, are often based on very approximate cost models due to the lack of precise modeling of hierarchical cache. The challenge of accurately modeling cache misses has made trace-based simulation the current method of choice. This dissertation takes a fundamentally different approach for polyhedral programs, developed a closed-form solution for modeling of misses of set-associative cache by leveraging the power of polyhedral analysis. This solution can enable program transformation choice at compile time to optimize cache misses.In sum, the dissertation makes contributions to advance compiler technology to achieve program transformation verification, to reduce energy costs, and to effectively modeling cache behaviors. Advisors/Committee Members: Sadayappan, Ponnuswamy (Advisor).

Subjects/Keywords: Computer Science; compiler optimization; polyhedral compilation; program verification; energy optimization; DVFS; cache modeling; vulnerability analysis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Bao, W. (2018). Compiler Techniques for Transformation Verification, Energy Efficiency and Cache Modeling. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1524073563586939

Chicago Manual of Style (16^th Edition):

Bao, Wenlei. “Compiler Techniques for Transformation Verification, Energy Efficiency and Cache Modeling.” 2018. Doctoral Dissertation, The Ohio State University. Accessed February 27, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=osu1524073563586939.

MLA Handbook (7^th Edition):

Bao, Wenlei. “Compiler Techniques for Transformation Verification, Energy Efficiency and Cache Modeling.” 2018. Web. 27 Feb 2021.

Vancouver:

Bao W. Compiler Techniques for Transformation Verification, Energy Efficiency and Cache Modeling. [Internet] [Doctoral dissertation]. The Ohio State University; 2018. [cited 2021 Feb 27]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1524073563586939.

Council of Science Editors:

Bao W. Compiler Techniques for Transformation Verification, Energy Efficiency and Cache Modeling. [Doctoral Dissertation]. The Ohio State University; 2018. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1524073563586939

NSYSU

29. Ke, Bao-chen. Hybrid Fuzzy Kalman Filter for Workload Prediction of 3D Graphic System.

Degree: Master, Computer Science and Engineering, 2011, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728111-174057

► In modern life, 3D graphics system is widely applied to portable product like Notebook, PDA and smart phone. Unlike desktop system, the capacity of batteries… (more)

Subjects/Keywords: Workload Prediction; 3D Graphic System; Fuzzy Controller; Power Management; Dynamic Voltage Frequency Scaling(DVFS); Kalman Filter

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Ke, B. (2011). Hybrid Fuzzy Kalman Filter for Workload Prediction of 3D Graphic System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728111-174057

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Ke, Bao-chen. “Hybrid Fuzzy Kalman Filter for Workload Prediction of 3D Graphic System.” 2011. Thesis, NSYSU. Accessed February 27, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728111-174057.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Ke, Bao-chen. “Hybrid Fuzzy Kalman Filter for Workload Prediction of 3D Graphic System.” 2011. Web. 27 Feb 2021.

Vancouver:

Ke B. Hybrid Fuzzy Kalman Filter for Workload Prediction of 3D Graphic System. [Internet] [Thesis]. NSYSU; 2011. [cited 2021 Feb 27]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728111-174057.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ke B. Hybrid Fuzzy Kalman Filter for Workload Prediction of 3D Graphic System. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728111-174057

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of California – Irvine

30. Park, Jurn-Gyu. Cooperative CPU-GPU Dynamic Power Management Methodologies for Energy-efficient Mobile Gaming.

Degree: Computer Science, 2017, University of California – Irvine

URL: http://www.escholarship.org/uc/item/8mq1n6sd

► One of the fundamental challenges to contemporary mobile platforms deploying heterogeneous CPU-GPU based architectures that execute mobile games and other graphics-intensive applications is to design… (more)

▼ One of the fundamental challenges to contemporary mobile platforms deploying heterogeneous CPU-GPU based architectures that execute mobile games and other graphics-intensive applications is to design software governors through Dynamic Voltage Frequency Scaling (DVFS) for achieving high performance with energy-efficiency on battery-based systems. However, separate CPU and GPU governors miss opportunities for further energy savings through cooperative/integrated CPU-GPU power management. Contemporary integrated CPU-GPU governors for diverse and dynamic gaming workloads utilize classical statistical or heuristic models with a small set of mobile games for both modeling and evaluation resulting in high prediction errors with lost potential for energy savings. To overcome these limitations, this thesis presents a comprehensive graphics workload characterization by developing custom micro-benchmarks and then proposes three different cooperative CPU-GPU dynamic power management methodologies by using large sets of real games and micro-benchmarks. As a first step, we present a study of mobile GPU graphics workload characterization for DVFS design considering performance and energy efficiency on a real smart-phone. We develop micro-benchmarks that stress specific stages of the graphics pipeline separately, and analyze the relationship between varying graphics workloads and resulting energy and performance of different mobile graphics pipeline stages. We then propose a simple yet effective strategy called Co-Cap (Cooperative Frequency-Capping), a cooperative CPU-GPU DVFS strategy that orchestrates energy-efficient CPU and GPU DVFS through coordinated CPU and GPU frequency capping to avoid frequency over-provisioning while maintaining desired performance. Furthermore, we propose a model-based DVFS design approach, a Hierarchical Finite State Machine (HFSM) based CPU-GPU governor that models the dynamic behavior of mobile gaming workloads, and applies a cooperative, dynamic CPU-GPU frequency-capping policy to yield energy efficiency adapting to the games' inherent dynamism. Finally, we present a machine learning enhanced integrated CPU-GPU governor that builds tree-based piecewise linear prediction models resulting in high accuracy and low complexity of cost functions using practical offline machine learning techniques, and integrate the models for online estimation into an integrated CPU-GPU DVFS governor applying piecewise policies based on the models. We demonstrate efficacy of our methodologies across over 100 real games and a few hundred custom micro-benchmarks, achieving substantial energy efficiency gains of up to 18% improvement in energy-per-frame over existing governor policies, with minimal loss in performance.

Subjects/Keywords: Computer science; Computer engineering; DVFS; Integrated GPU; Machine Learning techniques; Model-based design; Power management policies

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Park, J. (2017). Cooperative CPU-GPU Dynamic Power Management Methodologies for Energy-efficient Mobile Gaming. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/8mq1n6sd

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Park, Jurn-Gyu. “Cooperative CPU-GPU Dynamic Power Management Methodologies for Energy-efficient Mobile Gaming.” 2017. Thesis, University of California – Irvine. Accessed February 27, 2021. http://www.escholarship.org/uc/item/8mq1n6sd.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Park, Jurn-Gyu. “Cooperative CPU-GPU Dynamic Power Management Methodologies for Energy-efficient Mobile Gaming.” 2017. Web. 27 Feb 2021.

Vancouver:

Park J. Cooperative CPU-GPU Dynamic Power Management Methodologies for Energy-efficient Mobile Gaming. [Internet] [Thesis]. University of California – Irvine; 2017. [cited 2021 Feb 27]. Available from: http://www.escholarship.org/uc/item/8mq1n6sd.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Park J. Cooperative CPU-GPU Dynamic Power Management Methodologies for Energy-efficient Mobile Gaming. [Thesis]. University of California – Irvine; 2017. Available from: http://www.escholarship.org/uc/item/8mq1n6sd

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Open Access Theses and Dissertations