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You searched for subject:(DRAM). Showing records 1 – 30 of 116 total matches.

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University of Manitoba

1. Pilapil, Matt Andrew. Systematic Development and Characterization of a Polypyrrole Hybrid for Dynamic Random Access Memory.

Degree: Chemistry, 2010, University of Manitoba

 Conducting polymers have emerged as a class of innovative materials with tunable properties that are useful in a diverse range of applications. For example, the… (more)

Subjects/Keywords: Polypyrrole; DRAM

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APA (6th Edition):

Pilapil, M. A. (2010). Systematic Development and Characterization of a Polypyrrole Hybrid for Dynamic Random Access Memory. (Masters Thesis). University of Manitoba. Retrieved from http://hdl.handle.net/1993/3924

Chicago Manual of Style (16th Edition):

Pilapil, Matt Andrew. “Systematic Development and Characterization of a Polypyrrole Hybrid for Dynamic Random Access Memory.” 2010. Masters Thesis, University of Manitoba. Accessed February 25, 2020. http://hdl.handle.net/1993/3924.

MLA Handbook (7th Edition):

Pilapil, Matt Andrew. “Systematic Development and Characterization of a Polypyrrole Hybrid for Dynamic Random Access Memory.” 2010. Web. 25 Feb 2020.

Vancouver:

Pilapil MA. Systematic Development and Characterization of a Polypyrrole Hybrid for Dynamic Random Access Memory. [Internet] [Masters thesis]. University of Manitoba; 2010. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/1993/3924.

Council of Science Editors:

Pilapil MA. Systematic Development and Characterization of a Polypyrrole Hybrid for Dynamic Random Access Memory. [Masters Thesis]. University of Manitoba; 2010. Available from: http://hdl.handle.net/1993/3924


University of New South Wales

2. Shwe, Su. Energy-efficient low power optimisation methodologies for DRAM memory of embedded system.

Degree: Computer Science & Engineering, 2013, University of New South Wales

 The increased demand on the long battery life of complex SoC systems requires power/energy aware methodologies and a comprehensive design process flow to optimise DRAM(more)

Subjects/Keywords: Memory; DRAM; Power

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APA (6th Edition):

Shwe, S. (2013). Energy-efficient low power optimisation methodologies for DRAM memory of embedded system. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/53157 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:11848/SOURCE01?view=true

Chicago Manual of Style (16th Edition):

Shwe, Su. “Energy-efficient low power optimisation methodologies for DRAM memory of embedded system.” 2013. Doctoral Dissertation, University of New South Wales. Accessed February 25, 2020. http://handle.unsw.edu.au/1959.4/53157 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:11848/SOURCE01?view=true.

MLA Handbook (7th Edition):

Shwe, Su. “Energy-efficient low power optimisation methodologies for DRAM memory of embedded system.” 2013. Web. 25 Feb 2020.

Vancouver:

Shwe S. Energy-efficient low power optimisation methodologies for DRAM memory of embedded system. [Internet] [Doctoral dissertation]. University of New South Wales; 2013. [cited 2020 Feb 25]. Available from: http://handle.unsw.edu.au/1959.4/53157 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:11848/SOURCE01?view=true.

Council of Science Editors:

Shwe S. Energy-efficient low power optimisation methodologies for DRAM memory of embedded system. [Doctoral Dissertation]. University of New South Wales; 2013. Available from: http://handle.unsw.edu.au/1959.4/53157 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:11848/SOURCE01?view=true

3. Chang, Kevin K. Understanding and Improving the Latency of DRAM-Based Memory Systems.

Degree: 2017, Carnegie Mellon University

 Over the past two decades, the storage capacity and access bandwidth of main memory have improved tremendously, by 128x and 20x, respectively. These improvements are… (more)

Subjects/Keywords: DRAM; DRAM Architecture; DRAM Characterization; Memory Latency; Memory Systems; Performance

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APA (6th Edition):

Chang, K. K. (2017). Understanding and Improving the Latency of DRAM-Based Memory Systems. (Thesis). Carnegie Mellon University. Retrieved from http://repository.cmu.edu/dissertations/907

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Kevin K. “Understanding and Improving the Latency of DRAM-Based Memory Systems.” 2017. Thesis, Carnegie Mellon University. Accessed February 25, 2020. http://repository.cmu.edu/dissertations/907.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Kevin K. “Understanding and Improving the Latency of DRAM-Based Memory Systems.” 2017. Web. 25 Feb 2020.

Vancouver:

Chang KK. Understanding and Improving the Latency of DRAM-Based Memory Systems. [Internet] [Thesis]. Carnegie Mellon University; 2017. [cited 2020 Feb 25]. Available from: http://repository.cmu.edu/dissertations/907.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang KK. Understanding and Improving the Latency of DRAM-Based Memory Systems. [Thesis]. Carnegie Mellon University; 2017. Available from: http://repository.cmu.edu/dissertations/907

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Utah

4. Shevgoor, Manjunath. Enabling big memory with emerging technologies.

Degree: PhD, School of Computing, 2016, University of Utah

 The demand for main memory capacity has been increasing for many years and will continue to do so. In the past, Dynamic Random Access Memory… (more)

Subjects/Keywords: computer architecture; DRAM; memory

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APA (6th Edition):

Shevgoor, M. (2016). Enabling big memory with emerging technologies. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/4108/rec/865

Chicago Manual of Style (16th Edition):

Shevgoor, Manjunath. “Enabling big memory with emerging technologies.” 2016. Doctoral Dissertation, University of Utah. Accessed February 25, 2020. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/4108/rec/865.

MLA Handbook (7th Edition):

Shevgoor, Manjunath. “Enabling big memory with emerging technologies.” 2016. Web. 25 Feb 2020.

Vancouver:

Shevgoor M. Enabling big memory with emerging technologies. [Internet] [Doctoral dissertation]. University of Utah; 2016. [cited 2020 Feb 25]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/4108/rec/865.

Council of Science Editors:

Shevgoor M. Enabling big memory with emerging technologies. [Doctoral Dissertation]. University of Utah; 2016. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/4108/rec/865


University of Utah

5. Chatterjee, Niladrish. Designing efficient memory schedulers for future systems.

Degree: PhD, Computing (School of), 2013, University of Utah

 The internet-based information infrastructure that has powered the growth of modern personal/mobile computing is composed of powerful, warehouse-scale computers or datacenters. These heavily subscribed datacenters… (more)

Subjects/Keywords: DRAM; Memory system; Scheduling

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APA (6th Edition):

Chatterjee, N. (2013). Designing efficient memory schedulers for future systems. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/2678/rec/658

Chicago Manual of Style (16th Edition):

Chatterjee, Niladrish. “Designing efficient memory schedulers for future systems.” 2013. Doctoral Dissertation, University of Utah. Accessed February 25, 2020. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/2678/rec/658.

MLA Handbook (7th Edition):

Chatterjee, Niladrish. “Designing efficient memory schedulers for future systems.” 2013. Web. 25 Feb 2020.

Vancouver:

Chatterjee N. Designing efficient memory schedulers for future systems. [Internet] [Doctoral dissertation]. University of Utah; 2013. [cited 2020 Feb 25]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/2678/rec/658.

Council of Science Editors:

Chatterjee N. Designing efficient memory schedulers for future systems. [Doctoral Dissertation]. University of Utah; 2013. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/2678/rec/658


University of Edinburgh

6. Huang, Cheng-Chieh. Optimizing cache utilization in modern cache hierarchies.

Degree: PhD, 2016, University of Edinburgh

 Memory wall is one of the major performance bottlenecks in modern computer systems. SRAM caches have been used to successfully bridge the performance gap between… (more)

Subjects/Keywords: 004.5; cache; DRAM; memory hierarchy

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APA (6th Edition):

Huang, C. (2016). Optimizing cache utilization in modern cache hierarchies. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/19571

Chicago Manual of Style (16th Edition):

Huang, Cheng-Chieh. “Optimizing cache utilization in modern cache hierarchies.” 2016. Doctoral Dissertation, University of Edinburgh. Accessed February 25, 2020. http://hdl.handle.net/1842/19571.

MLA Handbook (7th Edition):

Huang, Cheng-Chieh. “Optimizing cache utilization in modern cache hierarchies.” 2016. Web. 25 Feb 2020.

Vancouver:

Huang C. Optimizing cache utilization in modern cache hierarchies. [Internet] [Doctoral dissertation]. University of Edinburgh; 2016. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/1842/19571.

Council of Science Editors:

Huang C. Optimizing cache utilization in modern cache hierarchies. [Doctoral Dissertation]. University of Edinburgh; 2016. Available from: http://hdl.handle.net/1842/19571


NSYSU

7. Peng, Wen-shiang. A Study of Loan Evaluation for DRAM Industry by Analytic Hierarchy Process.

Degree: Master, EMBA, 2008, NSYSU

 ABSTRACT Business loan is an important process and main revenue to bank. Loan asset is crucial in balance sheet. Asset quality is relevant to operating… (more)

Subjects/Keywords: AHP; loan evaluation; DRAM

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APA (6th Edition):

Peng, W. (2008). A Study of Loan Evaluation for DRAM Industry by Analytic Hierarchy Process. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812108-171317

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Peng, Wen-shiang. “A Study of Loan Evaluation for DRAM Industry by Analytic Hierarchy Process.” 2008. Thesis, NSYSU. Accessed February 25, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812108-171317.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Peng, Wen-shiang. “A Study of Loan Evaluation for DRAM Industry by Analytic Hierarchy Process.” 2008. Web. 25 Feb 2020.

Vancouver:

Peng W. A Study of Loan Evaluation for DRAM Industry by Analytic Hierarchy Process. [Internet] [Thesis]. NSYSU; 2008. [cited 2020 Feb 25]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812108-171317.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Peng W. A Study of Loan Evaluation for DRAM Industry by Analytic Hierarchy Process. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812108-171317

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

8. -Chieh, Jung. The Key Successful Factor study for Taiwan DRAM Maker.

Degree: Master, Business Management, 2004, NSYSU

 Abstract Observing the DRAM market, the price of DRAM is changing dramatically. According to SIA announcement that the average price and growth ratio of DRAM(more)

Subjects/Keywords: DRAM; SIA

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APA (6th Edition):

-Chieh, J. (2004). The Key Successful Factor study for Taiwan DRAM Maker. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627104-190226

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

-Chieh, Jung. “The Key Successful Factor study for Taiwan DRAM Maker.” 2004. Thesis, NSYSU. Accessed February 25, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627104-190226.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

-Chieh, Jung. “The Key Successful Factor study for Taiwan DRAM Maker.” 2004. Web. 25 Feb 2020.

Vancouver:

-Chieh J. The Key Successful Factor study for Taiwan DRAM Maker. [Internet] [Thesis]. NSYSU; 2004. [cited 2020 Feb 25]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627104-190226.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

-Chieh J. The Key Successful Factor study for Taiwan DRAM Maker. [Thesis]. NSYSU; 2004. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627104-190226

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

9. Chang, Chia-Hao. The Influences of Thermal Annealing and Oxygen Plasma Treatment on the Characteristics of High Dielectric Coefficient (Ba, Sr)(Ti, Zr)O3 Thin Films.

Degree: Master, Electrical Engineering, 2004, NSYSU

 In this thesis, the reactive rf magnetron sputtering was used to deposit (Ba,Sr)(Ti,Zr)O3 (BSTZ) thin films on Pt/Ti/SiO2/Si substrate with the optimal parameters. The post-treatments… (more)

Subjects/Keywords: DRAM; BSTZ

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APA (6th Edition):

Chang, C. (2004). The Influences of Thermal Annealing and Oxygen Plasma Treatment on the Characteristics of High Dielectric Coefficient (Ba, Sr)(Ti, Zr)O3 Thin Films. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0705104-165917

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Chia-Hao. “The Influences of Thermal Annealing and Oxygen Plasma Treatment on the Characteristics of High Dielectric Coefficient (Ba, Sr)(Ti, Zr)O3 Thin Films.” 2004. Thesis, NSYSU. Accessed February 25, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0705104-165917.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Chia-Hao. “The Influences of Thermal Annealing and Oxygen Plasma Treatment on the Characteristics of High Dielectric Coefficient (Ba, Sr)(Ti, Zr)O3 Thin Films.” 2004. Web. 25 Feb 2020.

Vancouver:

Chang C. The Influences of Thermal Annealing and Oxygen Plasma Treatment on the Characteristics of High Dielectric Coefficient (Ba, Sr)(Ti, Zr)O3 Thin Films. [Internet] [Thesis]. NSYSU; 2004. [cited 2020 Feb 25]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0705104-165917.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang C. The Influences of Thermal Annealing and Oxygen Plasma Treatment on the Characteristics of High Dielectric Coefficient (Ba, Sr)(Ti, Zr)O3 Thin Films. [Thesis]. NSYSU; 2004. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0705104-165917

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

10. Muralidhara, Sai Prashanth. Reducing Interference in Memory Hierarchy Resources Using Application Aware Management.

Degree: PhD, Computer Science and Engineering, 2011, Penn State University

 Aggressive technology scaling has resulted in an increase in number of cores being integrated on-chip. While on-chip cores are increasing at a fast rate, the… (more)

Subjects/Keywords: Multicores; memory hierarchy; caches; DRAM

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APA (6th Edition):

Muralidhara, S. P. (2011). Reducing Interference in Memory Hierarchy Resources Using Application Aware Management. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/12150

Chicago Manual of Style (16th Edition):

Muralidhara, Sai Prashanth. “Reducing Interference in Memory Hierarchy Resources Using Application Aware Management.” 2011. Doctoral Dissertation, Penn State University. Accessed February 25, 2020. https://etda.libraries.psu.edu/catalog/12150.

MLA Handbook (7th Edition):

Muralidhara, Sai Prashanth. “Reducing Interference in Memory Hierarchy Resources Using Application Aware Management.” 2011. Web. 25 Feb 2020.

Vancouver:

Muralidhara SP. Reducing Interference in Memory Hierarchy Resources Using Application Aware Management. [Internet] [Doctoral dissertation]. Penn State University; 2011. [cited 2020 Feb 25]. Available from: https://etda.libraries.psu.edu/catalog/12150.

Council of Science Editors:

Muralidhara SP. Reducing Interference in Memory Hierarchy Resources Using Application Aware Management. [Doctoral Dissertation]. Penn State University; 2011. Available from: https://etda.libraries.psu.edu/catalog/12150


Utah State University

11. Desai, Satyajit. Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block-Based Adaptive Body Biasing Algorithm.

Degree: MS, Electrical and Computer Engineering, 2012, Utah State University

  Large dense structures like DRAMs (Dynamic Random Access Memory) are particularly susceptible to process variation, which can lead to variable latencies in different memory… (more)

Subjects/Keywords: DRAM; Process Variation; Computer Engineering

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APA (6th Edition):

Desai, S. (2012). Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block-Based Adaptive Body Biasing Algorithm. (Masters Thesis). Utah State University. Retrieved from https://digitalcommons.usu.edu/etd/1419

Chicago Manual of Style (16th Edition):

Desai, Satyajit. “Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block-Based Adaptive Body Biasing Algorithm.” 2012. Masters Thesis, Utah State University. Accessed February 25, 2020. https://digitalcommons.usu.edu/etd/1419.

MLA Handbook (7th Edition):

Desai, Satyajit. “Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block-Based Adaptive Body Biasing Algorithm.” 2012. Web. 25 Feb 2020.

Vancouver:

Desai S. Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block-Based Adaptive Body Biasing Algorithm. [Internet] [Masters thesis]. Utah State University; 2012. [cited 2020 Feb 25]. Available from: https://digitalcommons.usu.edu/etd/1419.

Council of Science Editors:

Desai S. Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block-Based Adaptive Body Biasing Algorithm. [Masters Thesis]. Utah State University; 2012. Available from: https://digitalcommons.usu.edu/etd/1419


Georgia Tech

12. Kim, Woongrae. Design and test methodologies with statistical analysis for reliable memory and processor implementations.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 The object of the proposed research is to develop comprehensive methodologies, including circuit design, new test methodologies, and statistical failure analysis, to implement reliable microprocessor… (more)

Subjects/Keywords: Reliability; SRAM; DRAM; Processor

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APA (6th Edition):

Kim, W. (2016). Design and test methodologies with statistical analysis for reliable memory and processor implementations. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59737

Chicago Manual of Style (16th Edition):

Kim, Woongrae. “Design and test methodologies with statistical analysis for reliable memory and processor implementations.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 25, 2020. http://hdl.handle.net/1853/59737.

MLA Handbook (7th Edition):

Kim, Woongrae. “Design and test methodologies with statistical analysis for reliable memory and processor implementations.” 2016. Web. 25 Feb 2020.

Vancouver:

Kim W. Design and test methodologies with statistical analysis for reliable memory and processor implementations. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/1853/59737.

Council of Science Editors:

Kim W. Design and test methodologies with statistical analysis for reliable memory and processor implementations. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/59737


University of Minnesota

13. Chun, Ki Chul. Design techniques for dense embedded memory in advanced CMOS technologies.

Degree: PhD, Electrical Engineering, 2012, University of Minnesota

 On-die cache memory is a key component in advanced processors since it can boost micro-architectural level performance at a moderate power penalty. Demand for denser… (more)

Subjects/Keywords: 2T DRAM; 3T DRAM; Cache; Embedded memory; Microprocessor; STT-MRAM

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APA (6th Edition):

Chun, K. C. (2012). Design techniques for dense embedded memory in advanced CMOS technologies. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/162804

Chicago Manual of Style (16th Edition):

Chun, Ki Chul. “Design techniques for dense embedded memory in advanced CMOS technologies.” 2012. Doctoral Dissertation, University of Minnesota. Accessed February 25, 2020. http://hdl.handle.net/11299/162804.

MLA Handbook (7th Edition):

Chun, Ki Chul. “Design techniques for dense embedded memory in advanced CMOS technologies.” 2012. Web. 25 Feb 2020.

Vancouver:

Chun KC. Design techniques for dense embedded memory in advanced CMOS technologies. [Internet] [Doctoral dissertation]. University of Minnesota; 2012. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/11299/162804.

Council of Science Editors:

Chun KC. Design techniques for dense embedded memory in advanced CMOS technologies. [Doctoral Dissertation]. University of Minnesota; 2012. Available from: http://hdl.handle.net/11299/162804


Cornell University

14. Rajwade, Shantanu. Hybrid Approaches Towards High–Speed, Low–Voltage Flash Memory Design .

Degree: 2013, Cornell University

 Integration of discrete charge storage in nanocrystals (NC) or dielectric traps is shown to alleviate limitations on tunnel oxide scaling and operational voltage reduction in… (more)

Subjects/Keywords: ferroelectric; DRAM-Flash hybrid; nonvolatile memories

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APA (6th Edition):

Rajwade, S. (2013). Hybrid Approaches Towards High–Speed, Low–Voltage Flash Memory Design . (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/33943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rajwade, Shantanu. “Hybrid Approaches Towards High–Speed, Low–Voltage Flash Memory Design .” 2013. Thesis, Cornell University. Accessed February 25, 2020. http://hdl.handle.net/1813/33943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rajwade, Shantanu. “Hybrid Approaches Towards High–Speed, Low–Voltage Flash Memory Design .” 2013. Web. 25 Feb 2020.

Vancouver:

Rajwade S. Hybrid Approaches Towards High–Speed, Low–Voltage Flash Memory Design . [Internet] [Thesis]. Cornell University; 2013. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/1813/33943.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rajwade S. Hybrid Approaches Towards High–Speed, Low–Voltage Flash Memory Design . [Thesis]. Cornell University; 2013. Available from: http://hdl.handle.net/1813/33943

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

15. Zhang, Tao. A Study of DRAM Optimization to Break the Memory Wall.

Degree: PhD, Computer Science and Engineering, 2014, Penn State University

 The well-known “Memory Wall” has been raised in 1990s. At that time, the researchers noticed the diverging exponential increase in the performance of processor and… (more)

Subjects/Keywords: DRAM; Memory Wall; 3D-stacked DRAM; Wide IO; Activation; Precharge; Refresh; Sub-array Level Parallelism

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APA (6th Edition):

Zhang, T. (2014). A Study of DRAM Optimization to Break the Memory Wall. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/21517

Chicago Manual of Style (16th Edition):

Zhang, Tao. “A Study of DRAM Optimization to Break the Memory Wall.” 2014. Doctoral Dissertation, Penn State University. Accessed February 25, 2020. https://etda.libraries.psu.edu/catalog/21517.

MLA Handbook (7th Edition):

Zhang, Tao. “A Study of DRAM Optimization to Break the Memory Wall.” 2014. Web. 25 Feb 2020.

Vancouver:

Zhang T. A Study of DRAM Optimization to Break the Memory Wall. [Internet] [Doctoral dissertation]. Penn State University; 2014. [cited 2020 Feb 25]. Available from: https://etda.libraries.psu.edu/catalog/21517.

Council of Science Editors:

Zhang T. A Study of DRAM Optimization to Break the Memory Wall. [Doctoral Dissertation]. Penn State University; 2014. Available from: https://etda.libraries.psu.edu/catalog/21517

16. Rodriguez, Axel. Étude des mécanismes de déclenchement des Bits Collés dans les SRAM et DRAM en Environnement Radiatif Spatial : Study of Mechanisms Leading to Stuck Bits on SRAM and DRAM Memories in the Space Radiation Environment.

Degree: Docteur es, Électronique, 2017, Montpellier

Les résultats de différentes expériences du CNES (Centre National d’Études Spatiales) embarquées sur satellites montrent que des composants SRAM et SDRAM subissent des erreurs atypiques,… (more)

Subjects/Keywords: Sram; Dram; Tcad; Test; Proton; Neutron; Sram; Dram; Tcad; Testing; Proton; Neutron

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APA (6th Edition):

Rodriguez, A. (2017). Étude des mécanismes de déclenchement des Bits Collés dans les SRAM et DRAM en Environnement Radiatif Spatial : Study of Mechanisms Leading to Stuck Bits on SRAM and DRAM Memories in the Space Radiation Environment. (Doctoral Dissertation). Montpellier. Retrieved from http://www.theses.fr/2017MONTS032

Chicago Manual of Style (16th Edition):

Rodriguez, Axel. “Étude des mécanismes de déclenchement des Bits Collés dans les SRAM et DRAM en Environnement Radiatif Spatial : Study of Mechanisms Leading to Stuck Bits on SRAM and DRAM Memories in the Space Radiation Environment.” 2017. Doctoral Dissertation, Montpellier. Accessed February 25, 2020. http://www.theses.fr/2017MONTS032.

MLA Handbook (7th Edition):

Rodriguez, Axel. “Étude des mécanismes de déclenchement des Bits Collés dans les SRAM et DRAM en Environnement Radiatif Spatial : Study of Mechanisms Leading to Stuck Bits on SRAM and DRAM Memories in the Space Radiation Environment.” 2017. Web. 25 Feb 2020.

Vancouver:

Rodriguez A. Étude des mécanismes de déclenchement des Bits Collés dans les SRAM et DRAM en Environnement Radiatif Spatial : Study of Mechanisms Leading to Stuck Bits on SRAM and DRAM Memories in the Space Radiation Environment. [Internet] [Doctoral dissertation]. Montpellier; 2017. [cited 2020 Feb 25]. Available from: http://www.theses.fr/2017MONTS032.

Council of Science Editors:

Rodriguez A. Étude des mécanismes de déclenchement des Bits Collés dans les SRAM et DRAM en Environnement Radiatif Spatial : Study of Mechanisms Leading to Stuck Bits on SRAM and DRAM Memories in the Space Radiation Environment. [Doctoral Dissertation]. Montpellier; 2017. Available from: http://www.theses.fr/2017MONTS032


Université de Grenoble

17. Bougerol, Antonin. Modes de défaillance induits par l'environnement radiatif naturel dans les mémoires DRAMs : étude, méthodologie de test et protection : Failure modes induced by natural radiation environments on dram memories : study, test methodology and mitigation technique.

Degree: Docteur es, Sciences et technologie industrielles, 2011, Université de Grenoble

Les DRAMs sont des mémoires fréquemment utilisées dans les systèmes aéronautiques et spatiaux. Leur tenue aux radiations doit être connue pour satisfaire les exigences de… (more)

Subjects/Keywords: DRAM; Environnement radiatif; Laser; SEU; SEFI; Tolérance aux fautes; DRAM; Radiative Environments; Laser; SEU; SEFI; Fault tolerance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bougerol, A. (2011). Modes de défaillance induits par l'environnement radiatif naturel dans les mémoires DRAMs : étude, méthodologie de test et protection : Failure modes induced by natural radiation environments on dram memories : study, test methodology and mitigation technique. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2011GRENT020

Chicago Manual of Style (16th Edition):

Bougerol, Antonin. “Modes de défaillance induits par l'environnement radiatif naturel dans les mémoires DRAMs : étude, méthodologie de test et protection : Failure modes induced by natural radiation environments on dram memories : study, test methodology and mitigation technique.” 2011. Doctoral Dissertation, Université de Grenoble. Accessed February 25, 2020. http://www.theses.fr/2011GRENT020.

MLA Handbook (7th Edition):

Bougerol, Antonin. “Modes de défaillance induits par l'environnement radiatif naturel dans les mémoires DRAMs : étude, méthodologie de test et protection : Failure modes induced by natural radiation environments on dram memories : study, test methodology and mitigation technique.” 2011. Web. 25 Feb 2020.

Vancouver:

Bougerol A. Modes de défaillance induits par l'environnement radiatif naturel dans les mémoires DRAMs : étude, méthodologie de test et protection : Failure modes induced by natural radiation environments on dram memories : study, test methodology and mitigation technique. [Internet] [Doctoral dissertation]. Université de Grenoble; 2011. [cited 2020 Feb 25]. Available from: http://www.theses.fr/2011GRENT020.

Council of Science Editors:

Bougerol A. Modes de défaillance induits par l'environnement radiatif naturel dans les mémoires DRAMs : étude, méthodologie de test et protection : Failure modes induced by natural radiation environments on dram memories : study, test methodology and mitigation technique. [Doctoral Dissertation]. Université de Grenoble; 2011. Available from: http://www.theses.fr/2011GRENT020


University of Florida

18. Zhou, Zhenming. Physical Analysis, Modeling, and Design of Nanoscale Finfet-Based Memory Cells.

Degree: PhD, Electrical and Computer Engineering, 2010, University of Florida

 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of… (more)

Subjects/Keywords: Cells; DRAM; Electric current; Electric potential; Electrons; Flash memory; Modeling; Oxides; Simulations; Transistors; dram, fbc, finfet, flash, soi

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhou, Z. (2010). Physical Analysis, Modeling, and Design of Nanoscale Finfet-Based Memory Cells. (Doctoral Dissertation). University of Florida. Retrieved from http://ufdc.ufl.edu/UFE0042406

Chicago Manual of Style (16th Edition):

Zhou, Zhenming. “Physical Analysis, Modeling, and Design of Nanoscale Finfet-Based Memory Cells.” 2010. Doctoral Dissertation, University of Florida. Accessed February 25, 2020. http://ufdc.ufl.edu/UFE0042406.

MLA Handbook (7th Edition):

Zhou, Zhenming. “Physical Analysis, Modeling, and Design of Nanoscale Finfet-Based Memory Cells.” 2010. Web. 25 Feb 2020.

Vancouver:

Zhou Z. Physical Analysis, Modeling, and Design of Nanoscale Finfet-Based Memory Cells. [Internet] [Doctoral dissertation]. University of Florida; 2010. [cited 2020 Feb 25]. Available from: http://ufdc.ufl.edu/UFE0042406.

Council of Science Editors:

Zhou Z. Physical Analysis, Modeling, and Design of Nanoscale Finfet-Based Memory Cells. [Doctoral Dissertation]. University of Florida; 2010. Available from: http://ufdc.ufl.edu/UFE0042406


Virginia Commonwealth University

19. Guo, Yuhua. IMPROVING THE PERFORMANCE AND ENERGY EFFICIENCY OF EMERGING MEMORY SYSTEMS.

Degree: PhD, Electrical & Computer Engineering, 2018, Virginia Commonwealth University

  Modern main memory is primarily built using dynamic random access memory (DRAM) chips. As DRAM chip scales to higher density, there are mainly three… (more)

Subjects/Keywords: Hybrid Memory Systems; DRAM; Die-stacked DRAM; NVM; Energy-efficient; Computer and Systems Architecture; Data Storage Systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Guo, Y. (2018). IMPROVING THE PERFORMANCE AND ENERGY EFFICIENCY OF EMERGING MEMORY SYSTEMS. (Doctoral Dissertation). Virginia Commonwealth University. Retrieved from https://scholarscompass.vcu.edu/etd/5317

Chicago Manual of Style (16th Edition):

Guo, Yuhua. “IMPROVING THE PERFORMANCE AND ENERGY EFFICIENCY OF EMERGING MEMORY SYSTEMS.” 2018. Doctoral Dissertation, Virginia Commonwealth University. Accessed February 25, 2020. https://scholarscompass.vcu.edu/etd/5317.

MLA Handbook (7th Edition):

Guo, Yuhua. “IMPROVING THE PERFORMANCE AND ENERGY EFFICIENCY OF EMERGING MEMORY SYSTEMS.” 2018. Web. 25 Feb 2020.

Vancouver:

Guo Y. IMPROVING THE PERFORMANCE AND ENERGY EFFICIENCY OF EMERGING MEMORY SYSTEMS. [Internet] [Doctoral dissertation]. Virginia Commonwealth University; 2018. [cited 2020 Feb 25]. Available from: https://scholarscompass.vcu.edu/etd/5317.

Council of Science Editors:

Guo Y. IMPROVING THE PERFORMANCE AND ENERGY EFFICIENCY OF EMERGING MEMORY SYSTEMS. [Doctoral Dissertation]. Virginia Commonwealth University; 2018. Available from: https://scholarscompass.vcu.edu/etd/5317


University of Minnesota

20. Liu, Qunzeng. Statistical analysis techniques for logic and memory circuits.

Degree: PhD, Electrical Engineering, 2010, University of Minnesota

 Process variations have become increasingly important as feature sizes enter the sub- 100nm regime and continue to shrink. Both logic and memory circuits have seen… (more)

Subjects/Keywords: Embedded DRAM; Post-silicon optimization; SSTA; Statistical analysis; Electrical Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, Q. (2010). Statistical analysis techniques for logic and memory circuits. (Doctoral Dissertation). University of Minnesota. Retrieved from http://purl.umn.edu/95019

Chicago Manual of Style (16th Edition):

Liu, Qunzeng. “Statistical analysis techniques for logic and memory circuits.” 2010. Doctoral Dissertation, University of Minnesota. Accessed February 25, 2020. http://purl.umn.edu/95019.

MLA Handbook (7th Edition):

Liu, Qunzeng. “Statistical analysis techniques for logic and memory circuits.” 2010. Web. 25 Feb 2020.

Vancouver:

Liu Q. Statistical analysis techniques for logic and memory circuits. [Internet] [Doctoral dissertation]. University of Minnesota; 2010. [cited 2020 Feb 25]. Available from: http://purl.umn.edu/95019.

Council of Science Editors:

Liu Q. Statistical analysis techniques for logic and memory circuits. [Doctoral Dissertation]. University of Minnesota; 2010. Available from: http://purl.umn.edu/95019


NSYSU

21. Chang, Cheng-Hsien. A New Extended Body FinFET for 1T-DRAM Application.

Degree: Master, Electrical Engineering, 2014, NSYSU

 In this paper, we propose a new extended body FinFET (EB-FinFET) for one transistor dynamic random access memory (1T-DRAM) application. As the device scales down,… (more)

Subjects/Keywords: 1T-DRAM; FinFET; Extended Body Region; GIDL Mechanism; Programming Window

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, C. (2014). A New Extended Body FinFET for 1T-DRAM Application. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701114-104442

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Cheng-Hsien. “A New Extended Body FinFET for 1T-DRAM Application.” 2014. Thesis, NSYSU. Accessed February 25, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701114-104442.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Cheng-Hsien. “A New Extended Body FinFET for 1T-DRAM Application.” 2014. Web. 25 Feb 2020.

Vancouver:

Chang C. A New Extended Body FinFET for 1T-DRAM Application. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Feb 25]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701114-104442.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang C. A New Extended Body FinFET for 1T-DRAM Application. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701114-104442

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

22. Sfikas, Georgios. Fault models, test algorithms and embedded test techniques for DRAM circuits.

Degree: 2015, University of Ioannina; Πανεπιστήμιο Ιωαννίνων

 Due to the revolutionary progress in the manufacturing process of Integrated Circuits (ICs) the last decades, electronic systems have become a part of everyday life.… (more)

Subjects/Keywords: Μνήμη; Έλεγχος ορθής λειτουργίας; Ε.Ο.Λ.; Memory; DRAM; Testing; BIST

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APA (6th Edition):

Sfikas, G. (2015). Fault models, test algorithms and embedded test techniques for DRAM circuits. (Thesis). University of Ioannina; Πανεπιστήμιο Ιωαννίνων. Retrieved from http://hdl.handle.net/10442/hedi/42884

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sfikas, Georgios. “Fault models, test algorithms and embedded test techniques for DRAM circuits.” 2015. Thesis, University of Ioannina; Πανεπιστήμιο Ιωαννίνων. Accessed February 25, 2020. http://hdl.handle.net/10442/hedi/42884.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sfikas, Georgios. “Fault models, test algorithms and embedded test techniques for DRAM circuits.” 2015. Web. 25 Feb 2020.

Vancouver:

Sfikas G. Fault models, test algorithms and embedded test techniques for DRAM circuits. [Internet] [Thesis]. University of Ioannina; Πανεπιστήμιο Ιωαννίνων; 2015. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/10442/hedi/42884.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sfikas G. Fault models, test algorithms and embedded test techniques for DRAM circuits. [Thesis]. University of Ioannina; Πανεπιστήμιο Ιωαννίνων; 2015. Available from: http://hdl.handle.net/10442/hedi/42884

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

23. Chen, Yi-Jei. Vertical Double Gate Transistor with N-Bridge for Low Power 1T-DRAM.

Degree: Master, Institute Of Electrical Engineering, 2018, NSYSU

 In this thesis, we propose a Vertical double gate transistor with n-bridge DRAM (VN-DRAM) for low power applications. Unlike conventional current bridge architecture which has… (more)

Subjects/Keywords: Data Retention Time; Programming Window; n-bridge; Vertical Channel; 1T-DRAM

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APA (6th Edition):

Chen, Y. (2018). Vertical Double Gate Transistor with N-Bridge for Low Power 1T-DRAM. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0717118-102927

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Yi-Jei. “Vertical Double Gate Transistor with N-Bridge for Low Power 1T-DRAM.” 2018. Thesis, NSYSU. Accessed February 25, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0717118-102927.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Yi-Jei. “Vertical Double Gate Transistor with N-Bridge for Low Power 1T-DRAM.” 2018. Web. 25 Feb 2020.

Vancouver:

Chen Y. Vertical Double Gate Transistor with N-Bridge for Low Power 1T-DRAM. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Feb 25]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0717118-102927.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Y. Vertical Double Gate Transistor with N-Bridge for Low Power 1T-DRAM. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0717118-102927

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

24. Lin, Hung-Hsiu. Doping-less 1T-DRAM With Schottky Contact and Raised Body For Low Power Application.

Degree: Master, Chinese Literature, 2018, NSYSU

 In this thesis, we propose a novel structure of Doping-less 1T-DRAM with raised body and Schottky contact S/D. As the device has not any physical… (more)

Subjects/Keywords: Raised Body; Schottky Source/Drain; Capacitorless; Doping-less; 1T-DRAM

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APA (6th Edition):

Lin, H. (2018). Doping-less 1T-DRAM With Schottky Contact and Raised Body For Low Power Application. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0714118-163047

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Hung-Hsiu. “Doping-less 1T-DRAM With Schottky Contact and Raised Body For Low Power Application.” 2018. Thesis, NSYSU. Accessed February 25, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0714118-163047.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Hung-Hsiu. “Doping-less 1T-DRAM With Schottky Contact and Raised Body For Low Power Application.” 2018. Web. 25 Feb 2020.

Vancouver:

Lin H. Doping-less 1T-DRAM With Schottky Contact and Raised Body For Low Power Application. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Feb 25]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0714118-163047.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin H. Doping-less 1T-DRAM With Schottky Contact and Raised Body For Low Power Application. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0714118-163047

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Waterloo

25. Hassan, Mohamed. Predictable Shared Memory Resources for Multi-Core Real-Time Systems.

Degree: 2017, University of Waterloo

 A major challenge in multi-core real-time systems is the interference problem on the shared hardware components amongst cores. Examples of these shared components include buses,… (more)

Subjects/Keywords: Real-time; Embedded Systems; Comptuer Hardware; Memory Systems; DRAM; Timing analysis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hassan, M. (2017). Predictable Shared Memory Resources for Multi-Core Real-Time Systems. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/11676

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hassan, Mohamed. “Predictable Shared Memory Resources for Multi-Core Real-Time Systems.” 2017. Thesis, University of Waterloo. Accessed February 25, 2020. http://hdl.handle.net/10012/11676.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hassan, Mohamed. “Predictable Shared Memory Resources for Multi-Core Real-Time Systems.” 2017. Web. 25 Feb 2020.

Vancouver:

Hassan M. Predictable Shared Memory Resources for Multi-Core Real-Time Systems. [Internet] [Thesis]. University of Waterloo; 2017. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/10012/11676.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hassan M. Predictable Shared Memory Resources for Multi-Core Real-Time Systems. [Thesis]. University of Waterloo; 2017. Available from: http://hdl.handle.net/10012/11676

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

26. Judd, Patrick. Bundling Spatially Correlated Prefetches for Improved Main Memory Row Buffer Locality.

Degree: 2014, University of Toronto

Row buffer locality is a consequence of programs' inherent spatial locality that the memory system can easily exploit for significant performance gains and power savings.… (more)

Subjects/Keywords: DRAM; memory controller; prefetching; row buffer locality; scheduling; 0464

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APA (6th Edition):

Judd, P. (2014). Bundling Spatially Correlated Prefetches for Improved Main Memory Row Buffer Locality. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/67890

Chicago Manual of Style (16th Edition):

Judd, Patrick. “Bundling Spatially Correlated Prefetches for Improved Main Memory Row Buffer Locality.” 2014. Masters Thesis, University of Toronto. Accessed February 25, 2020. http://hdl.handle.net/1807/67890.

MLA Handbook (7th Edition):

Judd, Patrick. “Bundling Spatially Correlated Prefetches for Improved Main Memory Row Buffer Locality.” 2014. Web. 25 Feb 2020.

Vancouver:

Judd P. Bundling Spatially Correlated Prefetches for Improved Main Memory Row Buffer Locality. [Internet] [Masters thesis]. University of Toronto; 2014. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/1807/67890.

Council of Science Editors:

Judd P. Bundling Spatially Correlated Prefetches for Improved Main Memory Row Buffer Locality. [Masters Thesis]. University of Toronto; 2014. Available from: http://hdl.handle.net/1807/67890


Western Kentucky University

27. Mendis, Ruchini Dilinika. Sensitivity Analyses for Tumor Growth Models.

Degree: MS, Department of Mathematics, 2019, Western Kentucky University

  This study consists of the sensitivity analysis for two previously developed tumor growth models: Gompertz model and quotient model. The two models are considered… (more)

Subjects/Keywords: statistics; Random Walk Metropolis Algorithm; DRAM; Credible intervals; Applied Statistics

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APA (6th Edition):

Mendis, R. D. (2019). Sensitivity Analyses for Tumor Growth Models. (Masters Thesis). Western Kentucky University. Retrieved from https://digitalcommons.wku.edu/theses/3113

Chicago Manual of Style (16th Edition):

Mendis, Ruchini Dilinika. “Sensitivity Analyses for Tumor Growth Models.” 2019. Masters Thesis, Western Kentucky University. Accessed February 25, 2020. https://digitalcommons.wku.edu/theses/3113.

MLA Handbook (7th Edition):

Mendis, Ruchini Dilinika. “Sensitivity Analyses for Tumor Growth Models.” 2019. Web. 25 Feb 2020.

Vancouver:

Mendis RD. Sensitivity Analyses for Tumor Growth Models. [Internet] [Masters thesis]. Western Kentucky University; 2019. [cited 2020 Feb 25]. Available from: https://digitalcommons.wku.edu/theses/3113.

Council of Science Editors:

Mendis RD. Sensitivity Analyses for Tumor Growth Models. [Masters Thesis]. Western Kentucky University; 2019. Available from: https://digitalcommons.wku.edu/theses/3113


University of Toronto

28. Nacouzi, Michel El. On Optimizing Die-stacked DRAM Caches.

Degree: 2013, University of Toronto

Die-stacking is a new technology that allows multiple integrated circuits to be stacked on top of each other while connected with a high-bandwidth and high-speed… (more)

Subjects/Keywords: Die-Stacked DRAM caches; Computer Architecture; 0984; 0544; 0537

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APA (6th Edition):

Nacouzi, M. E. (2013). On Optimizing Die-stacked DRAM Caches. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/42831

Chicago Manual of Style (16th Edition):

Nacouzi, Michel El. “On Optimizing Die-stacked DRAM Caches.” 2013. Masters Thesis, University of Toronto. Accessed February 25, 2020. http://hdl.handle.net/1807/42831.

MLA Handbook (7th Edition):

Nacouzi, Michel El. “On Optimizing Die-stacked DRAM Caches.” 2013. Web. 25 Feb 2020.

Vancouver:

Nacouzi ME. On Optimizing Die-stacked DRAM Caches. [Internet] [Masters thesis]. University of Toronto; 2013. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/1807/42831.

Council of Science Editors:

Nacouzi ME. On Optimizing Die-stacked DRAM Caches. [Masters Thesis]. University of Toronto; 2013. Available from: http://hdl.handle.net/1807/42831


University of Texas – Austin

29. -0784-923X. Nearly free resilient memory architectures that balance resilience, performance, and cost.

Degree: PhD, Electrical and Computer Engineering, 2017, University of Texas – Austin

 Memory reliability has been a major design constraint for mission-critical and large-scale systems for many years. Continued innovation is still necessary because the rate of… (more)

Subjects/Keywords: Memory; Resilience; Fault tolerance; DRAM; GPU; CPU; Cache; Repair; Retirement; Microarchitecture

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APA (6th Edition):

-0784-923X. (2017). Nearly free resilient memory architectures that balance resilience, performance, and cost. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/63490

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-0784-923X. “Nearly free resilient memory architectures that balance resilience, performance, and cost.” 2017. Doctoral Dissertation, University of Texas – Austin. Accessed February 25, 2020. http://hdl.handle.net/2152/63490.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-0784-923X. “Nearly free resilient memory architectures that balance resilience, performance, and cost.” 2017. Web. 25 Feb 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-0784-923X. Nearly free resilient memory architectures that balance resilience, performance, and cost. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2017. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/2152/63490.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-0784-923X. Nearly free resilient memory architectures that balance resilience, performance, and cost. [Doctoral Dissertation]. University of Texas – Austin; 2017. Available from: http://hdl.handle.net/2152/63490

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


George Mason University

30. Badwan, Ahmad Zuhdi. Physics and Design of SOI FED Based Memory Cells .

Degree: 2016, George Mason University

 Memory arrays occupy a very large area in chip designs; yet memory cell scaling lags significantly transistor scaling. With transistor channel lengths in the nanoscale… (more)

Subjects/Keywords: Electrical engineering; DRAM; FED; field effect diode; SRAM; Thyristor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Badwan, A. Z. (2016). Physics and Design of SOI FED Based Memory Cells . (Thesis). George Mason University. Retrieved from http://hdl.handle.net/1920/10200

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Badwan, Ahmad Zuhdi. “Physics and Design of SOI FED Based Memory Cells .” 2016. Thesis, George Mason University. Accessed February 25, 2020. http://hdl.handle.net/1920/10200.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Badwan, Ahmad Zuhdi. “Physics and Design of SOI FED Based Memory Cells .” 2016. Web. 25 Feb 2020.

Vancouver:

Badwan AZ. Physics and Design of SOI FED Based Memory Cells . [Internet] [Thesis]. George Mason University; 2016. [cited 2020 Feb 25]. Available from: http://hdl.handle.net/1920/10200.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Badwan AZ. Physics and Design of SOI FED Based Memory Cells . [Thesis]. George Mason University; 2016. Available from: http://hdl.handle.net/1920/10200

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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