Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(Custom accelerators). Showing records 1 – 3 of 3 total matches.

Search Limiters

Last 2 Years | English Only

No search limiters apply to these results.

▼ Search Limiters


McMaster University

1. Kinsman, Adam. A Computational Approach to Custom Data Representation for Hardware Accelerators.

Degree: PhD, 2010, McMaster University

This thesis details the application of computational methods to the problem of determining custom data representations when building hardware accelerators for numerical computations. A majority of scientific applications which require hardware acceleration are implemented in IEEE-754 double precision. However, in many cases the error tolerance requirements of the application are much less than the accuracy which IEEE-754 double precision provides. By leveraging custom data representations, a more resource efficient hardware implementation arises thereby enabling greater parallelism and thus higher performance of the accelerator. The existing custom representation methods are unable to guarantee robust representations while at the same time adequately supporting ill-conditioned operators. Support for both of these scenarios is necessary for accelerating scientific calculations. To address this, we propose the use of a computational method based on Satisfiability-Modulo Theory (SMT). By capturing a calculation as a set of constraints, an SMT instance can be formulated which provides meaningful bounds even in the presence of ill-conditioned operators. At the same time, the analytical nature of SMT satisfies the need for robustness. Utilizing block vector arithmetic, our SMT approach is extended to provide scalability to large instances involving vector calculus which arise in scientific calculations. Atop this foundation, a unified error model is proposed which deals simultaneously with absolute and relative error, thereby providing the means of supporting both fixed-point and custom floating-point data types. Iterative algorithm analysis is leveraged to derive constraints for the SMT method. The application of the method to several scientific algorithms is discussed by way of case studies.

Thesis

Doctor of Philosophy (PhD)

Advisors/Committee Members: Nicolici, Nicola, Electrical and Computer Engineering.

Subjects/Keywords: custom data representation; hardware accelerators; computational method; numerical computation

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kinsman, A. (2010). A Computational Approach to Custom Data Representation for Hardware Accelerators. (Doctoral Dissertation). McMaster University. Retrieved from http://hdl.handle.net/11375/18990

Chicago Manual of Style (16th Edition):

Kinsman, Adam. “A Computational Approach to Custom Data Representation for Hardware Accelerators.” 2010. Doctoral Dissertation, McMaster University. Accessed November 21, 2019. http://hdl.handle.net/11375/18990.

MLA Handbook (7th Edition):

Kinsman, Adam. “A Computational Approach to Custom Data Representation for Hardware Accelerators.” 2010. Web. 21 Nov 2019.

Vancouver:

Kinsman A. A Computational Approach to Custom Data Representation for Hardware Accelerators. [Internet] [Doctoral dissertation]. McMaster University; 2010. [cited 2019 Nov 21]. Available from: http://hdl.handle.net/11375/18990.

Council of Science Editors:

Kinsman A. A Computational Approach to Custom Data Representation for Hardware Accelerators. [Doctoral Dissertation]. McMaster University; 2010. Available from: http://hdl.handle.net/11375/18990


University of Illinois – Chicago

2. Di Tucci, Lorenzo. Efficient High Performance FPGA-Based Applications Design via SDAccel.

Degree: 2016, University of Illinois – Chicago

Custom hardware accelerators are widely used to improve the performance of software appli- cations in terms of execution times and to reduce energy consumption. However, the realization of a hardware accelerator and its integration into the final system is a difficult and error prone process. For this reason, both industry and academy are continuously developing Computer Aided Design (CAD) tools to assist the designer in the development process. Although many of the steps of the design are now automated, system integration, SW/HW interfaces definition and drivers generation are still almost completely manual tasks. The latest tool by Xilinx how- ever, aims at improving the hardware design experience by automating the majority of the steps in the design flow and by leveraging the OpenCL standard to enhance the overall productivity and to enable code portability. This work provides an analysis and an overview of the new Xilinx SDAccel framework, comparing its design flow to other state of the art frameworks. In this context we use this tool to accelerate two case studies from the bioinformatics field. The first case study concerns pairwise alignment and the second one the protein folding problem. The work is organized as follows: • We start with an introduction to our work, followed by a brief introduction to the context and our contributions in Chapter 1.• Chapter 2 gives the reader an overview of Field Programmable Gate Arrays (FPGAs), followed by an introduction to the Hardware Design Flow (HDF). The chapter ends with a theoretical introduction of the two case studies that we developed. • Chapter 3 describes some state of the art tools used in the design of hardware applications, comparing them and highlighting the main features of each. • Chapter 4 analyzes the problem presented in this dissertation. It starts by describing the design for HPC and ends by talking of how new CAD tools aims at automating the steps of the hardware design flow. • Chapter 5 introduces the tool we used to accelerate our case studies: SDAccel. It starts with an introduction to the framework, then it introduces its architecture and its main features. Finally, it discusses how we faced the problems of the tool and our contributions to its development. • Chapter 6 describes how we decided to accelerate the two case studies introduced in Chapter 2. It explains the architectural choices that we’ve made, as well as the reasons that lead us to choose them. • Chapter 7, presents the results of the two case studies, the experimental settings and the comparison of our result with state of the art implementation of the same algorithm. • Finally, in Chapter 8 we draw the conclusions of this work and we provide some insights into possible future work. Advisors/Committee Members: Rao, Wejing (advisor).

Subjects/Keywords: FPGA; SDAccel; EDA; CAD; Smith-Waterman; Protein Folding; Hardware Acceleration; Hardware Design Flow; High Level Synthesis; System Level Design; Hardware Architecture; Custom Hardware Accelerators

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Di Tucci, L. (2016). Efficient High Performance FPGA-Based Applications Design via SDAccel. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/21325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Di Tucci, Lorenzo. “Efficient High Performance FPGA-Based Applications Design via SDAccel.” 2016. Thesis, University of Illinois – Chicago. Accessed November 21, 2019. http://hdl.handle.net/10027/21325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Di Tucci, Lorenzo. “Efficient High Performance FPGA-Based Applications Design via SDAccel.” 2016. Web. 21 Nov 2019.

Vancouver:

Di Tucci L. Efficient High Performance FPGA-Based Applications Design via SDAccel. [Internet] [Thesis]. University of Illinois – Chicago; 2016. [cited 2019 Nov 21]. Available from: http://hdl.handle.net/10027/21325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Di Tucci L. Efficient High Performance FPGA-Based Applications Design via SDAccel. [Thesis]. University of Illinois – Chicago; 2016. Available from: http://hdl.handle.net/10027/21325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arkansas

3. Ma, Sen. Just In Time Assembly (JITA) - A Run Time Interpretation Approach for Achieving Productivity of Creating Custom Accelerators in FPGAs.

Degree: PhD, 2016, University of Arkansas

The reconfigurable computing community has yet to be successful in allowing programmers to access FPGAs through traditional software development flows. Existing barriers that prevent programmers from using FPGAs include: 1) knowledge of hardware programming models, 2) the need to work within the vendor specific CAD tools and hardware synthesis. This thesis presents a series of published papers that explore different aspects of a new approach being developed to remove the barriers and enable programmers to compile accelerators on next generation reconfigurable manycore architectures. The approach is entitled Just In Time Assembly (JITA) of hardware accelerators. The approach has been defined to allow hardware accelerators to be built and run through software compilation and run time interpretation outside of CAD tools and without requiring each new accelerator to be synthesized. The approach advocates the use of libraries of pre-synthesized components that can be referenced through symbolic links in a similar fashion to dynamically linked software libraries. Synthesis still must occur but is moved out of the application programmers software flow and into the initial coding process that occurs when programming patterns that define a Domain Specific Language (DSL) are first coded. Programmers see no difference between creating software or hardware functionality when using the DSL. A new run time interpreter is introduced to assemble the individual pre-synthesized hardware accelerators that comprise the accelerator functionality within a configurable tile array of partially reconfigurable slots at run time. Quantitative results are presented that compares utilization, performance, and productivity of the approach to what would be achieved by full custom accelerators created through traditional CAD flows using hardware programming models and passing through synthesis. Advisors/Committee Members: David Andrews, Christophe Bobda, John Gauch.

Subjects/Keywords: Applied sciences; Custom accelerators; Field-Programmable Gate Arrays; Just in time; Productivity; Run time interpretation; Computer and Systems Architecture; Programming Languages and Compilers; Software Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ma, S. (2016). Just In Time Assembly (JITA) - A Run Time Interpretation Approach for Achieving Productivity of Creating Custom Accelerators in FPGAs. (Doctoral Dissertation). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1810

Chicago Manual of Style (16th Edition):

Ma, Sen. “Just In Time Assembly (JITA) - A Run Time Interpretation Approach for Achieving Productivity of Creating Custom Accelerators in FPGAs.” 2016. Doctoral Dissertation, University of Arkansas. Accessed November 21, 2019. https://scholarworks.uark.edu/etd/1810.

MLA Handbook (7th Edition):

Ma, Sen. “Just In Time Assembly (JITA) - A Run Time Interpretation Approach for Achieving Productivity of Creating Custom Accelerators in FPGAs.” 2016. Web. 21 Nov 2019.

Vancouver:

Ma S. Just In Time Assembly (JITA) - A Run Time Interpretation Approach for Achieving Productivity of Creating Custom Accelerators in FPGAs. [Internet] [Doctoral dissertation]. University of Arkansas; 2016. [cited 2019 Nov 21]. Available from: https://scholarworks.uark.edu/etd/1810.

Council of Science Editors:

Ma S. Just In Time Assembly (JITA) - A Run Time Interpretation Approach for Achieving Productivity of Creating Custom Accelerators in FPGAs. [Doctoral Dissertation]. University of Arkansas; 2016. Available from: https://scholarworks.uark.edu/etd/1810

.