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McMaster University
1. Kinsman, Adam. A Computational Approach to Custom Data Representation for Hardware Accelerators.
Degree: PhD, 2010, McMaster University
URL: http://hdl.handle.net/11375/18990
This thesis details the application of computational methods to the problem of determining custom data representations when building hardware accelerators for numerical computations. A majority of scientific applications which require hardware acceleration are implemented in IEEE-754 double precision. However, in many cases the error tolerance requirements of the application are much less than the accuracy which IEEE-754 double precision provides. By leveraging custom data representations, a more resource efficient hardware implementation arises thereby enabling greater parallelism and thus higher performance of the accelerator. The existing custom representation methods are unable to guarantee robust representations while at the same time adequately supporting ill-conditioned operators. Support for both of these scenarios is necessary for accelerating scientific calculations. To address this, we propose the use of a computational method based on Satisfiability-Modulo Theory (SMT). By capturing a calculation as a set of constraints, an SMT instance can be formulated which provides meaningful bounds even in the presence of ill-conditioned operators. At the same time, the analytical nature of SMT satisfies the need for robustness. Utilizing block vector arithmetic, our SMT approach is extended to provide scalability to large instances involving vector calculus which arise in scientific calculations. Atop this foundation, a unified error model is proposed which deals simultaneously with absolute and relative error, thereby providing the means of supporting both fixed-point and custom floating-point data types. Iterative algorithm analysis is leveraged to derive constraints for the SMT method. The application of the method to several scientific algorithms is discussed by way of case studies.
Thesis
Doctor of Philosophy (PhD)
Advisors/Committee Members: Nicolici, Nicola, Electrical and Computer Engineering.Subjects/Keywords: custom data representation; hardware accelerators; computational method; numerical computation
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Kinsman, A. (2010). A Computational Approach to Custom Data Representation for Hardware Accelerators. (Doctoral Dissertation). McMaster University. Retrieved from http://hdl.handle.net/11375/18990
Chicago Manual of Style (16th Edition):
Kinsman, Adam. “A Computational Approach to Custom Data Representation for Hardware Accelerators.” 2010. Doctoral Dissertation, McMaster University. Accessed January 16, 2021. http://hdl.handle.net/11375/18990.
MLA Handbook (7th Edition):
Kinsman, Adam. “A Computational Approach to Custom Data Representation for Hardware Accelerators.” 2010. Web. 16 Jan 2021.
Vancouver:
Kinsman A. A Computational Approach to Custom Data Representation for Hardware Accelerators. [Internet] [Doctoral dissertation]. McMaster University; 2010. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/11375/18990.
Council of Science Editors:
Kinsman A. A Computational Approach to Custom Data Representation for Hardware Accelerators. [Doctoral Dissertation]. McMaster University; 2010. Available from: http://hdl.handle.net/11375/18990
University of Illinois – Chicago
2. Di Tucci, Lorenzo. Efficient High Performance FPGA-Based Applications Design via SDAccel.
Degree: 2016, University of Illinois – Chicago
URL: http://hdl.handle.net/10027/21325
Subjects/Keywords: FPGA; SDAccel; EDA; CAD; Smith-Waterman; Protein Folding; Hardware Acceleration; Hardware Design Flow; High Level Synthesis; System Level Design; Hardware Architecture; Custom Hardware Accelerators
Record Details
Similar Records
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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Di Tucci, L. (2016). Efficient High Performance FPGA-Based Applications Design via SDAccel. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/21325
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Di Tucci, Lorenzo. “Efficient High Performance FPGA-Based Applications Design via SDAccel.” 2016. Thesis, University of Illinois – Chicago. Accessed January 16, 2021. http://hdl.handle.net/10027/21325.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Di Tucci, Lorenzo. “Efficient High Performance FPGA-Based Applications Design via SDAccel.” 2016. Web. 16 Jan 2021.
Vancouver:
Di Tucci L. Efficient High Performance FPGA-Based Applications Design via SDAccel. [Internet] [Thesis]. University of Illinois – Chicago; 2016. [cited 2021 Jan 16]. Available from: http://hdl.handle.net/10027/21325.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Di Tucci L. Efficient High Performance FPGA-Based Applications Design via SDAccel. [Thesis]. University of Illinois – Chicago; 2016. Available from: http://hdl.handle.net/10027/21325
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Arkansas
3. Ma, Sen. Just In Time Assembly (JITA) - A Run Time Interpretation Approach for Achieving Productivity of Creating Custom Accelerators in FPGAs.
Degree: PhD, 2016, University of Arkansas
URL: https://scholarworks.uark.edu/etd/1810
Subjects/Keywords: Applied sciences; Custom accelerators; Field-Programmable Gate Arrays; Just in time; Productivity; Run time interpretation; Computer and Systems Architecture; Programming Languages and Compilers; Software Engineering
Record Details
Similar Records
❌
APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager
APA (6th Edition):
Ma, S. (2016). Just In Time Assembly (JITA) - A Run Time Interpretation Approach for Achieving Productivity of Creating Custom Accelerators in FPGAs. (Doctoral Dissertation). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1810
Chicago Manual of Style (16th Edition):
Ma, Sen. “Just In Time Assembly (JITA) - A Run Time Interpretation Approach for Achieving Productivity of Creating Custom Accelerators in FPGAs.” 2016. Doctoral Dissertation, University of Arkansas. Accessed January 16, 2021. https://scholarworks.uark.edu/etd/1810.
MLA Handbook (7th Edition):
Ma, Sen. “Just In Time Assembly (JITA) - A Run Time Interpretation Approach for Achieving Productivity of Creating Custom Accelerators in FPGAs.” 2016. Web. 16 Jan 2021.
Vancouver:
Ma S. Just In Time Assembly (JITA) - A Run Time Interpretation Approach for Achieving Productivity of Creating Custom Accelerators in FPGAs. [Internet] [Doctoral dissertation]. University of Arkansas; 2016. [cited 2021 Jan 16]. Available from: https://scholarworks.uark.edu/etd/1810.
Council of Science Editors:
Ma S. Just In Time Assembly (JITA) - A Run Time Interpretation Approach for Achieving Productivity of Creating Custom Accelerators in FPGAs. [Doctoral Dissertation]. University of Arkansas; 2016. Available from: https://scholarworks.uark.edu/etd/1810