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You searched for subject:(Current mode logic). Showing records 1 – 12 of 12 total matches.

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California State University – Sacramento

1. Silva, William. A tapered CML buffer chain design for a 1 GHz interpolating flash ADC.

Degree: MS, Electrical and Electronic Engineering, 2010, California State University – Sacramento

Current Mode Logic buffers are based on the MOS differential amplifier circuit. Since CML buffers utilize a differential circuit topology, they are less vulnerable to… (more)

Subjects/Keywords: Current; Mode; Logic

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APA (6th Edition):

Silva, W. (2010). A tapered CML buffer chain design for a 1 GHz interpolating flash ADC. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.9/461

Chicago Manual of Style (16th Edition):

Silva, William. “A tapered CML buffer chain design for a 1 GHz interpolating flash ADC.” 2010. Masters Thesis, California State University – Sacramento. Accessed January 23, 2017. http://hdl.handle.net/10211.9/461.

MLA Handbook (7th Edition):

Silva, William. “A tapered CML buffer chain design for a 1 GHz interpolating flash ADC.” 2010. Web. 23 Jan 2017.

Vancouver:

Silva W. A tapered CML buffer chain design for a 1 GHz interpolating flash ADC. [Internet] [Masters thesis]. California State University – Sacramento; 2010. [cited 2017 Jan 23]. Available from: http://hdl.handle.net/10211.9/461.

Council of Science Editors:

Silva W. A tapered CML buffer chain design for a 1 GHz interpolating flash ADC. [Masters Thesis]. California State University – Sacramento; 2010. Available from: http://hdl.handle.net/10211.9/461


University of Rochester

2. Bai, Yuxin. Energy efficient microarchitectures for on-chip voltage regulation and low noise computing.

Degree: PhD, 2016, University of Rochester

 Power- and energy-efficiency are significant requirements in virtually all computer systems, from mobile devices to large-scale data centers. Power delivery is a process that distributes… (more)

Subjects/Keywords: Energy efficiency; Microarchitecture; Microprocessor; MOS current mode logic; Power management; Voltage regulator

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APA (6th Edition):

Bai, Y. (2016). Energy efficient microarchitectures for on-chip voltage regulation and low noise computing. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/30825

Chicago Manual of Style (16th Edition):

Bai, Yuxin. “Energy efficient microarchitectures for on-chip voltage regulation and low noise computing.” 2016. Doctoral Dissertation, University of Rochester. Accessed January 23, 2017. http://hdl.handle.net/1802/30825.

MLA Handbook (7th Edition):

Bai, Yuxin. “Energy efficient microarchitectures for on-chip voltage regulation and low noise computing.” 2016. Web. 23 Jan 2017.

Vancouver:

Bai Y. Energy efficient microarchitectures for on-chip voltage regulation and low noise computing. [Internet] [Doctoral dissertation]. University of Rochester; 2016. [cited 2017 Jan 23]. Available from: http://hdl.handle.net/1802/30825.

Council of Science Editors:

Bai Y. Energy efficient microarchitectures for on-chip voltage regulation and low noise computing. [Doctoral Dissertation]. University of Rochester; 2016. Available from: http://hdl.handle.net/1802/30825

3. Novak, Ashley. Mixed-Signal Carry Look-Ahead Adder with Constant Power for Cryptographic Applications.

Degree: MA, Electrical and Computer Engineering, 2012, National Library of Canada

 Due to the ubiquity of electronic communication systems in consumers' lives, it is necessary to ensure that the sensitive information being transmitted is not accessible… (more)

Subjects/Keywords: Applied sciences; Constant power; Cryptography; Current-mode logic; Hardware; Multiple-valued adder; Power analysis attack

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APA (6th Edition):

Novak, A. (2012). Mixed-Signal Carry Look-Ahead Adder with Constant Power for Cryptographic Applications. (Masters Thesis). National Library of Canada. Retrieved from http://scholar.uwindsor.ca/etd/4833

Chicago Manual of Style (16th Edition):

Novak, Ashley. “Mixed-Signal Carry Look-Ahead Adder with Constant Power for Cryptographic Applications.” 2012. Masters Thesis, National Library of Canada. Accessed January 23, 2017. http://scholar.uwindsor.ca/etd/4833.

MLA Handbook (7th Edition):

Novak, Ashley. “Mixed-Signal Carry Look-Ahead Adder with Constant Power for Cryptographic Applications.” 2012. Web. 23 Jan 2017.

Vancouver:

Novak A. Mixed-Signal Carry Look-Ahead Adder with Constant Power for Cryptographic Applications. [Internet] [Masters thesis]. National Library of Canada; 2012. [cited 2017 Jan 23]. Available from: http://scholar.uwindsor.ca/etd/4833.

Council of Science Editors:

Novak A. Mixed-Signal Carry Look-Ahead Adder with Constant Power for Cryptographic Applications. [Masters Thesis]. National Library of Canada; 2012. Available from: http://scholar.uwindsor.ca/etd/4833


University of Windsor

4. Novak, Ashley. Mixed-Signal Carry Look-Ahead Adder with Constant Power for Cryptographic Applications.

Degree: MA, Electrical and Computer Engineering, 2012, University of Windsor

 Due to the ubiquity of electronic communication systems in consumers' lives, it is necessary to ensure that the sensitive information being transmitted is not accessible… (more)

Subjects/Keywords: Applied sciences; Constant power; Cryptography; Current-mode logic; Hardware; Multiple-valued adder; Power analysis attack

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APA (6th Edition):

Novak, A. (2012). Mixed-Signal Carry Look-Ahead Adder with Constant Power for Cryptographic Applications. (Masters Thesis). University of Windsor. Retrieved from http://scholar.uwindsor.ca/etd/4833

Chicago Manual of Style (16th Edition):

Novak, Ashley. “Mixed-Signal Carry Look-Ahead Adder with Constant Power for Cryptographic Applications.” 2012. Masters Thesis, University of Windsor. Accessed January 23, 2017. http://scholar.uwindsor.ca/etd/4833.

MLA Handbook (7th Edition):

Novak, Ashley. “Mixed-Signal Carry Look-Ahead Adder with Constant Power for Cryptographic Applications.” 2012. Web. 23 Jan 2017.

Vancouver:

Novak A. Mixed-Signal Carry Look-Ahead Adder with Constant Power for Cryptographic Applications. [Internet] [Masters thesis]. University of Windsor; 2012. [cited 2017 Jan 23]. Available from: http://scholar.uwindsor.ca/etd/4833.

Council of Science Editors:

Novak A. Mixed-Signal Carry Look-Ahead Adder with Constant Power for Cryptographic Applications. [Masters Thesis]. University of Windsor; 2012. Available from: http://scholar.uwindsor.ca/etd/4833


Indian Institute of Science

5. Bhat, Shankaranarayana M. Current-Mode Techniques In The Synthesis And Applications Of Analog And Multi-Valued Logic In Mixed Signal Design.

Degree: 2006, Indian Institute of Science

 The development of modern integration technologies is normally driven by the needs of digital CMOS circuit design. Rapid progress in silicon VLSI technologies has made… (more)

Subjects/Keywords: Signal Processing - Digital Techniques; Multiple-Valued Logic (MVL); CMOS Design; Complementary Metal Oxide Semiconductors; Genetic Algorithm; Current-Mode Circuits; Circuit Design; Current-Mode Signaling; Communication Engineering

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APA (6th Edition):

Bhat, S. M. (2006). Current-Mode Techniques In The Synthesis And Applications Of Analog And Multi-Valued Logic In Mixed Signal Design. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/373

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bhat, Shankaranarayana M. “Current-Mode Techniques In The Synthesis And Applications Of Analog And Multi-Valued Logic In Mixed Signal Design.” 2006. Thesis, Indian Institute of Science. Accessed January 23, 2017. http://hdl.handle.net/2005/373.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bhat, Shankaranarayana M. “Current-Mode Techniques In The Synthesis And Applications Of Analog And Multi-Valued Logic In Mixed Signal Design.” 2006. Web. 23 Jan 2017.

Vancouver:

Bhat SM. Current-Mode Techniques In The Synthesis And Applications Of Analog And Multi-Valued Logic In Mixed Signal Design. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2017 Jan 23]. Available from: http://hdl.handle.net/2005/373.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bhat SM. Current-Mode Techniques In The Synthesis And Applications Of Analog And Multi-Valued Logic In Mixed Signal Design. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/373

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

6. Ravikumar, Sabareeshkumar. Circuit architectures for high speed CMOS clock and data recovery circuits.

Degree: MS, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 As semiconductor process technologies continue to scale and the demand for ubiquitous computing devices continues to grow with paradigms such as the internet of things… (more)

Subjects/Keywords: Serial link; Clock and data recovery (CDR); Current mode logic; Complementary metal-oxide semiconductor (CMOS); Circuit architecture

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APA (6th Edition):

Ravikumar, S. (2015). Circuit architectures for high speed CMOS clock and data recovery circuits. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78416

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ravikumar, Sabareeshkumar. “Circuit architectures for high speed CMOS clock and data recovery circuits.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed January 23, 2017. http://hdl.handle.net/2142/78416.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ravikumar, Sabareeshkumar. “Circuit architectures for high speed CMOS clock and data recovery circuits.” 2015. Web. 23 Jan 2017.

Vancouver:

Ravikumar S. Circuit architectures for high speed CMOS clock and data recovery circuits. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2017 Jan 23]. Available from: http://hdl.handle.net/2142/78416.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ravikumar S. Circuit architectures for high speed CMOS clock and data recovery circuits. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78416

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

7. Canal, Bruno. MCML gate design methodology ante the tradeoffs between MCML and CMOS applications.

Degree: 2016, Universidade do Rio Grande do Sul

This work proposes a simulation-based methodology to design MOS Current-Mode Logic (MCML) gates and addresses the tradeoffs of the MCML versus static CMOS circuits. MCML… (more)

Subjects/Keywords: Microeletronica; MOS current-mode logic; MCML; Cmos : Circuitos integrados : Eletronica; Portas logicas; MCML gate design; MCML application

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APA (6th Edition):

Canal, B. (2016). MCML gate design methodology ante the tradeoffs between MCML and CMOS applications. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/142585

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Canal, Bruno. “MCML gate design methodology ante the tradeoffs between MCML and CMOS applications.” 2016. Thesis, Universidade do Rio Grande do Sul. Accessed January 23, 2017. http://hdl.handle.net/10183/142585.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Canal, Bruno. “MCML gate design methodology ante the tradeoffs between MCML and CMOS applications.” 2016. Web. 23 Jan 2017.

Vancouver:

Canal B. MCML gate design methodology ante the tradeoffs between MCML and CMOS applications. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2016. [cited 2017 Jan 23]. Available from: http://hdl.handle.net/10183/142585.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Canal B. MCML gate design methodology ante the tradeoffs between MCML and CMOS applications. [Thesis]. Universidade do Rio Grande do Sul; 2016. Available from: http://hdl.handle.net/10183/142585

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

8. Jeon, Hyung-Joon. Design of Mixed-mode Adaptive Loop Gain Bang-Bang Clock and Data Recovery and Process-Variation-Resilient Current Mode Logic.

Degree: 2013, Texas A&M University

 As the volume of data processed by computers and telecommunication devices rapidly increases, high speed serial link has been challenged to maximize its I/O bandwidth… (more)

Subjects/Keywords: Integrated circuit; Mixed signal; Serial link; Clock and Data Recovery; CDR; Current Mode Logic; CML; Phase Locked Loop; PLL

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APA (6th Edition):

Jeon, H. (2013). Design of Mixed-mode Adaptive Loop Gain Bang-Bang Clock and Data Recovery and Process-Variation-Resilient Current Mode Logic. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149205

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jeon, Hyung-Joon. “Design of Mixed-mode Adaptive Loop Gain Bang-Bang Clock and Data Recovery and Process-Variation-Resilient Current Mode Logic.” 2013. Thesis, Texas A&M University. Accessed January 23, 2017. http://hdl.handle.net/1969.1/149205.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jeon, Hyung-Joon. “Design of Mixed-mode Adaptive Loop Gain Bang-Bang Clock and Data Recovery and Process-Variation-Resilient Current Mode Logic.” 2013. Web. 23 Jan 2017.

Vancouver:

Jeon H. Design of Mixed-mode Adaptive Loop Gain Bang-Bang Clock and Data Recovery and Process-Variation-Resilient Current Mode Logic. [Internet] [Thesis]. Texas A&M University; 2013. [cited 2017 Jan 23]. Available from: http://hdl.handle.net/1969.1/149205.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jeon H. Design of Mixed-mode Adaptive Loop Gain Bang-Bang Clock and Data Recovery and Process-Variation-Resilient Current Mode Logic. [Thesis]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149205

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


California State University – Sacramento

9. Penmetsa, Sruthi. A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS.

Degree: MS, Electrical and Electronic Engineering, 2016, California State University – Sacramento

 A phase-locked loop (PLL) is an important mixed-signal circuit that is used on almost every integrated circuit. A frequency divider is needed in the PLL… (more)

Subjects/Keywords: CML; CML Buffer; Current-mode logic; All-digital phase-locked loop; Design of CML toggle flip-flop; CML to CMOS converter

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APA (6th Edition):

Penmetsa, S. (2016). A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/182788

Chicago Manual of Style (16th Edition):

Penmetsa, Sruthi. “A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS.” 2016. Masters Thesis, California State University – Sacramento. Accessed January 23, 2017. http://hdl.handle.net/10211.3/182788.

MLA Handbook (7th Edition):

Penmetsa, Sruthi. “A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS.” 2016. Web. 23 Jan 2017.

Vancouver:

Penmetsa S. A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS. [Internet] [Masters thesis]. California State University – Sacramento; 2016. [cited 2017 Jan 23]. Available from: http://hdl.handle.net/10211.3/182788.

Council of Science Editors:

Penmetsa S. A current-mode logic frequency divider for an all digital phase-locked loop in 0.18um CMOS. [Masters Thesis]. California State University – Sacramento; 2016. Available from: http://hdl.handle.net/10211.3/182788

10. Mishra, Satyabh. Design of charge pump phase locked loop.

Degree: 2012, Texas Tech University

 Phase Locked Loop system is around since 1932. The versatility of PLL systems and where it can apply makes it very useful. It can be… (more)

Subjects/Keywords: Phase locked loop; Pump frequency detector (PFD); Charge pump; Low pass filter; Voltage-controlled oscillator (VCO); Ring oscillator; Frequency divider; Current mode logic; Lock time

…problem, Current Mode Logic (CML) Frequency Dividers are used; the CML dividers can operate at a… …frequency detector in the feedback part can be implemented as the Current Mode Logic or Voltage… …for high output frequency in the GHz range a Current Mode Logic (CML) frequency divider is… …detectors. It also contains one Level Shifter. The Current Mode Logic Divider as well as Digital… …both Current Mode Logic and Voltage Mode Divider is implemented to facilitate high frequency… 

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APA (6th Edition):

Mishra, S. (2012). Design of charge pump phase locked loop. (Masters Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/46975

Chicago Manual of Style (16th Edition):

Mishra, Satyabh. “Design of charge pump phase locked loop.” 2012. Masters Thesis, Texas Tech University. Accessed January 23, 2017. http://hdl.handle.net/2346/46975.

MLA Handbook (7th Edition):

Mishra, Satyabh. “Design of charge pump phase locked loop.” 2012. Web. 23 Jan 2017.

Vancouver:

Mishra S. Design of charge pump phase locked loop. [Internet] [Masters thesis]. Texas Tech University; 2012. [cited 2017 Jan 23]. Available from: http://hdl.handle.net/2346/46975.

Council of Science Editors:

Mishra S. Design of charge pump phase locked loop. [Masters Thesis]. Texas Tech University; 2012. Available from: http://hdl.handle.net/2346/46975

11. LAU WEE YEE WENDY. A high-frequency quad-modulus prescaler for fractional-N frequency synthesizer.

Degree: 2009, National University of Singapore

Subjects/Keywords: quad-modulus prescaler; current mode logic (CML); CMOS; high-frequency; fractional-N frequency synthesizer; phase-locked loop (PLL)

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APA (6th Edition):

WENDY, L. W. Y. (2009). A high-frequency quad-modulus prescaler for fractional-N frequency synthesizer. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/16823 ; http://scholarbank.nus.edu.sg/bitstream/10635%2F16823/1/bitstream ; http://scholarbank.nus.edu.sg/bitstream/10635%2F16823/2/bitstream

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

WENDY, LAU WEE YEE. “A high-frequency quad-modulus prescaler for fractional-N frequency synthesizer.” 2009. Thesis, National University of Singapore. Accessed January 23, 2017. http://scholarbank.nus.edu.sg/handle/10635/16823 ; http://scholarbank.nus.edu.sg/bitstream/10635%2F16823/1/bitstream ; http://scholarbank.nus.edu.sg/bitstream/10635%2F16823/2/bitstream.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

WENDY, LAU WEE YEE. “A high-frequency quad-modulus prescaler for fractional-N frequency synthesizer.” 2009. Web. 23 Jan 2017.

Vancouver:

WENDY LWY. A high-frequency quad-modulus prescaler for fractional-N frequency synthesizer. [Internet] [Thesis]. National University of Singapore; 2009. [cited 2017 Jan 23]. Available from: http://scholarbank.nus.edu.sg/handle/10635/16823 ; http://scholarbank.nus.edu.sg/bitstream/10635%2F16823/1/bitstream ; http://scholarbank.nus.edu.sg/bitstream/10635%2F16823/2/bitstream.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

WENDY LWY. A high-frequency quad-modulus prescaler for fractional-N frequency synthesizer. [Thesis]. National University of Singapore; 2009. Available from: http://scholarbank.nus.edu.sg/handle/10635/16823 ; http://scholarbank.nus.edu.sg/bitstream/10635%2F16823/1/bitstream ; http://scholarbank.nus.edu.sg/bitstream/10635%2F16823/2/bitstream

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

12. Θωίδης, Ιωάννης. Σχεδιασμός συστημάτων VLSI παράλληλης αρχιτεκτονικής με λογική πολλαπλών τιμών.

Degree: 2001, Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ); Democritus University of Thrace (DUTH)

Subjects/Keywords: Αρχιτεκτονική; Λογική πολλαπλών τιμών; Ολοκληρωμένα κυκλώματα; Τασικά κυκλώματα; Εντασικά κυκλώματα; Architecture; Multiple-valued logic; Integrated circuits; Current-mode circuits; Voltage-mode circuits

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APA (6th Edition):

Θωίδης, . (2001). Σχεδιασμός συστημάτων VLSI παράλληλης αρχιτεκτονικής με λογική πολλαπλών τιμών. (Thesis). Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ); Democritus University of Thrace (DUTH). Retrieved from http://hdl.handle.net/10442/hedi/13049

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Θωίδης, Ιωάννης. “Σχεδιασμός συστημάτων VLSI παράλληλης αρχιτεκτονικής με λογική πολλαπλών τιμών.” 2001. Thesis, Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ); Democritus University of Thrace (DUTH). Accessed January 23, 2017. http://hdl.handle.net/10442/hedi/13049.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Θωίδης, Ιωάννης. “Σχεδιασμός συστημάτων VLSI παράλληλης αρχιτεκτονικής με λογική πολλαπλών τιμών.” 2001. Web. 23 Jan 2017.

Vancouver:

Θωίδης . Σχεδιασμός συστημάτων VLSI παράλληλης αρχιτεκτονικής με λογική πολλαπλών τιμών. [Internet] [Thesis]. Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ); Democritus University of Thrace (DUTH); 2001. [cited 2017 Jan 23]. Available from: http://hdl.handle.net/10442/hedi/13049.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Θωίδης . Σχεδιασμός συστημάτων VLSI παράλληλης αρχιτεκτονικής με λογική πολλαπλών τιμών. [Thesis]. Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ); Democritus University of Thrace (DUTH); 2001. Available from: http://hdl.handle.net/10442/hedi/13049

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.