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You searched for subject:(Computer memory). Showing records 1 – 30 of 780 total matches.

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Cornell University

1. Yu, Wing-kei. Hybrid Memories For Energy Efficient Computing Systems .

Degree: 2016, Cornell University

 To sustain processor performance, demand for memory capacity and bandwidth continues to grow. Computer architects use different memories, structured in a hierarchy, to build memory(more)

Subjects/Keywords: computer architecture; non-volatile memory; hybrid memory

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APA (6th Edition):

Yu, W. (2016). Hybrid Memories For Energy Efficient Computing Systems . (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/43729

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yu, Wing-kei. “Hybrid Memories For Energy Efficient Computing Systems .” 2016. Thesis, Cornell University. Accessed January 24, 2020. http://hdl.handle.net/1813/43729.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yu, Wing-kei. “Hybrid Memories For Energy Efficient Computing Systems .” 2016. Web. 24 Jan 2020.

Vancouver:

Yu W. Hybrid Memories For Energy Efficient Computing Systems . [Internet] [Thesis]. Cornell University; 2016. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1813/43729.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yu W. Hybrid Memories For Energy Efficient Computing Systems . [Thesis]. Cornell University; 2016. Available from: http://hdl.handle.net/1813/43729

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

2. Poremba, Matthew Raymond. Architecting Byte-addressable Non-volatile Memories for Main Memory.

Degree: PhD, Computer Science and Engineering, 2015, Penn State University

 New breakthroughs in memory technology in recent years has lead to increased research efforts in so-called byte-addressable non-volatile memories (NVM). As a result, questions of… (more)

Subjects/Keywords: Computer Memory; Non-Volatile Memory; DRAM; Memory Scheduling; Memory Modeling; Memory Simulation

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APA (6th Edition):

Poremba, M. R. (2015). Architecting Byte-addressable Non-volatile Memories for Main Memory. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/25034

Chicago Manual of Style (16th Edition):

Poremba, Matthew Raymond. “Architecting Byte-addressable Non-volatile Memories for Main Memory.” 2015. Doctoral Dissertation, Penn State University. Accessed January 24, 2020. https://etda.libraries.psu.edu/catalog/25034.

MLA Handbook (7th Edition):

Poremba, Matthew Raymond. “Architecting Byte-addressable Non-volatile Memories for Main Memory.” 2015. Web. 24 Jan 2020.

Vancouver:

Poremba MR. Architecting Byte-addressable Non-volatile Memories for Main Memory. [Internet] [Doctoral dissertation]. Penn State University; 2015. [cited 2020 Jan 24]. Available from: https://etda.libraries.psu.edu/catalog/25034.

Council of Science Editors:

Poremba MR. Architecting Byte-addressable Non-volatile Memories for Main Memory. [Doctoral Dissertation]. Penn State University; 2015. Available from: https://etda.libraries.psu.edu/catalog/25034


University of Utah

3. Shevgoor, Manjunath. Enabling big memory with emerging technologies.

Degree: PhD, School of Computing, 2016, University of Utah

 The demand for main memory capacity has been increasing for many years and will continue to do so. In the past, Dynamic Random Access Memory(more)

Subjects/Keywords: computer architecture; DRAM; memory

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APA (6th Edition):

Shevgoor, M. (2016). Enabling big memory with emerging technologies. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/4108/rec/865

Chicago Manual of Style (16th Edition):

Shevgoor, Manjunath. “Enabling big memory with emerging technologies.” 2016. Doctoral Dissertation, University of Utah. Accessed January 24, 2020. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/4108/rec/865.

MLA Handbook (7th Edition):

Shevgoor, Manjunath. “Enabling big memory with emerging technologies.” 2016. Web. 24 Jan 2020.

Vancouver:

Shevgoor M. Enabling big memory with emerging technologies. [Internet] [Doctoral dissertation]. University of Utah; 2016. [cited 2020 Jan 24]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/4108/rec/865.

Council of Science Editors:

Shevgoor M. Enabling big memory with emerging technologies. [Doctoral Dissertation]. University of Utah; 2016. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/4108/rec/865


Drexel University

4. Reza, Md. Alimoor. Automated categorization of drosophila learning and memory behaviors using video analysis.

Degree: 2011, Drexel University

The ability to study learning and memory behavior in living organisms has signi cantly increased our understanding of what genes a ect this behavior, allowing… (more)

Subjects/Keywords: Computer science; Drosophila melanogaster; Memory

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APA (6th Edition):

Reza, M. A. (2011). Automated categorization of drosophila learning and memory behaviors using video analysis. (Thesis). Drexel University. Retrieved from http://hdl.handle.net/1860/3908

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Reza, Md Alimoor. “Automated categorization of drosophila learning and memory behaviors using video analysis.” 2011. Thesis, Drexel University. Accessed January 24, 2020. http://hdl.handle.net/1860/3908.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Reza, Md Alimoor. “Automated categorization of drosophila learning and memory behaviors using video analysis.” 2011. Web. 24 Jan 2020.

Vancouver:

Reza MA. Automated categorization of drosophila learning and memory behaviors using video analysis. [Internet] [Thesis]. Drexel University; 2011. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1860/3908.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Reza MA. Automated categorization of drosophila learning and memory behaviors using video analysis. [Thesis]. Drexel University; 2011. Available from: http://hdl.handle.net/1860/3908

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Northeastern University

5. Lahiry, Akshay. Exploring Compression In The Gpu Memory Hierarchy For Graphics And Compute.

Degree: PhD, Department of Electrical and Computer Engineering, 2018, Northeastern University

 Asgamedeveloperspushthelimitsofgraphicsprocessors(GPUs)intheirquesttoachieve photorealism, modern games are becoming increasingly memory bound. At the same time display vendors are pushing the boundaries of display technology with ultra high… (more)

Subjects/Keywords: Compression; GPU; Memory; Computer engineering

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APA (6th Edition):

Lahiry, A. (2018). Exploring Compression In The Gpu Memory Hierarchy For Graphics And Compute. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/D20316358

Chicago Manual of Style (16th Edition):

Lahiry, Akshay. “Exploring Compression In The Gpu Memory Hierarchy For Graphics And Compute.” 2018. Doctoral Dissertation, Northeastern University. Accessed January 24, 2020. http://hdl.handle.net/2047/D20316358.

MLA Handbook (7th Edition):

Lahiry, Akshay. “Exploring Compression In The Gpu Memory Hierarchy For Graphics And Compute.” 2018. Web. 24 Jan 2020.

Vancouver:

Lahiry A. Exploring Compression In The Gpu Memory Hierarchy For Graphics And Compute. [Internet] [Doctoral dissertation]. Northeastern University; 2018. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/2047/D20316358.

Council of Science Editors:

Lahiry A. Exploring Compression In The Gpu Memory Hierarchy For Graphics And Compute. [Doctoral Dissertation]. Northeastern University; 2018. Available from: http://hdl.handle.net/2047/D20316358


University of Arizona

6. Simons, Brad. Set-Associative History-Aided Adaptive Replacement for On-Chip Caches .

Degree: 2016, University of Arizona

 Last Level Caches (LLCs) are critical to reducing processor stalls to off-chip memory and improving processing throughput, and replacement policy plays an important role in… (more)

Subjects/Keywords: Memory; Electrical & Computer Engineering; Cache

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APA (6th Edition):

Simons, B. (2016). Set-Associative History-Aided Adaptive Replacement for On-Chip Caches . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/621128

Chicago Manual of Style (16th Edition):

Simons, Brad. “Set-Associative History-Aided Adaptive Replacement for On-Chip Caches .” 2016. Masters Thesis, University of Arizona. Accessed January 24, 2020. http://hdl.handle.net/10150/621128.

MLA Handbook (7th Edition):

Simons, Brad. “Set-Associative History-Aided Adaptive Replacement for On-Chip Caches .” 2016. Web. 24 Jan 2020.

Vancouver:

Simons B. Set-Associative History-Aided Adaptive Replacement for On-Chip Caches . [Internet] [Masters thesis]. University of Arizona; 2016. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/10150/621128.

Council of Science Editors:

Simons B. Set-Associative History-Aided Adaptive Replacement for On-Chip Caches . [Masters Thesis]. University of Arizona; 2016. Available from: http://hdl.handle.net/10150/621128


University of Texas – Austin

7. -6845-8988. Scalable virtual memory via tailored and larger page sizes.

Degree: PhD, Electrical and Computer Engineering, 2019, University of Texas – Austin

 Main memory capacity continues to soar, resulting in TLB misses becoming an increasingly significant performance bottleneck. The 4KB default minimum page size in architectures like… (more)

Subjects/Keywords: Virtual memory; Microarchitecture; Computer architecture

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APA (6th Edition):

-6845-8988. (2019). Scalable virtual memory via tailored and larger page sizes. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/3003

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-6845-8988. “Scalable virtual memory via tailored and larger page sizes.” 2019. Doctoral Dissertation, University of Texas – Austin. Accessed January 24, 2020. http://dx.doi.org/10.26153/tsw/3003.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-6845-8988. “Scalable virtual memory via tailored and larger page sizes.” 2019. Web. 24 Jan 2020.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-6845-8988. Scalable virtual memory via tailored and larger page sizes. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2019. [cited 2020 Jan 24]. Available from: http://dx.doi.org/10.26153/tsw/3003.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-6845-8988. Scalable virtual memory via tailored and larger page sizes. [Doctoral Dissertation]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/3003

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


University of Michigan

8. Singh, Abhayendra Narayan. A Safety-First Approach to Memory Models.

Degree: PhD, Computer Science and Engineering, 2016, University of Michigan

 Sequential consistency (SC) is arguably the most intuitive behavior for a shared-memory multithreaded program. It is widely accepted that language-level SC could significantly improve programmability… (more)

Subjects/Keywords: Memory Consistency Model; Memory Model; DRFx memory model; Computer Science; Engineering

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APA (6th Edition):

Singh, A. N. (2016). A Safety-First Approach to Memory Models. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/120794

Chicago Manual of Style (16th Edition):

Singh, Abhayendra Narayan. “A Safety-First Approach to Memory Models.” 2016. Doctoral Dissertation, University of Michigan. Accessed January 24, 2020. http://hdl.handle.net/2027.42/120794.

MLA Handbook (7th Edition):

Singh, Abhayendra Narayan. “A Safety-First Approach to Memory Models.” 2016. Web. 24 Jan 2020.

Vancouver:

Singh AN. A Safety-First Approach to Memory Models. [Internet] [Doctoral dissertation]. University of Michigan; 2016. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/2027.42/120794.

Council of Science Editors:

Singh AN. A Safety-First Approach to Memory Models. [Doctoral Dissertation]. University of Michigan; 2016. Available from: http://hdl.handle.net/2027.42/120794

9. Elghamrawy, Karim Yehia. Memory Page Stability and its Application to Memory Deduplication.

Degree: 2016, University of California – eScholarship, University of California

 In virtualized environments, typically cloud computing environments, multiple virtual machines run on the same physical host. These virtual machines usually run the same operating systems… (more)

Subjects/Keywords: Computer science; Computer engineering; live migration; memory deduplication; memory prediction; memory stability; virtualization

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APA (6th Edition):

Elghamrawy, K. Y. (2016). Memory Page Stability and its Application to Memory Deduplication. (Thesis). University of California – eScholarship, University of California. Retrieved from http://www.escholarship.org/uc/item/366585kt

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Elghamrawy, Karim Yehia. “Memory Page Stability and its Application to Memory Deduplication.” 2016. Thesis, University of California – eScholarship, University of California. Accessed January 24, 2020. http://www.escholarship.org/uc/item/366585kt.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Elghamrawy, Karim Yehia. “Memory Page Stability and its Application to Memory Deduplication.” 2016. Web. 24 Jan 2020.

Vancouver:

Elghamrawy KY. Memory Page Stability and its Application to Memory Deduplication. [Internet] [Thesis]. University of California – eScholarship, University of California; 2016. [cited 2020 Jan 24]. Available from: http://www.escholarship.org/uc/item/366585kt.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Elghamrawy KY. Memory Page Stability and its Application to Memory Deduplication. [Thesis]. University of California – eScholarship, University of California; 2016. Available from: http://www.escholarship.org/uc/item/366585kt

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Kansas

10. Sengupta, Saikat. Understanding Memory Access Behavior for Heterogeneous Memory Systems.

Degree: MS, Electrical Engineering & Computer Science, 2018, University of Kansas

 Present day manufacturers have invented different memory technologies with distinct bandwidth, energy and cost trade-offs. Systems with such heterogeneous memory technologies can only achieve the… (more)

Subjects/Keywords: Computer engineering; Computer science; Access behavior; Heterogeneous Memory; Intel pinplay; Memory; Memory Pages; Similarity Metric

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APA (6th Edition):

Sengupta, S. (2018). Understanding Memory Access Behavior for Heterogeneous Memory Systems. (Masters Thesis). University of Kansas. Retrieved from http://hdl.handle.net/1808/27768

Chicago Manual of Style (16th Edition):

Sengupta, Saikat. “Understanding Memory Access Behavior for Heterogeneous Memory Systems.” 2018. Masters Thesis, University of Kansas. Accessed January 24, 2020. http://hdl.handle.net/1808/27768.

MLA Handbook (7th Edition):

Sengupta, Saikat. “Understanding Memory Access Behavior for Heterogeneous Memory Systems.” 2018. Web. 24 Jan 2020.

Vancouver:

Sengupta S. Understanding Memory Access Behavior for Heterogeneous Memory Systems. [Internet] [Masters thesis]. University of Kansas; 2018. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1808/27768.

Council of Science Editors:

Sengupta S. Understanding Memory Access Behavior for Heterogeneous Memory Systems. [Masters Thesis]. University of Kansas; 2018. Available from: http://hdl.handle.net/1808/27768


Hong Kong University of Science and Technology

11. Wei, Zhewei. Classic and new data structure problems in external memory.

Degree: 2012, Hong Kong University of Science and Technology

 The demand of efficient data structures for query processing on massive data sets has grown tremendously in the past decades. Traditionally, data structures are designed… (more)

Subjects/Keywords: Random access memory ; Data structures (Computer science) ; Memory management (Computer science)

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APA (6th Edition):

Wei, Z. (2012). Classic and new data structure problems in external memory. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-7529 ; https://doi.org/10.14711/thesis-b1176705 ; http://repository.ust.hk/ir/bitstream/1783.1-7529/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wei, Zhewei. “Classic and new data structure problems in external memory.” 2012. Thesis, Hong Kong University of Science and Technology. Accessed January 24, 2020. http://repository.ust.hk/ir/Record/1783.1-7529 ; https://doi.org/10.14711/thesis-b1176705 ; http://repository.ust.hk/ir/bitstream/1783.1-7529/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wei, Zhewei. “Classic and new data structure problems in external memory.” 2012. Web. 24 Jan 2020.

Vancouver:

Wei Z. Classic and new data structure problems in external memory. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2012. [cited 2020 Jan 24]. Available from: http://repository.ust.hk/ir/Record/1783.1-7529 ; https://doi.org/10.14711/thesis-b1176705 ; http://repository.ust.hk/ir/bitstream/1783.1-7529/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wei Z. Classic and new data structure problems in external memory. [Thesis]. Hong Kong University of Science and Technology; 2012. Available from: http://repository.ust.hk/ir/Record/1783.1-7529 ; https://doi.org/10.14711/thesis-b1176705 ; http://repository.ust.hk/ir/bitstream/1783.1-7529/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

12. Leung, Kiu Kwan. Cache filtering algorithm for least frequently used data with accurate memory simulation.

Degree: 2010, Ryerson University

 We propose a cache filtering algorithm to improve processor performance using a small buffer inside the processor and an algorithm to filter least frequently used… (more)

Subjects/Keywords: Computer storage devices  – Mathematical models.; Cache memory; Memory management (Computer science); Computer algorithms

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APA (6th Edition):

Leung, K. K. (2010). Cache filtering algorithm for least frequently used data with accurate memory simulation. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A6712

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Leung, Kiu Kwan. “Cache filtering algorithm for least frequently used data with accurate memory simulation.” 2010. Thesis, Ryerson University. Accessed January 24, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A6712.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Leung, Kiu Kwan. “Cache filtering algorithm for least frequently used data with accurate memory simulation.” 2010. Web. 24 Jan 2020.

Vancouver:

Leung KK. Cache filtering algorithm for least frequently used data with accurate memory simulation. [Internet] [Thesis]. Ryerson University; 2010. [cited 2020 Jan 24]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6712.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Leung KK. Cache filtering algorithm for least frequently used data with accurate memory simulation. [Thesis]. Ryerson University; 2010. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6712

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Florida Atlantic University

13. Rani, Manira S. An efficient and scalable core allocation strategy for multicore systems.

Degree: M.S.C.S., 2011, Florida Atlantic University

Summary: Multiple threads can run concurrently on multiple cores in a multicore system and improve performance/power ratio. However, effective core allocation in multicore and manycore… (more)

Subjects/Keywords: Modularity (Engineering); Multicasting (Computer networks); Convergence (Telecommunication); Computer architecture; Memory management (Computer science); Cache memory

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rani, M. S. (2011). An efficient and scalable core allocation strategy for multicore systems. (Masters Thesis). Florida Atlantic University. Retrieved from http://purl.flvc.org/FAU/3172698

Chicago Manual of Style (16th Edition):

Rani, Manira S. “An efficient and scalable core allocation strategy for multicore systems.” 2011. Masters Thesis, Florida Atlantic University. Accessed January 24, 2020. http://purl.flvc.org/FAU/3172698.

MLA Handbook (7th Edition):

Rani, Manira S. “An efficient and scalable core allocation strategy for multicore systems.” 2011. Web. 24 Jan 2020.

Vancouver:

Rani MS. An efficient and scalable core allocation strategy for multicore systems. [Internet] [Masters thesis]. Florida Atlantic University; 2011. [cited 2020 Jan 24]. Available from: http://purl.flvc.org/FAU/3172698.

Council of Science Editors:

Rani MS. An efficient and scalable core allocation strategy for multicore systems. [Masters Thesis]. Florida Atlantic University; 2011. Available from: http://purl.flvc.org/FAU/3172698

14. Chi, Ping. Facilitating Emerging Non-volatile Memories in Next-Generation Memory System Design: Architecture-Level and Application-Level Perspectives.

Degree: 2016, University of California – eScholarship, University of California

 This dissertation focuses on three types of emerging NVMs, spin-transfer torque RAM (STT-RAM), phase change memory (PCM), and metal-oxide resistive RAM (ReRAM). STT-RAM has been… (more)

Subjects/Keywords: Computer engineering; memory system design; non-volatile memory; phase change memory; ReRAM; STT-RAM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chi, P. (2016). Facilitating Emerging Non-volatile Memories in Next-Generation Memory System Design: Architecture-Level and Application-Level Perspectives. (Thesis). University of California – eScholarship, University of California. Retrieved from http://www.escholarship.org/uc/item/2g6962cg

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chi, Ping. “Facilitating Emerging Non-volatile Memories in Next-Generation Memory System Design: Architecture-Level and Application-Level Perspectives.” 2016. Thesis, University of California – eScholarship, University of California. Accessed January 24, 2020. http://www.escholarship.org/uc/item/2g6962cg.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chi, Ping. “Facilitating Emerging Non-volatile Memories in Next-Generation Memory System Design: Architecture-Level and Application-Level Perspectives.” 2016. Web. 24 Jan 2020.

Vancouver:

Chi P. Facilitating Emerging Non-volatile Memories in Next-Generation Memory System Design: Architecture-Level and Application-Level Perspectives. [Internet] [Thesis]. University of California – eScholarship, University of California; 2016. [cited 2020 Jan 24]. Available from: http://www.escholarship.org/uc/item/2g6962cg.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chi P. Facilitating Emerging Non-volatile Memories in Next-Generation Memory System Design: Architecture-Level and Application-Level Perspectives. [Thesis]. University of California – eScholarship, University of California; 2016. Available from: http://www.escholarship.org/uc/item/2g6962cg

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

15. Xu, Cong. Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory.

Degree: PhD, Computer Science and Engineering, 2014, Penn State University

 Conventional memories technologies such as SRAM, DRAM, and NAND flash are facing formidable device scaling challenges. Various new non-volatile memory (NVM) technologies have emerged recently,… (more)

Subjects/Keywords: Non-Volatile Memory; ReRAM; Computer Architecture; Memory System

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xu, C. (2014). Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/23577

Chicago Manual of Style (16th Edition):

Xu, Cong. “Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory.” 2014. Doctoral Dissertation, Penn State University. Accessed January 24, 2020. https://etda.libraries.psu.edu/catalog/23577.

MLA Handbook (7th Edition):

Xu, Cong. “Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory.” 2014. Web. 24 Jan 2020.

Vancouver:

Xu C. Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory. [Internet] [Doctoral dissertation]. Penn State University; 2014. [cited 2020 Jan 24]. Available from: https://etda.libraries.psu.edu/catalog/23577.

Council of Science Editors:

Xu C. Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory. [Doctoral Dissertation]. Penn State University; 2014. Available from: https://etda.libraries.psu.edu/catalog/23577


University of Colorado

16. Caldwell, Blake. Fluidmem: Open Source Full Memory Disaggregation.

Degree: PhD, 2019, University of Colorado

 To satisfy the performance demands of memory-intensive applications facing DRAM shortages, the focus of previous work has been on incorporating remote memory to expand capacity.… (more)

Subjects/Keywords: cloud computing; data center; memory disaggregation; remote memory; virtualization; Computer Sciences

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APA (6th Edition):

Caldwell, B. (2019). Fluidmem: Open Source Full Memory Disaggregation. (Doctoral Dissertation). University of Colorado. Retrieved from https://scholar.colorado.edu/csci_gradetds/205

Chicago Manual of Style (16th Edition):

Caldwell, Blake. “Fluidmem: Open Source Full Memory Disaggregation.” 2019. Doctoral Dissertation, University of Colorado. Accessed January 24, 2020. https://scholar.colorado.edu/csci_gradetds/205.

MLA Handbook (7th Edition):

Caldwell, Blake. “Fluidmem: Open Source Full Memory Disaggregation.” 2019. Web. 24 Jan 2020.

Vancouver:

Caldwell B. Fluidmem: Open Source Full Memory Disaggregation. [Internet] [Doctoral dissertation]. University of Colorado; 2019. [cited 2020 Jan 24]. Available from: https://scholar.colorado.edu/csci_gradetds/205.

Council of Science Editors:

Caldwell B. Fluidmem: Open Source Full Memory Disaggregation. [Doctoral Dissertation]. University of Colorado; 2019. Available from: https://scholar.colorado.edu/csci_gradetds/205


Iowa State University

17. Cao, Yanan. Introducing memory versatility to enhance memory system performance, energy efficiency and reliability.

Degree: 2016, Iowa State University

 Main memory system is facing increasingly high pressure from the advances of computation power scaling. Nowadays memory systems are expected to have much higher capacity… (more)

Subjects/Keywords: Computer Engineering; Computer Memory; DRAM; Energy; Evaluation; Performance; Reliability; Computer Engineering

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APA (6th Edition):

Cao, Y. (2016). Introducing memory versatility to enhance memory system performance, energy efficiency and reliability. (Thesis). Iowa State University. Retrieved from https://lib.dr.iastate.edu/etd/15132

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cao, Yanan. “Introducing memory versatility to enhance memory system performance, energy efficiency and reliability.” 2016. Thesis, Iowa State University. Accessed January 24, 2020. https://lib.dr.iastate.edu/etd/15132.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cao, Yanan. “Introducing memory versatility to enhance memory system performance, energy efficiency and reliability.” 2016. Web. 24 Jan 2020.

Vancouver:

Cao Y. Introducing memory versatility to enhance memory system performance, energy efficiency and reliability. [Internet] [Thesis]. Iowa State University; 2016. [cited 2020 Jan 24]. Available from: https://lib.dr.iastate.edu/etd/15132.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cao Y. Introducing memory versatility to enhance memory system performance, energy efficiency and reliability. [Thesis]. Iowa State University; 2016. Available from: https://lib.dr.iastate.edu/etd/15132

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Edinburgh

18. Zhang, Jining. Multitasking and prospective memory: Resistance to the effect of interruptions in a computer-based student study setting.

Degree: 2013, University of Edinburgh

 The present experiment examined the effect of frequent, complex and dissimilar interruptions on multitasking and prospective memory (PM) performance in a computer-based student study setting.… (more)

Subjects/Keywords: Prospective Memory; Interruptions; Multitasking; Computer; Study

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APA (6th Edition):

Zhang, J. (2013). Multitasking and prospective memory: Resistance to the effect of interruptions in a computer-based student study setting. (Thesis). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/8667

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhang, Jining. “Multitasking and prospective memory: Resistance to the effect of interruptions in a computer-based student study setting.” 2013. Thesis, University of Edinburgh. Accessed January 24, 2020. http://hdl.handle.net/1842/8667.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhang, Jining. “Multitasking and prospective memory: Resistance to the effect of interruptions in a computer-based student study setting.” 2013. Web. 24 Jan 2020.

Vancouver:

Zhang J. Multitasking and prospective memory: Resistance to the effect of interruptions in a computer-based student study setting. [Internet] [Thesis]. University of Edinburgh; 2013. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1842/8667.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang J. Multitasking and prospective memory: Resistance to the effect of interruptions in a computer-based student study setting. [Thesis]. University of Edinburgh; 2013. Available from: http://hdl.handle.net/1842/8667

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Alberta

19. Wall, David G. A Hole in the World, for Electric Guitar and MAX.

Degree: Doctor of Music, Department of Music, 2015, University of Alberta

 A Hole in the World is an open composition for prepared electric guitar, archival recording, and audio programming. Text-fragments culled from my father’s recorded autobiography… (more)

Subjects/Keywords: improvisation; cyborg; computer; guitar; posthumanism; programming; memory

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wall, D. G. (2015). A Hole in the World, for Electric Guitar and MAX. (Doctoral Dissertation). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/p2676z007

Chicago Manual of Style (16th Edition):

Wall, David G. “A Hole in the World, for Electric Guitar and MAX.” 2015. Doctoral Dissertation, University of Alberta. Accessed January 24, 2020. https://era.library.ualberta.ca/files/p2676z007.

MLA Handbook (7th Edition):

Wall, David G. “A Hole in the World, for Electric Guitar and MAX.” 2015. Web. 24 Jan 2020.

Vancouver:

Wall DG. A Hole in the World, for Electric Guitar and MAX. [Internet] [Doctoral dissertation]. University of Alberta; 2015. [cited 2020 Jan 24]. Available from: https://era.library.ualberta.ca/files/p2676z007.

Council of Science Editors:

Wall DG. A Hole in the World, for Electric Guitar and MAX. [Doctoral Dissertation]. University of Alberta; 2015. Available from: https://era.library.ualberta.ca/files/p2676z007


University of Minnesota

20. Chen, Tong. Memory profiling and management.

Degree: PhD, Computer Science, 2011, University of Minnesota

 The performance gap between the CPU and memory has been widened after decades of advance in technologies. Memory operations have become more and more expensive… (more)

Subjects/Keywords: Alias; Dependence; Memory; Profiling; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, T. (2011). Memory profiling and management. (Doctoral Dissertation). University of Minnesota. Retrieved from http://purl.umn.edu/107756

Chicago Manual of Style (16th Edition):

Chen, Tong. “Memory profiling and management.” 2011. Doctoral Dissertation, University of Minnesota. Accessed January 24, 2020. http://purl.umn.edu/107756.

MLA Handbook (7th Edition):

Chen, Tong. “Memory profiling and management.” 2011. Web. 24 Jan 2020.

Vancouver:

Chen T. Memory profiling and management. [Internet] [Doctoral dissertation]. University of Minnesota; 2011. [cited 2020 Jan 24]. Available from: http://purl.umn.edu/107756.

Council of Science Editors:

Chen T. Memory profiling and management. [Doctoral Dissertation]. University of Minnesota; 2011. Available from: http://purl.umn.edu/107756


University of Rochester

21. Nazm Bojnordi, Mahdi. Memory system optimizations for energy and bandwidth efficient data movement.

Degree: PhD, 2016, University of Rochester

 Since the early 2000s, power dissipation and memory bandwidth have been two of the most critical challenges that limit the performance of computer systems, from… (more)

Subjects/Keywords: Computer architecture; Data movement; Memory system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nazm Bojnordi, M. (2016). Memory system optimizations for energy and bandwidth efficient data movement. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/31311

Chicago Manual of Style (16th Edition):

Nazm Bojnordi, Mahdi. “Memory system optimizations for energy and bandwidth efficient data movement.” 2016. Doctoral Dissertation, University of Rochester. Accessed January 24, 2020. http://hdl.handle.net/1802/31311.

MLA Handbook (7th Edition):

Nazm Bojnordi, Mahdi. “Memory system optimizations for energy and bandwidth efficient data movement.” 2016. Web. 24 Jan 2020.

Vancouver:

Nazm Bojnordi M. Memory system optimizations for energy and bandwidth efficient data movement. [Internet] [Doctoral dissertation]. University of Rochester; 2016. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1802/31311.

Council of Science Editors:

Nazm Bojnordi M. Memory system optimizations for energy and bandwidth efficient data movement. [Doctoral Dissertation]. University of Rochester; 2016. Available from: http://hdl.handle.net/1802/31311


University of Manchester

22. Herath, Herath Mudiyanselage Isuru Prasenajith. Data centric and adaptive source changing transactional memory with exit functionality.

Degree: PhD, 2012, University of Manchester

 Multi-core computing is becoming ubiquitous due to the scaling limitations of single-core computing. It is inevitable that parallel programming will become the mainstream for such… (more)

Subjects/Keywords: 004; Parallel Computer Architecture; Hardware Transactional Memory

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Herath, H. M. I. P. (2012). Data centric and adaptive source changing transactional memory with exit functionality. (Doctoral Dissertation). University of Manchester. Retrieved from https://www.research.manchester.ac.uk/portal/en/theses/data-centric-and-adaptive-source-changing-transactional-memory-with-exit-functionality(b304862a-3c88-4d79-9b5f-0f7b99b7cebc).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.564352

Chicago Manual of Style (16th Edition):

Herath, Herath Mudiyanselage Isuru Prasenajith. “Data centric and adaptive source changing transactional memory with exit functionality.” 2012. Doctoral Dissertation, University of Manchester. Accessed January 24, 2020. https://www.research.manchester.ac.uk/portal/en/theses/data-centric-and-adaptive-source-changing-transactional-memory-with-exit-functionality(b304862a-3c88-4d79-9b5f-0f7b99b7cebc).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.564352.

MLA Handbook (7th Edition):

Herath, Herath Mudiyanselage Isuru Prasenajith. “Data centric and adaptive source changing transactional memory with exit functionality.” 2012. Web. 24 Jan 2020.

Vancouver:

Herath HMIP. Data centric and adaptive source changing transactional memory with exit functionality. [Internet] [Doctoral dissertation]. University of Manchester; 2012. [cited 2020 Jan 24]. Available from: https://www.research.manchester.ac.uk/portal/en/theses/data-centric-and-adaptive-source-changing-transactional-memory-with-exit-functionality(b304862a-3c88-4d79-9b5f-0f7b99b7cebc).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.564352.

Council of Science Editors:

Herath HMIP. Data centric and adaptive source changing transactional memory with exit functionality. [Doctoral Dissertation]. University of Manchester; 2012. Available from: https://www.research.manchester.ac.uk/portal/en/theses/data-centric-and-adaptive-source-changing-transactional-memory-with-exit-functionality(b304862a-3c88-4d79-9b5f-0f7b99b7cebc).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.564352


Duke University

23. Razeen, Ali. Parallel Memory Permissions and Their Applications .

Degree: 2018, Duke University

  A process can voluntarily set memory protections to different portions of its address space. As threads in a process share the same address space,… (more)

Subjects/Keywords: Computer science; Address space; Memory permissions; OS

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APA (6th Edition):

Razeen, A. (2018). Parallel Memory Permissions and Their Applications . (Thesis). Duke University. Retrieved from http://hdl.handle.net/10161/16850

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Razeen, Ali. “Parallel Memory Permissions and Their Applications .” 2018. Thesis, Duke University. Accessed January 24, 2020. http://hdl.handle.net/10161/16850.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Razeen, Ali. “Parallel Memory Permissions and Their Applications .” 2018. Web. 24 Jan 2020.

Vancouver:

Razeen A. Parallel Memory Permissions and Their Applications . [Internet] [Thesis]. Duke University; 2018. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/10161/16850.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Razeen A. Parallel Memory Permissions and Their Applications . [Thesis]. Duke University; 2018. Available from: http://hdl.handle.net/10161/16850

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arizona

24. Bi, Mingsong. OPTIMIZING PROCESSOR AND MEMORY FOR GREEN COMPUTING .

Degree: 2011, University of Arizona

 Energy efficiency has become one of the most important factors in the development of computer systems. Increasingly power-hungry processors and memory subsystem have reinforced the… (more)

Subjects/Keywords: OS; Processor; Computer Science; Energy; Memory

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bi, M. (2011). OPTIMIZING PROCESSOR AND MEMORY FOR GREEN COMPUTING . (Doctoral Dissertation). University of Arizona. Retrieved from http://hdl.handle.net/10150/205424

Chicago Manual of Style (16th Edition):

Bi, Mingsong. “OPTIMIZING PROCESSOR AND MEMORY FOR GREEN COMPUTING .” 2011. Doctoral Dissertation, University of Arizona. Accessed January 24, 2020. http://hdl.handle.net/10150/205424.

MLA Handbook (7th Edition):

Bi, Mingsong. “OPTIMIZING PROCESSOR AND MEMORY FOR GREEN COMPUTING .” 2011. Web. 24 Jan 2020.

Vancouver:

Bi M. OPTIMIZING PROCESSOR AND MEMORY FOR GREEN COMPUTING . [Internet] [Doctoral dissertation]. University of Arizona; 2011. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/10150/205424.

Council of Science Editors:

Bi M. OPTIMIZING PROCESSOR AND MEMORY FOR GREEN COMPUTING . [Doctoral Dissertation]. University of Arizona; 2011. Available from: http://hdl.handle.net/10150/205424


Cornell University

25. Ghose, Saugata. Criticality-Aware Memory Systems .

Degree: 2014, Cornell University

 Research on computer memory systems has been of increasing importance over the last decade, as they have become a significant bottleneck for application performance. While… (more)

Subjects/Keywords: load criticality; memory systems; computer architecture

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APA (6th Edition):

Ghose, S. (2014). Criticality-Aware Memory Systems . (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/38922

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ghose, Saugata. “Criticality-Aware Memory Systems .” 2014. Thesis, Cornell University. Accessed January 24, 2020. http://hdl.handle.net/1813/38922.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ghose, Saugata. “Criticality-Aware Memory Systems .” 2014. Web. 24 Jan 2020.

Vancouver:

Ghose S. Criticality-Aware Memory Systems . [Internet] [Thesis]. Cornell University; 2014. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/1813/38922.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ghose S. Criticality-Aware Memory Systems . [Thesis]. Cornell University; 2014. Available from: http://hdl.handle.net/1813/38922

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


California State University – Sacramento

26. Bandri Anand, Kiran. Design and implementation of a sensor hub interface using an ARM cortex m0 processor.

Degree: MS, Electrical and Electronic Engineering, 2019, California State University – Sacramento

 Smart Devices and the need for intelligent systems has brought about a revolution in Technology. With devices getting smaller, yet more effective, there is a… (more)

Subjects/Keywords: Sensor applications; Computer architecture; Cache memory system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bandri Anand, K. (2019). Design and implementation of a sensor hub interface using an ARM cortex m0 processor. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/207768

Chicago Manual of Style (16th Edition):

Bandri Anand, Kiran. “Design and implementation of a sensor hub interface using an ARM cortex m0 processor.” 2019. Masters Thesis, California State University – Sacramento. Accessed January 24, 2020. http://hdl.handle.net/10211.3/207768.

MLA Handbook (7th Edition):

Bandri Anand, Kiran. “Design and implementation of a sensor hub interface using an ARM cortex m0 processor.” 2019. Web. 24 Jan 2020.

Vancouver:

Bandri Anand K. Design and implementation of a sensor hub interface using an ARM cortex m0 processor. [Internet] [Masters thesis]. California State University – Sacramento; 2019. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/10211.3/207768.

Council of Science Editors:

Bandri Anand K. Design and implementation of a sensor hub interface using an ARM cortex m0 processor. [Masters Thesis]. California State University – Sacramento; 2019. Available from: http://hdl.handle.net/10211.3/207768


Duke University

27. Kunjir, Mayuresh. Automating Memory Management in Data Analytics .

Degree: 2019, Duke University

  Recent years have seen unprecedented growth in the volume, velocity, and variety of the data managed by data analytics platforms. At the same time,… (more)

Subjects/Keywords: Computer science; Data Analytics; Memory Management

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kunjir, M. (2019). Automating Memory Management in Data Analytics . (Thesis). Duke University. Retrieved from http://hdl.handle.net/10161/18767

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kunjir, Mayuresh. “Automating Memory Management in Data Analytics .” 2019. Thesis, Duke University. Accessed January 24, 2020. http://hdl.handle.net/10161/18767.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kunjir, Mayuresh. “Automating Memory Management in Data Analytics .” 2019. Web. 24 Jan 2020.

Vancouver:

Kunjir M. Automating Memory Management in Data Analytics . [Internet] [Thesis]. Duke University; 2019. [cited 2020 Jan 24]. Available from: http://hdl.handle.net/10161/18767.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kunjir M. Automating Memory Management in Data Analytics . [Thesis]. Duke University; 2019. Available from: http://hdl.handle.net/10161/18767

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of North Texas

28. Scrbak, Marko. Methodical Evaluation of Processing-in-Memory Alternatives.

Degree: 2019, University of North Texas

 In this work, I characterized a series of potential application kernels using a set of architectural and non-architectural metrics, and performed a comparison of four… (more)

Subjects/Keywords: Processing-in-Memory; PIM; Computer Architecture

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Scrbak, M. (2019). Methodical Evaluation of Processing-in-Memory Alternatives. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc1505199/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Scrbak, Marko. “Methodical Evaluation of Processing-in-Memory Alternatives.” 2019. Thesis, University of North Texas. Accessed January 24, 2020. https://digital.library.unt.edu/ark:/67531/metadc1505199/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Scrbak, Marko. “Methodical Evaluation of Processing-in-Memory Alternatives.” 2019. Web. 24 Jan 2020.

Vancouver:

Scrbak M. Methodical Evaluation of Processing-in-Memory Alternatives. [Internet] [Thesis]. University of North Texas; 2019. [cited 2020 Jan 24]. Available from: https://digital.library.unt.edu/ark:/67531/metadc1505199/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Scrbak M. Methodical Evaluation of Processing-in-Memory Alternatives. [Thesis]. University of North Texas; 2019. Available from: https://digital.library.unt.edu/ark:/67531/metadc1505199/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Neely, Brian. Improving Non-Volatile Memory Lifetime through Temporal Wear-Limiting.

Degree: 2014, University of California – eScholarship, University of California

 Non-volatile memory technologies provide a low-power, high-density alternative to traditional DRAM main memories, yet all suffer from some degree of limited write endurance. The non-uniformity… (more)

Subjects/Keywords: Computer science; Endurance; Non-volatile memory

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APA (6th Edition):

Neely, B. (2014). Improving Non-Volatile Memory Lifetime through Temporal Wear-Limiting. (Thesis). University of California – eScholarship, University of California. Retrieved from http://www.escholarship.org/uc/item/2mf1f983

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Neely, Brian. “Improving Non-Volatile Memory Lifetime through Temporal Wear-Limiting.” 2014. Thesis, University of California – eScholarship, University of California. Accessed January 24, 2020. http://www.escholarship.org/uc/item/2mf1f983.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Neely, Brian. “Improving Non-Volatile Memory Lifetime through Temporal Wear-Limiting.” 2014. Web. 24 Jan 2020.

Vancouver:

Neely B. Improving Non-Volatile Memory Lifetime through Temporal Wear-Limiting. [Internet] [Thesis]. University of California – eScholarship, University of California; 2014. [cited 2020 Jan 24]. Available from: http://www.escholarship.org/uc/item/2mf1f983.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Neely B. Improving Non-Volatile Memory Lifetime through Temporal Wear-Limiting. [Thesis]. University of California – eScholarship, University of California; 2014. Available from: http://www.escholarship.org/uc/item/2mf1f983

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Arizona State University

30. Cai, Jian. Scratchpad Management in Software Managed Manycore Architectures.

Degree: Computer Science, 2017, Arizona State University

 Caches have long been used to reduce memory access latency. However, the increased complexity of cache coherence brings significant challenges in processor design as the… (more)

Subjects/Keywords: Computer science; compiler; multicore; scratchpad memory; SPM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cai, J. (2017). Scratchpad Management in Software Managed Manycore Architectures. (Doctoral Dissertation). Arizona State University. Retrieved from http://repository.asu.edu/items/46214

Chicago Manual of Style (16th Edition):

Cai, Jian. “Scratchpad Management in Software Managed Manycore Architectures.” 2017. Doctoral Dissertation, Arizona State University. Accessed January 24, 2020. http://repository.asu.edu/items/46214.

MLA Handbook (7th Edition):

Cai, Jian. “Scratchpad Management in Software Managed Manycore Architectures.” 2017. Web. 24 Jan 2020.

Vancouver:

Cai J. Scratchpad Management in Software Managed Manycore Architectures. [Internet] [Doctoral dissertation]. Arizona State University; 2017. [cited 2020 Jan 24]. Available from: http://repository.asu.edu/items/46214.

Council of Science Editors:

Cai J. Scratchpad Management in Software Managed Manycore Architectures. [Doctoral Dissertation]. Arizona State University; 2017. Available from: http://repository.asu.edu/items/46214

[1] [2] [3] [4] [5] … [26]

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