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1.
La Delfa, Gaetano Carmelo.
Methodologies and Technologies for Indoor Localization: a Computer Vision Based Approach.
Degree: 2016, Università degli Studi di Catania
URL: http://hdl.handle.net/10761/3928 
► The massive diffusion of smartphones we are seeing in the last years, the growing interest for everything related to wearable devices and Internet of Things…
(more)
▼ The massive diffusion of smartphones we are seeing in the last years, the growing interest for everything related to wearable devices and Internet of Things (IoT), the exponential rise of Location Based Services (LBS: services based on the position of the users and accessible through the device) has meant that technologies capable of determining the position of the user inside a specific context have taken a crucial role in the consumer sector. In outdoor environments, GPS (Global Positioning System) can be considered today as a standard de facto , while the localization and navigation in indoor environments still remains one of the technological challenges of the next years.
Indoor Positioning Systems (IPS) have a remarkable importance in a lot of important market segments such as the retail sectors for con- textual advertising (commercial centers, supermarkets), touristic and transportation sectors (airports, museums), healthcare sectors (hospitals). Sometimes, in emergency situations they can make the difference between life and death. Even if actually doesn t exist a definitive solution as efficient and precise as GPS and with all its advantages, various approaches and methodologies has been proposed in the last years in scientific literature, and several technologies are appearing into the market. The researches have focused, rather than on realizing a general purpose IPS with high performances everywhere, on the development of a variety of solutions suitable for the specific place of deployment and which meet the specifics precision, security, invasiveness and cost requirements.
In the first part of this doctoral dissertation, after an overview on the main methodologies used for locating a user in an indoor environment, we will analyze the state of the art and present some of the most interesting cases. We will focus particularly on approaches which utilize the smartphone s inertial sensors and 2D visual markers based computer vision techniques. In the second part of the dissertation we will propose our own solution to the indoor localization problem. Such solution consists in a visual markers system deployed onto the area of interest s floor and a step detection algorithm. We will compare the performances of three types of markers, taken from the scientific literature, from the point of view of the specifications required by the suggested solution, and choose the most better performing one. We will then propose a client - server architecture for managing the whole process of tracking the user inside a building, and present an implementation of the client, on the iOS platform. Finally in the last part of the dissertation, we will show the obtained results, and talk about the possible future works.
Subjects/Keywords: Area 09 - Ingegneria industriale e dell'informazione; indoor localization,visual markers,computer vision
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APA (6th Edition):
La Delfa, G. C. (2016). Methodologies and Technologies for Indoor Localization: a Computer Vision Based Approach. (Thesis). Università degli Studi di Catania. Retrieved from http://hdl.handle.net/10761/3928
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
La Delfa, Gaetano Carmelo. “Methodologies and Technologies for Indoor Localization: a Computer Vision Based Approach.” 2016. Thesis, Università degli Studi di Catania. Accessed February 27, 2021.
http://hdl.handle.net/10761/3928.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
La Delfa, Gaetano Carmelo. “Methodologies and Technologies for Indoor Localization: a Computer Vision Based Approach.” 2016. Web. 27 Feb 2021.
Vancouver:
La Delfa GC. Methodologies and Technologies for Indoor Localization: a Computer Vision Based Approach. [Internet] [Thesis]. Università degli Studi di Catania; 2016. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/10761/3928.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
La Delfa GC. Methodologies and Technologies for Indoor Localization: a Computer Vision Based Approach. [Thesis]. Università degli Studi di Catania; 2016. Available from: http://hdl.handle.net/10761/3928
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
2.
Palazzo, Simone.
Hybrid human-machine vision systems for automated object segmentation and categorization.
Degree: 2017, Università degli Studi di Catania
URL: http://hdl.handle.net/10761/3985
► Emulating human perception is a foundational component in the research towards artificial intelligence (AI). Computer vision, in particular, is now one of the most active…
(more)
▼ Emulating human perception is a foundational component in the research towards artificial intelligence (AI). Computer vision, in particular, is now one of the most active and fastest growing research topics in AI, and its field of practical applications range from video-survaillance to robotics to ecological monitoring. However, in spite of all the recent progress, humans still greatly outperform machines in most visual tasks, and even competitive artificial models require thousands of examples to learn concepts that children learn easily. Hence, given the objective difficulty in emulating the human visual system, the question that we intended to investigate in this thesis is in which ways humans can support the advancement of computer vision techniques. More precisely, we investigated how the synergy between human vision expertise and automated methods can be shifted from a top-down paradigm where direct user action or human perception principles explicitly guide the software component to a bottom-up paradigm, where instead of trying to copy the way our mind works, we exploit the by-product (i.e. some kind of measured feedback) of its workings to extract information on how visual tasks are performed. Starting from a purely top-down approach, where a fully-automated video object segmentation algorithm is extended to encode and include principles of human perceptual organization, we moved to interactive methods, where the same task is performed involving
humans in the loop by means of gamification and eye-gaze analysis strategies, in a progressively increasing bottom-up fashion. Lastly, we pushed this trend to the limit by investigating brain-driven image classification approaches, where brain signals were used to extract compact representation of image contents. Performance evaluation of the tested approaches shows that involving people in automated vision methods can enhance their accuracy. Our experiments, carried out at different degrees of awareness and control of the generated human feedback, show that top-down approaches may achieve a better accuracy than bottom-up ones, at the cost of higher user interaction time and effort. As for our most ambitious objective, the purely bottom-up image classification system from brain pattern analysis, we were able to outperform the current state of the art with a method trained to extract brain-inspired visual content descriptors, thus removing the need of undergoing EEG recording for unseen images.
Subjects/Keywords: Area 09 - Ingegneria industriale e dell'informazione; computer vision,interactive,object segmentation,object classification,eeg
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APA (6th Edition):
Palazzo, S. (2017). Hybrid human-machine vision systems for automated object segmentation and categorization. (Thesis). Università degli Studi di Catania. Retrieved from http://hdl.handle.net/10761/3985
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Palazzo, Simone. “Hybrid human-machine vision systems for automated object segmentation and categorization.” 2017. Thesis, Università degli Studi di Catania. Accessed February 27, 2021.
http://hdl.handle.net/10761/3985.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Palazzo, Simone. “Hybrid human-machine vision systems for automated object segmentation and categorization.” 2017. Web. 27 Feb 2021.
Vancouver:
Palazzo S. Hybrid human-machine vision systems for automated object segmentation and categorization. [Internet] [Thesis]. Università degli Studi di Catania; 2017. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/10761/3985.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Palazzo S. Hybrid human-machine vision systems for automated object segmentation and categorization. [Thesis]. Università degli Studi di Catania; 2017. Available from: http://hdl.handle.net/10761/3985
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Missouri – Columbia
3.
Sajjapongse, Kittisak.
Hierarchical scheduling and uniform access programming frameworks for heterogeneous CPU-GPU computing clusters.
Degree: 2016, University of Missouri – Columbia
URL: http://pqdtopen.proquest.com/#viewpdf?dispub=10178997
► The advance of the GPU hardware architecture has made GPUs attractive devices for general-purpose computing. Modern GPUs are equipped with an increasing number of…
(more)
▼ The advance of the GPU hardware architecture has made GPUs attractive devices for general-purpose computing. Modern GPUs are equipped with an increasing number of cores, a flexible memory hierarchy, and a large memory capacity. While the computational power of modern GPU devices has allowed their introduction in high-performance computing (HPC) clusters and the efficient processing of ever larger workloads, existing software components for HPC clusters still offer basic support for hardware heterogeneity and often cause performance limitations in the presence of GPU devices. In particular, two kinds of limitations are associated with these software components: <i> runtime support</i> and <i>programmability.</i> We found that these limitations are due to the fact that existing software frameworks for heterogeneous clusters treat GPUs as dedicated coprocessor devices. In this dissertation, we propose two software frameworks for addressing the performance and hardware underutilization issues found in heterogeneous CPU-GPU clusters as well as increasing their programmability. Our frameworks provide a uniform view of compute resources and treat CPUs and GPUs equally as first-class resources, allowing efficient management of heterogeneous compute resources. First, we propose a hierarchical scheduling framework consisting of a node-level runtime and a cluster-level scheduler that provides abstraction of heterogeneous compute resources at different granularities. This hierarchical framework targets existing applications and does not require their modification. In the node-level runtime, we identify and design mechanisms, such as <i> virtual GPUs, GPU virtual memory, dynamic load balancing</i> and <i> pre-emption,</i> which are necessary to support efficient sharing and load balancing schemes for GPUs within a compute node. In the cluster-level scheduler, we introduce mechanisms to abstract compute nodes and perform load balancing in concert with the node-level runtime. Our hierarchical scheduling framework allows supporting different load balancing policies and does not require additional inputs (such as profiling information) from users. Second, we propose a programming framework based on a novel memory and execution model. Our memory model hides disjoint addressing spaces (corresponding to different CPUs, GPUs and compute nodes) and provides a view of a single virtual memory space that can be accessed by all compute resources in a heterogeneous cluster. Our execution model provides uniform access to compute resources and allows our framework to treat all CPUs and GPUs equally and to access data in the virtual memory space.
Subjects/Keywords: Computer engineering; Engineering; Computer science
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APA (6th Edition):
Sajjapongse, K. (2016). Hierarchical scheduling and uniform access programming frameworks for heterogeneous CPU-GPU computing clusters. (Thesis). University of Missouri – Columbia. Retrieved from http://pqdtopen.proquest.com/#viewpdf?dispub=10178997
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Sajjapongse, Kittisak. “Hierarchical scheduling and uniform access programming frameworks for heterogeneous CPU-GPU computing clusters.” 2016. Thesis, University of Missouri – Columbia. Accessed February 27, 2021.
http://pqdtopen.proquest.com/#viewpdf?dispub=10178997.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Sajjapongse, Kittisak. “Hierarchical scheduling and uniform access programming frameworks for heterogeneous CPU-GPU computing clusters.” 2016. Web. 27 Feb 2021.
Vancouver:
Sajjapongse K. Hierarchical scheduling and uniform access programming frameworks for heterogeneous CPU-GPU computing clusters. [Internet] [Thesis]. University of Missouri – Columbia; 2016. [cited 2021 Feb 27].
Available from: http://pqdtopen.proquest.com/#viewpdf?dispub=10178997.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Sajjapongse K. Hierarchical scheduling and uniform access programming frameworks for heterogeneous CPU-GPU computing clusters. [Thesis]. University of Missouri – Columbia; 2016. Available from: http://pqdtopen.proquest.com/#viewpdf?dispub=10178997
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Indiana State University
4.
Freet, David Nathan.
A Security Visualization Analysis Methodology for Improving Network Intrusion Detection Efficiency.
Degree: 2017, Indiana State University
URL: http://pqdtopen.proquest.com/#viewpdf?dispub=10261868
► The flood of raw data generated by intrusion detection and other network monitoring devices can be so overwhelming that it causes great difficulty in…
(more)
▼ The flood of raw data generated by intrusion detection and other network monitoring devices can be so overwhelming that it causes great difficulty in detecting patterns that might indicate malicious traffic. In order to more effectively monitor and process network and forensic data within a virtualized environment, Security Visualization (SecViz) provides software-based visual interfaces to analyze live and logged network data within the domains of network security, network and cloud forensics, attack prevention, compliance management, wireless security, secure coding, and penetration testing. Modern networks generate enormous amounts of data that is often stored in logs. Due to the lack of effective approaches to organizing and visualizing log data, most network monitoring tools focus at a high level on data throughput and efficiency, or dig too far down into the packet level to allow for useful analysis by network administrators. SecViz offers a simpler and more effective approach to analyzing the massive amounts of log data generated on a regular basis. Graphical representations make it possible to identify and detect malicious activity, and spot general trends and relationships among individual data points. The human brain can rapidly process visual information in a detailed and meaningful manner. By converting network security and forensic data into a human-readable picture, SecViz can address and solve complex data analysis challenges and significantly increase the efficiency by which data is processed by information security professionals. This study utilizes the Snort intrusion detection system and SecViz tools to monitor and analyze various attack scenarios in a virtualized cloud computing environment. Real-time attacks are conducted in order to generate traffic and log data that can then be re-played in a number of software applications for analysis. A Java-based program is written to aggregate and display Snort data, and then incorporated into a custom Linux-based software environment along with select open-source SecViz tools. A methodology is developed to correlate Snort intrusion alerts with log data in order to create a visual picture that can significantly enhance the identification of malicious network activity and discrimination from normal traffic within a virtualized cloud-based network.
Subjects/Keywords: Computer engineering; Engineering; Computer science
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APA (6th Edition):
Freet, D. N. (2017). A Security Visualization Analysis Methodology for Improving Network Intrusion Detection Efficiency. (Thesis). Indiana State University. Retrieved from http://pqdtopen.proquest.com/#viewpdf?dispub=10261868
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Freet, David Nathan. “A Security Visualization Analysis Methodology for Improving Network Intrusion Detection Efficiency.” 2017. Thesis, Indiana State University. Accessed February 27, 2021.
http://pqdtopen.proquest.com/#viewpdf?dispub=10261868.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Freet, David Nathan. “A Security Visualization Analysis Methodology for Improving Network Intrusion Detection Efficiency.” 2017. Web. 27 Feb 2021.
Vancouver:
Freet DN. A Security Visualization Analysis Methodology for Improving Network Intrusion Detection Efficiency. [Internet] [Thesis]. Indiana State University; 2017. [cited 2021 Feb 27].
Available from: http://pqdtopen.proquest.com/#viewpdf?dispub=10261868.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Freet DN. A Security Visualization Analysis Methodology for Improving Network Intrusion Detection Efficiency. [Thesis]. Indiana State University; 2017. Available from: http://pqdtopen.proquest.com/#viewpdf?dispub=10261868
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
5.
Raufdeen, Ramzi A.
SE4S toolkit extension project vision diagramming tool build your vision.
Degree: 2016, California State University, Long Beach
URL: http://pqdtopen.proquest.com/#viewpdf?dispub=10147325
► Sustainability is an important topic when developing software because it helps develop ecofriendly programs. Software can contribute towards sustainability by supporting sustainable goals, which…
(more)
▼ Sustainability is an important topic when developing software because it helps develop ecofriendly programs. Software can contribute towards sustainability by supporting sustainable goals, which can be efficiently supported if considered early on in a project by requirements engineers. This project helps requirements engineers make that sustainable contribution through the development of the SE4S toolkit extension project–a vision diagramming tool that contributes towards sustainability. This interactive tool is developed using HTML, SVG, and JointJS library. The vision diagramming tool is an open source project that can be used in any browser, which allows requirements engineers to bring their visions to life while keeping sustainability in mind. Requirements engineers, with help from this tool, would be able to easily demonstrate their sustainability vision to their stakeholders and pass it on to rest of the development team.
Subjects/Keywords: Computer engineering; Engineering; Computer science
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APA (6th Edition):
Raufdeen, R. A. (2016). SE4S toolkit extension project vision diagramming tool build your vision. (Thesis). California State University, Long Beach. Retrieved from http://pqdtopen.proquest.com/#viewpdf?dispub=10147325
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Raufdeen, Ramzi A. “SE4S toolkit extension project vision diagramming tool build your vision.” 2016. Thesis, California State University, Long Beach. Accessed February 27, 2021.
http://pqdtopen.proquest.com/#viewpdf?dispub=10147325.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Raufdeen, Ramzi A. “SE4S toolkit extension project vision diagramming tool build your vision.” 2016. Web. 27 Feb 2021.
Vancouver:
Raufdeen RA. SE4S toolkit extension project vision diagramming tool build your vision. [Internet] [Thesis]. California State University, Long Beach; 2016. [cited 2021 Feb 27].
Available from: http://pqdtopen.proquest.com/#viewpdf?dispub=10147325.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Raufdeen RA. SE4S toolkit extension project vision diagramming tool build your vision. [Thesis]. California State University, Long Beach; 2016. Available from: http://pqdtopen.proquest.com/#viewpdf?dispub=10147325
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Texas A&M University
6.
Grande, Marcus Bryan.
Multiported storage devices.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2000-THESIS-G73
► In the past decade the demand for systems that can process and deliver massive amounts of storage has increased. Traditionally, large disk farms have been…
(more)
▼ In the past decade the demand for systems that can process and deliver massive amounts of storage has increased. Traditionally, large disk farms have been deployed by connecting several disks to a single server. A problem with this configuration is that a given storage server can become a bottleneck, as all disk activity for a particular server has to be processed by that server. Increasing performance and decreasing cost of microprocessors are making it feasible to move more processing power to the data source. This allows us to investigate new methods of storage delivery that were not plausible in the past. In this thesis we present a new "enhanced" storage device called a Multiported Storage Device which is endowed with more processing power and intelligence than the traditional block storage device. A multiported storage device allows application-specific code that we call filter applets to be downloaded to the device while still maintaining the simple block-level interface. The device contains several software ports through which read and write requests pass. Each filter applet is associated with a particular software port in the device. We present a prototype implementation of a multiported storage device using the Linux operating system. We implement our device using kernel driver modules and by performing several modifications to the Linux kernel to accommodate the multiported storage device architecture. We also present experimental results showing the impact of our layered drivers on I/O performance.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA (6th Edition):
Grande, M. B. (2012). Multiported storage devices. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2000-THESIS-G73
Chicago Manual of Style (16th Edition):
Grande, Marcus Bryan. “Multiported storage devices.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2000-THESIS-G73.
MLA Handbook (7th Edition):
Grande, Marcus Bryan. “Multiported storage devices.” 2012. Web. 27 Feb 2021.
Vancouver:
Grande MB. Multiported storage devices. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2000-THESIS-G73.
Council of Science Editors:
Grande MB. Multiported storage devices. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2000-THESIS-G73
Texas A&M University
7.
Ren, Qian.
MPEG-aware disk storage system.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2000-THESIS-R457
► In the past decades the demand for systems that can process and deliver massive amount of storage has increased. Multimedia applications such as streaming audio…
(more)
▼ In the past decades the demand for systems that can process and deliver massive amount of storage has increased. Multimedia applications such as streaming audio and video require large amounts of data to be read from disk and processed for timely delivery to the client. Large decision support data bases not only need to read large amounts of data from storage media but also require scalable processing power as the data set size grows. Increasing performance and decreasing cost of microprocessors are making it feasible to move more processing power to the data source as proposed in active disks or multiported storage devices. This allows us to investigate new methods of multimedia disk storage system that were not plausible in the past. MPEG-aware disk storage system is a disk storage system with intelligence about the MPEG formatted multimedia data. MPEG-aware disk has a powerful CPU in the disk controller. In a multimedia server with an MPEG-aware disk storage system, common functions of preprocessing MPEG data from the disk is done by the disk CPU instead of the server CPU, resulting in considerable system-level performance improvements. This allows more multimedia files to be serviced by one server. The presented prototype implementation of MPEG-aware disk storage system is built on Linux operating system.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA ·
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APA (6th Edition):
Ren, Q. (2012). MPEG-aware disk storage system. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2000-THESIS-R457
Chicago Manual of Style (16th Edition):
Ren, Qian. “MPEG-aware disk storage system.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2000-THESIS-R457.
MLA Handbook (7th Edition):
Ren, Qian. “MPEG-aware disk storage system.” 2012. Web. 27 Feb 2021.
Vancouver:
Ren Q. MPEG-aware disk storage system. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2000-THESIS-R457.
Council of Science Editors:
Ren Q. MPEG-aware disk storage system. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2000-THESIS-R457
Texas A&M University
8.
Bhandarkar, Sumitha.
Delayed congestion response protocols.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-B492
► There has been a surge of new real-time multimedia applications over the IP network which cannot use TCP because the congestion control algorithm of TCP…
(more)
▼ There has been a surge of new real-time multimedia applications over the IP network which cannot use TCP because the congestion control algorithm of TCP results in drastic variations in the sending rate, which in turn affect the user perceived quality. As a result several of these applications use UDP. The fact that UDP does not respond to congestion in any way has raised several questions about possible congestion collapse of the Internet and fairness to existing TCP-based applications. Several congestion control algorithms suited for such applications have been proposed which claim bandwidth in a "TCP-friendly" manner. However all of them reduce their sending rate once and as soon as allowed by the protocol design, when a packet drop occurs. In this thesis we have proposed a novel scheme by which response to congestion is deliberately delayed by [] RTTs. We have provided the framework for this class of protocols in general and examined three cases in particular. For these three cases we have developed analytical models and derived the conditions under which they are TCP-friendly. With these conditions we have run simulations on the ns-2 platform to show that they are indeed TCP-friendly. By showing that delayed congestion response is possible, we have laid the ground work for the development of a whole new class of protocols which are not just TCP-friendly and capable of providing early warning to the application regarding an impending reduction in the sending rate but also can be designed to have a smooth congestion response.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA ·
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APA (6th Edition):
Bhandarkar, S. (2012). Delayed congestion response protocols. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-B492
Chicago Manual of Style (16th Edition):
Bhandarkar, Sumitha. “Delayed congestion response protocols.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-B492.
MLA Handbook (7th Edition):
Bhandarkar, Sumitha. “Delayed congestion response protocols.” 2012. Web. 27 Feb 2021.
Vancouver:
Bhandarkar S. Delayed congestion response protocols. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-B492.
Council of Science Editors:
Bhandarkar S. Delayed congestion response protocols. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-B492
Texas A&M University
9.
Doddapaneni, Krishnamohan.
Using Multiprotocol Label Switching in Virtual Private Networks.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-D63
► This thesis presents the design of Multiprotocol Label Switching Virtual Private Networks(MPLS VPN). MPLS VPNs are true peer models, which perform traffic separation at Layer…
(more)
▼ This thesis presents the design of Multiprotocol Label Switching Virtual Private Networks(MPLS VPN). MPLS VPNs are true peer models, which perform traffic separation at Layer 3, through the implementation of separate IP VPN forwarding tables. MPLS allows ISPs to offer VPN services by providing a simple, flexible, and powerful tunneling mechanism. An ISP can deploy a VPN by provisioning a set of LSPs to provide connectivity among the different sites in the VPN. Each VPN site then advertises to the ISP a set of prefixes that are reachable within the local site. The ISPs routing system distributes this information by piggybacking labels in routing protocol updates or by using a label distribution protocol. VPN Identifiers allow a single routing system to support multiple VPNs whose internal address spaces overlap with each other. Finally, each ingress LSR places traffic into LSPs based on a combination of a packet's destination address and VPN membership information.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA (6th Edition):
Doddapaneni, K. (2012). Using Multiprotocol Label Switching in Virtual Private Networks. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-D63
Chicago Manual of Style (16th Edition):
Doddapaneni, Krishnamohan. “Using Multiprotocol Label Switching in Virtual Private Networks.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-D63.
MLA Handbook (7th Edition):
Doddapaneni, Krishnamohan. “Using Multiprotocol Label Switching in Virtual Private Networks.” 2012. Web. 27 Feb 2021.
Vancouver:
Doddapaneni K. Using Multiprotocol Label Switching in Virtual Private Networks. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-D63.
Council of Science Editors:
Doddapaneni K. Using Multiprotocol Label Switching in Virtual Private Networks. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-D63
Texas A&M University
10.
Dugar, Anurag.
Priority and fair scheduling in wireless local area networks.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-D83
► In recent years, fair scheduling and quality of service (QoS) in Wireless Local Area Networks have received significant attention from the networking research community. This…
(more)
▼ In recent years, fair scheduling and quality of service (QoS) in Wireless Local Area Networks have received significant attention from the networking research community. This thesis presents a distributed Medium Access Control (MAC) protocol for priority and fair scheduling in a Wireless Local Area Network. The proposed protocol supports multiple priorities, as well as a mechanism (using weights) for controlling the way bandwidth is shared by flows within a given priority level.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA (6th Edition):
Dugar, A. (2012). Priority and fair scheduling in wireless local area networks. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-D83
Chicago Manual of Style (16th Edition):
Dugar, Anurag. “Priority and fair scheduling in wireless local area networks.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-D83.
MLA Handbook (7th Edition):
Dugar, Anurag. “Priority and fair scheduling in wireless local area networks.” 2012. Web. 27 Feb 2021.
Vancouver:
Dugar A. Priority and fair scheduling in wireless local area networks. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-D83.
Council of Science Editors:
Dugar A. Priority and fair scheduling in wireless local area networks. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-D83
Texas A&M University
11.
Garg, Aman.
Mitigating Denial of Service using QoS regulation.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-G3714
► As more and more critical services are provided over the Internet, the risk to these services from malicious users is also increasing. Several networks have…
(more)
▼ As more and more critical services are provided over the Internet, the risk to these services from malicious users is also increasing. Several networks have witnessed problems like Denial of Service attacks over the recent past. Denial of Service attacks work by flooding a network, router or an end server with malicious packets and fooling the underlying system into believing that these malicious packets were legitimate. An excess of these packets can cause overload conditions in the network and on the end servers. The purpose of this research is to provide an efficient way to keep track of server and network resources in an attempt to mitigate the effect of such attacks. Our scheme provides a general, and not attack specific, mechanism to provide graceful server degradation in the face of such an attack. Our solution is based on two seemingly different paradigms – Denial of Service, and Quality of Service. The solution has two parts. The first part is to maintain sufficient state information per resource in the network layer, so as to be able to get a high-level picture of current network behavior and resource consumption status. The second part is a policing or enforcing mechanism which can regulate resource consumption and recover excess resources if they are believed to be held by malicious flows. A Window Regulation based scheme is proposed and implemented to do the regulation of traffic. It is shown that this scheme works better than conventional rate-based QoS regulation.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA ·
Chicago ·
MLA ·
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APA (6th Edition):
Garg, A. (2012). Mitigating Denial of Service using QoS regulation. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-G3714
Chicago Manual of Style (16th Edition):
Garg, Aman. “Mitigating Denial of Service using QoS regulation.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-G3714.
MLA Handbook (7th Edition):
Garg, Aman. “Mitigating Denial of Service using QoS regulation.” 2012. Web. 27 Feb 2021.
Vancouver:
Garg A. Mitigating Denial of Service using QoS regulation. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-G3714.
Council of Science Editors:
Garg A. Mitigating Denial of Service using QoS regulation. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-G3714
Texas A&M University
12.
Kim, In-Koo.
Analyzing network traces to identify long-term high rate flows.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-K542
► In this thesis we look at a scalable way of identifying long-term high rate flows without maintaining per flow state information proportional to the number…
(more)
▼ In this thesis we look at a scalable way of identifying long-term high rate flows without maintaining per flow state information proportional to the number of flows. Identification of high-rate flows is useful at the time of congestion. This thesis proposes and evaluates a scheme for identifying high-rate flows without explicitly measuring the rates of the flows. Typical Internet traffic consists of a large fraction of flows that are ON/OFF in nature. Maintaining state information for every flow is unnecessary and expensive. We observe that this is a situation similar to the cache memory management in that we want to maintain information only on high rate flows (corresponding to frequently-referenced data items) using fixed space. We apply the LRU (least recent used) policy in selecting the high rate flows only. We observe that the single definition of a flow by the address/port/protocol quintuple unduly increases the observed number of flows, since approximately more than half of all flows so-defined are single-packet flows, i.e. about 50% of such quintuples are observed in only one packet over a timeout interval, e.g. of 100 seconds. We introduce a random decimator to filter them out statistically.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA ·
Chicago ·
MLA ·
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APA (6th Edition):
Kim, I. (2012). Analyzing network traces to identify long-term high rate flows. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-K542
Chicago Manual of Style (16th Edition):
Kim, In-Koo. “Analyzing network traces to identify long-term high rate flows.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-K542.
MLA Handbook (7th Edition):
Kim, In-Koo. “Analyzing network traces to identify long-term high rate flows.” 2012. Web. 27 Feb 2021.
Vancouver:
Kim I. Analyzing network traces to identify long-term high rate flows. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-K542.
Council of Science Editors:
Kim I. Analyzing network traces to identify long-term high rate flows. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-K542
Texas A&M University
13.
Mohanty, Debashis.
Design space exploration for multiprocessor-based embedded systems.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-M645
► Design space exploration is the process of obtaining the optimal design out of all possible design alternatives. The design-space becomes very large when the target…
(more)
▼ Design space exploration is the process of obtaining the optimal design out of all possible design alternatives. The design-space becomes very large when the target architecture consists of heterogeneous components, and it is not possible to explore it in a very short time frame. This thesis attempts to reduce the design-space that has multiplied with the advent of the multiprocessor system-on-chip (MSoC). Traditional methodology suits the single processor system-on-chip, which has fixed allocated components and the embedded-system designer has to partition the specification between hardware and software. However, in MSoC allocation is not fixed. A new stage in the design cycle called "Pre-Allocation" is introduced. It determines the number and type of components required for the implementation at system-level based on performance estimation. Pre-allocation can reduce the design-time for multiprocessor-based embedded systems.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA ·
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MLA ·
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APA (6th Edition):
Mohanty, D. (2012). Design space exploration for multiprocessor-based embedded systems. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-M645
Chicago Manual of Style (16th Edition):
Mohanty, Debashis. “Design space exploration for multiprocessor-based embedded systems.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-M645.
MLA Handbook (7th Edition):
Mohanty, Debashis. “Design space exploration for multiprocessor-based embedded systems.” 2012. Web. 27 Feb 2021.
Vancouver:
Mohanty D. Design space exploration for multiprocessor-based embedded systems. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-M645.
Council of Science Editors:
Mohanty D. Design space exploration for multiprocessor-based embedded systems. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-M645
Texas A&M University
14.
Roy, Siddhartha.
A visualized conflict resolution framework for software requirements negotiation.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-R684
► Effective and efficient requirements negotiation, a key factor in the success of large software projects, is difficult when combining input from geographically distributed experts and…
(more)
▼ Effective and efficient requirements negotiation, a key factor in the success of large software projects, is difficult when combining input from geographically distributed experts and reaching consensus from different stakeholders (e.g., end-users, developers, software assurance, customers) as well as different aspects of software requirements (e.g., functionality, non-functional quality, and infrastructure). Stakeholder perception conflicts should be anticipated and resolved at the early stage of decision making to achieve a shared vision of the requirements. Stakeholder conflict negotiation processes produce a massive amount of negotiation data wherein meaningful information is buried, and so is impractical for use. Our central hypothesis is that intuitive visualization of perceptions and conflicts in perceptions enables stakeholder understanding of mutual concerns and discernment of underlying trends leading to decisions based on sound consensus between stakeholders. We propose a Visualized Conflict Resolution (VCR) framework for requirements conflict negotiation among stakeholders by providing a platform for collecting stakeholder perception data, analyzing the degree of the perception conflicts, visualizing the perceptions and conflicts using intuitive graphical presentations, and providing conflict resolution guidance.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA ·
Chicago ·
MLA ·
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APA (6th Edition):
Roy, S. (2012). A visualized conflict resolution framework for software requirements negotiation. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-R684
Chicago Manual of Style (16th Edition):
Roy, Siddhartha. “A visualized conflict resolution framework for software requirements negotiation.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-R684.
MLA Handbook (7th Edition):
Roy, Siddhartha. “A visualized conflict resolution framework for software requirements negotiation.” 2012. Web. 27 Feb 2021.
Vancouver:
Roy S. A visualized conflict resolution framework for software requirements negotiation. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-R684.
Council of Science Editors:
Roy S. A visualized conflict resolution framework for software requirements negotiation. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-R684
Texas A&M University
15.
Selvarathinam, Anand Manivannan.
Generation of RTL verification input stimulus.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-S38
► This thesis presents an approach for generating input stimulus for verification of register-transfer level (RTL) design of VLSI circuits. RTL design is often subjected to…
(more)
▼ This thesis presents an approach for generating input stimulus for verification of register-transfer level (RTL) design of VLSI circuits. RTL design is often subjected to a significant verification effort due to errors introduced during manual intervention. Simulation is widely used for verifying RTL designs despite its limitation. For a given coverage metric, the verification input vectors are generated to attain a higher level of coverage. Many verification coverage measures were proposed in the past that include code and branch coverage. Their limitations led to coverage based on control path. However, control based coverage provides good verification quality. Recent control based coverage approaches such as Extended Condition Coverage (ECC) provide better coverage quality through condition variable excitation and observation. The purpose of this research is to generate input stimulus for verification, based on ECC. The input stimulus is generated through gate-level analysis. Conventional automatic test pattern generation (ATPG) tools generate input vectors for the gate-level design. The proposed approach maps the condition cases in the RTL design to the gate-level stuck-at-faults. These stuck-at-faults are included in the fault list that guides the ATPG tool to generate input vectors for the gate-level design. These input vectors are sorted and re-mapped to generate verification input stimulus for the RTL design.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA (6th Edition):
Selvarathinam, A. M. (2012). Generation of RTL verification input stimulus. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-S38
Chicago Manual of Style (16th Edition):
Selvarathinam, Anand Manivannan. “Generation of RTL verification input stimulus.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-S38.
MLA Handbook (7th Edition):
Selvarathinam, Anand Manivannan. “Generation of RTL verification input stimulus.” 2012. Web. 27 Feb 2021.
Vancouver:
Selvarathinam AM. Generation of RTL verification input stimulus. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-S38.
Council of Science Editors:
Selvarathinam AM. Generation of RTL verification input stimulus. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-S38
Texas A&M University
16.
Thadhlani, Ajaykumar A.
Realistic fault modeling and quality test generation of combined delay faults.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-T423
► With increasing operating speed and shrinking technology, timing defects in integrated circuits are becoming increasingly important. The well established stuck-at-fault model is not sufficient because…
(more)
▼ With increasing operating speed and shrinking technology, timing defects in integrated circuits are becoming increasingly important. The well established stuck-at-fault model is not sufficient because it is a static fault model and does not account for the dynamic behavior of the circuit. Due to the signal integrity problem, the testing of VLSI-chips is becoming more complex. A static test vector generated to test a defect in an integrated chip can be found ineffective under the effect of capacitively coupled lines. To cope up with these realistic testing problems, it is necessary to model the circuit defects by considering the capacitively coupling between lines. This needs a better fault model which can incorporate the local defects (such as bridging defects) as well as global defects (such as cross-talk). Also it is necessary to generate test vectors which maximize the delay effect due to these combined faults. The test vectors should be generated so as to detect the maximum number of defects in real chips. In this research, we model the combined effect of local and global faults, and the model is called a combined delay fault model. We use the transition delay fault model to model the local defects on each line. Various quality constraints are imposed during test generation so that better quality test vectors are achieved. We impose strong driving constraints on gates to maximize the transition delay and propagate the transition effect along the longest, robust paths to increase the detection of small timing defects. We compare the test generation results for ISCAS85 benchmark circuits and see how efficient our quality test vectors are in detecting these combined delay faults. Finally, we study the DOREME vectors in reference to their efficiency in detecting transition faults and compare our quality test vectors with DOREME test vectors.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA (6th Edition):
Thadhlani, A. A. (2012). Realistic fault modeling and quality test generation of combined delay faults. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-T423
Chicago Manual of Style (16th Edition):
Thadhlani, Ajaykumar A. “Realistic fault modeling and quality test generation of combined delay faults.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-T423.
MLA Handbook (7th Edition):
Thadhlani, Ajaykumar A. “Realistic fault modeling and quality test generation of combined delay faults.” 2012. Web. 27 Feb 2021.
Vancouver:
Thadhlani AA. Realistic fault modeling and quality test generation of combined delay faults. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-T423.
Council of Science Editors:
Thadhlani AA. Realistic fault modeling and quality test generation of combined delay faults. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2001-THESIS-T423
Texas A&M University
17.
Bhosekar, Sunil.
High level power estimation of cache and TLB using complete machine simulation.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-B473
► The power dissipation of the modern processor has rapidly increased along with increasing transistor counts and clock frequencies. This is detrimental to the battery lifetime…
(more)
▼ The power dissipation of the modern processor has rapidly increased along with increasing transistor counts and clock frequencies. This is detrimental to the battery lifetime in the embedded processor, and also to the reliability. Therefore, designing a processor with the intent of minimizing system costs, especially that arise from high power consumption, requires attention at all design stages. Thus, power estimation tools are required in all the design stages and tools exist to perform power-estimation and optimization a lower levels of abstraction. While these tools typically provide accurate results, it is often difficult to use the estimates to make optimization at the higher levels. These tools are reasonably mature; however greater attention is necessary at higher abstraction levels. As power becomes a critical design constraint, there is a need to open the power problems to the architects and compiler writers also, thus leading to a design, which is optimized for power and performance. The goal of this thesis is to address the power problem in embedded processors and propose a methodology for high-level power estimation and optimization. The primary objective of high-level power estimation is the ability to quickly decide which solution utilizes minimal power rather than determining the accurate amount of power dissipation. Upon the best solution determination, a more accurate estimate may be given at the lower levels of abstraction. After system design, the power optimization can be performed at any design stage. Among all techniques, the optimization problems can be formulated more precisely at the circuit level. Significant improvements are possible in cell based designs such as memories. There are important techniques such as voltage cell reduction and memory cell redesign. Our methodology is based on the memory cell redesign, specifically the redesign of the content addressable memory (CAM). In this work, we estimate the power dissipation in the cache and the Translation Lookaside Buffer (TLB) of an embedded processor. In order to get an accurate estimate, we combine the power models derived from the transistor level structures with a complete machine simulator.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA ·
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MLA ·
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APA (6th Edition):
Bhosekar, S. (2012). High level power estimation of cache and TLB using complete machine simulation. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-B473
Chicago Manual of Style (16th Edition):
Bhosekar, Sunil. “High level power estimation of cache and TLB using complete machine simulation.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-B473.
MLA Handbook (7th Edition):
Bhosekar, Sunil. “High level power estimation of cache and TLB using complete machine simulation.” 2012. Web. 27 Feb 2021.
Vancouver:
Bhosekar S. High level power estimation of cache and TLB using complete machine simulation. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-B473.
Council of Science Editors:
Bhosekar S. High level power estimation of cache and TLB using complete machine simulation. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-B473
Texas A&M University
18.
Swaminathan, Narayanan.
Communication synthesis for on chip networks.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-S87
► The modern day System on Chip (SoC) is made up of a large number of heterogeneous cores with varied communication requirements. On chip networks are…
(more)
▼ The modern day System on Chip (SoC) is made up of a large number of heterogeneous cores with varied communication requirements. On chip networks are the scalable, global interconnection solutions for these explicitly parallel systems. In this thesis, we have analyzed the issues involved in synthesizing these networks and proposed a methodology that will help to arrive at an optimal Network on Chip (NoC) design. Some of the important issues that we consider for synthesis are the quality of service (QoS) requirements of the communicating cores like latency and data rate, the utilization of the network resources and implementation cost issues like area, power and wiring complexity. We have developed a tool-set written mainly in C++, which comprises of an IP clustering engine and an on chip network simulator, to aid the synthesis. We have annotated the models used for communication architecture synthesis with design parameters obtained from gate level synthesis. The tool-set can aid the designer in predicting the various cost parameters and configuring the network on chip architecture for optimal performance. The network simulator, NoCSIM, can be extended to evaluate the performance and feasibility of new and innovative network architectures developed for on chip environment.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA (6th Edition):
Swaminathan, N. (2012). Communication synthesis for on chip networks. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-S87
Chicago Manual of Style (16th Edition):
Swaminathan, Narayanan. “Communication synthesis for on chip networks.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-S87.
MLA Handbook (7th Edition):
Swaminathan, Narayanan. “Communication synthesis for on chip networks.” 2012. Web. 27 Feb 2021.
Vancouver:
Swaminathan N. Communication synthesis for on chip networks. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-S87.
Council of Science Editors:
Swaminathan N. Communication synthesis for on chip networks. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-S87
Texas A&M University
19.
Thoppae, Mothi M.
Software branch prediction via inter-procedural path profiling.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-T47
► The technique of predicting branch directions before execution is defined as branch prediction. Conditional branches pose a hazard to the instruction flow since the instruction…
(more)
▼ The technique of predicting branch directions before execution is defined as branch prediction. Conditional branches pose a hazard to the instruction flow since the instruction that executes after the branch is not known. When a branch appears, the next instruction is not known till the branch is executed. Either instruction fetch has to be halted or the branch direction has to be predicted. With some degree of probability the latter method of predicting branch directions has yielded good results. Several authors have suggested ways of predicting the direction of conditional branches with hardware that uses the history of previous branches. The branches are predicted statically, which occurs during compile time, or dynamically, which occurs during run-time. Dynamic methods have shown the better performance over static schemes. They employ one or two levels of history information and prediction accuracy scales proportional to the history information. So employing larger branch tables, which store the branch histories, we get good performance With reducing chip area, larger tables would occupy a significant portion of chip area. We propose a technique called software branch prediction, where the branch tables reside in the physical memory along with the application. The branch tables no longer reside in the hardware and so chip area occupied by the tables is freed. Software branch prediction performs as well as hardware predictions in terms of prediction accuracy, but the execution time of the application is increased by 50 - 100 %. Since accessing software tables takes longer than hardware tables, the execution time is higher. We need to identify ways to reduce the execution time. We propose one such mechanism called pivot branches. Pivot branches are branches whose execution can determine the direction taken by a few or more branches. We could predict more than one branch direction by correctly predicting pivot branches at one time. Two different methods were attempted to determine the existence of pivot branches. They are code inspection and inter-procedural path profiling. Path profiling was done on two SPEC benchmarks. The results did not clearly indicate if pivot branches exist, but it shows that there are gains doing predictions this way.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA (6th Edition):
Thoppae, M. M. (2012). Software branch prediction via inter-procedural path profiling. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-T47
Chicago Manual of Style (16th Edition):
Thoppae, Mothi M. “Software branch prediction via inter-procedural path profiling.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-T47.
MLA Handbook (7th Edition):
Thoppae, Mothi M. “Software branch prediction via inter-procedural path profiling.” 2012. Web. 27 Feb 2021.
Vancouver:
Thoppae MM. Software branch prediction via inter-procedural path profiling. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-T47.
Council of Science Editors:
Thoppae MM. Software branch prediction via inter-procedural path profiling. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-T47
Texas A&M University
20.
Zhu, Ye.
Application-aware resource control in support of network-level QOS.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-Z48
► Facing limited network resources such as bandwidth and processing capability, the Internet will have congestion from time to time. In this thesis, we propose a…
(more)
▼ Facing limited network resources such as bandwidth and processing capability, the Internet will have congestion from time to time. In this thesis, we propose a scheme to maximize the total utility offered by the network to the end user during congested times. We believe the only way to achieve our goal is to make the scheme application-aware, that is, to take advantage of the characteristics of the application. To make our scheme scalable, it is designed to be class-based. Traffic from applications with similar characteristics is classified into the same class. We adopted the RED queue management mechanism to adaptively control the traffic belonging to the same class. To achieve the optimal utility, the traffic belonging to different classes should be controlled differently. By adjusting link bandwidth assignments of different classes, the scheme can achieve the goal and adapt to the changes of dynamical incoming traffic. We use the control heoretical approach to analyze our scheme.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA (6th Edition):
Zhu, Y. (2012). Application-aware resource control in support of network-level QOS. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-Z48
Chicago Manual of Style (16th Edition):
Zhu, Ye. “Application-aware resource control in support of network-level QOS.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-Z48.
MLA Handbook (7th Edition):
Zhu, Ye. “Application-aware resource control in support of network-level QOS.” 2012. Web. 27 Feb 2021.
Vancouver:
Zhu Y. Application-aware resource control in support of network-level QOS. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-Z48.
Council of Science Editors:
Zhu Y. Application-aware resource control in support of network-level QOS. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-Z48
Texas A&M University
21.
Kappagantula, Vijay Rama Pramod.
A power aware partitioning framework for hardware-software codesign.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2003-THESIS-K37
► Existing approaches in hardware-software partitioning do not consider the maximum available system power while making the partitioning decision. Such a decision is sensitive to design…
(more)
▼ Existing approaches in hardware-software partitioning do not consider the maximum available system power while making the partitioning decision. Such a decision is sensitive to design efficiency when the target system is reconfigurable and supports multiple applications. Since partitioning and scheduling are interdependent, neglecting the available system power could result in an infeasible schedule. In this thesis, we present a power-aware partitioning technique for embedded systems that could support a set of applications. The applications specified at a task level of granularity are partitioned and scheduled such that timing and maximum available system power constraints are satisfied with minimum hardware logic.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA (6th Edition):
Kappagantula, V. R. P. (2012). A power aware partitioning framework for hardware-software codesign. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2003-THESIS-K37
Chicago Manual of Style (16th Edition):
Kappagantula, Vijay Rama Pramod. “A power aware partitioning framework for hardware-software codesign.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2003-THESIS-K37.
MLA Handbook (7th Edition):
Kappagantula, Vijay Rama Pramod. “A power aware partitioning framework for hardware-software codesign.” 2012. Web. 27 Feb 2021.
Vancouver:
Kappagantula VRP. A power aware partitioning framework for hardware-software codesign. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2003-THESIS-K37.
Council of Science Editors:
Kappagantula VRP. A power aware partitioning framework for hardware-software codesign. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2003-THESIS-K37
Texas A&M University
22.
Wisinger, John L.
FPGA based image processing with R-fuctions and the curvelet transform.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2003-THESIS-W378
► In the past few years, image processing has begun to make its way into many new areas, both academic and commercial. One of the most…
(more)
▼ In the past few years, image processing has begun to make its way into many new areas, both academic and commercial. One of the most popular areas is in computer generated animation. This includes films, video games, medical imaging, and various other multimedia systems for both entertainment and more serious applications. Two fairly recent independent developments in this field are R-functions and the curvelet transform. R-functions were developed to make it possible to represent complex objects by using a collection of simpler primitives. The curvelet transform was designed to extract specific features from complex objects. Although impressive performance can be achieved with R-functions and curvelets, the complexity of their implementation is quite a drain on standard microprocessors. It is for this reason that an FPGA implementation was developed. By offloading some of the processing work into a properly configured FPGA, speeds can be achieved in excess of one hundred times faster than current high end servers. This increase in processing speed and image representation ability combine to have some useful applications. Now, highly complex image processing can be done in small areas allowing for the design of systems that were previously not feasible to develop. By using the concepts presented in this thesis, ideas have come about for the development of a large scale Boltzman equation solver, and a satellite hyperspectral imaging system. The Boltzman equation solver has been developed before, but only by using very costly and space consuming servers. Design of the satellite hyperspectral imaging system has been hindered by the low data transmission rate of the communication system. By processing some of the data on the system itself this problem is removed. This thesis proves that R-functions and numeric transforms can be done in an FPGA to give far better performance than regular microprocessors. It also shows the power of the R-function and the curvelet and ridgelet transforms. With further development, this could yield some amazing results.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA (6th Edition):
Wisinger, J. L. (2012). FPGA based image processing with R-fuctions and the curvelet transform. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2003-THESIS-W378
Chicago Manual of Style (16th Edition):
Wisinger, John L. “FPGA based image processing with R-fuctions and the curvelet transform.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2003-THESIS-W378.
MLA Handbook (7th Edition):
Wisinger, John L. “FPGA based image processing with R-fuctions and the curvelet transform.” 2012. Web. 27 Feb 2021.
Vancouver:
Wisinger JL. FPGA based image processing with R-fuctions and the curvelet transform. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2003-THESIS-W378.
Council of Science Editors:
Wisinger JL. FPGA based image processing with R-fuctions and the curvelet transform. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2003-THESIS-W378
Texas A&M University
23.
Kini, Savita.
Myrinet Real Time Protocol with flexible routing.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-1998-THESIS-K572
► Real Time communication relies on resource reservation ics. along the path of the connection for performance guarantees, typically in terms of bounded delays. A fully…
(more)
▼ Real Time communication relies on resource reservation ics. along the path of the connection for performance guarantees, typically in terms of bounded delays. A fully distributed admission control scheme for resource allocation in real-time communications was developed for Myrinet style networks. However, this scheme, also called as the Myrinet Real-Time Protocol (MyRTP), was limited to using a priori routes provided by Myrinet. We have developed and integrated a deadlock-free routing and a resource reservation mechanism based on the above admission control algorithm. Routes are computed dynamically during connection establishment process. Flexible ding a dynamic route management infrastructure for routing is implemented by bull the Myrinet firmware in the network interface card. The advantage of flexible routing is better resource utilization but at the cost of increased connection establishment time. A suite of experiments was performed to measure the connection establishment time and admission probability for connections under varying amount of loads.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA (6th Edition):
Kini, S. (2012). Myrinet Real Time Protocol with flexible routing. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-1998-THESIS-K572
Chicago Manual of Style (16th Edition):
Kini, Savita. “Myrinet Real Time Protocol with flexible routing.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-1998-THESIS-K572.
MLA Handbook (7th Edition):
Kini, Savita. “Myrinet Real Time Protocol with flexible routing.” 2012. Web. 27 Feb 2021.
Vancouver:
Kini S. Myrinet Real Time Protocol with flexible routing. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1998-THESIS-K572.
Council of Science Editors:
Kini S. Myrinet Real Time Protocol with flexible routing. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1998-THESIS-K572
Texas A&M University
24.
Kunapareddy, Padmaja.
On the performance management of heterogeneous networks using SNMP.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-1998-THESIS-K86
► and WANs with multi-vendor devices strongly perceives the need for an effective network management system. This burgeoning demand has lead to proliferation of different ways…
(more)
▼ and WANs with multi-vendor devices strongly perceives the need for an effective network management system. This burgeoning demand has lead to proliferation of different ways of managing and monitoring the devices. As a result there are a number of platforms and tools developed for and by diverse groups of end users- from academia to industry-which integrate multiple management functions. However, considering the wide range of network management issues, no single network management product can effectively address the myriad needs of a typical distributed network viz. simple IP node discovery, alarm handling, modeling or performance monitoring. Based on an extensive analysis of these tools on (live' network devices, a design strategy for a Performance Management solution using SNMPvI is put forth. In order to support a mid-level manager framework for remote monitoring, the most important aspects focussed on are-Management Information Base (M1B) management and monitoring strategies. This approach proposes the merging of the existing peer and the hierarchical network management architectures. This scheme also examines the various implications and emphasizes the need and ways to use some of the new features of SNMPv2. These could be built upon by complete coexistence with vl. Parallel growth in remote monitoring and Web based management has been explored so that the mid-level manager is remotely accusable and could be deployed on any system.
Subjects/Keywords: computer engineering.; Major computer engineering.
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Manager
APA (6th Edition):
Kunapareddy, P. (2012). On the performance management of heterogeneous networks using SNMP. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-1998-THESIS-K86
Chicago Manual of Style (16th Edition):
Kunapareddy, Padmaja. “On the performance management of heterogeneous networks using SNMP.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-1998-THESIS-K86.
MLA Handbook (7th Edition):
Kunapareddy, Padmaja. “On the performance management of heterogeneous networks using SNMP.” 2012. Web. 27 Feb 2021.
Vancouver:
Kunapareddy P. On the performance management of heterogeneous networks using SNMP. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1998-THESIS-K86.
Council of Science Editors:
Kunapareddy P. On the performance management of heterogeneous networks using SNMP. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1998-THESIS-K86
Texas A&M University
25.
Yeom, Ik-Jun.
ENDE: an End-to-end Network Delay Emulator.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-1998-THESIS-Y36
► The Internet provides a common interface between ographics. different types of computers and networks, and various applications and protocols are constantly being developed. A new…
(more)
▼ The Internet provides a common interface between ographics. different types of computers and networks, and various applications and protocols are constantly being developed. A new protocol or application after being developed has to be tested on the real Internet or simulated on a testbed for debugging and performance evaluation. protocol developer typically requires access to multiple machines across the Internet for this reason. In this thesis we present a new took that can emulate end-to-end delays between two hosts without requiring access to the second host. The tool enables the user to test new protocols realistically on a single machine. The tool observes network status on a particular path using ICMP packets and uses it as a real-time traffic source. Experimented results are presented to show that this approach is effective and quite accurate.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA (6th Edition):
Yeom, I. (2012). ENDE: an End-to-end Network Delay Emulator. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-1998-THESIS-Y36
Chicago Manual of Style (16th Edition):
Yeom, Ik-Jun. “ENDE: an End-to-end Network Delay Emulator.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-1998-THESIS-Y36.
MLA Handbook (7th Edition):
Yeom, Ik-Jun. “ENDE: an End-to-end Network Delay Emulator.” 2012. Web. 27 Feb 2021.
Vancouver:
Yeom I. ENDE: an End-to-end Network Delay Emulator. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1998-THESIS-Y36.
Council of Science Editors:
Yeom I. ENDE: an End-to-end Network Delay Emulator. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1998-THESIS-Y36
Texas A&M University
26.
Koh, T Pinn Ronnie.
A study of compatibility in conjunction with implication based optimization and different forms of implications.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-1999-THESIS-K64
► This research is a study of multilevel logic optimization based on a functional approach using ordered binary decision diagrams (OBDD). Compatibility relationships between internal nodes…
(more)
▼ This research is a study of multilevel logic optimization based on a functional approach using ordered binary decision diagrams (OBDD). Compatibility relationships between internal nodes in a circuit are used in conjunction with implication based transformations to optimize multilevel combinational circuits. Implications are further partitioned into four classifications; in-line, off-line, strictly-strong and strictly-weak. The CUDD library package for BDD manipulation is used here to find all compatibilities by building all internal functions and finding all boolean differences. Redundancies are eliminated by the characteristics inherent in the compatibility criteria. Compatibility allows for the substitution of non equivalent nodes based on observability at the outputs and thus generating redundancies upstream. Implication transformations are then applied and a search for compatibilities is performed again. Since the search for compatibilities involves a wider set than redundancies, the potential for greater reduction increases. Implications are further divided into more specific catagories based on whether one node is upstream of the other node (in-line) else (off-line), and if the implications are found using absolute internal functions (strictly-strong) or permissible functions based on boolean differences (strictly-weak). A study of the success rates of using Strictly-strong-in-line, Strictly-strong-Off-line, Strictly-weak-in-line and Strictly-weak-off-line implications for generating redundancies is made to see if any of the catagories are better suited for optimization. Verification of the reduced circuit is trivial since the BDD for a given order is canonical, and thus compatibility substitution and implication transformation should not change the output BDD's.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA (6th Edition):
Koh, T. P. R. (2012). A study of compatibility in conjunction with implication based optimization and different forms of implications. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-1999-THESIS-K64
Chicago Manual of Style (16th Edition):
Koh, T Pinn Ronnie. “A study of compatibility in conjunction with implication based optimization and different forms of implications.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-1999-THESIS-K64.
MLA Handbook (7th Edition):
Koh, T Pinn Ronnie. “A study of compatibility in conjunction with implication based optimization and different forms of implications.” 2012. Web. 27 Feb 2021.
Vancouver:
Koh TPR. A study of compatibility in conjunction with implication based optimization and different forms of implications. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1999-THESIS-K64.
Council of Science Editors:
Koh TPR. A study of compatibility in conjunction with implication based optimization and different forms of implications. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1999-THESIS-K64
Texas A&M University
27.
Murray, Brian.
Development of an embedded 3D graphics processor.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-M87
► Limitations in processing ability cause major graphical enhancements, such as support for real-time 3D graphics, to be next to impossible within embedded devices. Due to…
(more)
▼ Limitations in processing ability cause major graphical enhancements, such as support for real-time 3D graphics, to be next to impossible within embedded devices. Due to the size, power, and heat dissipation requirements, modern graphics hardware is usually restricted to systems on the scale of personal computers or larger. For this thesis, we have defined a 3D graphics co-processor that is targeted to work on a more embedded scale. The system is specified by limiting it to fixed-point light processing and rasterization. A set of object primitives and instructions are defined to adequately describe almost any scene. These primitives are used to design the algorithms and architecture behind a set of modular functional units. The units are used to realize the processor requirements and features, which include light processing, z-buffering, texturing, and transparency. In order to ensure that the system architecture is versatile in its design, the functional units are analyzed for performance, reconfigurability, and possible trade-offs. A set of both synchronous and asynchronous architectures are proposed using the functional unit blocks. Through cycle accurate comparative simulation, we analyzed the effectiveness of each architecture and found that a hybrid architecture provides the best hardware to speed trade-off between the architectures considered. An appropriate system interface and parallel configuration are also discussed. The end result of the thesis provides a road map for anyone designing a general purpose or application optimized embedded 3D co-processor.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA (6th Edition):
Murray, B. (2012). Development of an embedded 3D graphics processor. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-M87
Chicago Manual of Style (16th Edition):
Murray, Brian. “Development of an embedded 3D graphics processor.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-M87.
MLA Handbook (7th Edition):
Murray, Brian. “Development of an embedded 3D graphics processor.” 2012. Web. 27 Feb 2021.
Vancouver:
Murray B. Development of an embedded 3D graphics processor. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-M87.
Council of Science Editors:
Murray B. Development of an embedded 3D graphics processor. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-M87
Texas A&M University
28.
Okorafor, Ekpe Apia.
Design, analysis and simulation study of a Scalable all-Optical Interconnection Network (SCOPIN) for multiprocessing systems.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-O53
► With the pressure mounting for more efficient and robust interconnection schemes required for multiprocessing systems and used in massively parallel computing, the advent of optical…
(more)
▼ With the pressure mounting for more efficient and robust interconnection schemes required for multiprocessing systems and used in massively parallel computing, the advent of optical interconnection networks is a welcome development. Already many optical media have been investigated and some have been practically demonstrated to be quite feasible. It is left for the computer designers to come up with brilliant schemes to harness the immense possibilities that exist using optical interconnects. Aspects like the use of totally free space optics, fiber optics, electro-optics, light splitting and grating, etc. are all under research. Optical systems offer the strengths of both temporal and spatial bandwidth to be exploited in the construction of computer communication systems. Many topologies have been researched and some have been implemented successfully. Scalable networks add another interesting dimension to the problem complexity. This thesis will introduce yet another way to optimize the use of optics for interprocessor communication. It will include a detailed analysis and simulation study of the design space, an evaluation of the feasibility of implementation and pointers to future areas of improvement. The aim will be to develop a scalable and flexible all-optical single-hop interconnection network, called Scalable Optical Interconnection Network (SCOPIN).
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA (6th Edition):
Okorafor, E. A. (2012). Design, analysis and simulation study of a Scalable all-Optical Interconnection Network (SCOPIN) for multiprocessing systems. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-O53
Chicago Manual of Style (16th Edition):
Okorafor, Ekpe Apia. “Design, analysis and simulation study of a Scalable all-Optical Interconnection Network (SCOPIN) for multiprocessing systems.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-O53.
MLA Handbook (7th Edition):
Okorafor, Ekpe Apia. “Design, analysis and simulation study of a Scalable all-Optical Interconnection Network (SCOPIN) for multiprocessing systems.” 2012. Web. 27 Feb 2021.
Vancouver:
Okorafor EA. Design, analysis and simulation study of a Scalable all-Optical Interconnection Network (SCOPIN) for multiprocessing systems. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-O53.
Council of Science Editors:
Okorafor EA. Design, analysis and simulation study of a Scalable all-Optical Interconnection Network (SCOPIN) for multiprocessing systems. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-O53
Texas A&M University
29.
Ramanathan, Anu.
WADeS: a tool for Distributed Denial of Service Attack detection.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-R35
► The increasing popularity of web-based applications has led to several critical services being provided over the Internet. This has made it imperative to monitor the…
(more)
▼ The increasing popularity of web-based applications has led to several critical services being provided over the Internet. This has made it imperative to monitor the network traffic so as to prevent malicious attackers from depleting the network's resources and denying service to legitimate users. In our research work, we propose WADeS (Wavelet based Attack Detection Signatures), an approach to detect a Distributed Denial of Service Attack using Wavelet methods. We develop a new framework that uses LRU cache filtering to capture the high bandwidth flows followed by computation of wavelet variance on the aggregate miss traffic. The introduction of attack traffic in the network would elicit changes in the wavelet variance. This is combined with thresholding methods to enable attack detection. Sampling techniques can be used to tailor the cost of our detection mechanism. The mechanism we suggest is independent of routing information, thereby making attack detection immune to IP address spoofing. Using simulations and quantitative measures, we find that our mechanism works successfully on several kinds of attacks. We also use statistical methods to validate the results obtained.
Subjects/Keywords: computer engineering.; Major computer engineering.
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APA (6th Edition):
Ramanathan, A. (2012). WADeS: a tool for Distributed Denial of Service Attack detection. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-R35
Chicago Manual of Style (16th Edition):
Ramanathan, Anu. “WADeS: a tool for Distributed Denial of Service Attack detection.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-R35.
MLA Handbook (7th Edition):
Ramanathan, Anu. “WADeS: a tool for Distributed Denial of Service Attack detection.” 2012. Web. 27 Feb 2021.
Vancouver:
Ramanathan A. WADeS: a tool for Distributed Denial of Service Attack detection. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-R35.
Council of Science Editors:
Ramanathan A. WADeS: a tool for Distributed Denial of Service Attack detection. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-R35
Texas A&M University
30.
El-Haj Mahmoud, Samer Ahmad.
A UNIX security log analyzer based on from/to access matrix.
Degree: MS, computer engineering, 2012, Texas A&M University
URL: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-E39
► System log files are valuable assets in detecting security violations and malicious attacks as well as in holding users responsible for their actions. However, the…
(more)
▼ System log files are valuable assets in detecting security violations and malicious attacks as well as in holding users responsible for their actions. However, the huge size of these logs makes it impractical for system administrators to examine them manually. This leaves potential threats logged but undetected. Several tools exist for automated log analysis and reporting, such as Swatch, Logsurfer, and Logcheck. Most of these tools depend on either detecting patterns of known attacks or eliminating patterns of normal behavior. This research aims to study UNIX system log files and log analyzers, and to present a new method for log analysis. The method is based on a systems access matrix that provides a set of rules for services in the network. For each service listed in the matrix, the rules specify access rights for every user, indicating the source hosts that the user can access that service from, and the destination hosts on which the service can be accessed. A tool called LogMatrix has been developed to examine the system logs and analyze them by comparing the actual events to the rules in the from/to access matrix.
Subjects/Keywords: computer engineering.; Major computer engineering.
Record Details
Similar Records
Cite
Share »
Record Details
Similar Records
Cite
« Share
❌
APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
El-Haj Mahmoud, S. A. (2012). A UNIX security log analyzer based on from/to access matrix. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-E39
Chicago Manual of Style (16th Edition):
El-Haj Mahmoud, Samer Ahmad. “A UNIX security log analyzer based on from/to access matrix.” 2012. Masters Thesis, Texas A&M University. Accessed February 27, 2021.
http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-E39.
MLA Handbook (7th Edition):
El-Haj Mahmoud, Samer Ahmad. “A UNIX security log analyzer based on from/to access matrix.” 2012. Web. 27 Feb 2021.
Vancouver:
El-Haj Mahmoud SA. A UNIX security log analyzer based on from/to access matrix. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Feb 27].
Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-E39.
Council of Science Editors:
El-Haj Mahmoud SA. A UNIX security log analyzer based on from/to access matrix. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2002-THESIS-E39
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