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You searched for `subject:(Computer arithmetic AND logic units)`

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Rutgers University

1.
Kumar, Mrinal, 1990-.
Lower bounds for bounded depth *arithmetic* circuits.

Degree: PhD, Computer Science, 2017, Rutgers University

URL: https://rucore.libraries.rutgers.edu/rutgers-lib/54175/

► Proving lower bounds for *arithmetic* circuits is a problem of fundamental importance in theoretical *computer* science. In recent years, an approach to this problem has…
(more)

Subjects/Keywords: Computer arithmetic and logic units

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APA (6^{th} Edition):

Kumar, Mrinal, 1. (2017). Lower bounds for bounded depth arithmetic circuits. (Doctoral Dissertation). Rutgers University. Retrieved from https://rucore.libraries.rutgers.edu/rutgers-lib/54175/

Chicago Manual of Style (16^{th} Edition):

Kumar, Mrinal, 1990-. “Lower bounds for bounded depth arithmetic circuits.” 2017. Doctoral Dissertation, Rutgers University. Accessed September 20, 2020. https://rucore.libraries.rutgers.edu/rutgers-lib/54175/.

MLA Handbook (7^{th} Edition):

Kumar, Mrinal, 1990-. “Lower bounds for bounded depth arithmetic circuits.” 2017. Web. 20 Sep 2020.

Vancouver:

Kumar, Mrinal 1. Lower bounds for bounded depth arithmetic circuits. [Internet] [Doctoral dissertation]. Rutgers University; 2017. [cited 2020 Sep 20]. Available from: https://rucore.libraries.rutgers.edu/rutgers-lib/54175/.

Council of Science Editors:

Kumar, Mrinal 1. Lower bounds for bounded depth arithmetic circuits. [Doctoral Dissertation]. Rutgers University; 2017. Available from: https://rucore.libraries.rutgers.edu/rutgers-lib/54175/

Michigan State University

2.
Naseem, Asif.
Implementation of parallel computational algorithms on a modified cordic *arithmetic* *logic* unit.

Degree: PhD, Department of Electrical Engineering and System, 1984, Michigan State University

URL: http://etd.lib.msu.edu/islandora/object/etd:24758

Subjects/Keywords: Algorithms; Computer arithmetic and logic units

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APA (6^{th} Edition):

Naseem, A. (1984). Implementation of parallel computational algorithms on a modified cordic arithmetic logic unit. (Doctoral Dissertation). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:24758

Chicago Manual of Style (16^{th} Edition):

Naseem, Asif. “Implementation of parallel computational algorithms on a modified cordic arithmetic logic unit.” 1984. Doctoral Dissertation, Michigan State University. Accessed September 20, 2020. http://etd.lib.msu.edu/islandora/object/etd:24758.

MLA Handbook (7^{th} Edition):

Naseem, Asif. “Implementation of parallel computational algorithms on a modified cordic arithmetic logic unit.” 1984. Web. 20 Sep 2020.

Vancouver:

Naseem A. Implementation of parallel computational algorithms on a modified cordic arithmetic logic unit. [Internet] [Doctoral dissertation]. Michigan State University; 1984. [cited 2020 Sep 20]. Available from: http://etd.lib.msu.edu/islandora/object/etd:24758.

Council of Science Editors:

Naseem A. Implementation of parallel computational algorithms on a modified cordic arithmetic logic unit. [Doctoral Dissertation]. Michigan State University; 1984. Available from: http://etd.lib.msu.edu/islandora/object/etd:24758

Michigan State University

3. Erdal, Abdullah Celik. Binary tree structures for matrix multiplication.

Degree: MS, Department of Electrical Engineering and Systems Science, 1983, Michigan State University

URL: http://etd.lib.msu.edu/islandora/object/etd:45492

Subjects/Keywords: Matrices; Computer arithmetic and logic units

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APA (6^{th} Edition):

Erdal, A. C. (1983). Binary tree structures for matrix multiplication. (Masters Thesis). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:45492

Chicago Manual of Style (16^{th} Edition):

Erdal, Abdullah Celik. “Binary tree structures for matrix multiplication.” 1983. Masters Thesis, Michigan State University. Accessed September 20, 2020. http://etd.lib.msu.edu/islandora/object/etd:45492.

MLA Handbook (7^{th} Edition):

Erdal, Abdullah Celik. “Binary tree structures for matrix multiplication.” 1983. Web. 20 Sep 2020.

Vancouver:

Erdal AC. Binary tree structures for matrix multiplication. [Internet] [Masters thesis]. Michigan State University; 1983. [cited 2020 Sep 20]. Available from: http://etd.lib.msu.edu/islandora/object/etd:45492.

Council of Science Editors:

Erdal AC. Binary tree structures for matrix multiplication. [Masters Thesis]. Michigan State University; 1983. Available from: http://etd.lib.msu.edu/islandora/object/etd:45492

University of Arizona

4. Stemple, Eugene Powers, 1939-. Development of a digital pseudorandom noise generator .

Degree: 1974, University of Arizona

URL: http://hdl.handle.net/10150/554733

Subjects/Keywords: Computer arithmetic and logic units.; Minicomputers.

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APA (6^{th} Edition):

Stemple, Eugene Powers, 1. (1974). Development of a digital pseudorandom noise generator . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/554733

Chicago Manual of Style (16^{th} Edition):

Stemple, Eugene Powers, 1939-. “Development of a digital pseudorandom noise generator .” 1974. Masters Thesis, University of Arizona. Accessed September 20, 2020. http://hdl.handle.net/10150/554733.

MLA Handbook (7^{th} Edition):

Stemple, Eugene Powers, 1939-. “Development of a digital pseudorandom noise generator .” 1974. Web. 20 Sep 2020.

Vancouver:

Stemple, Eugene Powers 1. Development of a digital pseudorandom noise generator . [Internet] [Masters thesis]. University of Arizona; 1974. [cited 2020 Sep 20]. Available from: http://hdl.handle.net/10150/554733.

Council of Science Editors:

Stemple, Eugene Powers 1. Development of a digital pseudorandom noise generator . [Masters Thesis]. University of Arizona; 1974. Available from: http://hdl.handle.net/10150/554733

Michigan State University

5.
Chang, Sin-Min.
The design of C-testable *arithmetic* * units*.

Degree: MS, Department of Electrical Engineering and Systems Science, 1988, Michigan State University

URL: http://etd.lib.msu.edu/islandora/object/etd:29622

Subjects/Keywords: Computer arithmetic and logic units; Logic circuits

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APA (6^{th} Edition):

Chang, S. (1988). The design of C-testable arithmetic units. (Masters Thesis). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:29622

Chicago Manual of Style (16^{th} Edition):

Chang, Sin-Min. “The design of C-testable arithmetic units.” 1988. Masters Thesis, Michigan State University. Accessed September 20, 2020. http://etd.lib.msu.edu/islandora/object/etd:29622.

MLA Handbook (7^{th} Edition):

Chang, Sin-Min. “The design of C-testable arithmetic units.” 1988. Web. 20 Sep 2020.

Vancouver:

Chang S. The design of C-testable arithmetic units. [Internet] [Masters thesis]. Michigan State University; 1988. [cited 2020 Sep 20]. Available from: http://etd.lib.msu.edu/islandora/object/etd:29622.

Council of Science Editors:

Chang S. The design of C-testable arithmetic units. [Masters Thesis]. Michigan State University; 1988. Available from: http://etd.lib.msu.edu/islandora/object/etd:29622

University of Arizona

6. Wiatrowski, Claude A. DESIGN OF A FLOATING-POINT PROCESSOR FOR DIGITAL SIMULATION .

Degree: 1973, University of Arizona

URL: http://hdl.handle.net/10150/288035

Subjects/Keywords: Computer arithmetic and logic units.; Computer storage devices.

Record Details Similar Records

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APA (6^{th} Edition):

Wiatrowski, C. A. (1973). DESIGN OF A FLOATING-POINT PROCESSOR FOR DIGITAL SIMULATION . (Doctoral Dissertation). University of Arizona. Retrieved from http://hdl.handle.net/10150/288035

Chicago Manual of Style (16^{th} Edition):

Wiatrowski, Claude A. “DESIGN OF A FLOATING-POINT PROCESSOR FOR DIGITAL SIMULATION .” 1973. Doctoral Dissertation, University of Arizona. Accessed September 20, 2020. http://hdl.handle.net/10150/288035.

MLA Handbook (7^{th} Edition):

Wiatrowski, Claude A. “DESIGN OF A FLOATING-POINT PROCESSOR FOR DIGITAL SIMULATION .” 1973. Web. 20 Sep 2020.

Vancouver:

Wiatrowski CA. DESIGN OF A FLOATING-POINT PROCESSOR FOR DIGITAL SIMULATION . [Internet] [Doctoral dissertation]. University of Arizona; 1973. [cited 2020 Sep 20]. Available from: http://hdl.handle.net/10150/288035.

Council of Science Editors:

Wiatrowski CA. DESIGN OF A FLOATING-POINT PROCESSOR FOR DIGITAL SIMULATION . [Doctoral Dissertation]. University of Arizona; 1973. Available from: http://hdl.handle.net/10150/288035

Kansas State University

7. Lin, Shu-Mei. Transformation of hierarchical structure in Warnier-Orr diagrams : examples and rules: Warnier-Orr diagrams.

Degree: 1982, Kansas State University

URL: http://hdl.handle.net/2097/9592

Subjects/Keywords: Computer programs; Computer arithmetic and logic units

Record Details Similar Records

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Lin, S. (1982). Transformation of hierarchical structure in Warnier-Orr diagrams : examples and rules: Warnier-Orr diagrams. (Thesis). Kansas State University. Retrieved from http://hdl.handle.net/2097/9592

Note: this citation may be lacking information needed for this citation format:

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Lin, Shu-Mei. “Transformation of hierarchical structure in Warnier-Orr diagrams : examples and rules: Warnier-Orr diagrams.” 1982. Thesis, Kansas State University. Accessed September 20, 2020. http://hdl.handle.net/2097/9592.

Note: this citation may be lacking information needed for this citation format:

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Lin, Shu-Mei. “Transformation of hierarchical structure in Warnier-Orr diagrams : examples and rules: Warnier-Orr diagrams.” 1982. Web. 20 Sep 2020.

Vancouver:

Lin S. Transformation of hierarchical structure in Warnier-Orr diagrams : examples and rules: Warnier-Orr diagrams. [Internet] [Thesis]. Kansas State University; 1982. [cited 2020 Sep 20]. Available from: http://hdl.handle.net/2097/9592.

Note: this citation may be lacking information needed for this citation format:

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin S. Transformation of hierarchical structure in Warnier-Orr diagrams : examples and rules: Warnier-Orr diagrams. [Thesis]. Kansas State University; 1982. Available from: http://hdl.handle.net/2097/9592

Not specified: Masters Thesis or Doctoral Dissertation

Kansas State University

8. Gilliland, Don A. Software operations manual of a computerized beef grading instrument.

Degree: 1982, Kansas State University

URL: http://hdl.handle.net/2097/12109

Subjects/Keywords: Beef – Grading; Computer arithmetic and logic units

Record Details Similar Records

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APA (6^{th} Edition):

Gilliland, D. A. (1982). Software operations manual of a computerized beef grading instrument. (Thesis). Kansas State University. Retrieved from http://hdl.handle.net/2097/12109

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Gilliland, Don A. “Software operations manual of a computerized beef grading instrument.” 1982. Thesis, Kansas State University. Accessed September 20, 2020. http://hdl.handle.net/2097/12109.

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Gilliland, Don A. “Software operations manual of a computerized beef grading instrument.” 1982. Web. 20 Sep 2020.

Vancouver:

Gilliland DA. Software operations manual of a computerized beef grading instrument. [Internet] [Thesis]. Kansas State University; 1982. [cited 2020 Sep 20]. Available from: http://hdl.handle.net/2097/12109.

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gilliland DA. Software operations manual of a computerized beef grading instrument. [Thesis]. Kansas State University; 1982. Available from: http://hdl.handle.net/2097/12109

Not specified: Masters Thesis or Doctoral Dissertation

Texas Tech University

9.
Hubbard, Charlie J.
A design of a ternary *arithmetic* *logic* unit.

Degree: 1979, Texas Tech University

URL: http://hdl.handle.net/2346/21860

► The digital industry is at the threshold of a new era in digital design. Current complementary metal oxide semiconductor, CMOS, Integrated Circuit Technology provides a…
(more)

Subjects/Keywords: Logic circuits; Many-valued logic; Switching theory; Computer arithmetic and logic units

Record Details Similar Records

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APA (6^{th} Edition):

Hubbard, C. J. (1979). A design of a ternary arithmetic logic unit. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/21860

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Hubbard, Charlie J. “A design of a ternary arithmetic logic unit.” 1979. Thesis, Texas Tech University. Accessed September 20, 2020. http://hdl.handle.net/2346/21860.

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Hubbard, Charlie J. “A design of a ternary arithmetic logic unit.” 1979. Web. 20 Sep 2020.

Vancouver:

Hubbard CJ. A design of a ternary arithmetic logic unit. [Internet] [Thesis]. Texas Tech University; 1979. [cited 2020 Sep 20]. Available from: http://hdl.handle.net/2346/21860.

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hubbard CJ. A design of a ternary arithmetic logic unit. [Thesis]. Texas Tech University; 1979. Available from: http://hdl.handle.net/2346/21860

Not specified: Masters Thesis or Doctoral Dissertation

Rutgers University

10.
Savulimedu Veeravalli, Varadan.
Diagnosis and error correction for a fault-tolerant *arithmetic* and *logic* unit for medical microprocessors.

Degree: MS, Electrical and Computer Engineering, 2008, Rutgers University

URL: http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17565

► We present a fault tolerant *Arithmetic* and *Logic* Unit (ALU) for medical systems. Real-time medical systems possess stringent requirements for fault tolerance because faulty hardware…
(more)

Subjects/Keywords: Computer arithmetic and logic units; Fault-tolerant computing; Microprocessors; Medicine – Data processing

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APA (6^{th} Edition):

Savulimedu Veeravalli, V. (2008). Diagnosis and error correction for a fault-tolerant arithmetic and logic unit for medical microprocessors. (Masters Thesis). Rutgers University. Retrieved from http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17565

Chicago Manual of Style (16^{th} Edition):

Savulimedu Veeravalli, Varadan. “Diagnosis and error correction for a fault-tolerant arithmetic and logic unit for medical microprocessors.” 2008. Masters Thesis, Rutgers University. Accessed September 20, 2020. http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17565.

MLA Handbook (7^{th} Edition):

Savulimedu Veeravalli, Varadan. “Diagnosis and error correction for a fault-tolerant arithmetic and logic unit for medical microprocessors.” 2008. Web. 20 Sep 2020.

Vancouver:

Savulimedu Veeravalli V. Diagnosis and error correction for a fault-tolerant arithmetic and logic unit for medical microprocessors. [Internet] [Masters thesis]. Rutgers University; 2008. [cited 2020 Sep 20]. Available from: http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17565.

Council of Science Editors:

Savulimedu Veeravalli V. Diagnosis and error correction for a fault-tolerant arithmetic and logic unit for medical microprocessors. [Masters Thesis]. Rutgers University; 2008. Available from: http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17565

Texas Tech University

11. Mula, Pavan R. Modular CMOS ALU control unit.

Degree: Electrical and Computer Engineering, 1999, Texas Tech University

URL: http://hdl.handle.net/2346/15747

► Modular based design is used for flexibility, simplicity and to lower the cost and labor in designing general purpose or application specific digital circuits. This…
(more)

Subjects/Keywords: Computer arithmetic and logic units; Metal oxide semiconductors; Complementary; Digital electronics; Modularity (Engineering)

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APA (6^{th} Edition):

Mula, P. R. (1999). Modular CMOS ALU control unit. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/15747

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Mula, Pavan R. “Modular CMOS ALU control unit.” 1999. Thesis, Texas Tech University. Accessed September 20, 2020. http://hdl.handle.net/2346/15747.

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Mula, Pavan R. “Modular CMOS ALU control unit.” 1999. Web. 20 Sep 2020.

Vancouver:

Mula PR. Modular CMOS ALU control unit. [Internet] [Thesis]. Texas Tech University; 1999. [cited 2020 Sep 20]. Available from: http://hdl.handle.net/2346/15747.

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mula PR. Modular CMOS ALU control unit. [Thesis]. Texas Tech University; 1999. Available from: http://hdl.handle.net/2346/15747

Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

12.
Tsai, Ming-Yu.
An Efficient Hybrid CMOS/PTL (Pass-Transistor-*Logic*) Synthesizer and Its Applications to the Design of *Arithmetic* *Units* and 3D Graphics Processors.

Degree: PhD, Computer Science and Engineering, 2009, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529

► The mainstream of current VLSI design and *logic* synthesis is based on traditional CMOS *logic* circuits. However, in the past two decades, various new *logic*…
(more)

Subjects/Keywords: 3D Graphics Processors; Arithmetic Units; Standard Cell Library; ASIC Cell-Based Design Flow; Logic Synthesizer; Pass-Transistor-Logic (PTL); CMOS logic

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Tsai, M. (2009). An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529

Chicago Manual of Style (16^{th} Edition):

Tsai, Ming-Yu. “An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors.” 2009. Doctoral Dissertation, NSYSU. Accessed September 20, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529.

MLA Handbook (7^{th} Edition):

Tsai, Ming-Yu. “An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors.” 2009. Web. 20 Sep 2020.

Vancouver:

Tsai M. An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors. [Internet] [Doctoral dissertation]. NSYSU; 2009. [cited 2020 Sep 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529.

Council of Science Editors:

Tsai M. An Efficient Hybrid CMOS/PTL (Pass-Transistor-Logic) Synthesizer and Its Applications to the Design of Arithmetic Units and 3D Graphics Processors. [Doctoral Dissertation]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1020109-194529

Michigan State University

13. Tseng, Yeong-Jeng. A floating-point inner product step processor for use in a VLSI Systolic array.

Degree: MS, Department of Electrical Engineering and Systems Science, 1983, Michigan State University

URL: http://etd.lib.msu.edu/islandora/object/etd:19061

Subjects/Keywords: Electronic digital computers – Circuits; Computer arithmetic and logic units; Floating-point arithmetic; Integrated circuits – Very large scale integration

Record Details Similar Records

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Tseng, Y. (1983). A floating-point inner product step processor for use in a VLSI Systolic array. (Masters Thesis). Michigan State University. Retrieved from http://etd.lib.msu.edu/islandora/object/etd:19061

Chicago Manual of Style (16^{th} Edition):

Tseng, Yeong-Jeng. “A floating-point inner product step processor for use in a VLSI Systolic array.” 1983. Masters Thesis, Michigan State University. Accessed September 20, 2020. http://etd.lib.msu.edu/islandora/object/etd:19061.

MLA Handbook (7^{th} Edition):

Tseng, Yeong-Jeng. “A floating-point inner product step processor for use in a VLSI Systolic array.” 1983. Web. 20 Sep 2020.

Vancouver:

Tseng Y. A floating-point inner product step processor for use in a VLSI Systolic array. [Internet] [Masters thesis]. Michigan State University; 1983. [cited 2020 Sep 20]. Available from: http://etd.lib.msu.edu/islandora/object/etd:19061.

Council of Science Editors:

Tseng Y. A floating-point inner product step processor for use in a VLSI Systolic array. [Masters Thesis]. Michigan State University; 1983. Available from: http://etd.lib.msu.edu/islandora/object/etd:19061

RMIT University

14.
Kim, M.
Null convention *logic* circuits for asynchronous *computer* architecture.

Degree: 2019, RMIT University

URL: http://researchbank.rmit.edu.au/view/rmit:163013

► For most of its history, *computer* architecture has been able to benefit from a rapid scaling in semiconductor technology, resulting in continuous improvements to CPU…
(more)

Subjects/Keywords: Fields of Research; null convention logic; asynchronous; computer architecture; RISC-V; arithmetic logic unit

Record Details Similar Records

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APA (6^{th} Edition):

Kim, M. (2019). Null convention logic circuits for asynchronous computer architecture. (Thesis). RMIT University. Retrieved from http://researchbank.rmit.edu.au/view/rmit:163013

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Kim, M. “Null convention logic circuits for asynchronous computer architecture.” 2019. Thesis, RMIT University. Accessed September 20, 2020. http://researchbank.rmit.edu.au/view/rmit:163013.

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Kim, M. “Null convention logic circuits for asynchronous computer architecture.” 2019. Web. 20 Sep 2020.

Vancouver:

Kim M. Null convention logic circuits for asynchronous computer architecture. [Internet] [Thesis]. RMIT University; 2019. [cited 2020 Sep 20]. Available from: http://researchbank.rmit.edu.au/view/rmit:163013.

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim M. Null convention logic circuits for asynchronous computer architecture. [Thesis]. RMIT University; 2019. Available from: http://researchbank.rmit.edu.au/view/rmit:163013

Not specified: Masters Thesis or Doctoral Dissertation

Nanyang Technological University

15. Xu, Simin. Efficient polynomial evaluation algorithm and implementation on FPGA .

Degree: 2013, Nanyang Technological University

URL: http://hdl.handle.net/10356/54869

► In this thesis, an optimized polynomial evaluation algorithm is presented. Compared to Horner's Rule which has the least number of computation steps but longest latency,…
(more)

Subjects/Keywords: DRNTU::Engineering::Computer science and engineering::Hardware::Arithmetic and logic structures

Record Details Similar Records

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Xu, S. (2013). Efficient polynomial evaluation algorithm and implementation on FPGA . (Thesis). Nanyang Technological University. Retrieved from http://hdl.handle.net/10356/54869

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Xu, Simin. “Efficient polynomial evaluation algorithm and implementation on FPGA .” 2013. Thesis, Nanyang Technological University. Accessed September 20, 2020. http://hdl.handle.net/10356/54869.

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Xu, Simin. “Efficient polynomial evaluation algorithm and implementation on FPGA .” 2013. Web. 20 Sep 2020.

Vancouver:

Xu S. Efficient polynomial evaluation algorithm and implementation on FPGA . [Internet] [Thesis]. Nanyang Technological University; 2013. [cited 2020 Sep 20]. Available from: http://hdl.handle.net/10356/54869.

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xu S. Efficient polynomial evaluation algorithm and implementation on FPGA . [Thesis]. Nanyang Technological University; 2013. Available from: http://hdl.handle.net/10356/54869

Not specified: Masters Thesis or Doctoral Dissertation

16. Sassi, André Berti. Projeto de uma ULA de inteiros e de baixo consumo em tecnologia CMOS.

Degree: Mestrado, Telecomunicações, 2013, University of São Paulo

URL: http://www.teses.usp.br/teses/disponiveis/18/18155/tde-26082013-133826/ ;

►

A redução no consumo de potência em circuitos eletrônicos tem se tornado um dos requisitos mais importantes em projetos, especialmente com o recente aumento no… (more)

Subjects/Keywords: Arithmetic and logic units; Circuitos integrados; CMOS; CMOS; Consumo de potência; Integrated circuits; Power consumption; Unidades lógico-aritméticas

Record Details Similar Records

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APA (6^{th} Edition):

Sassi, A. B. (2013). Projeto de uma ULA de inteiros e de baixo consumo em tecnologia CMOS. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/18/18155/tde-26082013-133826/ ;

Chicago Manual of Style (16^{th} Edition):

Sassi, André Berti. “Projeto de uma ULA de inteiros e de baixo consumo em tecnologia CMOS.” 2013. Masters Thesis, University of São Paulo. Accessed September 20, 2020. http://www.teses.usp.br/teses/disponiveis/18/18155/tde-26082013-133826/ ;.

MLA Handbook (7^{th} Edition):

Sassi, André Berti. “Projeto de uma ULA de inteiros e de baixo consumo em tecnologia CMOS.” 2013. Web. 20 Sep 2020.

Vancouver:

Sassi AB. Projeto de uma ULA de inteiros e de baixo consumo em tecnologia CMOS. [Internet] [Masters thesis]. University of São Paulo; 2013. [cited 2020 Sep 20]. Available from: http://www.teses.usp.br/teses/disponiveis/18/18155/tde-26082013-133826/ ;.

Council of Science Editors:

Sassi AB. Projeto de uma ULA de inteiros e de baixo consumo em tecnologia CMOS. [Masters Thesis]. University of São Paulo; 2013. Available from: http://www.teses.usp.br/teses/disponiveis/18/18155/tde-26082013-133826/ ;

Texas A&M University

17.
Burgess, Bradley Gene.
A carry-save datapath for high-speed * arithmetic*.

Degree: MS, electrical engineering, 2012, Texas A&M University

URL: http://hdl.handle.net/1969.1/ETD-TAMU-1986-THESIS-B955

Subjects/Keywords: electrical engineering.; Major electrical engineering.; Computer arithmetic and logic units - Design and construction.; Electronic digital computers - Design and construction.

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APA (6^{th} Edition):

Burgess, B. G. (2012). A carry-save datapath for high-speed arithmetic. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-1986-THESIS-B955

Chicago Manual of Style (16^{th} Edition):

Burgess, Bradley Gene. “A carry-save datapath for high-speed arithmetic.” 2012. Masters Thesis, Texas A&M University. Accessed September 20, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-1986-THESIS-B955.

MLA Handbook (7^{th} Edition):

Burgess, Bradley Gene. “A carry-save datapath for high-speed arithmetic.” 2012. Web. 20 Sep 2020.

Vancouver:

Burgess BG. A carry-save datapath for high-speed arithmetic. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Sep 20]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1986-THESIS-B955.

Council of Science Editors:

Burgess BG. A carry-save datapath for high-speed arithmetic. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-1986-THESIS-B955

University of Oklahoma

18. Wang, Guoping. A high-performance inner-product processor for real and complex numbers.

Degree: PhD, School of Electrical and Computer Engineering, 2003, University of Oklahoma

URL: http://hdl.handle.net/11244/1168

► A novel, high-performance fixed-point inner-product processor based on a redundant binary number system is investigated in this dissertation. This scheme decreases the number of partial…
(more)

Subjects/Keywords: Signal processing Digital techniques.; Engineering, Electronics and Electrical.; Computer arithmetic and logic units.; Integrated circuits Very large scale integration.

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APA (6^{th} Edition):

Wang, G. (2003). A high-performance inner-product processor for real and complex numbers. (Doctoral Dissertation). University of Oklahoma. Retrieved from http://hdl.handle.net/11244/1168

Chicago Manual of Style (16^{th} Edition):

Wang, Guoping. “A high-performance inner-product processor for real and complex numbers.” 2003. Doctoral Dissertation, University of Oklahoma. Accessed September 20, 2020. http://hdl.handle.net/11244/1168.

MLA Handbook (7^{th} Edition):

Wang, Guoping. “A high-performance inner-product processor for real and complex numbers.” 2003. Web. 20 Sep 2020.

Vancouver:

Wang G. A high-performance inner-product processor for real and complex numbers. [Internet] [Doctoral dissertation]. University of Oklahoma; 2003. [cited 2020 Sep 20]. Available from: http://hdl.handle.net/11244/1168.

Council of Science Editors:

Wang G. A high-performance inner-product processor for real and complex numbers. [Doctoral Dissertation]. University of Oklahoma; 2003. Available from: http://hdl.handle.net/11244/1168

University of Florida

19. Yin, Yue, 1976- ( Dissertant ). Models of computation for performance estimation in a parallel image processing system.

Degree: M.S, Computer and Information Science and Engineering, 2000, University of Florida

URL: https://ufdc.ufl.edu/UF00100759

► Image and signal processing applications usually require high computational power. One common approach is to partition image data across several processors, and then to process…
(more)

Subjects/Keywords: Algorithms; Architectural models; Arithmetic logic units; Bandwidth; Buffer storage; Computer memory; Input output; Modeling; Multilevel models; Simulations; Image processing – Computer programs; Parallel processing (Electronic computers)

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APA (6^{th} Edition):

Yin, Yue, 1. (. D. ). (2000). Models of computation for performance estimation in a parallel image processing system. (Masters Thesis). University of Florida. Retrieved from https://ufdc.ufl.edu/UF00100759

Chicago Manual of Style (16^{th} Edition):

Yin, Yue, 1976- ( Dissertant ). “Models of computation for performance estimation in a parallel image processing system.” 2000. Masters Thesis, University of Florida. Accessed September 20, 2020. https://ufdc.ufl.edu/UF00100759.

MLA Handbook (7^{th} Edition):

Yin, Yue, 1976- ( Dissertant ). “Models of computation for performance estimation in a parallel image processing system.” 2000. Web. 20 Sep 2020.

Vancouver:

Yin, Yue 1(D). Models of computation for performance estimation in a parallel image processing system. [Internet] [Masters thesis]. University of Florida; 2000. [cited 2020 Sep 20]. Available from: https://ufdc.ufl.edu/UF00100759.

Council of Science Editors:

Yin, Yue 1(D). Models of computation for performance estimation in a parallel image processing system. [Masters Thesis]. University of Florida; 2000. Available from: https://ufdc.ufl.edu/UF00100759

University of California – Berkeley

20. Haken, Ian Robert. Randomizing Reals and the First-Order Consequences of Randoms.

Degree: Mathematics, 2014, University of California – Berkeley

URL: http://www.escholarship.org/uc/item/1pj1b1vk

► In this dissertation we investigate two questions in the *subject* of algorithmic randomness. The first question we address is "Given a real, is there a…
(more)

Subjects/Keywords: Mathematics; Arithmetic; Logic; Measures; Randomness

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APA (6^{th} Edition):

Haken, I. R. (2014). Randomizing Reals and the First-Order Consequences of Randoms. (Thesis). University of California – Berkeley. Retrieved from http://www.escholarship.org/uc/item/1pj1b1vk

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Haken, Ian Robert. “Randomizing Reals and the First-Order Consequences of Randoms.” 2014. Thesis, University of California – Berkeley. Accessed September 20, 2020. http://www.escholarship.org/uc/item/1pj1b1vk.

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Haken, Ian Robert. “Randomizing Reals and the First-Order Consequences of Randoms.” 2014. Web. 20 Sep 2020.

Vancouver:

Haken IR. Randomizing Reals and the First-Order Consequences of Randoms. [Internet] [Thesis]. University of California – Berkeley; 2014. [cited 2020 Sep 20]. Available from: http://www.escholarship.org/uc/item/1pj1b1vk.

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Haken IR. Randomizing Reals and the First-Order Consequences of Randoms. [Thesis]. University of California – Berkeley; 2014. Available from: http://www.escholarship.org/uc/item/1pj1b1vk

Not specified: Masters Thesis or Doctoral Dissertation

21.
Huang, Walter.
Implementation of adaptive digital FIR and reprogrammable mixed-signal filters using distributed * arithmetic*.

Degree: PhD, Electrical and Computer Engineering, 2009, Georgia Tech

URL: http://hdl.handle.net/1853/31653

► When computational resources are limited, especially multipliers, distributed *arithmetic* (DA) is used in lieu of the typical multiplier-based filtering structures. However, DA is not well…
(more)

Subjects/Keywords: Mixed-signal implementations; Reprogrammable; Distributed arithmetic; Adaptive filtering implementations; Adaptive filters; Signal processing Digital techniques Mathematics; Adaptive signal processing; Computer arithmetic and logic units; Computer algorithms

…samples among multiple *units*. . . . . . . . . . . . . . . . . . . . . . 30
Figure 3.1
MATLAB… …the number of *logic* elements of CDA versus a traditional multiply-and-accumulate based… …architecture. . . . . . . . . . . . 39
Figure 3.5
*Logic* element efficiency comparison of CDA versus… …diagram for the proposed second-order section implementation using distributed *arithmetic*… …distributed *arithmetic*
(DA) is used in lieu of the typical multiplier-based filtering…

Record Details Similar Records

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Huang, W. (2009). Implementation of adaptive digital FIR and reprogrammable mixed-signal filters using distributed arithmetic. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/31653

Chicago Manual of Style (16^{th} Edition):

Huang, Walter. “Implementation of adaptive digital FIR and reprogrammable mixed-signal filters using distributed arithmetic.” 2009. Doctoral Dissertation, Georgia Tech. Accessed September 20, 2020. http://hdl.handle.net/1853/31653.

MLA Handbook (7^{th} Edition):

Huang, Walter. “Implementation of adaptive digital FIR and reprogrammable mixed-signal filters using distributed arithmetic.” 2009. Web. 20 Sep 2020.

Vancouver:

Huang W. Implementation of adaptive digital FIR and reprogrammable mixed-signal filters using distributed arithmetic. [Internet] [Doctoral dissertation]. Georgia Tech; 2009. [cited 2020 Sep 20]. Available from: http://hdl.handle.net/1853/31653.

Council of Science Editors:

Huang W. Implementation of adaptive digital FIR and reprogrammable mixed-signal filters using distributed arithmetic. [Doctoral Dissertation]. Georgia Tech; 2009. Available from: http://hdl.handle.net/1853/31653

University of Michigan

22. Chen, Te-Hsuan. Designing Accurate and Low-Cost Stochastic Circuits.

Degree: PhD, Computer Science and Engineering, 2016, University of Michigan

URL: http://hdl.handle.net/2027.42/133255

► Stochastic computing (SC) is an unconventional computing approach that processes data represented by pseudo-random bit-streams called stochastic numbers (SNs). It enables *arithmetic* functions to be…
(more)

Subjects/Keywords: Stochastic computing; Approximate computing; Logic synthesis and optimization; Stochastic circuit design; Computer arithmetic; Computer Science; Engineering

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APA (6^{th} Edition):

Chen, T. (2016). Designing Accurate and Low-Cost Stochastic Circuits. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/133255

Chicago Manual of Style (16^{th} Edition):

Chen, Te-Hsuan. “Designing Accurate and Low-Cost Stochastic Circuits.” 2016. Doctoral Dissertation, University of Michigan. Accessed September 20, 2020. http://hdl.handle.net/2027.42/133255.

MLA Handbook (7^{th} Edition):

Chen, Te-Hsuan. “Designing Accurate and Low-Cost Stochastic Circuits.” 2016. Web. 20 Sep 2020.

Vancouver:

Chen T. Designing Accurate and Low-Cost Stochastic Circuits. [Internet] [Doctoral dissertation]. University of Michigan; 2016. [cited 2020 Sep 20]. Available from: http://hdl.handle.net/2027.42/133255.

Council of Science Editors:

Chen T. Designing Accurate and Low-Cost Stochastic Circuits. [Doctoral Dissertation]. University of Michigan; 2016. Available from: http://hdl.handle.net/2027.42/133255

University of Stirling

23. Ireland, Andrew. Mechanization of program construction in Martin-Löf's Theory of Types.

Degree: PhD, 1989, University of Stirling

URL: http://hdl.handle.net/1893/29578

► The constructive approach to the problem of program correctness dates to the late 1960's. During the early 1970's interest developed in the application of constructive…
(more)

Subjects/Keywords: 005; Computer programming; Computer science – Mathematics; Computer arithmetic and logic unit

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APA (6^{th} Edition):

Ireland, A. (1989). Mechanization of program construction in Martin-Löf's Theory of Types. (Doctoral Dissertation). University of Stirling. Retrieved from http://hdl.handle.net/1893/29578

Chicago Manual of Style (16^{th} Edition):

Ireland, Andrew. “Mechanization of program construction in Martin-Löf's Theory of Types.” 1989. Doctoral Dissertation, University of Stirling. Accessed September 20, 2020. http://hdl.handle.net/1893/29578.

MLA Handbook (7^{th} Edition):

Ireland, Andrew. “Mechanization of program construction in Martin-Löf's Theory of Types.” 1989. Web. 20 Sep 2020.

Vancouver:

Ireland A. Mechanization of program construction in Martin-Löf's Theory of Types. [Internet] [Doctoral dissertation]. University of Stirling; 1989. [cited 2020 Sep 20]. Available from: http://hdl.handle.net/1893/29578.

Council of Science Editors:

Ireland A. Mechanization of program construction in Martin-Löf's Theory of Types. [Doctoral Dissertation]. University of Stirling; 1989. Available from: http://hdl.handle.net/1893/29578

University of Alberta

24.
Tedder, Andrew J.
Paraconsistent *Logic* for Dialethic Arithmetics.

Degree: MA, Department of Philosophy, 2014, University of Alberta

URL: https://era.library.ualberta.ca/files/gb19f6175

► Inconsistent and collapse models of *arithmetic* are presented in the language and semantics of the simple paraconsistent *logic* LP. I present a *logic* which extends…
(more)

Subjects/Keywords: Non-standard Models of Arithmetic; Paraconsistent Logic; Logic

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APA (6^{th} Edition):

Tedder, A. J. (2014). Paraconsistent Logic for Dialethic Arithmetics. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/gb19f6175

Chicago Manual of Style (16^{th} Edition):

Tedder, Andrew J. “Paraconsistent Logic for Dialethic Arithmetics.” 2014. Masters Thesis, University of Alberta. Accessed September 20, 2020. https://era.library.ualberta.ca/files/gb19f6175.

MLA Handbook (7^{th} Edition):

Tedder, Andrew J. “Paraconsistent Logic for Dialethic Arithmetics.” 2014. Web. 20 Sep 2020.

Vancouver:

Tedder AJ. Paraconsistent Logic for Dialethic Arithmetics. [Internet] [Masters thesis]. University of Alberta; 2014. [cited 2020 Sep 20]. Available from: https://era.library.ualberta.ca/files/gb19f6175.

Council of Science Editors:

Tedder AJ. Paraconsistent Logic for Dialethic Arithmetics. [Masters Thesis]. University of Alberta; 2014. Available from: https://era.library.ualberta.ca/files/gb19f6175

Nanyang Technological University

25. Sharad Sinha. Intelligent high level synthesis for customization on reconfigurable platforms .

Degree: 2014, Nanyang Technological University

URL: http://hdl.handle.net/10356/61691

► High level synthesis (HLS) using C/C++ has increasingly become a critical step in the realization of complex digital systems. One of the major research focus…
(more)

Subjects/Keywords: DRNTU::Engineering::Computer science and engineering::Hardware::Arithmetic and logic structures; DRNTU::Engineering::Computer science and engineering::Hardware::Register-transfer-level implementation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Sinha, S. (2014). Intelligent high level synthesis for customization on reconfigurable platforms . (Thesis). Nanyang Technological University. Retrieved from http://hdl.handle.net/10356/61691

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Sinha, Sharad. “Intelligent high level synthesis for customization on reconfigurable platforms .” 2014. Thesis, Nanyang Technological University. Accessed September 20, 2020. http://hdl.handle.net/10356/61691.

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Sinha, Sharad. “Intelligent high level synthesis for customization on reconfigurable platforms .” 2014. Web. 20 Sep 2020.

Vancouver:

Sinha S. Intelligent high level synthesis for customization on reconfigurable platforms . [Internet] [Thesis]. Nanyang Technological University; 2014. [cited 2020 Sep 20]. Available from: http://hdl.handle.net/10356/61691.

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sinha S. Intelligent high level synthesis for customization on reconfigurable platforms . [Thesis]. Nanyang Technological University; 2014. Available from: http://hdl.handle.net/10356/61691

Not specified: Masters Thesis or Doctoral Dissertation

26.
Ratan, Amrita.
Hardware Modules for Safe Integer and Floating-Point
* Arithmetic*.

Degree: MS, Engineering and Applied Science: Computer Engineering, 2013, University of Cincinnati

URL: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1383812316

► Integer and floating-point data types are widely used to represent numerical data in *computer* *arithmetic*. Since the range of values representable in a *computer* are…
(more)

Subjects/Keywords: Computer Engineering; computer arithmetic; integer overflows; floating-point overflows; arithmetic and logic unit; floating-point unit

…*arithmetic* is a well-established area of research and *arithmetic* *units* are of utmost
importance to… …emergence of new
technologies, research in the area of *computer* *arithmetic* has also been evolving… …the *computer* *arithmetic*
domain [32]. Some of the important topics in this area are… …floating-point data. We present our hardware *logic* design of an *Arithmetic* and *Logic* Unit (… …*arithmetic* exceptions on the accuracy of *computer* *arithmetic* and the previous
work done in this…

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Ratan, A. (2013). Hardware Modules for Safe Integer and Floating-Point Arithmetic. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1383812316

Chicago Manual of Style (16^{th} Edition):

Ratan, Amrita. “Hardware Modules for Safe Integer and Floating-Point Arithmetic.” 2013. Masters Thesis, University of Cincinnati. Accessed September 20, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1383812316.

MLA Handbook (7^{th} Edition):

Ratan, Amrita. “Hardware Modules for Safe Integer and Floating-Point Arithmetic.” 2013. Web. 20 Sep 2020.

Vancouver:

Ratan A. Hardware Modules for Safe Integer and Floating-Point Arithmetic. [Internet] [Masters thesis]. University of Cincinnati; 2013. [cited 2020 Sep 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1383812316.

Council of Science Editors:

Ratan A. Hardware Modules for Safe Integer and Floating-Point Arithmetic. [Masters Thesis]. University of Cincinnati; 2013. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1383812316

Nanyang Technological University

27. Faust, Mathias. Design methodologies for complexity reduction of FIR filters .

Degree: 2014, Nanyang Technological University

URL: http://hdl.handle.net/10356/61746

► Digital signal processing is ubiquitous and many new applications have been developed for portable wireless communication devices due to the demand for connectivity. Versatile applications…
(more)

Subjects/Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic systems::Signal processing; DRNTU::Engineering::Computer science and engineering::Hardware::Arithmetic and logic structures; DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Faust, M. (2014). Design methodologies for complexity reduction of FIR filters . (Thesis). Nanyang Technological University. Retrieved from http://hdl.handle.net/10356/61746

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Faust, Mathias. “Design methodologies for complexity reduction of FIR filters .” 2014. Thesis, Nanyang Technological University. Accessed September 20, 2020. http://hdl.handle.net/10356/61746.

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Faust, Mathias. “Design methodologies for complexity reduction of FIR filters .” 2014. Web. 20 Sep 2020.

Vancouver:

Faust M. Design methodologies for complexity reduction of FIR filters . [Internet] [Thesis]. Nanyang Technological University; 2014. [cited 2020 Sep 20]. Available from: http://hdl.handle.net/10356/61746.

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Faust M. Design methodologies for complexity reduction of FIR filters . [Thesis]. Nanyang Technological University; 2014. Available from: http://hdl.handle.net/10356/61746

Not specified: Masters Thesis or Doctoral Dissertation

Rochester Institute of Technology

28. Levitan, Sabrina Rose. Investigation of the Benefits of Interlocked Synchronous Pipelines.

Degree: MS, Electrical Engineering, 2019, Rochester Institute of Technology

URL: https://scholarworks.rit.edu/theses/10068

► The majority of today’s digital circuits use synchronous pipelines. As the technology nodes get smaller, these pipelines are facing problems with area, power, and…
(more)

Subjects/Keywords: asynchronous circuits; CMOS logic circuits; current-mode logic; low-power electronics; pipeline arithmetic; Pipelines

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Levitan, S. R. (2019). Investigation of the Benefits of Interlocked Synchronous Pipelines. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/10068

Chicago Manual of Style (16^{th} Edition):

Levitan, Sabrina Rose. “Investigation of the Benefits of Interlocked Synchronous Pipelines.” 2019. Masters Thesis, Rochester Institute of Technology. Accessed September 20, 2020. https://scholarworks.rit.edu/theses/10068.

MLA Handbook (7^{th} Edition):

Levitan, Sabrina Rose. “Investigation of the Benefits of Interlocked Synchronous Pipelines.” 2019. Web. 20 Sep 2020.

Vancouver:

Levitan SR. Investigation of the Benefits of Interlocked Synchronous Pipelines. [Internet] [Masters thesis]. Rochester Institute of Technology; 2019. [cited 2020 Sep 20]. Available from: https://scholarworks.rit.edu/theses/10068.

Council of Science Editors:

Levitan SR. Investigation of the Benefits of Interlocked Synchronous Pipelines. [Masters Thesis]. Rochester Institute of Technology; 2019. Available from: https://scholarworks.rit.edu/theses/10068

Nanyang Technological University

29. Suchitra Sathyanarayana. Detection of road markings for advanced driver assistance .

Degree: 2013, Nanyang Technological University

URL: http://hdl.handle.net/10356/54995

► Automatic detection of road markings will enhance the capabilities of Advanced Driver Assistance Systems (ADAS) as road markings denote vital information pertaining to traffic safety…
(more)

Subjects/Keywords: DRNTU::Engineering::Computer science and engineering::Computing methodologies::Image processing and computer vision; DRNTU::Engineering::Computer science and engineering::Hardware::Arithmetic and logic structures; DRNTU::Engineering::Computer science and engineering::Computer systems organization::Special-purpose and application-based systems

Record Details Similar Records

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^{th} Edition):

Sathyanarayana, S. (2013). Detection of road markings for advanced driver assistance . (Thesis). Nanyang Technological University. Retrieved from http://hdl.handle.net/10356/54995

Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^{th} Edition):

Sathyanarayana, Suchitra. “Detection of road markings for advanced driver assistance .” 2013. Thesis, Nanyang Technological University. Accessed September 20, 2020. http://hdl.handle.net/10356/54995.

Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^{th} Edition):

Sathyanarayana, Suchitra. “Detection of road markings for advanced driver assistance .” 2013. Web. 20 Sep 2020.

Vancouver:

Sathyanarayana S. Detection of road markings for advanced driver assistance . [Internet] [Thesis]. Nanyang Technological University; 2013. [cited 2020 Sep 20]. Available from: http://hdl.handle.net/10356/54995.

Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sathyanarayana S. Detection of road markings for advanced driver assistance . [Thesis]. Nanyang Technological University; 2013. Available from: http://hdl.handle.net/10356/54995

Not specified: Masters Thesis or Doctoral Dissertation

University of Cambridge

30.
Wrigley, Wesley Duncan.
Axiomatization and Incompleteness in *Arithmetic* and Set Theory.

Degree: PhD, 2019, University of Cambridge

URL: https://www.repository.cam.ac.uk/handle/1810/298096

► Axiomatization and Incompleteness in *Arithmetic* and Set Theory Wesley Duncan Wrigley I argue that are (at least) two distinct kinds of mathematical incompleteness. Part A…
(more)

Subjects/Keywords: Philosophy of Mathematics; Logic; Gödel; Reflection Principles; Incompleteness; Arithmetic; Set Theory

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APA (6^{th} Edition):

Wrigley, W. D. (2019). Axiomatization and Incompleteness in Arithmetic and Set Theory. (Doctoral Dissertation). University of Cambridge. Retrieved from https://www.repository.cam.ac.uk/handle/1810/298096

Chicago Manual of Style (16^{th} Edition):

Wrigley, Wesley Duncan. “Axiomatization and Incompleteness in Arithmetic and Set Theory.” 2019. Doctoral Dissertation, University of Cambridge. Accessed September 20, 2020. https://www.repository.cam.ac.uk/handle/1810/298096.

MLA Handbook (7^{th} Edition):

Wrigley, Wesley Duncan. “Axiomatization and Incompleteness in Arithmetic and Set Theory.” 2019. Web. 20 Sep 2020.

Vancouver:

Wrigley WD. Axiomatization and Incompleteness in Arithmetic and Set Theory. [Internet] [Doctoral dissertation]. University of Cambridge; 2019. [cited 2020 Sep 20]. Available from: https://www.repository.cam.ac.uk/handle/1810/298096.

Council of Science Editors:

Wrigley WD. Axiomatization and Incompleteness in Arithmetic and Set Theory. [Doctoral Dissertation]. University of Cambridge; 2019. Available from: https://www.repository.cam.ac.uk/handle/1810/298096