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Dates: 2004 – 2008 University: Indian Institute of Science  

You searched for subject:(Computer Science). Showing records 1 – 30 of 90 total matches.

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Indian Institute of Science

1. Shyam, K. Power-Aware Compilation Techniques For Embedded Systems.

Degree: 2006, Indian Institute of Science

 The demand for devices like Personal Digital Assistants (PDA’s), Laptops, Smart Mobile Phones, are at an all time high. As the demand for these devices… (more)

Subjects/Keywords: Electric Power Control; Compilers; Embedded Systems; Computer Memory Architecture; Voltages; Dynamic Voltage Scaling; Memory Architectures; Integer Linear Programming (ILP); Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shyam, K. (2006). Power-Aware Compilation Techniques For Embedded Systems. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/348

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shyam, K. “Power-Aware Compilation Techniques For Embedded Systems.” 2006. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/348.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shyam, K. “Power-Aware Compilation Techniques For Embedded Systems.” 2006. Web. 19 Jan 2019.

Vancouver:

Shyam K. Power-Aware Compilation Techniques For Embedded Systems. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/348.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shyam K. Power-Aware Compilation Techniques For Embedded Systems. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/348

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

2. Bharath Kumar, M. Discovering Roles In The Evolution Of Collaboration Networks.

Degree: 2006, Indian Institute of Science

 Searching the Web involves more than sifting through a huge graph of pages and hyperlinks. Specific collaboration networks have emerged that serve domain-specific queries better… (more)

Subjects/Keywords: Computer Network; Data Mining; Nurturers; Collaboration Networks; Collaborative Filtering; Recommender Systems; Social Network Analysis; Scouts; Promoters; Connectors; Computer Science

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APA (6th Edition):

Bharath Kumar, M. (2006). Discovering Roles In The Evolution Of Collaboration Networks. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/446

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bharath Kumar, M. “Discovering Roles In The Evolution Of Collaboration Networks.” 2006. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/446.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bharath Kumar, M. “Discovering Roles In The Evolution Of Collaboration Networks.” 2006. Web. 19 Jan 2019.

Vancouver:

Bharath Kumar M. Discovering Roles In The Evolution Of Collaboration Networks. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/446.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bharath Kumar M. Discovering Roles In The Evolution Of Collaboration Networks. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/446

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

3. Roy, Sharmili. Pricing Network Resources : A New Perspective.

Degree: 2006, Indian Institute of Science

 The aim of the work is to examine the issue of pricing network resources so as to ensure fair and efficient resource-sharing among users. The… (more)

Subjects/Keywords: Computer Networks; Internet-Pricing; Network Resources - Pricing; Network - Pricing Strategy; Resource Pricing; Pricing Network Resources; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Roy, S. (2006). Pricing Network Resources : A New Perspective. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1081

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Roy, Sharmili. “Pricing Network Resources : A New Perspective.” 2006. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/1081.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Roy, Sharmili. “Pricing Network Resources : A New Perspective.” 2006. Web. 19 Jan 2019.

Vancouver:

Roy S. Pricing Network Resources : A New Perspective. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/1081.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Roy S. Pricing Network Resources : A New Perspective. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/1081

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

4. Vivekanandham, Rajesh. Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors.

Degree: 2006, Indian Institute of Science

 A Large instruction window is a key requirement to exploit greater Instruction Level Parallelism in out-of-order superscalar processors. Along with the instruction window size, the… (more)

Subjects/Keywords: Parallel Processing (Computer Science); Queing Processes; Queue Design; Scalable Low Power Issue Queue (SLIQ) Microarchitecture; Scalable Low Power Store Queue (SLSQ) Microarchitecture; Superscalar Processors; Large Instruction Window; Computer Science

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APA (6th Edition):

Vivekanandham, R. (2006). Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/413

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vivekanandham, Rajesh. “Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors.” 2006. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/413.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vivekanandham, Rajesh. “Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors.” 2006. Web. 19 Jan 2019.

Vancouver:

Vivekanandham R. Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/413.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vivekanandham R. Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/413

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

5. Rao, M V Panduranga. Bounds On Augmented Automata And Quantum Adiabatic Optimization.

Degree: 2007, Indian Institute of Science

 Quantum computing has generated a lot of interested in the past two decades. Research into powerful models of quantum computation has yielded important and elegant… (more)

Subjects/Keywords: Quantum Theory; Computer Science - Quantum Theory; Quantum Computing; Quantum Computing - Interference; Quantum Adiabatic Algorithms; Quantum Finite Automata; Quantum Adiabatic Optimization; Bounds; Computer Science

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APA (6th Edition):

Rao, M. V. P. (2007). Bounds On Augmented Automata And Quantum Adiabatic Optimization. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/518

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rao, M V Panduranga. “Bounds On Augmented Automata And Quantum Adiabatic Optimization.” 2007. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/518.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rao, M V Panduranga. “Bounds On Augmented Automata And Quantum Adiabatic Optimization.” 2007. Web. 19 Jan 2019.

Vancouver:

Rao MVP. Bounds On Augmented Automata And Quantum Adiabatic Optimization. [Internet] [Thesis]. Indian Institute of Science; 2007. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/518.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rao MVP. Bounds On Augmented Automata And Quantum Adiabatic Optimization. [Thesis]. Indian Institute of Science; 2007. Available from: http://hdl.handle.net/2005/518

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

6. Jindal, Prachee. Compiler Assisted Energy Management For Sensor Network Nodes.

Degree: 2008, Indian Institute of Science

 Emerging low power, embedded, wireless sensor devices are useful for wide range of applications, yet have very limited processing storage and especially energy resources. Sensor… (more)

Subjects/Keywords: Sensor Networks - Data Processing; Electronic Detector Networks; Data Processing; Compilers (Computer Science); Dynamic Voltage Scaling; Energy Optimization; Scratchpad Memory; Sensor Node Architecture; Sensor Network Node; Node Architecture; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jindal, P. (2008). Compiler Assisted Energy Management For Sensor Network Nodes. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/819

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jindal, Prachee. “Compiler Assisted Energy Management For Sensor Network Nodes.” 2008. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/819.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jindal, Prachee. “Compiler Assisted Energy Management For Sensor Network Nodes.” 2008. Web. 19 Jan 2019.

Vancouver:

Jindal P. Compiler Assisted Energy Management For Sensor Network Nodes. [Internet] [Thesis]. Indian Institute of Science; 2008. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/819.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jindal P. Compiler Assisted Energy Management For Sensor Network Nodes. [Thesis]. Indian Institute of Science; 2008. Available from: http://hdl.handle.net/2005/819

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

7. Srikanth, Cherukupally. Large Scale Implementation Of The Block Lanczos Algorithm.

Degree: 2008, Indian Institute of Science

 Large sparse matrices arise in many applications, especially in the major problems of Cryptography of factoring integers and computing discrete logarithms. We focus attention on… (more)

Subjects/Keywords: Block Lanczos Algorithm; Algorithms (Computer Science); Sieve Matrices; Number Field Sieve (NFS); Wiedemann Algorithm; Sparse Matrices; Block Lanczos; Sieve Matrix; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Srikanth, C. (2008). Large Scale Implementation Of The Block Lanczos Algorithm. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/820

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Srikanth, Cherukupally. “Large Scale Implementation Of The Block Lanczos Algorithm.” 2008. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/820.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Srikanth, Cherukupally. “Large Scale Implementation Of The Block Lanczos Algorithm.” 2008. Web. 19 Jan 2019.

Vancouver:

Srikanth C. Large Scale Implementation Of The Block Lanczos Algorithm. [Internet] [Thesis]. Indian Institute of Science; 2008. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/820.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Srikanth C. Large Scale Implementation Of The Block Lanczos Algorithm. [Thesis]. Indian Institute of Science; 2008. Available from: http://hdl.handle.net/2005/820

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

8. Rajan, Kaushik. Efficient Cache Organization For Application Specific And General Purpose Processors.

Degree: 2008, Indian Institute of Science

 The performance gap between processor and memory continues to remain a major performance bottleneck in both application specific and general purpose processors. This thesis strives… (more)

Subjects/Keywords: Internet Cache Organization (Computer Science); Internet Microprocessors; Processor Architectures; Packet Forwarding Engines (Routers); General Purpose Processors; Heterogeneously Segmented Cache Architecture; Shephepherd Cache; Cache Architecture; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rajan, K. (2008). Efficient Cache Organization For Application Specific And General Purpose Processors. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/838

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rajan, Kaushik. “Efficient Cache Organization For Application Specific And General Purpose Processors.” 2008. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/838.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rajan, Kaushik. “Efficient Cache Organization For Application Specific And General Purpose Processors.” 2008. Web. 19 Jan 2019.

Vancouver:

Rajan K. Efficient Cache Organization For Application Specific And General Purpose Processors. [Internet] [Thesis]. Indian Institute of Science; 2008. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/838.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rajan K. Efficient Cache Organization For Application Specific And General Purpose Processors. [Thesis]. Indian Institute of Science; 2008. Available from: http://hdl.handle.net/2005/838

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

9. Kumar, V Santhosh. Improving The Communication Performance Of I/O Intensive And Communication Intensive Application In Cluster Computer Systems.

Degree: 2006, Indian Institute of Science

 Cluster computer systems assembled from commodity off-the-shelf components have emerged as a viable and cost-effective alternative to high-end custom parallel computer systems.In this thesis, we… (more)

Subjects/Keywords: Computer Communication; Input/output Communication; Database Query Processing; Community Atmospheric Model (CAM); Network Processors; Bloom Filter Processing; Cluster Computer Systems; Offloading Application; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kumar, V. S. (2006). Improving The Communication Performance Of I/O Intensive And Communication Intensive Application In Cluster Computer Systems. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/453

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kumar, V Santhosh. “Improving The Communication Performance Of I/O Intensive And Communication Intensive Application In Cluster Computer Systems.” 2006. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/453.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kumar, V Santhosh. “Improving The Communication Performance Of I/O Intensive And Communication Intensive Application In Cluster Computer Systems.” 2006. Web. 19 Jan 2019.

Vancouver:

Kumar VS. Improving The Communication Performance Of I/O Intensive And Communication Intensive Application In Cluster Computer Systems. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/453.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kumar VS. Improving The Communication Performance Of I/O Intensive And Communication Intensive Application In Cluster Computer Systems. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/453

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

10. Bharadwaj, Subramanya B V. The Isoperimetric Problem On Trees And Bounded Tree Width Graphs.

Degree: 2008, Indian Institute of Science

 In this thesis we study the isoperimetric problem on trees and graphs with bounded treewidth. Let G = (V,E) be a finite, simple and undirected… (more)

Subjects/Keywords: Computer Graphics - Algorithms; Computer Graphics - Mathematical Models; Isoperimetric Inequalities; Meta-Fibonacci Sequences; Graph Theory; Trees (Graph Theory); Treewidth Graphs; Weighted Graphs; Infinite Binary Tree; Isoperimetric Problem; Computer Science

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APA (6th Edition):

Bharadwaj, S. B. V. (2008). The Isoperimetric Problem On Trees And Bounded Tree Width Graphs. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/844

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bharadwaj, Subramanya B V. “The Isoperimetric Problem On Trees And Bounded Tree Width Graphs.” 2008. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/844.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bharadwaj, Subramanya B V. “The Isoperimetric Problem On Trees And Bounded Tree Width Graphs.” 2008. Web. 19 Jan 2019.

Vancouver:

Bharadwaj SBV. The Isoperimetric Problem On Trees And Bounded Tree Width Graphs. [Internet] [Thesis]. Indian Institute of Science; 2008. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/844.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bharadwaj SBV. The Isoperimetric Problem On Trees And Bounded Tree Width Graphs. [Thesis]. Indian Institute of Science; 2008. Available from: http://hdl.handle.net/2005/844

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

11. Ravindar, Archana. CLUSTER AND COLLECT : Compile Time Optimization For Effective Garbage Collection.

Degree: 2005, Indian Institute of Science

Subjects/Keywords: Compilers; Garbage (Computer Science); Object Clustering; Cluster Detection Algorithm; Cluster (Computing); Cluster Analysis; Clustering; Garbage Collection (Computer Science); Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ravindar, A. (2005). CLUSTER AND COLLECT : Compile Time Optimization For Effective Garbage Collection. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1444

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ravindar, Archana. “CLUSTER AND COLLECT : Compile Time Optimization For Effective Garbage Collection.” 2005. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/1444.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ravindar, Archana. “CLUSTER AND COLLECT : Compile Time Optimization For Effective Garbage Collection.” 2005. Web. 19 Jan 2019.

Vancouver:

Ravindar A. CLUSTER AND COLLECT : Compile Time Optimization For Effective Garbage Collection. [Internet] [Thesis]. Indian Institute of Science; 2005. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/1444.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ravindar A. CLUSTER AND COLLECT : Compile Time Optimization For Effective Garbage Collection. [Thesis]. Indian Institute of Science; 2005. Available from: http://hdl.handle.net/2005/1444

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

12. Ravindar, Archana. CLUSTER AND COLLECT : Compile Time Optimization For Effective Garbage Collection.

Degree: 2005, Indian Institute of Science

Subjects/Keywords: Compilers; Garbage (Computer Science); Object Clustering; Cluster Detection Algorithm; Cluster (Computing); Cluster Analysis; Clustering; Garbage Collection (Computer Science); Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ravindar, A. (2005). CLUSTER AND COLLECT : Compile Time Optimization For Effective Garbage Collection. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/1444 ; http://etd.ncsi.iisc.ernet.in/abstracts/1861/G19193-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ravindar, Archana. “CLUSTER AND COLLECT : Compile Time Optimization For Effective Garbage Collection.” 2005. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://etd.iisc.ernet.in/handle/2005/1444 ; http://etd.ncsi.iisc.ernet.in/abstracts/1861/G19193-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ravindar, Archana. “CLUSTER AND COLLECT : Compile Time Optimization For Effective Garbage Collection.” 2005. Web. 19 Jan 2019.

Vancouver:

Ravindar A. CLUSTER AND COLLECT : Compile Time Optimization For Effective Garbage Collection. [Internet] [Thesis]. Indian Institute of Science; 2005. [cited 2019 Jan 19]. Available from: http://etd.iisc.ernet.in/handle/2005/1444 ; http://etd.ncsi.iisc.ernet.in/abstracts/1861/G19193-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ravindar A. CLUSTER AND COLLECT : Compile Time Optimization For Effective Garbage Collection. [Thesis]. Indian Institute of Science; 2005. Available from: http://etd.iisc.ernet.in/handle/2005/1444 ; http://etd.ncsi.iisc.ernet.in/abstracts/1861/G19193-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

13. Nainwal, Kalash Chandra. Adaptive Grid Meta Scheduling - A QoS Perspective.

Degree: 2005, Indian Institute of Science

Subjects/Keywords: Computer Software - Development; Software Maintenance; Grid Computing; Computer Architecture; Computer Software - Distributed Processing; Grid Architecture; Adaptive Grid Meta Scheduling; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nainwal, K. C. (2005). Adaptive Grid Meta Scheduling - A QoS Perspective. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1397

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nainwal, Kalash Chandra. “Adaptive Grid Meta Scheduling - A QoS Perspective.” 2005. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/1397.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nainwal, Kalash Chandra. “Adaptive Grid Meta Scheduling - A QoS Perspective.” 2005. Web. 19 Jan 2019.

Vancouver:

Nainwal KC. Adaptive Grid Meta Scheduling - A QoS Perspective. [Internet] [Thesis]. Indian Institute of Science; 2005. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/1397.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nainwal KC. Adaptive Grid Meta Scheduling - A QoS Perspective. [Thesis]. Indian Institute of Science; 2005. Available from: http://hdl.handle.net/2005/1397

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

14. Pranav, R. Fast And Efficient Submesh Determination In Faulty Tori.

Degree: 2005, Indian Institute of Science

Subjects/Keywords: Parallel Processing; Torus (Computer Networks); Fault-Tolerant Computing; Parallel Computer Structure; Mesh Based Computer Architecture; Submesh Determination; Faulty Tori; Computer Science

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APA (6th Edition):

Pranav, R. (2005). Fast And Efficient Submesh Determination In Faulty Tori. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1437

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pranav, R. “Fast And Efficient Submesh Determination In Faulty Tori.” 2005. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/1437.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pranav, R. “Fast And Efficient Submesh Determination In Faulty Tori.” 2005. Web. 19 Jan 2019.

Vancouver:

Pranav R. Fast And Efficient Submesh Determination In Faulty Tori. [Internet] [Thesis]. Indian Institute of Science; 2005. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/1437.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pranav R. Fast And Efficient Submesh Determination In Faulty Tori. [Thesis]. Indian Institute of Science; 2005. Available from: http://hdl.handle.net/2005/1437

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

15. Nainwal, Kalash Chandra. Adaptive Grid Meta Scheduling - A QoS Perspective.

Degree: 2005, Indian Institute of Science

Subjects/Keywords: Computer Software - Development; Software Maintenance; Grid Computing; Computer Architecture; Computer Software - Distributed Processing; Grid Architecture; Adaptive Grid Meta Scheduling; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nainwal, K. C. (2005). Adaptive Grid Meta Scheduling - A QoS Perspective. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/1397 ; http://etd.ncsi.iisc.ernet.in/abstracts/1805/G19039-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nainwal, Kalash Chandra. “Adaptive Grid Meta Scheduling - A QoS Perspective.” 2005. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://etd.iisc.ernet.in/handle/2005/1397 ; http://etd.ncsi.iisc.ernet.in/abstracts/1805/G19039-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nainwal, Kalash Chandra. “Adaptive Grid Meta Scheduling - A QoS Perspective.” 2005. Web. 19 Jan 2019.

Vancouver:

Nainwal KC. Adaptive Grid Meta Scheduling - A QoS Perspective. [Internet] [Thesis]. Indian Institute of Science; 2005. [cited 2019 Jan 19]. Available from: http://etd.iisc.ernet.in/handle/2005/1397 ; http://etd.ncsi.iisc.ernet.in/abstracts/1805/G19039-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nainwal KC. Adaptive Grid Meta Scheduling - A QoS Perspective. [Thesis]. Indian Institute of Science; 2005. Available from: http://etd.iisc.ernet.in/handle/2005/1397 ; http://etd.ncsi.iisc.ernet.in/abstracts/1805/G19039-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

16. Pranav, R. Fast And Efficient Submesh Determination In Faulty Tori.

Degree: 2005, Indian Institute of Science

Subjects/Keywords: Parallel Processing; Torus (Computer Networks); Fault-Tolerant Computing; Parallel Computer Structure; Mesh Based Computer Architecture; Submesh Determination; Faulty Tori; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pranav, R. (2005). Fast And Efficient Submesh Determination In Faulty Tori. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/1437 ; http://etd.ncsi.iisc.ernet.in/abstracts/1853/G19738-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pranav, R. “Fast And Efficient Submesh Determination In Faulty Tori.” 2005. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://etd.iisc.ernet.in/handle/2005/1437 ; http://etd.ncsi.iisc.ernet.in/abstracts/1853/G19738-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pranav, R. “Fast And Efficient Submesh Determination In Faulty Tori.” 2005. Web. 19 Jan 2019.

Vancouver:

Pranav R. Fast And Efficient Submesh Determination In Faulty Tori. [Internet] [Thesis]. Indian Institute of Science; 2005. [cited 2019 Jan 19]. Available from: http://etd.iisc.ernet.in/handle/2005/1437 ; http://etd.ncsi.iisc.ernet.in/abstracts/1853/G19738-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pranav R. Fast And Efficient Submesh Determination In Faulty Tori. [Thesis]. Indian Institute of Science; 2005. Available from: http://etd.iisc.ernet.in/handle/2005/1437 ; http://etd.ncsi.iisc.ernet.in/abstracts/1853/G19738-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

17. Govind, S. Performance Modeling And Evaluation Of Network Processors.

Degree: 2006, Indian Institute of Science

 In recent years there has been an exponential growth in Internet traffic resulting in increased network bandwidth requirements which, in turn, has led to stringent… (more)

Subjects/Keywords: Network Processors; Computer Networks; Petri Nets; Petri Net Model; Network Processors - Packet Reordering; Network Processors - Perormance Analysis; Internet Traffic - Network Processor Performance; Bursty Traffic; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Govind, S. (2006). Performance Modeling And Evaluation Of Network Processors. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/388

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Govind, S. “Performance Modeling And Evaluation Of Network Processors.” 2006. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/388.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Govind, S. “Performance Modeling And Evaluation Of Network Processors.” 2006. Web. 19 Jan 2019.

Vancouver:

Govind S. Performance Modeling And Evaluation Of Network Processors. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/388.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Govind S. Performance Modeling And Evaluation Of Network Processors. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/388

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

18. Phani, B. Applications Of Machine Learning To Anomaly Based Intrusion Detection.

Degree: 2006, Indian Institute of Science

 This thesis concerns anomaly detection as a mechanism for intrusion detection in a machine learning framework, using two kinds of audit data : system call… (more)

Subjects/Keywords: Intrusion Detection; Cryptography; Computer Access Control; Machine Learning; Sequence Kernel; Anomaly Detection; Data Mining; System Call Traces; Intrusion Detection Systems (IDS); Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Phani, B. (2006). Applications Of Machine Learning To Anomaly Based Intrusion Detection. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/391

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Phani, B. “Applications Of Machine Learning To Anomaly Based Intrusion Detection.” 2006. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/391.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Phani, B. “Applications Of Machine Learning To Anomaly Based Intrusion Detection.” 2006. Web. 19 Jan 2019.

Vancouver:

Phani B. Applications Of Machine Learning To Anomaly Based Intrusion Detection. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/391.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Phani B. Applications Of Machine Learning To Anomaly Based Intrusion Detection. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/391

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

19. Vasanta Lakshmi, Kommineni. Integrating A New Cluster Assignment And Scheduling Algorithm Into An Experimental Retargetable Code Generation Framework.

Degree: 2006, Indian Institute of Science

 This thesis presents a new unified algorithm for cluster assignment and acyclic region scheduling in a partitioned architecture, and preliminary results on its integration into… (more)

Subjects/Keywords: Computer Architecture; HMDES Architecture; Tree Transformer Generator; Register Allocation Algorithm; Integrated Scheduling Algorithm; TI Code; Retargetable Code Generation Framework; Target Processor; Computer Science

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APA (6th Edition):

Vasanta Lakshmi, K. (2006). Integrating A New Cluster Assignment And Scheduling Algorithm Into An Experimental Retargetable Code Generation Framework. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/414

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vasanta Lakshmi, Kommineni. “Integrating A New Cluster Assignment And Scheduling Algorithm Into An Experimental Retargetable Code Generation Framework.” 2006. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/414.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vasanta Lakshmi, Kommineni. “Integrating A New Cluster Assignment And Scheduling Algorithm Into An Experimental Retargetable Code Generation Framework.” 2006. Web. 19 Jan 2019.

Vancouver:

Vasanta Lakshmi K. Integrating A New Cluster Assignment And Scheduling Algorithm Into An Experimental Retargetable Code Generation Framework. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/414.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vasanta Lakshmi K. Integrating A New Cluster Assignment And Scheduling Algorithm Into An Experimental Retargetable Code Generation Framework. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/414

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

20. Subbian, Karthik. Design Of Incentive Compatible Mechanisms For Ticket Allocation In Software Maintenance Services.

Degree: 2007, Indian Institute of Science

 Software Maintenance is becoming more and more challenging due to rapidly changing customer needs, technologies and need for highly skilled labor. Many problems that existed… (more)

Subjects/Keywords: Computer Software - Testing And Measurement; Software Maintenance - Ticket Allocation; Game Theory; Software Maintenance; Mechanisms Design Theory; Ticket Allocation; Software Maintenance Services; Incentive Compatible Mechanisms; Computer Science

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APA (6th Edition):

Subbian, K. (2007). Design Of Incentive Compatible Mechanisms For Ticket Allocation In Software Maintenance Services. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/520

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Subbian, Karthik. “Design Of Incentive Compatible Mechanisms For Ticket Allocation In Software Maintenance Services.” 2007. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/520.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Subbian, Karthik. “Design Of Incentive Compatible Mechanisms For Ticket Allocation In Software Maintenance Services.” 2007. Web. 19 Jan 2019.

Vancouver:

Subbian K. Design Of Incentive Compatible Mechanisms For Ticket Allocation In Software Maintenance Services. [Internet] [Thesis]. Indian Institute of Science; 2007. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/520.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Subbian K. Design Of Incentive Compatible Mechanisms For Ticket Allocation In Software Maintenance Services. [Thesis]. Indian Institute of Science; 2007. Available from: http://hdl.handle.net/2005/520

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

21. Ravindranath, C K. A Peer To Peer Web Proxy Cache For Enterprise Networks.

Degree: 2007, Indian Institute of Science

 In this thesis, we propose a decentralized peer-to-peer (P2P) Web proxy cache for enterprise networks (ENs). Currently, enterprises use a centralized proxy-based Web cache, where… (more)

Subjects/Keywords: Computer Networks; Web Proxy Cache; Peer-to-Peer Web Proxy Cache; Web Caching; Enterprise Networks (ENs); P2P Protocols; Web Proxy Caching; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ravindranath, C. K. (2007). A Peer To Peer Web Proxy Cache For Enterprise Networks. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/612

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ravindranath, C K. “A Peer To Peer Web Proxy Cache For Enterprise Networks.” 2007. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/612.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ravindranath, C K. “A Peer To Peer Web Proxy Cache For Enterprise Networks.” 2007. Web. 19 Jan 2019.

Vancouver:

Ravindranath CK. A Peer To Peer Web Proxy Cache For Enterprise Networks. [Internet] [Thesis]. Indian Institute of Science; 2007. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/612.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ravindranath CK. A Peer To Peer Web Proxy Cache For Enterprise Networks. [Thesis]. Indian Institute of Science; 2007. Available from: http://hdl.handle.net/2005/612

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

22. Nagpal, Rahul. Compiler-Assisted Energy Optimization For Clustered VLIW Processors.

Degree: 2008, Indian Institute of Science

 Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption.… (more)

Subjects/Keywords: Embedded Systems; Computer Architecture; Algorithms; Very Long Instruction Word Architecture; Energy Optimization; Energy Management; Interconnect Modeling; Clustered VLIW Architectures; Clustered VLIW Processors; Power Optimization; Micro-architetural Explorations; Computer Science

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APA (6th Edition):

Nagpal, R. (2008). Compiler-Assisted Energy Optimization For Clustered VLIW Processors. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/684

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nagpal, Rahul. “Compiler-Assisted Energy Optimization For Clustered VLIW Processors.” 2008. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/684.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nagpal, Rahul. “Compiler-Assisted Energy Optimization For Clustered VLIW Processors.” 2008. Web. 19 Jan 2019.

Vancouver:

Nagpal R. Compiler-Assisted Energy Optimization For Clustered VLIW Processors. [Internet] [Thesis]. Indian Institute of Science; 2008. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/684.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nagpal R. Compiler-Assisted Energy Optimization For Clustered VLIW Processors. [Thesis]. Indian Institute of Science; 2008. Available from: http://hdl.handle.net/2005/684

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

23. Yekkala, Anil Kumar. Analysis And Design Of Image And Video Encryption Algorithms.

Degree: 2006, Indian Institute of Science

 The rapid growth in multimedia based Internet systems and applications like video telephony, video on demand, network based DVD recorders and IP television has created… (more)

Subjects/Keywords: Encryption Algorithms; Multimedia Encryption; Multimedia Security; Lightweight Encryption; Cryptanalysis; Image Compression; Image And Video Encryption; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yekkala, A. K. (2006). Analysis And Design Of Image And Video Encryption Algorithms. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/436

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yekkala, Anil Kumar. “Analysis And Design Of Image And Video Encryption Algorithms.” 2006. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/436.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yekkala, Anil Kumar. “Analysis And Design Of Image And Video Encryption Algorithms.” 2006. Web. 19 Jan 2019.

Vancouver:

Yekkala AK. Analysis And Design Of Image And Video Encryption Algorithms. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/436.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yekkala AK. Analysis And Design Of Image And Video Encryption Algorithms. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/436

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

24. Thakur, Aditya. Comprehensive Path-sensitive Data-flow Analysis.

Degree: 2008, Indian Institute of Science

 Data-flow analysis is an integral part of any aggressive optimizing compiler. We propose a framework for improving the precision of data-flow analysis in the presence… (more)

Subjects/Keywords: Compilers; Data-flow Analysis; Control-flow Graphs; Automata Theory; Destructive Merge; Scale Compiler; Split Approach; Complex Control-flow; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Thakur, A. (2008). Comprehensive Path-sensitive Data-flow Analysis. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/836

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Thakur, Aditya. “Comprehensive Path-sensitive Data-flow Analysis.” 2008. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/836.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Thakur, Aditya. “Comprehensive Path-sensitive Data-flow Analysis.” 2008. Web. 19 Jan 2019.

Vancouver:

Thakur A. Comprehensive Path-sensitive Data-flow Analysis. [Internet] [Thesis]. Indian Institute of Science; 2008. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/836.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Thakur A. Comprehensive Path-sensitive Data-flow Analysis. [Thesis]. Indian Institute of Science; 2008. Available from: http://hdl.handle.net/2005/836

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

25. Sarvani, V V N S. Compiler Techniques For Code Size And Power Reduction For Embedded Processors.

Degree: 2004, Indian Institute of Science

Subjects/Keywords: Microprocessors; Embedded Systems; Compilers; Embedded Processors; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sarvani, V. V. N. S. (2004). Compiler Techniques For Code Size And Power Reduction For Embedded Processors. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1135

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sarvani, V V N S. “Compiler Techniques For Code Size And Power Reduction For Embedded Processors.” 2004. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/1135.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sarvani, V V N S. “Compiler Techniques For Code Size And Power Reduction For Embedded Processors.” 2004. Web. 19 Jan 2019.

Vancouver:

Sarvani VVNS. Compiler Techniques For Code Size And Power Reduction For Embedded Processors. [Internet] [Thesis]. Indian Institute of Science; 2004. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/1135.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sarvani VVNS. Compiler Techniques For Code Size And Power Reduction For Embedded Processors. [Thesis]. Indian Institute of Science; 2004. Available from: http://hdl.handle.net/2005/1135

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

26. Sanjay, H A. Performance Modeling Based Scheduling And Rescheduling Of Parallel Applications On Computational Grids.

Degree: 2008, Indian Institute of Science

 As computational grids have become popular and ubiquitous, users have access to large number and different types of geographically distributed grid resources. Many computational grid… (more)

Subjects/Keywords: Computational Grids; Performance Modeling; Scheduling; Rescheduling; Grid Computing; Scheduling Algorithms; Rescheduling Algorithms; Grid Scheduling; Grids; Tightly-Coupled Parallel Applications; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sanjay, H. A. (2008). Performance Modeling Based Scheduling And Rescheduling Of Parallel Applications On Computational Grids. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/701

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sanjay, H A. “Performance Modeling Based Scheduling And Rescheduling Of Parallel Applications On Computational Grids.” 2008. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/701.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sanjay, H A. “Performance Modeling Based Scheduling And Rescheduling Of Parallel Applications On Computational Grids.” 2008. Web. 19 Jan 2019.

Vancouver:

Sanjay HA. Performance Modeling Based Scheduling And Rescheduling Of Parallel Applications On Computational Grids. [Internet] [Thesis]. Indian Institute of Science; 2008. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/701.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sanjay HA. Performance Modeling Based Scheduling And Rescheduling Of Parallel Applications On Computational Grids. [Thesis]. Indian Institute of Science; 2008. Available from: http://hdl.handle.net/2005/701

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

27. Nori, Aditya Vithal. Unifying Views Of Tail-Biting Trellises For Linear Block Codes.

Degree: 2005, Indian Institute of Science

Subjects/Keywords: Algorithms (Computer Science); Block Codes; Linear Block Codes; Error-Correcting Codes (Information Theory); Trellises; Linear Codes; Computer Science

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APA (6th Edition):

Nori, A. V. (2005). Unifying Views Of Tail-Biting Trellises For Linear Block Codes. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1441

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nori, Aditya Vithal. “Unifying Views Of Tail-Biting Trellises For Linear Block Codes.” 2005. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/1441.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nori, Aditya Vithal. “Unifying Views Of Tail-Biting Trellises For Linear Block Codes.” 2005. Web. 19 Jan 2019.

Vancouver:

Nori AV. Unifying Views Of Tail-Biting Trellises For Linear Block Codes. [Internet] [Thesis]. Indian Institute of Science; 2005. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/1441.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nori AV. Unifying Views Of Tail-Biting Trellises For Linear Block Codes. [Thesis]. Indian Institute of Science; 2005. Available from: http://hdl.handle.net/2005/1441

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

28. Nori, Aditya Vithal. Unifying Views Of Tail-Biting Trellises For Linear Block Codes.

Degree: 2005, Indian Institute of Science

Subjects/Keywords: Algorithms (Computer Science); Block Codes; Linear Block Codes; Error-Correcting Codes (Information Theory); Trellises; Linear Codes; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nori, A. V. (2005). Unifying Views Of Tail-Biting Trellises For Linear Block Codes. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/1441 ; http://etd.ncsi.iisc.ernet.in/abstracts/1858/G19134-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nori, Aditya Vithal. “Unifying Views Of Tail-Biting Trellises For Linear Block Codes.” 2005. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://etd.iisc.ernet.in/handle/2005/1441 ; http://etd.ncsi.iisc.ernet.in/abstracts/1858/G19134-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nori, Aditya Vithal. “Unifying Views Of Tail-Biting Trellises For Linear Block Codes.” 2005. Web. 19 Jan 2019.

Vancouver:

Nori AV. Unifying Views Of Tail-Biting Trellises For Linear Block Codes. [Internet] [Thesis]. Indian Institute of Science; 2005. [cited 2019 Jan 19]. Available from: http://etd.iisc.ernet.in/handle/2005/1441 ; http://etd.ncsi.iisc.ernet.in/abstracts/1858/G19134-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nori AV. Unifying Views Of Tail-Biting Trellises For Linear Block Codes. [Thesis]. Indian Institute of Science; 2005. Available from: http://etd.iisc.ernet.in/handle/2005/1441 ; http://etd.ncsi.iisc.ernet.in/abstracts/1858/G19134-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

29. Dharmadeep, M C. Optimizations In Storage Area Networks And Direct Attached Storage.

Degree: 2007, Indian Institute of Science

 The thesis consists of three parts. In the first part, we introduce the notion of device-cache-aware schedulers. Modern disk subsystems have many megabytes of memory… (more)

Subjects/Keywords: Computer Storage; Computer Memory Devices; Adaptive Caching Algorithms; Cooperative Caching; Redhat Global File System - Caching; Device-Cache-Aware Schedulers; Clustered Shared Disk Systems; Scheduler Architecture; Storage Area Networks; Direct Attached Storage; Distributed Lock Manager (DLM); Global File System (GFS); Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dharmadeep, M. C. (2007). Optimizations In Storage Area Networks And Direct Attached Storage. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/574

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dharmadeep, M C. “Optimizations In Storage Area Networks And Direct Attached Storage.” 2007. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/574.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dharmadeep, M C. “Optimizations In Storage Area Networks And Direct Attached Storage.” 2007. Web. 19 Jan 2019.

Vancouver:

Dharmadeep MC. Optimizations In Storage Area Networks And Direct Attached Storage. [Internet] [Thesis]. Indian Institute of Science; 2007. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/574.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dharmadeep MC. Optimizations In Storage Area Networks And Direct Attached Storage. [Thesis]. Indian Institute of Science; 2007. Available from: http://hdl.handle.net/2005/574

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

30. Sathish, Sriram J. Shape From Shading Analysis By Synthesis.

Degree: 2004, Indian Institute of Science

Subjects/Keywords: Computer Vision; Shapes (Mathematics) - Computer Vision; Shape from Shading (SfS); Impllcit Surfaces; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sathish, S. J. (2004). Shape From Shading Analysis By Synthesis. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1173

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sathish, Sriram J. “Shape From Shading Analysis By Synthesis.” 2004. Thesis, Indian Institute of Science. Accessed January 19, 2019. http://hdl.handle.net/2005/1173.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sathish, Sriram J. “Shape From Shading Analysis By Synthesis.” 2004. Web. 19 Jan 2019.

Vancouver:

Sathish SJ. Shape From Shading Analysis By Synthesis. [Internet] [Thesis]. Indian Institute of Science; 2004. [cited 2019 Jan 19]. Available from: http://hdl.handle.net/2005/1173.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sathish SJ. Shape From Shading Analysis By Synthesis. [Thesis]. Indian Institute of Science; 2004. Available from: http://hdl.handle.net/2005/1173

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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