Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

University: Indian Institute of Science

You searched for subject:(Computer Science). Showing records 1 – 30 of 475 total matches.

[1] [2] [3] [4] [5] … [16]

Search Limiters

Last 2 Years | English Only

▼ Search Limiters


Indian Institute of Science

1. Kamala, R. MIST : Mlgrate The Storage Too.

Degree: 2013, Indian Institute of Science

 We address the problem of migration of local storage of desktop users to remote sites. Assuming a network connection is maintained between the source and… (more)

Subjects/Keywords: Data Storage; Storage Migration; Data Collection; Computer Storage; Network File Systems; Remote Access; User Access Patterns; Clustering (Computers); Computer Memory; Virtual Storage (Computer Science); Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kamala, R. (2013). MIST : Mlgrate The Storage Too. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2630 ; http://etd.ncsi.iisc.ernet.in/abstracts/3380/G25995.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kamala, R. “MIST : Mlgrate The Storage Too.” 2013. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://etd.iisc.ernet.in/handle/2005/2630 ; http://etd.ncsi.iisc.ernet.in/abstracts/3380/G25995.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kamala, R. “MIST : Mlgrate The Storage Too.” 2013. Web. 16 Dec 2018.

Vancouver:

Kamala R. MIST : Mlgrate The Storage Too. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2018 Dec 16]. Available from: http://etd.iisc.ernet.in/handle/2005/2630 ; http://etd.ncsi.iisc.ernet.in/abstracts/3380/G25995.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kamala R. MIST : Mlgrate The Storage Too. [Thesis]. Indian Institute of Science; 2013. Available from: http://etd.iisc.ernet.in/handle/2005/2630 ; http://etd.ncsi.iisc.ernet.in/abstracts/3380/G25995.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

2. Kamala, R. MIST : Mlgrate The Storage Too.

Degree: 2013, Indian Institute of Science

 We address the problem of migration of local storage of desktop users to remote sites. Assuming a network connection is maintained between the source and… (more)

Subjects/Keywords: Data Storage; Storage Migration; Data Collection; Computer Storage; Network File Systems; Remote Access; User Access Patterns; Clustering (Computers); Computer Memory; Virtual Storage (Computer Science); Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kamala, R. (2013). MIST : Mlgrate The Storage Too. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2630

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kamala, R. “MIST : Mlgrate The Storage Too.” 2013. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/2630.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kamala, R. “MIST : Mlgrate The Storage Too.” 2013. Web. 16 Dec 2018.

Vancouver:

Kamala R. MIST : Mlgrate The Storage Too. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/2630.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kamala R. MIST : Mlgrate The Storage Too. [Thesis]. Indian Institute of Science; 2013. Available from: http://hdl.handle.net/2005/2630

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

3. Jayaram, Sampath. A Theoretical Study of the Synergy and Lazy Annotation Algorithms.

Degree: 2013, Indian Institute of Science

 Given a program with assertions, the assertion checking problem is to tell whether there is an execution of the program that violates one of the… (more)

Subjects/Keywords: Computer Programs; Program Semantics; Lazy Annotation Algorithms; Symbolic Execution; Synergy; Lazy Annotation; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jayaram, S. (2013). A Theoretical Study of the Synergy and Lazy Annotation Algorithms. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3321 ; http://etd.iisc.ernet.in/abstracts/4185/G25692-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jayaram, Sampath. “A Theoretical Study of the Synergy and Lazy Annotation Algorithms.” 2013. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://etd.iisc.ernet.in/2005/3321 ; http://etd.iisc.ernet.in/abstracts/4185/G25692-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jayaram, Sampath. “A Theoretical Study of the Synergy and Lazy Annotation Algorithms.” 2013. Web. 16 Dec 2018.

Vancouver:

Jayaram S. A Theoretical Study of the Synergy and Lazy Annotation Algorithms. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2018 Dec 16]. Available from: http://etd.iisc.ernet.in/2005/3321 ; http://etd.iisc.ernet.in/abstracts/4185/G25692-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jayaram S. A Theoretical Study of the Synergy and Lazy Annotation Algorithms. [Thesis]. Indian Institute of Science; 2013. Available from: http://etd.iisc.ernet.in/2005/3321 ; http://etd.iisc.ernet.in/abstracts/4185/G25692-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

4. Prasad, Ashwin. Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors.

Degree: 2012, Indian Institute of Science

 MATLAB is an array language, initially popular for rapid prototyping, but is now being in-creasingly used to develop production code for numerical and scientific applications.… (more)

Subjects/Keywords: Compilers (Computer Programs); MATLAB (Computer Program); MEGHA (Compiler); Parallel Processors; Heterogeneous Processors; MATLAB Programs - Compilation; MATLAB Program; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Prasad, A. (2012). Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2312

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Prasad, Ashwin. “Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors.” 2012. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/2312.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Prasad, Ashwin. “Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors.” 2012. Web. 16 Dec 2018.

Vancouver:

Prasad A. Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/2312.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Prasad A. Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors. [Thesis]. Indian Institute of Science; 2012. Available from: http://hdl.handle.net/2005/2312

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

5. Prasad, Ashwin. Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors.

Degree: 2012, Indian Institute of Science

 MATLAB is an array language, initially popular for rapid prototyping, but is now being in-creasingly used to develop production code for numerical and scientific applications.… (more)

Subjects/Keywords: Compilers (Computer Programs); MATLAB (Computer Program); MEGHA (Compiler); Parallel Processors; Heterogeneous Processors; MATLAB Programs - Compilation; MATLAB Program; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Prasad, A. (2012). Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2312 ; http://etd.ncsi.iisc.ernet.in/abstracts/2974/G25101-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Prasad, Ashwin. “Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors.” 2012. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://etd.iisc.ernet.in/handle/2005/2312 ; http://etd.ncsi.iisc.ernet.in/abstracts/2974/G25101-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Prasad, Ashwin. “Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors.” 2012. Web. 16 Dec 2018.

Vancouver:

Prasad A. Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2018 Dec 16]. Available from: http://etd.iisc.ernet.in/handle/2005/2312 ; http://etd.ncsi.iisc.ernet.in/abstracts/2974/G25101-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Prasad A. Automatic Compilation Of MATLAB Programs For Synergistic Execution On Heterogeneous Processors. [Thesis]. Indian Institute of Science; 2012. Available from: http://etd.iisc.ernet.in/handle/2005/2312 ; http://etd.ncsi.iisc.ernet.in/abstracts/2974/G25101-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

6. Agarwal, Tanuj Kumar. Cache Coherence State Based Replacement Policies.

Degree: 2015, Indian Institute of Science

 Cache replacement policies can play a pivotal role in the overall performance of a system by preserving data locality and thus limiting the o -chip… (more)

Subjects/Keywords: Cache Replacement Policy; Cache Coherence; Computer Architecture; Cache Memory; Computer Storage Devices; Cache Replacement Policies; Cache Coherence Protocol; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Agarwal, T. K. (2015). Cache Coherence State Based Replacement Policies. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3822 ; http://etd.iisc.ernet.in/abstracts/4693/G26974-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Agarwal, Tanuj Kumar. “Cache Coherence State Based Replacement Policies.” 2015. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://etd.iisc.ernet.in/2005/3822 ; http://etd.iisc.ernet.in/abstracts/4693/G26974-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Agarwal, Tanuj Kumar. “Cache Coherence State Based Replacement Policies.” 2015. Web. 16 Dec 2018.

Vancouver:

Agarwal TK. Cache Coherence State Based Replacement Policies. [Internet] [Thesis]. Indian Institute of Science; 2015. [cited 2018 Dec 16]. Available from: http://etd.iisc.ernet.in/2005/3822 ; http://etd.iisc.ernet.in/abstracts/4693/G26974-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Agarwal TK. Cache Coherence State Based Replacement Policies. [Thesis]. Indian Institute of Science; 2015. Available from: http://etd.iisc.ernet.in/2005/3822 ; http://etd.iisc.ernet.in/abstracts/4693/G26974-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

7. Satrawala, Amar Nath. RETHROTTLE : Execution Throttling In The REDEFINE SoC Architecture.

Degree: 2009, Indian Institute of Science

 REDEFINE is a reconfigurable SoC architecture that provides a unique platform for high performance and low power computing by exploiting the synergistic interaction between coarse… (more)

Subjects/Keywords: SoC Architecture; Computer Architecture; Semiconductor-on-Chip Architecture; Dataflow Models; Throttling; Computer Simulation; REDEFINE Architecture; Computer Architecture - Modeling; Hybrid Computer Simulation; Von Neumann Architecture; Coarse Grain; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Satrawala, A. N. (2009). RETHROTTLE : Execution Throttling In The REDEFINE SoC Architecture. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1017

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Satrawala, Amar Nath. “RETHROTTLE : Execution Throttling In The REDEFINE SoC Architecture.” 2009. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/1017.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Satrawala, Amar Nath. “RETHROTTLE : Execution Throttling In The REDEFINE SoC Architecture.” 2009. Web. 16 Dec 2018.

Vancouver:

Satrawala AN. RETHROTTLE : Execution Throttling In The REDEFINE SoC Architecture. [Internet] [Thesis]. Indian Institute of Science; 2009. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/1017.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Satrawala AN. RETHROTTLE : Execution Throttling In The REDEFINE SoC Architecture. [Thesis]. Indian Institute of Science; 2009. Available from: http://hdl.handle.net/2005/1017

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

8. Mannarswamy, Sandya S. Compiler Transformations For Improving The Performance Of Software Transactional Memory.

Degree: 2011, Indian Institute of Science

 Expressing synchronization using traditional lock based primitives has been found to be both error-prone and restrictive. Hence there has been considerable research work to develop… (more)

Subjects/Keywords: Compiler Transformation; Software Transactional Memory (STM); Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mannarswamy, S. S. (2011). Compiler Transformations For Improving The Performance Of Software Transactional Memory. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1955

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mannarswamy, Sandya S. “Compiler Transformations For Improving The Performance Of Software Transactional Memory.” 2011. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/1955.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mannarswamy, Sandya S. “Compiler Transformations For Improving The Performance Of Software Transactional Memory.” 2011. Web. 16 Dec 2018.

Vancouver:

Mannarswamy SS. Compiler Transformations For Improving The Performance Of Software Transactional Memory. [Internet] [Thesis]. Indian Institute of Science; 2011. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/1955.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mannarswamy SS. Compiler Transformations For Improving The Performance Of Software Transactional Memory. [Thesis]. Indian Institute of Science; 2011. Available from: http://hdl.handle.net/2005/1955

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

9. Mannarswamy, Sandya S. Compiler Transformations For Improving The Performance Of Software Transactional Memory.

Degree: 2011, Indian Institute of Science

 Expressing synchronization using traditional lock based primitives has been found to be both error-prone and restrictive. Hence there has been considerable research work to develop… (more)

Subjects/Keywords: Compiler Transformation; Software Transactional Memory (STM); Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mannarswamy, S. S. (2011). Compiler Transformations For Improving The Performance Of Software Transactional Memory. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/1955 ; http://etd.ncsi.iisc.ernet.in/abstracts/2533/G24967-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mannarswamy, Sandya S. “Compiler Transformations For Improving The Performance Of Software Transactional Memory.” 2011. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://etd.iisc.ernet.in/handle/2005/1955 ; http://etd.ncsi.iisc.ernet.in/abstracts/2533/G24967-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mannarswamy, Sandya S. “Compiler Transformations For Improving The Performance Of Software Transactional Memory.” 2011. Web. 16 Dec 2018.

Vancouver:

Mannarswamy SS. Compiler Transformations For Improving The Performance Of Software Transactional Memory. [Internet] [Thesis]. Indian Institute of Science; 2011. [cited 2018 Dec 16]. Available from: http://etd.iisc.ernet.in/handle/2005/1955 ; http://etd.ncsi.iisc.ernet.in/abstracts/2533/G24967-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mannarswamy SS. Compiler Transformations For Improving The Performance Of Software Transactional Memory. [Thesis]. Indian Institute of Science; 2011. Available from: http://etd.iisc.ernet.in/handle/2005/1955 ; http://etd.ncsi.iisc.ernet.in/abstracts/2533/G24967-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

10. Bandishti, Vinayaka Prakasha. Tiling Stencil Computations To Maximize Parallelism.

Degree: 2013, Indian Institute of Science

 Stencil computations are iterative kernels often used to simulate the change in a discretized spatial domain overtime (e.g., computational fluid dynamics) or to solve for… (more)

Subjects/Keywords: Stencil Computations; Concurrent Start-Up; Tiling Hyperplanes; Periodic Stencils; Compilers (Computer Programs); Multiprocessors; Computer Architecture; Parallelism (Computer Architecture); Tiling Stencil Computations; Automatic Parallelizers; Pluto-Source Level Automatic Parallelizer; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bandishti, V. P. (2013). Tiling Stencil Computations To Maximize Parallelism. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2619 ; http://etd.ncsi.iisc.ernet.in/abstracts/3407/G26301-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bandishti, Vinayaka Prakasha. “Tiling Stencil Computations To Maximize Parallelism.” 2013. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://etd.iisc.ernet.in/handle/2005/2619 ; http://etd.ncsi.iisc.ernet.in/abstracts/3407/G26301-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bandishti, Vinayaka Prakasha. “Tiling Stencil Computations To Maximize Parallelism.” 2013. Web. 16 Dec 2018.

Vancouver:

Bandishti VP. Tiling Stencil Computations To Maximize Parallelism. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2018 Dec 16]. Available from: http://etd.iisc.ernet.in/handle/2005/2619 ; http://etd.ncsi.iisc.ernet.in/abstracts/3407/G26301-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bandishti VP. Tiling Stencil Computations To Maximize Parallelism. [Thesis]. Indian Institute of Science; 2013. Available from: http://etd.iisc.ernet.in/handle/2005/2619 ; http://etd.ncsi.iisc.ernet.in/abstracts/3407/G26301-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

11. Bandishti, Vinayaka Prakasha. Tiling Stencil Computations To Maximize Parallelism.

Degree: 2013, Indian Institute of Science

 Stencil computations are iterative kernels often used to simulate the change in a discretized spatial domain overtime (e.g., computational fluid dynamics) or to solve for… (more)

Subjects/Keywords: Stencil Computations; Concurrent Start-Up; Tiling Hyperplanes; Periodic Stencils; Compilers (Computer Programs); Multiprocessors; Computer Architecture; Parallelism (Computer Architecture); Tiling Stencil Computations; Automatic Parallelizers; Pluto-Source Level Automatic Parallelizer; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bandishti, V. P. (2013). Tiling Stencil Computations To Maximize Parallelism. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2619

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bandishti, Vinayaka Prakasha. “Tiling Stencil Computations To Maximize Parallelism.” 2013. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/2619.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bandishti, Vinayaka Prakasha. “Tiling Stencil Computations To Maximize Parallelism.” 2013. Web. 16 Dec 2018.

Vancouver:

Bandishti VP. Tiling Stencil Computations To Maximize Parallelism. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/2619.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bandishti VP. Tiling Stencil Computations To Maximize Parallelism. [Thesis]. Indian Institute of Science; 2013. Available from: http://hdl.handle.net/2005/2619

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

12. Shyam, K. Power-Aware Compilation Techniques For Embedded Systems.

Degree: 2006, Indian Institute of Science

 The demand for devices like Personal Digital Assistants (PDA’s), Laptops, Smart Mobile Phones, are at an all time high. As the demand for these devices… (more)

Subjects/Keywords: Electric Power Control; Compilers; Embedded Systems; Computer Memory Architecture; Voltages; Dynamic Voltage Scaling; Memory Architectures; Integer Linear Programming (ILP); Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shyam, K. (2006). Power-Aware Compilation Techniques For Embedded Systems. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/348

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shyam, K. “Power-Aware Compilation Techniques For Embedded Systems.” 2006. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/348.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shyam, K. “Power-Aware Compilation Techniques For Embedded Systems.” 2006. Web. 16 Dec 2018.

Vancouver:

Shyam K. Power-Aware Compilation Techniques For Embedded Systems. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/348.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shyam K. Power-Aware Compilation Techniques For Embedded Systems. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/348

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

13. Bharath Kumar, M. Discovering Roles In The Evolution Of Collaboration Networks.

Degree: 2006, Indian Institute of Science

 Searching the Web involves more than sifting through a huge graph of pages and hyperlinks. Specific collaboration networks have emerged that serve domain-specific queries better… (more)

Subjects/Keywords: Computer Network; Data Mining; Nurturers; Collaboration Networks; Collaborative Filtering; Recommender Systems; Social Network Analysis; Scouts; Promoters; Connectors; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bharath Kumar, M. (2006). Discovering Roles In The Evolution Of Collaboration Networks. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/446

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bharath Kumar, M. “Discovering Roles In The Evolution Of Collaboration Networks.” 2006. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/446.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bharath Kumar, M. “Discovering Roles In The Evolution Of Collaboration Networks.” 2006. Web. 16 Dec 2018.

Vancouver:

Bharath Kumar M. Discovering Roles In The Evolution Of Collaboration Networks. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/446.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bharath Kumar M. Discovering Roles In The Evolution Of Collaboration Networks. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/446

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

14. Francis, Mathew C. Intersection Graphs Of Boxes And Cubes.

Degree: 2009, Indian Institute of Science

 A graph Gis said to be an intersection graph of sets from a family of sets if there exists a function ƒ : V(G)→ such… (more)

Subjects/Keywords: Computer Graphics; Boxicity (Graphs); Cubicity (Graphs); Interval Graphs; Halin Graphs; Planar Graphs; Intersection Graphs; Random Graphs; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Francis, M. C. (2009). Intersection Graphs Of Boxes And Cubes. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1027

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Francis, Mathew C. “Intersection Graphs Of Boxes And Cubes.” 2009. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/1027.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Francis, Mathew C. “Intersection Graphs Of Boxes And Cubes.” 2009. Web. 16 Dec 2018.

Vancouver:

Francis MC. Intersection Graphs Of Boxes And Cubes. [Internet] [Thesis]. Indian Institute of Science; 2009. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/1027.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Francis MC. Intersection Graphs Of Boxes And Cubes. [Thesis]. Indian Institute of Science; 2009. Available from: http://hdl.handle.net/2005/1027

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

15. Roy, Sharmili. Pricing Network Resources : A New Perspective.

Degree: 2006, Indian Institute of Science

 The aim of the work is to examine the issue of pricing network resources so as to ensure fair and efficient resource-sharing among users. The… (more)

Subjects/Keywords: Computer Networks; Internet-Pricing; Network Resources - Pricing; Network - Pricing Strategy; Resource Pricing; Pricing Network Resources; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Roy, S. (2006). Pricing Network Resources : A New Perspective. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1081

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Roy, Sharmili. “Pricing Network Resources : A New Perspective.” 2006. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/1081.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Roy, Sharmili. “Pricing Network Resources : A New Perspective.” 2006. Web. 16 Dec 2018.

Vancouver:

Roy S. Pricing Network Resources : A New Perspective. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/1081.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Roy S. Pricing Network Resources : A New Perspective. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/1081

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

16. Biswas, Prasenjit. Hardware Consolidation Of Systolic Algorithms On A Coarse Grained Runtime Reconfigurable Architecture.

Degree: 2011, Indian Institute of Science

 Application domains such as Bio-informatics, DSP, Structural Biology, Fluid Dynamics, high resolution direction finding, state estimation, adaptive noise cancellation etc. demand high performance computing solutions… (more)

Subjects/Keywords: Computer Architecture; Systolic Algorithms; REDEFINE; Numerical Linear Algebra Kernels; NLA Kernels; Custom Functional Units (CFU); Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Biswas, P. (2011). Hardware Consolidation Of Systolic Algorithms On A Coarse Grained Runtime Reconfigurable Architecture. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2108

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Biswas, Prasenjit. “Hardware Consolidation Of Systolic Algorithms On A Coarse Grained Runtime Reconfigurable Architecture.” 2011. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/2108.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Biswas, Prasenjit. “Hardware Consolidation Of Systolic Algorithms On A Coarse Grained Runtime Reconfigurable Architecture.” 2011. Web. 16 Dec 2018.

Vancouver:

Biswas P. Hardware Consolidation Of Systolic Algorithms On A Coarse Grained Runtime Reconfigurable Architecture. [Internet] [Thesis]. Indian Institute of Science; 2011. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/2108.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Biswas P. Hardware Consolidation Of Systolic Algorithms On A Coarse Grained Runtime Reconfigurable Architecture. [Thesis]. Indian Institute of Science; 2011. Available from: http://hdl.handle.net/2005/2108

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

17. Biswas, Prasenjit. Hardware Consolidation Of Systolic Algorithms On A Coarse Grained Runtime Reconfigurable Architecture.

Degree: 2011, Indian Institute of Science

 Application domains such as Bio-informatics, DSP, Structural Biology, Fluid Dynamics, high resolution direction finding, state estimation, adaptive noise cancellation etc. demand high performance computing solutions… (more)

Subjects/Keywords: Computer Architecture; Systolic Algorithms; REDEFINE; Numerical Linear Algebra Kernels; NLA Kernels; Custom Functional Units (CFU); Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Biswas, P. (2011). Hardware Consolidation Of Systolic Algorithms On A Coarse Grained Runtime Reconfigurable Architecture. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2108 ; http://etd.ncsi.iisc.ernet.in/abstracts/2705/G24895-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Biswas, Prasenjit. “Hardware Consolidation Of Systolic Algorithms On A Coarse Grained Runtime Reconfigurable Architecture.” 2011. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://etd.iisc.ernet.in/handle/2005/2108 ; http://etd.ncsi.iisc.ernet.in/abstracts/2705/G24895-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Biswas, Prasenjit. “Hardware Consolidation Of Systolic Algorithms On A Coarse Grained Runtime Reconfigurable Architecture.” 2011. Web. 16 Dec 2018.

Vancouver:

Biswas P. Hardware Consolidation Of Systolic Algorithms On A Coarse Grained Runtime Reconfigurable Architecture. [Internet] [Thesis]. Indian Institute of Science; 2011. [cited 2018 Dec 16]. Available from: http://etd.iisc.ernet.in/handle/2005/2108 ; http://etd.ncsi.iisc.ernet.in/abstracts/2705/G24895-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Biswas P. Hardware Consolidation Of Systolic Algorithms On A Coarse Grained Runtime Reconfigurable Architecture. [Thesis]. Indian Institute of Science; 2011. Available from: http://etd.iisc.ernet.in/handle/2005/2108 ; http://etd.ncsi.iisc.ernet.in/abstracts/2705/G24895-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

18. Vivekanandham, Rajesh. Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors.

Degree: 2006, Indian Institute of Science

 A Large instruction window is a key requirement to exploit greater Instruction Level Parallelism in out-of-order superscalar processors. Along with the instruction window size, the… (more)

Subjects/Keywords: Parallel Processing (Computer Science); Queing Processes; Queue Design; Scalable Low Power Issue Queue (SLIQ) Microarchitecture; Scalable Low Power Store Queue (SLSQ) Microarchitecture; Superscalar Processors; Large Instruction Window; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vivekanandham, R. (2006). Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/413

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vivekanandham, Rajesh. “Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors.” 2006. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/413.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vivekanandham, Rajesh. “Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors.” 2006. Web. 16 Dec 2018.

Vancouver:

Vivekanandham R. Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/413.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vivekanandham R. Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/413

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

19. Rao, M V Panduranga. Bounds On Augmented Automata And Quantum Adiabatic Optimization.

Degree: 2007, Indian Institute of Science

 Quantum computing has generated a lot of interested in the past two decades. Research into powerful models of quantum computation has yielded important and elegant… (more)

Subjects/Keywords: Quantum Theory; Computer Science - Quantum Theory; Quantum Computing; Quantum Computing - Interference; Quantum Adiabatic Algorithms; Quantum Finite Automata; Quantum Adiabatic Optimization; Bounds; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rao, M. V. P. (2007). Bounds On Augmented Automata And Quantum Adiabatic Optimization. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/518

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rao, M V Panduranga. “Bounds On Augmented Automata And Quantum Adiabatic Optimization.” 2007. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/518.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rao, M V Panduranga. “Bounds On Augmented Automata And Quantum Adiabatic Optimization.” 2007. Web. 16 Dec 2018.

Vancouver:

Rao MVP. Bounds On Augmented Automata And Quantum Adiabatic Optimization. [Internet] [Thesis]. Indian Institute of Science; 2007. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/518.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rao MVP. Bounds On Augmented Automata And Quantum Adiabatic Optimization. [Thesis]. Indian Institute of Science; 2007. Available from: http://hdl.handle.net/2005/518

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

20. Jindal, Prachee. Compiler Assisted Energy Management For Sensor Network Nodes.

Degree: 2008, Indian Institute of Science

 Emerging low power, embedded, wireless sensor devices are useful for wide range of applications, yet have very limited processing storage and especially energy resources. Sensor… (more)

Subjects/Keywords: Sensor Networks - Data Processing; Electronic Detector Networks; Data Processing; Compilers (Computer Science); Dynamic Voltage Scaling; Energy Optimization; Scratchpad Memory; Sensor Node Architecture; Sensor Network Node; Node Architecture; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jindal, P. (2008). Compiler Assisted Energy Management For Sensor Network Nodes. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/819

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jindal, Prachee. “Compiler Assisted Energy Management For Sensor Network Nodes.” 2008. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/819.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jindal, Prachee. “Compiler Assisted Energy Management For Sensor Network Nodes.” 2008. Web. 16 Dec 2018.

Vancouver:

Jindal P. Compiler Assisted Energy Management For Sensor Network Nodes. [Internet] [Thesis]. Indian Institute of Science; 2008. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/819.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jindal P. Compiler Assisted Energy Management For Sensor Network Nodes. [Thesis]. Indian Institute of Science; 2008. Available from: http://hdl.handle.net/2005/819

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

21. Srikanth, Cherukupally. Large Scale Implementation Of The Block Lanczos Algorithm.

Degree: 2008, Indian Institute of Science

 Large sparse matrices arise in many applications, especially in the major problems of Cryptography of factoring integers and computing discrete logarithms. We focus attention on… (more)

Subjects/Keywords: Block Lanczos Algorithm; Algorithms (Computer Science); Sieve Matrices; Number Field Sieve (NFS); Wiedemann Algorithm; Sparse Matrices; Block Lanczos; Sieve Matrix; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Srikanth, C. (2008). Large Scale Implementation Of The Block Lanczos Algorithm. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/820

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Srikanth, Cherukupally. “Large Scale Implementation Of The Block Lanczos Algorithm.” 2008. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/820.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Srikanth, Cherukupally. “Large Scale Implementation Of The Block Lanczos Algorithm.” 2008. Web. 16 Dec 2018.

Vancouver:

Srikanth C. Large Scale Implementation Of The Block Lanczos Algorithm. [Internet] [Thesis]. Indian Institute of Science; 2008. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/820.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Srikanth C. Large Scale Implementation Of The Block Lanczos Algorithm. [Thesis]. Indian Institute of Science; 2008. Available from: http://hdl.handle.net/2005/820

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

22. Rajan, Kaushik. Efficient Cache Organization For Application Specific And General Purpose Processors.

Degree: 2008, Indian Institute of Science

 The performance gap between processor and memory continues to remain a major performance bottleneck in both application specific and general purpose processors. This thesis strives… (more)

Subjects/Keywords: Internet Cache Organization (Computer Science); Internet Microprocessors; Processor Architectures; Packet Forwarding Engines (Routers); General Purpose Processors; Heterogeneously Segmented Cache Architecture; Shephepherd Cache; Cache Architecture; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rajan, K. (2008). Efficient Cache Organization For Application Specific And General Purpose Processors. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/838

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rajan, Kaushik. “Efficient Cache Organization For Application Specific And General Purpose Processors.” 2008. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/838.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rajan, Kaushik. “Efficient Cache Organization For Application Specific And General Purpose Processors.” 2008. Web. 16 Dec 2018.

Vancouver:

Rajan K. Efficient Cache Organization For Application Specific And General Purpose Processors. [Internet] [Thesis]. Indian Institute of Science; 2008. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/838.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rajan K. Efficient Cache Organization For Application Specific And General Purpose Processors. [Thesis]. Indian Institute of Science; 2008. Available from: http://hdl.handle.net/2005/838

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

23. Nasre, Rupesh. Scaling Context-Sensitive Points-To Analysis.

Degree: 2012, Indian Institute of Science

 Pointer analysis is one of the key static analyses during compilation. The efficiency of several compiler optimizations and transformations depends directly on the scalability and… (more)

Subjects/Keywords: Compilers; Pointer Analysis (Computer Science); Bloom Filters (Multibloom); Scalable Pointer Analysis; Randomized Pointer Analysis; Context-Sensitive Pointer Analysis; Points-to Analysis; Linear Equations; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nasre, R. (2012). Scaling Context-Sensitive Points-To Analysis. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2309

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nasre, Rupesh. “Scaling Context-Sensitive Points-To Analysis.” 2012. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/2309.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nasre, Rupesh. “Scaling Context-Sensitive Points-To Analysis.” 2012. Web. 16 Dec 2018.

Vancouver:

Nasre R. Scaling Context-Sensitive Points-To Analysis. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/2309.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nasre R. Scaling Context-Sensitive Points-To Analysis. [Thesis]. Indian Institute of Science; 2012. Available from: http://hdl.handle.net/2005/2309

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

24. Nasre, Rupesh. Scaling Context-Sensitive Points-To Analysis.

Degree: 2012, Indian Institute of Science

 Pointer analysis is one of the key static analyses during compilation. The efficiency of several compiler optimizations and transformations depends directly on the scalability and… (more)

Subjects/Keywords: Compilers; Pointer Analysis (Computer Science); Bloom Filters (Multibloom); Scalable Pointer Analysis; Randomized Pointer Analysis; Context-Sensitive Pointer Analysis; Points-to Analysis; Linear Equations; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nasre, R. (2012). Scaling Context-Sensitive Points-To Analysis. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2309 ; http://etd.ncsi.iisc.ernet.in/abstracts/2969/G25097-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nasre, Rupesh. “Scaling Context-Sensitive Points-To Analysis.” 2012. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://etd.iisc.ernet.in/handle/2005/2309 ; http://etd.ncsi.iisc.ernet.in/abstracts/2969/G25097-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nasre, Rupesh. “Scaling Context-Sensitive Points-To Analysis.” 2012. Web. 16 Dec 2018.

Vancouver:

Nasre R. Scaling Context-Sensitive Points-To Analysis. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2018 Dec 16]. Available from: http://etd.iisc.ernet.in/handle/2005/2309 ; http://etd.ncsi.iisc.ernet.in/abstracts/2969/G25097-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nasre R. Scaling Context-Sensitive Points-To Analysis. [Thesis]. Indian Institute of Science; 2012. Available from: http://etd.iisc.ernet.in/handle/2005/2309 ; http://etd.ncsi.iisc.ernet.in/abstracts/2969/G25097-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

25. Prabhu, Nikita. Image Representation using Attribute-Graphs.

Degree: 2016, Indian Institute of Science

 In a digital world of Flickr, Picasa and Google Images, developing a semantic image represen-tation has become a vital problem. Image processing and computer vision… (more)

Subjects/Keywords: Attribute-Graphs; Image Representation; Convolutional Neural Networks; Graphs; Attribute-Graph; Image Ranking; Datasets; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Prabhu, N. (2016). Image Representation using Attribute-Graphs. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2918

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Prabhu, Nikita. “Image Representation using Attribute-Graphs.” 2016. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/2918.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Prabhu, Nikita. “Image Representation using Attribute-Graphs.” 2016. Web. 16 Dec 2018.

Vancouver:

Prabhu N. Image Representation using Attribute-Graphs. [Internet] [Thesis]. Indian Institute of Science; 2016. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/2918.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Prabhu N. Image Representation using Attribute-Graphs. [Thesis]. Indian Institute of Science; 2016. Available from: http://hdl.handle.net/2005/2918

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

26. Roy, Arnab. Study of Proteome and Transcriptome of Escherichia Coli Bacteria to Probe its Regulatory Aspects.

Degree: 2015, Indian Institute of Science

 The information flow through the regulatory networks in biological systems has been a rapidly growing field of research. Translation, being a very important regulatory check… (more)

Subjects/Keywords: Proteomics; Transcriptomics; Escherichia coli - Transcriptomics Analysis; E coli - Omics; tRNA Mutant; Proteome; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Roy, A. (2015). Study of Proteome and Transcriptome of Escherichia Coli Bacteria to Probe its Regulatory Aspects. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3932 ; http://etd.iisc.ernet.in/abstracts/4810/G27184-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Roy, Arnab. “Study of Proteome and Transcriptome of Escherichia Coli Bacteria to Probe its Regulatory Aspects.” 2015. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://etd.iisc.ernet.in/2005/3932 ; http://etd.iisc.ernet.in/abstracts/4810/G27184-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Roy, Arnab. “Study of Proteome and Transcriptome of Escherichia Coli Bacteria to Probe its Regulatory Aspects.” 2015. Web. 16 Dec 2018.

Vancouver:

Roy A. Study of Proteome and Transcriptome of Escherichia Coli Bacteria to Probe its Regulatory Aspects. [Internet] [Thesis]. Indian Institute of Science; 2015. [cited 2018 Dec 16]. Available from: http://etd.iisc.ernet.in/2005/3932 ; http://etd.iisc.ernet.in/abstracts/4810/G27184-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Roy A. Study of Proteome and Transcriptome of Escherichia Coli Bacteria to Probe its Regulatory Aspects. [Thesis]. Indian Institute of Science; 2015. Available from: http://etd.iisc.ernet.in/2005/3932 ; http://etd.iisc.ernet.in/abstracts/4810/G27184-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

27. Kumar, V Santhosh. Improving The Communication Performance Of I/O Intensive And Communication Intensive Application In Cluster Computer Systems.

Degree: 2006, Indian Institute of Science

 Cluster computer systems assembled from commodity off-the-shelf components have emerged as a viable and cost-effective alternative to high-end custom parallel computer systems.In this thesis, we… (more)

Subjects/Keywords: Computer Communication; Input/output Communication; Database Query Processing; Community Atmospheric Model (CAM); Network Processors; Bloom Filter Processing; Cluster Computer Systems; Offloading Application; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kumar, V. S. (2006). Improving The Communication Performance Of I/O Intensive And Communication Intensive Application In Cluster Computer Systems. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/453

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kumar, V Santhosh. “Improving The Communication Performance Of I/O Intensive And Communication Intensive Application In Cluster Computer Systems.” 2006. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/453.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kumar, V Santhosh. “Improving The Communication Performance Of I/O Intensive And Communication Intensive Application In Cluster Computer Systems.” 2006. Web. 16 Dec 2018.

Vancouver:

Kumar VS. Improving The Communication Performance Of I/O Intensive And Communication Intensive Application In Cluster Computer Systems. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/453.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kumar VS. Improving The Communication Performance Of I/O Intensive And Communication Intensive Application In Cluster Computer Systems. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/453

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

28. Bharadwaj, Subramanya B V. The Isoperimetric Problem On Trees And Bounded Tree Width Graphs.

Degree: 2008, Indian Institute of Science

 In this thesis we study the isoperimetric problem on trees and graphs with bounded treewidth. Let G = (V,E) be a finite, simple and undirected… (more)

Subjects/Keywords: Computer Graphics - Algorithms; Computer Graphics - Mathematical Models; Isoperimetric Inequalities; Meta-Fibonacci Sequences; Graph Theory; Trees (Graph Theory); Treewidth Graphs; Weighted Graphs; Infinite Binary Tree; Isoperimetric Problem; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bharadwaj, S. B. V. (2008). The Isoperimetric Problem On Trees And Bounded Tree Width Graphs. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/844

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bharadwaj, Subramanya B V. “The Isoperimetric Problem On Trees And Bounded Tree Width Graphs.” 2008. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/844.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bharadwaj, Subramanya B V. “The Isoperimetric Problem On Trees And Bounded Tree Width Graphs.” 2008. Web. 16 Dec 2018.

Vancouver:

Bharadwaj SBV. The Isoperimetric Problem On Trees And Bounded Tree Width Graphs. [Internet] [Thesis]. Indian Institute of Science; 2008. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/844.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bharadwaj SBV. The Isoperimetric Problem On Trees And Bounded Tree Width Graphs. [Thesis]. Indian Institute of Science; 2008. Available from: http://hdl.handle.net/2005/844

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

29. Yadwadkar, Neeraja. Discovery Of Application Workloads From Network File Traces.

Degree: 2009, Indian Institute of Science

 An understanding of Input/Output data access patterns of applications is useful in several situations. First, gaining an insight into what applications are doing with their… (more)

Subjects/Keywords: File Tracing (Computer Networks); Computer Communication; Profile Hidden Markov Models; Sequence Alignment; Network File System (NFS); Network File Traces; Hidden Markov Models (HMMs); Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yadwadkar, N. (2009). Discovery Of Application Workloads From Network File Traces. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1213

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yadwadkar, Neeraja. “Discovery Of Application Workloads From Network File Traces.” 2009. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/1213.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yadwadkar, Neeraja. “Discovery Of Application Workloads From Network File Traces.” 2009. Web. 16 Dec 2018.

Vancouver:

Yadwadkar N. Discovery Of Application Workloads From Network File Traces. [Internet] [Thesis]. Indian Institute of Science; 2009. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/1213.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yadwadkar N. Discovery Of Application Workloads From Network File Traces. [Thesis]. Indian Institute of Science; 2009. Available from: http://hdl.handle.net/2005/1213

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

30. Margoor, Amogh. Improving the Precision of a Scalable Demand-Driven Null- Dereference Verification for Java.

Degree: 2013, Indian Institute of Science

 The problem addressed in this thesis is sound, scalable, demand-driven null-dereference verification for Java programs via over-approximated weakest preconditions analysis. The base version of this… (more)

Subjects/Keywords: Java (Computer Programme Language); Java Programs - Verification; Java Collections; Java Maps; Java Programs - Base Analysis; Computer Programs - Verification; Java Container Class Methods; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Margoor, A. (2013). Improving the Precision of a Scalable Demand-Driven Null- Dereference Verification for Java. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/3284

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Margoor, Amogh. “Improving the Precision of a Scalable Demand-Driven Null- Dereference Verification for Java.” 2013. Thesis, Indian Institute of Science. Accessed December 16, 2018. http://hdl.handle.net/2005/3284.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Margoor, Amogh. “Improving the Precision of a Scalable Demand-Driven Null- Dereference Verification for Java.” 2013. Web. 16 Dec 2018.

Vancouver:

Margoor A. Improving the Precision of a Scalable Demand-Driven Null- Dereference Verification for Java. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2018 Dec 16]. Available from: http://hdl.handle.net/2005/3284.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Margoor A. Improving the Precision of a Scalable Demand-Driven Null- Dereference Verification for Java. [Thesis]. Indian Institute of Science; 2013. Available from: http://hdl.handle.net/2005/3284

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2] [3] [4] [5] … [16]

.