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Euskal Herriko Unibertsitatea / Universidad del País Vasco
1.
Pérez López, Juan Eduardo.
Assisted Interaction for Improving Web Accessibility: An Approach Driven and Tested by Userswith Disabilities
.
Degree: 2020, Euskal Herriko Unibertsitatea / Universidad del País Vasco
URL: http://hdl.handle.net/10810/50417 
► Un porcentaje cada vez mayor de la población mundial depende de la Web para trabajar, socializar, opara informarse entre otras muchas actividades. Los beneficios de…
(more)
▼ Un porcentaje cada vez mayor de la población mundial depende de la Web para trabajar, socializar, opara informarse entre otras muchas actividades. Los beneficios de la Web son todavía más cruciales paralas personas con discapacidades ya que les permite realizar un sinfín de tareas que en el mundo físico lesestán restringidas debido distintas barreras de accesibilidad. A pesar de sus ventajas, la mayoría depáginas web suelen ignoran las necesidades especiales de las personas con discapacidad, e incluyen undiseño único para todos los usuarios. Existen diversos métodos para combatir este problema, como porejemplo los sistemas de ¿transcoding¿, que transforman automáticamente páginas web inaccesibles enaccesibles. Para mejorar la accesibilidad web a grupos específicos de personas, estos métodos requiereninformación sobre las técnicas de adaptación más adecuadas que deben aplicarse.En esta tesis se han realizado una serie de estudios sobre la idoneidad de diversas técnicas de adaptaciónpara mejorar la navegación web para dos grupos diferentes de personas con discapacidad: personas conmovilidad reducida en miembros superiores y personas con baja visión. Basado en revisionesbibliográficas y estudios observacionales, se han desarrollado diferentes adaptaciones de interfaces web ytécnicas alternativas de interacción, que posteriormente han sido evaluadas a lo largo de varios estudioscon usuarios con necesidades especiales. Mediante análisis cualitativos y cuantitativos del rendimiento yla satisfacción de los participantes, se han evaluado diversas adaptaciones de interfaz y métodosalternativos de interacción. Los resultados han demostrado que las técnicas probadas mejoran el acceso ala Web y que los beneficios varían según la tecnología asistiva usada para acceder al ordenador.
Advisors/Committee Members: Arrue Recondo, Myriam (advisor), Abascal González, Julio (advisor).
Subjects/Keywords: computer architecture;
arquitectura de computadores
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APA (6th Edition):
Pérez López, J. E. (2020). Assisted Interaction for Improving Web Accessibility: An Approach Driven and Tested by Userswith Disabilities
. (Doctoral Dissertation). Euskal Herriko Unibertsitatea / Universidad del País Vasco. Retrieved from http://hdl.handle.net/10810/50417
Chicago Manual of Style (16th Edition):
Pérez López, Juan Eduardo. “Assisted Interaction for Improving Web Accessibility: An Approach Driven and Tested by Userswith Disabilities
.” 2020. Doctoral Dissertation, Euskal Herriko Unibertsitatea / Universidad del País Vasco. Accessed April 12, 2021.
http://hdl.handle.net/10810/50417.
MLA Handbook (7th Edition):
Pérez López, Juan Eduardo. “Assisted Interaction for Improving Web Accessibility: An Approach Driven and Tested by Userswith Disabilities
.” 2020. Web. 12 Apr 2021.
Vancouver:
Pérez López JE. Assisted Interaction for Improving Web Accessibility: An Approach Driven and Tested by Userswith Disabilities
. [Internet] [Doctoral dissertation]. Euskal Herriko Unibertsitatea / Universidad del País Vasco; 2020. [cited 2021 Apr 12].
Available from: http://hdl.handle.net/10810/50417.
Council of Science Editors:
Pérez López JE. Assisted Interaction for Improving Web Accessibility: An Approach Driven and Tested by Userswith Disabilities
. [Doctoral Dissertation]. Euskal Herriko Unibertsitatea / Universidad del País Vasco; 2020. Available from: http://hdl.handle.net/10810/50417
Nelson Mandela Metropolitan University
2.
Barnes, Meredith Anne.
A comprehensive evaluation framework for system modernization : a case study using data services.
Degree: Faculty of Science, 2011, Nelson Mandela Metropolitan University
URL: http://hdl.handle.net/10948/1499
► Modernization is a solution to migrate cumbersome existing systems to a new architecture for improved longevity of business processes. Three modernization approaches exist. White-box and…
(more)
▼ Modernization is a solution to migrate cumbersome existing systems to a new architecture for improved longevity of business processes. Three modernization approaches exist. White-box and black-box modernization are distinct from one another. Grey-box modernization is a hybrid of the white-box and black-box approaches. Modernization can be utilised to create data services for a Service Oriented Architecture. Since it is unclear which modernization approach is more suitable for the development of data services, a comprehensive evaluation framework is proposed to evaluate which of the white- or black-box approaches is more suitable. The comprehensive framework consists of three evaluation components. Firstly, developer effort to modernize existing code is measured by acknowledged software metrics. Secondly, the quality of the data services is measured against identified Quality of Service criteria for data services in particular. Thirdly, the effectiveness of the modernized data services is measured through usability evaluations. By inspection of the combination of application of each of the evaluation components, a recommended approach is identified for the modernization of data services. The comprehensive framework was successfully employed to compare the white-box and black-box modernization approaches applied to a case study. Results indicated that had only a single evaluation component been used, inconclusive results of the more suitable approach may have been obtained. The findings of this research contribute a comprehensive evaluation framework which can be applied to compare modernization approaches and measure modernization success.
Subjects/Keywords: Computer architecture
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APA (6th Edition):
Barnes, M. A. (2011). A comprehensive evaluation framework for system modernization : a case study using data services. (Thesis). Nelson Mandela Metropolitan University. Retrieved from http://hdl.handle.net/10948/1499
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Barnes, Meredith Anne. “A comprehensive evaluation framework for system modernization : a case study using data services.” 2011. Thesis, Nelson Mandela Metropolitan University. Accessed April 12, 2021.
http://hdl.handle.net/10948/1499.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Barnes, Meredith Anne. “A comprehensive evaluation framework for system modernization : a case study using data services.” 2011. Web. 12 Apr 2021.
Vancouver:
Barnes MA. A comprehensive evaluation framework for system modernization : a case study using data services. [Internet] [Thesis]. Nelson Mandela Metropolitan University; 2011. [cited 2021 Apr 12].
Available from: http://hdl.handle.net/10948/1499.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Barnes MA. A comprehensive evaluation framework for system modernization : a case study using data services. [Thesis]. Nelson Mandela Metropolitan University; 2011. Available from: http://hdl.handle.net/10948/1499
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Delaware
3.
Garcia, Elkin.
Toward high performance and energy efficiency on many-core architectures.
Degree: PhD, University of Delaware, Department of Electrical and Computer Engineering, 2014, University of Delaware
URL: http://udspace.udel.edu/handle/19716/16724
► The research proposed in this thesis will provide an analysis of these new scenarios, proposing new methodologies and solutions that leverage these new challenges in…
(more)
▼ The research proposed in this thesis will provide an analysis of these new scenarios, proposing new methodologies and solutions that leverage these new challenges in order to increase the performance and energy efficiency of modern many-core architectures. During the pursue of these objectives, this research intends to answer the following question: 1. Which is the impact of low-level compiler transformations such as tiling and percolation to effectively produce high performance code for many-core architectures? 2. What are the tradeoffs of static and dynamic scheduling techniques to efficiently schedule fine grain tasks with hundreds of threads sharing multiple resources under different conditions in a single chip? 3. Which hardware
architecture features can contribute to better scalability and higher performance of scheduling techniques on many-core architectures on a single-chip? 4. How to effectively model high performance programs on many-core architectures under resource coordination conditions? 5. How to efficiently model energy consumption on many-cores managing tradeoffs between scalability and accuracy? 6. Which are feasible methodologies for designing power-aware tiling transformations on many-core architectures? (Abstract shortened by UMI.)
Advisors/Committee Members: Gao, Guang R..
Subjects/Keywords: Computer architecture.
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APA (6th Edition):
Garcia, E. (2014). Toward high performance and energy efficiency on many-core architectures. (Doctoral Dissertation). University of Delaware. Retrieved from http://udspace.udel.edu/handle/19716/16724
Chicago Manual of Style (16th Edition):
Garcia, Elkin. “Toward high performance and energy efficiency on many-core architectures.” 2014. Doctoral Dissertation, University of Delaware. Accessed April 12, 2021.
http://udspace.udel.edu/handle/19716/16724.
MLA Handbook (7th Edition):
Garcia, Elkin. “Toward high performance and energy efficiency on many-core architectures.” 2014. Web. 12 Apr 2021.
Vancouver:
Garcia E. Toward high performance and energy efficiency on many-core architectures. [Internet] [Doctoral dissertation]. University of Delaware; 2014. [cited 2021 Apr 12].
Available from: http://udspace.udel.edu/handle/19716/16724.
Council of Science Editors:
Garcia E. Toward high performance and energy efficiency on many-core architectures. [Doctoral Dissertation]. University of Delaware; 2014. Available from: http://udspace.udel.edu/handle/19716/16724
Universidad Nacional de Colombia
4.
Hincapié Sánchez, Andrés Felipe.
Disrupción digital: diálogos entre arquitectura - Téchne - prácticas artísticas.
Degree: http://bdigital.unal.edu.co/54641/, 2016, Universidad Nacional de Colombia
URL: http://bdigital.unal.edu.co/54641/1/1036931897.2016.pdf
► Al establecer estos diálogos pretendo generar laboratorios de enfrentamiento y ejercicio transdisciplinar en el campo de las prácticas artísticas, haciendo uso de técnicas y tecnologías…
(more)
▼ Al establecer estos diálogos pretendo generar laboratorios de enfrentamiento y ejercicio transdisciplinar en el campo de las prácticas artísticas, haciendo uso de técnicas y tecnologías propias de otras disciplinas que tradicionalmente han sido usadas en el ámbito de la arquitectura como medios e instrumentos de creación. En este sentido, las nuevas tecnologías definen los motores de creación que amplían el espectro formal de las prácticas artísticas. Entenderemos la técnica como un espacio donde se despliega la condición humana, la colaboración entre hombre y materia para configurar mundo es decir Espacio. El tiempo figura como un vector donde el hombre, vitalizándolo y exteriorizándolo, puede construir sus relatos. Conciliar el espacio humano como la forma que a su vez vitalizándolo, construye, hábitats, aquello que la arquitectura ha hecho la base de ocupación. Espacio y tiempo humanos quiere decir, que no hay espacio que no obedezca a una configuración humana y que no hay tiempo que sea básicamente el relato de una memoria tanto individual como colectiva. Las técnicas configuran el espacio virtual .Espacio y tiempo aparecen como el horizonte donde la hominización se despliega. Si se modifica la técnica, se modifican las condiciones espacio / temporales en las cuales el hombre cambia, porque cambian sus condiciones y su relación de constitución con el entorno. No hay un hombre o un entorno que esté por fuera de un despliegue tecnológico. La técnica aparece como el espacio donde el hombre y el mundo se configuran para armar espacios de existencia. Cuando miro los espacios técnicos desde esta perspectiva, encuentro que las prácticas artísticas son unas técnicas y enfocándome en su carácter de poiética se aprovechan para innovar y para generar procesos de investigación. ¿Qué pasa hoy con las nuevas tecnologías? Son una DISRUPCION DIGITAL y según lo muestra Michel Serres, son el vector de hominización que ha logrado plantear en los procesos de configuración de las técnicas contemporáneas, nuevas formas de ser, nuevos cuerpos, por tanto nuevos tipos de experiencia. Estas experiencias se han llamado experiencias simuladas o experiencias virtuales. Esos nuevos espacios son espacios digitales que llamamos: redes, nodos y líneas de fuga. Al igual esos nuevos tiempos permiten hablar de espacios fragmentados; son memorias propias, son temporalidades propias, son nuevos discursos y narrativas que me soportan las formas de actual. Espacios digitales como cuerpos fragmentados y con experiencias simuladas. Se han elegido unos espacios que han sido llamados espacios selectivos en los cuales desplegaré estos ejercicios, para literalmente “ponerlos en obra” y “exhibirlos”, pues es justo allí donde el ejercicio intenta inscribirse como una práctica artístico-estética. Para hacer visible el proceso se hace uso de lo que he designado como nuevas superficies: cuerpo, espacio, fotografía y luz. Estos deberán ser redefinidos y reapropiados, para ponerlos en otros contextos y producir nuevos espacios. Se trata pues de proponer un…
Subjects/Keywords: 72 Arquitectura / Architecture; 77 Fotografía y fotografias / Photography & computer art
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APA (6th Edition):
Hincapié Sánchez, A. F. (2016). Disrupción digital: diálogos entre arquitectura - Téchne - prácticas artísticas. (Thesis). Universidad Nacional de Colombia. Retrieved from http://bdigital.unal.edu.co/54641/1/1036931897.2016.pdf
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Hincapié Sánchez, Andrés Felipe. “Disrupción digital: diálogos entre arquitectura - Téchne - prácticas artísticas.” 2016. Thesis, Universidad Nacional de Colombia. Accessed April 12, 2021.
http://bdigital.unal.edu.co/54641/1/1036931897.2016.pdf.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Hincapié Sánchez, Andrés Felipe. “Disrupción digital: diálogos entre arquitectura - Téchne - prácticas artísticas.” 2016. Web. 12 Apr 2021.
Vancouver:
Hincapié Sánchez AF. Disrupción digital: diálogos entre arquitectura - Téchne - prácticas artísticas. [Internet] [Thesis]. Universidad Nacional de Colombia; 2016. [cited 2021 Apr 12].
Available from: http://bdigital.unal.edu.co/54641/1/1036931897.2016.pdf.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Hincapié Sánchez AF. Disrupción digital: diálogos entre arquitectura - Téchne - prácticas artísticas. [Thesis]. Universidad Nacional de Colombia; 2016. Available from: http://bdigital.unal.edu.co/54641/1/1036931897.2016.pdf
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Texas A&M University
5.
Byoun, Jae Guen.
Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU.
Degree: MS, Computer Science, 2018, Texas A&M University
URL: http://hdl.handle.net/1969.1/173719
► Graphics Processing Units (GPUs) have been predominantly accepted for various general purpose applications due to a massive degree of parallelism. The demand for large-scale GPUs…
(more)
▼ Graphics Processing Units (GPUs) have been predominantly accepted for various general purpose
applications due to a massive degree of parallelism. The demand for large-scale GPUs processing
an enormous volume of data with high throughput has been rising rapidly. However, the
performance of the massive parallelism workloads usually suffer from multiple constraints such
as memory bandwidth, high memory latency, and power/energy cost. Also a bandwidth efficient
network design is challenging in large-scale GPUs.
In this research, we focus on mitigating network bottlenecks by effectively reducing the size
of packets transferring through an interconnect network so that the overall system performance
improves.
The unused fraction of each L1 data cache block across a variety of benchmark suits is initially
investigated to see inefficient cache usage. Then, categorizing memory access patterns into several
types we introduce essential micro-architectural enhancements to support filtering out unnecessary
words in packets throughout the reply path. A compression scheme (Dual Pattern Compression)
adequate for packet compression is exploited to effectively reduce the size of reply packets. We
demonstrate that our scheme effectively improves system performance. Our approach yields 39%
IPC improvement across heterogeneous computing and text processing benchmarks over the baseline
cooperating with DPC. Comparing this work with DPC, we achieved 5% IPC improvement
for the overall benchmark suits and 20% IPC increase for favorable workloads to this scheme.
Advisors/Committee Members: Kim, Eun Jung (advisor), Walker, Duncan M. "Hank" (committee member), Hu, Jiang (committee member).
Subjects/Keywords: GPU; computer architecture
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APA ·
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Manager
APA (6th Edition):
Byoun, J. G. (2018). Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/173719
Chicago Manual of Style (16th Edition):
Byoun, Jae Guen. “Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU.” 2018. Masters Thesis, Texas A&M University. Accessed April 12, 2021.
http://hdl.handle.net/1969.1/173719.
MLA Handbook (7th Edition):
Byoun, Jae Guen. “Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU.” 2018. Web. 12 Apr 2021.
Vancouver:
Byoun JG. Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU. [Internet] [Masters thesis]. Texas A&M University; 2018. [cited 2021 Apr 12].
Available from: http://hdl.handle.net/1969.1/173719.
Council of Science Editors:
Byoun JG. Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU. [Masters Thesis]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/173719
Texas A&M University
6.
Byoun, Jae Guen.
Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU.
Degree: MS, Computer Science, 2018, Texas A&M University
URL: http://hdl.handle.net/1969.1/173814
► Graphics Processing Units (GPUs) have been predominantly accepted for various general purpose applications due to a massive degree of parallelism. The demand for large-scale GPUs…
(more)
▼ Graphics Processing Units (GPUs) have been predominantly accepted for various general purpose
applications due to a massive degree of parallelism. The demand for large-scale GPUs processing
an enormous volume of data with high throughput has been rising rapidly. However, the
performance of the massive parallelism workloads usually suffer from multiple constraints such
as memory bandwidth, high memory latency, and power/energy cost. Also a bandwidth efficient
network design is challenging in large-scale GPUs.
In this research, we focus on mitigating network bottlenecks by effectively reducing the size
of packets transferring through an interconnect network so that the overall system performance
improves.
The unused fraction of each L1 data cache block across a variety of benchmark suits is initially
investigated to see inefficient cache usage. Then, categorizing memory access patterns into several
types we introduce essential micro-architectural enhancements to support filtering out unnecessary
words in packets throughout the reply path. A compression scheme (Dual Pattern Compression)
adequate for packet compression is exploited to effectively reduce the size of reply packets. We
demonstrate that our scheme effectively improves system performance. Our approach yields 39%
IPC improvement across heterogeneous computing and text processing benchmarks over the baseline
cooperating with DPC. Comparing this work with DPC, we achieved 5% IPC improvement
for the overall benchmark suits and 20% IPC increase for favorable workloads to this scheme.
Advisors/Committee Members: Kim, Eun Jung (advisor), Walker, Duncan M. "Hank" (committee member), Hu, Jiang (committee member).
Subjects/Keywords: GPU; computer architecture
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APA ·
Chicago ·
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to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Byoun, J. G. (2018). Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/173814
Chicago Manual of Style (16th Edition):
Byoun, Jae Guen. “Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU.” 2018. Masters Thesis, Texas A&M University. Accessed April 12, 2021.
http://hdl.handle.net/1969.1/173814.
MLA Handbook (7th Edition):
Byoun, Jae Guen. “Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU.” 2018. Web. 12 Apr 2021.
Vancouver:
Byoun JG. Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU. [Internet] [Masters thesis]. Texas A&M University; 2018. [cited 2021 Apr 12].
Available from: http://hdl.handle.net/1969.1/173814.
Council of Science Editors:
Byoun JG. Data Traffic Reduction by Exploiting Data Criticality With A Compressor in GPU. [Masters Thesis]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/173814
Oregon State University
7.
Larsen, Steen K.
Offloading of I/O transactions in current CPU architectures.
Degree: PhD, Electrical and Computer Engineering, 2015, Oregon State University
URL: http://hdl.handle.net/1957/55572
► I/O transactions within a computer system have evolved along with other system components (i.e., CPU, memory, video) from programmed I/O (PIO). In current mainstream systems…
(more)
▼ I/O transactions within a
computer system have evolved along with other system components (i.e., CPU, memory, video) from programmed I/O (PIO). In current mainstream systems (spanning from HPC to mobile) the I/O transactions are CPU-centric descriptor-based DMA transactions. The key benefit is that slower I/O devices can DMA write system receive traffic to system memory and DMA read system transmit data at slower device throughput relative to the CPU. With the advent of more cores in a CPU, power restrictions and latency concerns, we show this approach has limitations and based on measurements we propose alternatives to descriptor-based DMA I/O transactions. We explore and quantify performance improvement in three options:
1) iDMA: Embedded smalller core to offload DMA descriptor processing from the larger application-oriented cores, reducing latency up to 16% and increasing bandwidth per pin up to 17%.
2) Hot-Potato: Where latency is a concern we re-visit using WC-buffers for direct I/O CPU transactions and avoiding CPU hardware changes. While keeping a specialized receive I/O device DMA engine, we reduce latency for small messages by 1.5 μs.
3) Device2Device: For applications moving data between devices, we propose how to bypass the CPU, improving latency, power, and CPU utilization.
Advisors/Committee Members: Lee, Ben (advisor), Bose, Bella (committee member).
Subjects/Keywords: CPU; Computer architecture
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APA (6th Edition):
Larsen, S. K. (2015). Offloading of I/O transactions in current CPU architectures. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/55572
Chicago Manual of Style (16th Edition):
Larsen, Steen K. “Offloading of I/O transactions in current CPU architectures.” 2015. Doctoral Dissertation, Oregon State University. Accessed April 12, 2021.
http://hdl.handle.net/1957/55572.
MLA Handbook (7th Edition):
Larsen, Steen K. “Offloading of I/O transactions in current CPU architectures.” 2015. Web. 12 Apr 2021.
Vancouver:
Larsen SK. Offloading of I/O transactions in current CPU architectures. [Internet] [Doctoral dissertation]. Oregon State University; 2015. [cited 2021 Apr 12].
Available from: http://hdl.handle.net/1957/55572.
Council of Science Editors:
Larsen SK. Offloading of I/O transactions in current CPU architectures. [Doctoral Dissertation]. Oregon State University; 2015. Available from: http://hdl.handle.net/1957/55572
University of Michigan
8.
Kloosterman, John.
Data Resource Management in Throughput Processors.
Degree: PhD, Computer Science & Engineering, 2018, University of Michigan
URL: http://hdl.handle.net/2027.42/146122
► Graphics Processing Units (GPUs) are becoming common in data centers for tasks like neural network training and image processing due to their high performance and…
(more)
▼ Graphics Processing Units (GPUs) are becoming common in data centers for tasks like neural network training and image processing due to their high performance and efficiency. GPUs maintain high throughput by running thousands of threads simultaneously, issuing instructions from ready threads to hide latency in others that are stalled. While this is effective for keeping the arithmetic units busy, the challenge in GPU design is moving the data for computation at the same high rate. Any inefficiency in data movement and storage will compromise the throughput and energy efficiency of the system.
Since energy consumption and cooling make up a large part of the cost of provisioning and running and a data center, making GPUs more suitable for this environment requires removing the bottlenecks and overheads that limit their efficiency. The performance of GPU workloads is often limited by the throughput of the memory resources inside each GPU core, and though many of the power-hungry structures in CPUs are not found in GPU designs, there is overhead for storing each thread's state. When sharing a GPU between workloads, contention for resources also causes interference and slowdown.
This thesis develops techniques to manage and streamline the data movement and storage resources in GPUs in each of these places. The first part of this thesis resolves data movement restrictions inside each GPU core. The GPU memory system is optimized for sequential accesses, but many workloads load data in irregular or transposed patterns that cause a throughput bottleneck even when all loads are cache hits. This work identifies and leverages opportunities to merge requests across threads before sending them to the cache. While requests are waiting for merges, they can be reordered to achieve a higher cache hit rate. These methods yielded a 38% speedup for memory throughput limited workloads.
Another opportunity for optimization is found in the register file. Since it must store the registers for thousands of active threads, it is the largest on-chip data storage structure on a GPU. The second work in this thesis replaces the register file with a smaller, more energy-efficient register buffer. Compiler directives allow the GPU to know ahead of time which registers will be accessed, allowing the hardware to store only the registers that will be imminently accessed in the buffer, with the rest moved to main memory. This technique reduced total GPU energy by 11%.
Finally, in a data center, many different applications will be launching GPU jobs, and just as multiple processes can share the same CPU to increase its utilization, running multiple workloads on the same GPU can increase its overall throughput. However, co-runners interfere with each other in unpredictable ways, especially when sharing memory resources. The final part of this thesis controls this interference, allowing a GPU to be shared between two tiers of workloads: one tier with a high performance target and another suitable for batch jobs without deadlines. At a 90% performance…
Advisors/Committee Members: Mahlke, Scott (committee member), Pipe, Kevin Patrick (committee member), Mudge, Trevor N (committee member), Tang, Lingjia (committee member).
Subjects/Keywords: Computer Architecture; Computer Science; Engineering
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Manager
APA (6th Edition):
Kloosterman, J. (2018). Data Resource Management in Throughput Processors. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/146122
Chicago Manual of Style (16th Edition):
Kloosterman, John. “Data Resource Management in Throughput Processors.” 2018. Doctoral Dissertation, University of Michigan. Accessed April 12, 2021.
http://hdl.handle.net/2027.42/146122.
MLA Handbook (7th Edition):
Kloosterman, John. “Data Resource Management in Throughput Processors.” 2018. Web. 12 Apr 2021.
Vancouver:
Kloosterman J. Data Resource Management in Throughput Processors. [Internet] [Doctoral dissertation]. University of Michigan; 2018. [cited 2021 Apr 12].
Available from: http://hdl.handle.net/2027.42/146122.
Council of Science Editors:
Kloosterman J. Data Resource Management in Throughput Processors. [Doctoral Dissertation]. University of Michigan; 2018. Available from: http://hdl.handle.net/2027.42/146122
University of Johannesburg
9.
Naidoo, Chintal Krishna.
Fitting an information security architecture to an enterprise architecture.
Degree: 2009, University of Johannesburg
URL: http://hdl.handle.net/10210/2539
► M.Phil. (Computer Science)
Despite the efforts at international and national level, security continues to pose challenging problems. Firstly, attacks on information systems are increasingly motivated…
(more)
▼ M.Phil. (Computer Science)
Despite the efforts at international and national level, security continues to pose challenging problems. Firstly, attacks on information systems are increasingly motivated by profit rather than by the desire to create disruption for its own sake. Data are illegally mined, increasingly without the user’s knowledge, while the number of variants (and the rate of evolution) of malicious software (malware) is increasing rapidly. Spam is a good example of this evolution. It is becoming a vehicle for viruses and fraudulent and criminal activities, such as spyware, phishing and other forms of malware. Its widespread distribution increasingly relies on botnets, i.e. compromised servers and PCs used as relays without the knowledge of their owners. The increasing deployment of mobile devices (including 3G mobile phones, portable videogames, etc.) and mobile-based network services will pose new challenges, as IP-based services develop rapidly. These could eventually prove to be a more common route for attacks than personal computers since the latter already deploy a significant level of security. Indeed, all new forms of communication platforms and information systems inevitably provide new windows of opportunity for malicious attacks. In order to successfully tackle the problems described above, a strategic approach to information security is required, rather than the implementation of ad hoc solutions and controls. The strategic approach requires the development of an Information Security Architecture. To be effective, an Information Security Architecture that is developed must be aligned with the organisation’s Enterprise Architecture and must be able to incorporate security into each domain of the Enterprise Architecture. This mini dissertation evaluates two current Information Security Architecture models and frameworks to find an Information Security Architecture that aligns with Eskom’s Enterprise Architecture.
Subjects/Keywords: Computer security; Computer architecture
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APA (6th Edition):
Naidoo, C. K. (2009). Fitting an information security architecture to an enterprise architecture. (Thesis). University of Johannesburg. Retrieved from http://hdl.handle.net/10210/2539
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Naidoo, Chintal Krishna. “Fitting an information security architecture to an enterprise architecture.” 2009. Thesis, University of Johannesburg. Accessed April 12, 2021.
http://hdl.handle.net/10210/2539.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Naidoo, Chintal Krishna. “Fitting an information security architecture to an enterprise architecture.” 2009. Web. 12 Apr 2021.
Vancouver:
Naidoo CK. Fitting an information security architecture to an enterprise architecture. [Internet] [Thesis]. University of Johannesburg; 2009. [cited 2021 Apr 12].
Available from: http://hdl.handle.net/10210/2539.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Naidoo CK. Fitting an information security architecture to an enterprise architecture. [Thesis]. University of Johannesburg; 2009. Available from: http://hdl.handle.net/10210/2539
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Euskal Herriko Unibertsitatea / Universidad del País Vasco
10.
Zorrilla Berasategui, Mikel Joseba.
Interoperable technologies for multi-device media services
.
Degree: 2016, Euskal Herriko Unibertsitatea / Universidad del País Vasco
URL: http://hdl.handle.net/10810/19636
► Estamos viviendo una clara y poderosa tendencia hacia aplicaciones basadas en la Web, sustentadas en el progreso de HTML5 y, cada vez, con más dispositivos…
(more)
▼ Estamos viviendo una clara y poderosa tendencia hacia aplicaciones basadas en la Web, sustentadas en el progreso de HTML5 y, cada vez, con más dispositivos capaces de ejecutar este tipo de aplicaciones. Sin embargo, las aplicaciones siempre se ejecutan de forma aislada una de otra, sin una comunicación real entre ellas. Además, el creciente interés en las soluciones de segunda pantalla para ampliar la experiencia del usuario con las televisiones conectadas, evidencia un claro auge del sector y unas expectativas de los usuarios hacia una experiencia más consistente a través de los diferentes dispositivos y los servicios. No obstante, para conseguir esto, actualmente los radiodifusores y los proveedores de servicio tienen que desarrollar e implementar soluciones muy complejas y especializadas para unos dispositivos concretos y unos casos de uso específicos. Es necesario encontrar una solución más versátil e interoperable, que permita la implementación de servicios multimedia de manera independiente del dispositivo final. El reto es modificar el paradigma de desarrollo de servicios conectados, estableciendo las bases para extender las aplicaciones basadas en HTML hacia una forma estándar e interoperable de especificar y desarrollar aplicaciones multimedia avanzadas conectadas a Internet. En este trabajo de investigación se proponen tecnologías interoperables para ofrecer servicios multimedia multi-dispositivo que aborden los siguientes retos: adaptación, sincronización y conexión. Del mismo modo, la investigación propone una solución para complementar los recursos de computación en dos direcciones.
Advisors/Committee Members: Florez Esnal, Julián (advisor), Lafuente Rojo, Julián Alberto (advisor).
Subjects/Keywords: computer architecture;
broadcasting, sound and television;
arquitectura de ordenadores;
radiodifusión, sonido y televisión
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APA (6th Edition):
Zorrilla Berasategui, M. J. (2016). Interoperable technologies for multi-device media services
. (Doctoral Dissertation). Euskal Herriko Unibertsitatea / Universidad del País Vasco. Retrieved from http://hdl.handle.net/10810/19636
Chicago Manual of Style (16th Edition):
Zorrilla Berasategui, Mikel Joseba. “Interoperable technologies for multi-device media services
.” 2016. Doctoral Dissertation, Euskal Herriko Unibertsitatea / Universidad del País Vasco. Accessed April 12, 2021.
http://hdl.handle.net/10810/19636.
MLA Handbook (7th Edition):
Zorrilla Berasategui, Mikel Joseba. “Interoperable technologies for multi-device media services
.” 2016. Web. 12 Apr 2021.
Vancouver:
Zorrilla Berasategui MJ. Interoperable technologies for multi-device media services
. [Internet] [Doctoral dissertation]. Euskal Herriko Unibertsitatea / Universidad del País Vasco; 2016. [cited 2021 Apr 12].
Available from: http://hdl.handle.net/10810/19636.
Council of Science Editors:
Zorrilla Berasategui MJ. Interoperable technologies for multi-device media services
. [Doctoral Dissertation]. Euskal Herriko Unibertsitatea / Universidad del País Vasco; 2016. Available from: http://hdl.handle.net/10810/19636
Universidad Nacional de Colombia
11.
Vela Oñate, Luis Alejandro.
Metodología para la coordinación de diseños técnicos en proyectos de construcción para vivienda de mediana complejidad en Bogotá apoyado en medios digitales.
Degree: http://bdigital.unal.edu.co/52083/, 2016, Universidad Nacional de Colombia
URL: http://bdigital.unal.edu.co/52083/1/luisalejandrovelao%C3%B1ate.2016.pdf
► Los procesos tradicionales para la elaboración de diseños técnicos en proyectos de vivienda multifamiliar de mediana complejidad en Bogotá presentan deficiencias en la integración y…
(more)
▼ Los procesos tradicionales para la elaboración de diseños técnicos en proyectos de vivienda multifamiliar de mediana complejidad en Bogotá presentan deficiencias en la integración y coordinación de la información entre las diferentes disciplinas que participan en su preparación, generándose conflictos y por ende sobrecostos y atrasos que repercuten negativamente en procesos posteriores de ejecución en obra, entrega final y puesta en funcionamiento del mismo.
El presente trabajo de investigación desarrolla una metodología que facilita la coordinación de diseños técnicos a través del uso de herramientas digitales de modelado tridimensional, donde se verifica la integración entre los diferentes componentes arquitectónico, estructural y de instalaciones, estableciéndose procedimientos para la validación y consolidación de la información del mismo.
Abstract. Traditional processes for the preparation of technical designs in multifamily housing projects of medium complexity in Bogotá have deficiencies in the integration and coordination of information between the different disciplines involved in its production, generating conflicts and in consequence cost overruns and delays that adversely affect in construction execution processes, final delivery and operation of the project.
This research develops a methodology that facilitates the coordination of technical designs through the use of 3D digital modeling tools, where the integration is verified among different architectural, structural and installations components, establishing procedures for validation and consolidation of their information.
Subjects/Keywords: 0 Generalidades / Computer science, information & general works; 69 Construcción / Building & construction; 72 Arquitectura / Architecture
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APA (6th Edition):
Vela Oñate, L. A. (2016). Metodología para la coordinación de diseños técnicos en proyectos de construcción para vivienda de mediana complejidad en Bogotá apoyado en medios digitales. (Thesis). Universidad Nacional de Colombia. Retrieved from http://bdigital.unal.edu.co/52083/1/luisalejandrovelao%C3%B1ate.2016.pdf
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Vela Oñate, Luis Alejandro. “Metodología para la coordinación de diseños técnicos en proyectos de construcción para vivienda de mediana complejidad en Bogotá apoyado en medios digitales.” 2016. Thesis, Universidad Nacional de Colombia. Accessed April 12, 2021.
http://bdigital.unal.edu.co/52083/1/luisalejandrovelao%C3%B1ate.2016.pdf.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Vela Oñate, Luis Alejandro. “Metodología para la coordinación de diseños técnicos en proyectos de construcción para vivienda de mediana complejidad en Bogotá apoyado en medios digitales.” 2016. Web. 12 Apr 2021.
Vancouver:
Vela Oñate LA. Metodología para la coordinación de diseños técnicos en proyectos de construcción para vivienda de mediana complejidad en Bogotá apoyado en medios digitales. [Internet] [Thesis]. Universidad Nacional de Colombia; 2016. [cited 2021 Apr 12].
Available from: http://bdigital.unal.edu.co/52083/1/luisalejandrovelao%C3%B1ate.2016.pdf.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Vela Oñate LA. Metodología para la coordinación de diseños técnicos en proyectos de construcción para vivienda de mediana complejidad en Bogotá apoyado en medios digitales. [Thesis]. Universidad Nacional de Colombia; 2016. Available from: http://bdigital.unal.edu.co/52083/1/luisalejandrovelao%C3%B1ate.2016.pdf
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Columbia University
12.
Garcia Cota, Emilio.
Scalable Emulation of Heterogeneous Systems.
Degree: 2019, Columbia University
URL: https://doi.org/10.7916/d8-a78j-z392
► The breakdown of Dennard's transistor scaling has driven computing systems toward application-specific accelerators, which can provide orders-of-magnitude improvements in performance and energy efficiency over general-purpose…
(more)
▼ The breakdown of Dennard's transistor scaling has driven computing systems toward application-specific accelerators, which can provide orders-of-magnitude improvements in performance and energy efficiency over general-purpose processors.
To enable the radical departures from conventional approaches that heterogeneous systems entail, research infrastructure must be able to model processors, memory and accelerators, as well as system-level changes – such as operating system or instruction set architecture (ISA) innovations – that might be needed to realize the accelerators' potential. Unfortunately, existing simulation tools that can support such system-level research are limited by the lack of fast, scalable machine emulators to drive execution.
To fill this need, in this dissertation we first present a novel machine emulator design based on dynamic binary translation that makes the following improvements over the state of the art: it scales on multicore hosts while remaining memory efficient, correctly handles cross-ISA differences in atomic instruction semantics, leverages the host floating point (FP) unit to speed up FP emulation without sacrificing correctness, and can be efficiently instrumented to – among other possible uses – drive the execution of a full-system, cross-ISA simulator with support for accelerators.
We then demonstrate the utility of machine emulation for studying heterogeneous systems by leveraging it to make two additional contributions. First, we quantify the trade-offs in different coupling models for on-chip accelerators. Second, we present a technique to reuse the private memories of on-chip accelerators when they are otherwise inactive to expand the system's last-level cache, thereby reducing the opportunity cost of the accelerators' integration.
Subjects/Keywords: Computer science; Emulators (Computer programs); Computer architecture
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APA ·
Chicago ·
MLA ·
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CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Garcia Cota, E. (2019). Scalable Emulation of Heterogeneous Systems. (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/d8-a78j-z392
Chicago Manual of Style (16th Edition):
Garcia Cota, Emilio. “Scalable Emulation of Heterogeneous Systems.” 2019. Doctoral Dissertation, Columbia University. Accessed April 12, 2021.
https://doi.org/10.7916/d8-a78j-z392.
MLA Handbook (7th Edition):
Garcia Cota, Emilio. “Scalable Emulation of Heterogeneous Systems.” 2019. Web. 12 Apr 2021.
Vancouver:
Garcia Cota E. Scalable Emulation of Heterogeneous Systems. [Internet] [Doctoral dissertation]. Columbia University; 2019. [cited 2021 Apr 12].
Available from: https://doi.org/10.7916/d8-a78j-z392.
Council of Science Editors:
Garcia Cota E. Scalable Emulation of Heterogeneous Systems. [Doctoral Dissertation]. Columbia University; 2019. Available from: https://doi.org/10.7916/d8-a78j-z392
13.
Raghavan, Arun.
Computational Sprinting: Exceeding Sustainable Power in Thermally Constrained Systems.
Degree: 2013, University of Pennsylvania
URL: https://repository.upenn.edu/edissertations/915
► Although process technology trends predict that transistor sizes will continue to shrink for a few more generations, voltage scaling has stalled and thus future chips…
(more)
▼ Although process technology trends predict that transistor sizes will continue to shrink for a few more generations, voltage scaling has stalled and thus future chips are projected to be increasingly more power hungry than previous generations. Particularly in mobile devices which are severely cooling constrained, it is estimated that the peak operation of a future chip could generate heat ten times faster than than the device can sustainably vent.
However, many mobile applications do not demand sustained performance; rather they comprise short bursts of computation in response to sporadic user activity. To improve responsiveness for such applications, this dissertation proposes computational sprinting, in which a system greatly exceeds sustainable power margins (by up to 10Ã?) to provide up to a few seconds of high-performance computation when a user interacts with the device. Computational sprinting exploits the material property of thermal capacitance to temporarily store the excess heat generated when sprinting. After sprinting, the chip returns to sustainable power levels and dissipates the stored heat when the system is idle.
This dissertation: (i) broadly analyzes thermal, electrical, hardware, and software considerations to analyze the feasibility of engineering a system which can provide the responsiveness of a plat- form with 10Ã? higher sustainable power within today's cooling constraints, (ii) leverages existing sources of thermal capacitance to demonstrate sprinting on a real system today, and (iii) identifies the energy-performance characteristics of sprinting operation to determine runtime sprint pacing policies.
Subjects/Keywords: Energy efficient computer architecture; Parallel mobile architecture; Themal-aware computer architecture; Computer Engineering; Computer Sciences
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APA (6th Edition):
Raghavan, A. (2013). Computational Sprinting: Exceeding Sustainable Power in Thermally Constrained Systems. (Thesis). University of Pennsylvania. Retrieved from https://repository.upenn.edu/edissertations/915
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Raghavan, Arun. “Computational Sprinting: Exceeding Sustainable Power in Thermally Constrained Systems.” 2013. Thesis, University of Pennsylvania. Accessed April 12, 2021.
https://repository.upenn.edu/edissertations/915.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Raghavan, Arun. “Computational Sprinting: Exceeding Sustainable Power in Thermally Constrained Systems.” 2013. Web. 12 Apr 2021.
Vancouver:
Raghavan A. Computational Sprinting: Exceeding Sustainable Power in Thermally Constrained Systems. [Internet] [Thesis]. University of Pennsylvania; 2013. [cited 2021 Apr 12].
Available from: https://repository.upenn.edu/edissertations/915.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Raghavan A. Computational Sprinting: Exceeding Sustainable Power in Thermally Constrained Systems. [Thesis]. University of Pennsylvania; 2013. Available from: https://repository.upenn.edu/edissertations/915
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
UCLA
14.
Zhou, Peipei.
A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture).
Degree: Electrical Engineering, 2014, UCLA
URL: http://www.escholarship.org/uc/item/9446s3nx
► Future processor will not be limited by the transistor resources, but will be mainly constrained by energy efficiency. Reconfigurable architecture offers higher energy efficiency than…
(more)
▼ Future processor will not be limited by the transistor resources, but will be mainly constrained by energy efficiency. Reconfigurable architecture offers higher energy efficiency than CPUs through customized hardware and more flexibility than ASICs. FPGAs allow configurability at bit level to keep both efficiency and flexibility. However, in many computation-intensive applications, only word level customizations are necessary, which inspires coarse-grained reconfigurable arrays(CGRAs) to raise configurability to word level and to reduce configuration information, and to enable on-the-fly customization. Traditional CGRAs are designed in the era when transistor resources are scarce. Previous work in CGRAs share hardware resources among different operations via modulo scheduling and time multiplexing processing elements. In the emerging scenario where transistor resources are rich, we develop a novel CGRA architecture that features full pipelining and dynamic composition to improve energy efficiency and implement the prototype on Xilinx Virtex-6 FPGA board. Experiments show that fully pipelined and dynamically composable architecture(FPCA) can exploit the energy benefits of customization for user applications when the transistor resources are rich.
Subjects/Keywords: Electrical engineering; Computer engineering; Computer science; CGRA; composable architecture; computer architecture; full pipeline; reconfigurable architecture
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APA (6th Edition):
Zhou, P. (2014). A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture). (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/9446s3nx
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Zhou, Peipei. “A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture).” 2014. Thesis, UCLA. Accessed April 12, 2021.
http://www.escholarship.org/uc/item/9446s3nx.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Zhou, Peipei. “A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture).” 2014. Web. 12 Apr 2021.
Vancouver:
Zhou P. A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture). [Internet] [Thesis]. UCLA; 2014. [cited 2021 Apr 12].
Available from: http://www.escholarship.org/uc/item/9446s3nx.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Zhou P. A Fully Pipelined and Dynamically Composable Architecture of CGRA (Coarse Grained Reconfigurable Architecture). [Thesis]. UCLA; 2014. Available from: http://www.escholarship.org/uc/item/9446s3nx
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
ETH Zürich
15.
Hua, Hao.
Architectural design as combined modeling.
Degree: 2013, ETH Zürich
URL: http://hdl.handle.net/20.500.11850/77858
Subjects/Keywords: COMPUTER APPLICATIONS IN ARCHITECTURE; COMPUTERANWENDUNGEN IN DER ARCHITEKTUR; CAD (RECHNERGESTÜTZTES ENTWERFEN UND KONSTRUIEREN); CAD (COMPUTER AIDED DESIGN); PROJEKTIERUNG, ENTWURF, PLANUNG (ARCHITEKTUR); PROJECT, DESIGN, PLANNING (ARCHITECTURE); info:eu-repo/classification/ddc/720; Architecture
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APA (6th Edition):
Hua, H. (2013). Architectural design as combined modeling. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/77858
Chicago Manual of Style (16th Edition):
Hua, Hao. “Architectural design as combined modeling.” 2013. Doctoral Dissertation, ETH Zürich. Accessed April 12, 2021.
http://hdl.handle.net/20.500.11850/77858.
MLA Handbook (7th Edition):
Hua, Hao. “Architectural design as combined modeling.” 2013. Web. 12 Apr 2021.
Vancouver:
Hua H. Architectural design as combined modeling. [Internet] [Doctoral dissertation]. ETH Zürich; 2013. [cited 2021 Apr 12].
Available from: http://hdl.handle.net/20.500.11850/77858.
Council of Science Editors:
Hua H. Architectural design as combined modeling. [Doctoral Dissertation]. ETH Zürich; 2013. Available from: http://hdl.handle.net/20.500.11850/77858
ETH Zürich
16.
Lang, Silke Berit.
The impact of video systems on architecture.
Degree: 2005, ETH Zürich
URL: http://hdl.handle.net/20.500.11850/49138
► Today, computers and digital media are common tools and supplies in the field of architecture. Recently, architects also integrate modern information and communication technologies in…
(more)
▼ Today, computers and digital media are common tools and supplies in the field of
architecture. Recently, architects also integrate modern information and communication technologies in their projects. The novel opportunities of these technologies enable two fields of activity: building intelligence and global communication. These two fields allow for the design of spaces that adapt to the changing social and cultural trends. This dissertation investigates video systems, especially three-dimensional video, as a category of information and communication technologies. The thesis presents and discusses solutions how video systems can be applied to overcome space and time distances in the context of
architecture. The dissertation explores the potential of three-dimensional video to interconnect the real and the virtual world by recombining the characteristics of both worlds. This research is embedded in the historical and architectural context of video systems. Various theses are proposed which are tied up to existing technologies and historical development directions are carried on. The contributions and advantages of video systems with respect to
architecture are analyzed and discussed. This research places a strong emphasis on the feasibility and elaboration in an architectural context. The development of prototype applications is the proof of concept, and demonstrates the real world value. To ensure the quality as well as the practicability, the applications and their integration into real locations are discussed with potential users from the industry. In the scope of this research, there is not a füll marketable product developed, but an emergent framework of possibilities to integrate video systems into
architecture. This research is closely linked to the interdisciplinary blue-c project at the ETH Zürich. Within blue-c a new generation of an immersive projection and three-dimensional video acquisition environmentis developed. blue-c integrates areas such as
computer graphics, vision, communication engineering, mechanical engineering, and
architecture.
Computer und digitale Medien sind heute auch im Bereich der Architektur Standardwerkzeuge. Architekten integrieren in jüngster Zeit auch zeitgemäße Informations- und Kommunikationstechnologien in ihre Projekte. Die neuartigen Möglichkeiten, die diese Technologienbieten, bringenzwei Gebietehervor: Intelligente Gebäudeund GlobaleKommunikation. Diese beiden Bereiche ermöglichen es, Räume zu gestalten, die sich den sozialen und kulturellen Veränderungen anpassen. Schwerpunkt dieser wissenschaftlichen Abhandlung sind Videosysteme, insbesondere dreidimensionales Video, die eine Kategorie der Informations- und Kommunikationstechnik darstellen. Die vorliegende Dissertation erörtert, wie im architektonischen Kontext Raum und Zeit mit Hilfe von Videosystemen überbrückt werden können. Diese Arbeit behandelt Möglichkeiten, wie sich mit Hilfe von dreidimensionalen Videosystemen reale und virtuelle Welten miteinander verknüpfen lassen. Die charakteristischen Eigenschaften…
Advisors/Committee Members: Hovestadt, Ludger, Gross, Markus.
Subjects/Keywords: VIDEO ENGINEERING; COMPUTER APPLICATIONS IN ARCHITECTURE; COMPUTERANWENDUNGEN IN DER ARCHITEKTUR; SPACE + SPATIAL COMPOSITION (ARCHITECTURE); RAUM + RAUMKOMPOSITION (ARCHITEKTUR); VIDEOTECHNIK; info:eu-repo/classification/ddc/720; info:eu-repo/classification/ddc/004; Architecture; Data processing, computer science
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APA ·
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MLA ·
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Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Lang, S. B. (2005). The impact of video systems on architecture. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/49138
Chicago Manual of Style (16th Edition):
Lang, Silke Berit. “The impact of video systems on architecture.” 2005. Doctoral Dissertation, ETH Zürich. Accessed April 12, 2021.
http://hdl.handle.net/20.500.11850/49138.
MLA Handbook (7th Edition):
Lang, Silke Berit. “The impact of video systems on architecture.” 2005. Web. 12 Apr 2021.
Vancouver:
Lang SB. The impact of video systems on architecture. [Internet] [Doctoral dissertation]. ETH Zürich; 2005. [cited 2021 Apr 12].
Available from: http://hdl.handle.net/20.500.11850/49138.
Council of Science Editors:
Lang SB. The impact of video systems on architecture. [Doctoral Dissertation]. ETH Zürich; 2005. Available from: http://hdl.handle.net/20.500.11850/49138
Oregon State University
17.
Zier, David A.
The dynamic speculation and performance prediction of parallel
loops.
Degree: PhD, Electrical and Computer Engineering, 2009, Oregon State University
URL: http://hdl.handle.net/1957/11579
► General purpose computer systems have seen increased performance potential through the parallel processing capabilities of multicore processors. Yet this potential performance can only be attained…
(more)
▼ General purpose
computer systems have seen increased performance potential through the parallel processing capabilities of multicore processors. Yet this potential performance can only be attained through parallel applications, thus forcing software developers to rethink how everyday applications are designed. The most readily form of Thread Level Parallelism (TLP) within any program are from loops. Unfortunately, the majority of loops cannot be easily multithreaded due to inter-iteration dependencies, conditional statements, nested functions, and dynamic memory allocation. This dissertation seeks to understand the fundamental characteristics and relationships of loops in order to assist programmers and compilers in exploiting TLP.
First, this dissertation explores a hardware solution that exploits (TLP) through Dynamic Speculative Multithreading (D-SpMT), which can extract multiple threads from a sequential program without compiler support or instruction set extensions. This dissertation presents Cascadia, a D-SpMT multicore
architecture that provides multi-grain thread-level support. Cascadia applies a unique sustainable IPC (sIPC) metric on a comprehensive loop tree to select the best performing nested loop level to multithread. Results showed that Cascadia can extract large amounts of TLP, but ultimately, only yielded moderate performance gains. The lack of overall performance gains exhibited by Cascadia were due to the sequential nature of applications, rather than Cascadia's ability to perform D-SpMT.
In order to fully exploit TLP through loops, some loop level analysis and transformation must first be performed. Therefore, second contribution of this dissertation is the development of several theoretical methodologies to aid programmers and auto-tuners in parallelizing loops. This work found that the inter-iteration dependencies have a two-fold effect on the loop's parallel performance. First, the performance is primarily affected by a single, dominant dependency, and it is the execution of the dominant dependency path that directly determines the parallel performance of the loop. Any additional dependencies cause a secondary effect that may increase the execution time due to relative dependency path differences. Furthermore, this study analyzes the effects of non-ideal conditions, such as a limited number of processors, multithreading overhead, and irregular loop structures.
Advisors/Committee Members: Lee, Ben (advisor), Bose, Bella (committee member).
Subjects/Keywords: Computer Architecture; Simultaneous multithreading processors
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APA (6th Edition):
Zier, D. A. (2009). The dynamic speculation and performance prediction of parallel
loops. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/11579
Chicago Manual of Style (16th Edition):
Zier, David A. “The dynamic speculation and performance prediction of parallel
loops.” 2009. Doctoral Dissertation, Oregon State University. Accessed April 12, 2021.
http://hdl.handle.net/1957/11579.
MLA Handbook (7th Edition):
Zier, David A. “The dynamic speculation and performance prediction of parallel
loops.” 2009. Web. 12 Apr 2021.
Vancouver:
Zier DA. The dynamic speculation and performance prediction of parallel
loops. [Internet] [Doctoral dissertation]. Oregon State University; 2009. [cited 2021 Apr 12].
Available from: http://hdl.handle.net/1957/11579.
Council of Science Editors:
Zier DA. The dynamic speculation and performance prediction of parallel
loops. [Doctoral Dissertation]. Oregon State University; 2009. Available from: http://hdl.handle.net/1957/11579
18.
Rankin, Linda J.
A dual-ported real memory architecture for the g-machine.
Degree: MS, 1986, Oregon Health Sciences University
URL: doi:10.6083/M4BC3WGW
;
http://digitalcommons.ohsu.edu/etd/214
Subjects/Keywords: Computer architecture
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APA (6th Edition):
Rankin, L. J. (1986). A dual-ported real memory architecture for the g-machine. (Thesis). Oregon Health Sciences University. Retrieved from doi:10.6083/M4BC3WGW ; http://digitalcommons.ohsu.edu/etd/214
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Rankin, Linda J. “A dual-ported real memory architecture for the g-machine.” 1986. Thesis, Oregon Health Sciences University. Accessed April 12, 2021.
doi:10.6083/M4BC3WGW ; http://digitalcommons.ohsu.edu/etd/214.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Rankin, Linda J. “A dual-ported real memory architecture for the g-machine.” 1986. Web. 12 Apr 2021.
Vancouver:
Rankin LJ. A dual-ported real memory architecture for the g-machine. [Internet] [Thesis]. Oregon Health Sciences University; 1986. [cited 2021 Apr 12].
Available from: doi:10.6083/M4BC3WGW ; http://digitalcommons.ohsu.edu/etd/214.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Rankin LJ. A dual-ported real memory architecture for the g-machine. [Thesis]. Oregon Health Sciences University; 1986. Available from: doi:10.6083/M4BC3WGW ; http://digitalcommons.ohsu.edu/etd/214
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Utah
19.
Shevgoor, Manjunath.
Enabling big memory with emerging technologies.
Degree: PhD, School of Computing, 2016, University of Utah
URL: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/4108/rec/865
► The demand for main memory capacity has been increasing for many years and will continue to do so. In the past, Dynamic Random Access Memory…
(more)
▼ The demand for main memory capacity has been increasing for many years and will continue to do so. In the past, Dynamic Random Access Memory (DRAM) process scaling has enabled this increase in memory capacity. Along with continued DRAM scaling, the emergence of new technologies like 3D-stacking, buffered Dual Inline Memory Modules (DIMMs), and crosspoint nonvolatile memory promise to continue this trend in the years ahead. However, these technologies will bring with them their own gamut of problems. In this dissertation, I look at the problems facing these technologies from a current delivery perspective. 3D-stacking increases memory capacity available per package, but the increased current requirement means that more pins on the package have to be now dedicated to provide Vdd/Vss, hence increasing cost. At the system level, using buffered DIMMs to increase the number of DRAM ranks increases the peak current requirements of the system if all the DRAM chips in the system are Refreshed simultaneously. Crosspoint memories promise to greatly increase bit densities but have long read latencies because of sneak currents in the cross-bar. In this dissertation, I provide architectural solutions to each of these problems. We observe that smart data placement by the architecture and the Operating System (OS) is a vital ingredient in all of these solutions. We thereby mitigate major bottlenecks in these technologies, hence enabling higher memory densities.
Subjects/Keywords: computer architecture; DRAM; memory
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APA (6th Edition):
Shevgoor, M. (2016). Enabling big memory with emerging technologies. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/4108/rec/865
Chicago Manual of Style (16th Edition):
Shevgoor, Manjunath. “Enabling big memory with emerging technologies.” 2016. Doctoral Dissertation, University of Utah. Accessed April 12, 2021.
http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/4108/rec/865.
MLA Handbook (7th Edition):
Shevgoor, Manjunath. “Enabling big memory with emerging technologies.” 2016. Web. 12 Apr 2021.
Vancouver:
Shevgoor M. Enabling big memory with emerging technologies. [Internet] [Doctoral dissertation]. University of Utah; 2016. [cited 2021 Apr 12].
Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/4108/rec/865.
Council of Science Editors:
Shevgoor M. Enabling big memory with emerging technologies. [Doctoral Dissertation]. University of Utah; 2016. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/4108/rec/865
University of Utah
20.
Kopta, Daniel.
Ray tracing from a data movement perspective.
Degree: PhD, School of Computing, 2016, University of Utah
URL: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/4083/rec/2026
► Ray tracing is becoming more widely adopted in offline rendering systems due to itsnatural support for high quality lighting. Since quality is also a concern…
(more)
▼ Ray tracing is becoming more widely adopted in offline rendering systems due to itsnatural support for high quality lighting. Since quality is also a concern in most real timesystems, we believe ray tracing would be a welcome change in the real time world, but isavoided due to insufficient performance. Since power consumption is one of the primaryfactors limiting the increase of processor performance, it must be addressed as a foremostconcern in any future ray tracing system designs. This will require cooperating advancesin both algorithms and architecture. In this dissertation I study ray tracing system designsfrom a data movement perspective, targeting the various memory resources that are theprimary consumer of power on a modern processor. The result is high performance, lowenergy ray tracing architectures.
Subjects/Keywords: Computer Architecture; Ray Tracing
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APA ·
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to Zotero / EndNote / Reference
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APA (6th Edition):
Kopta, D. (2016). Ray tracing from a data movement perspective. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/4083/rec/2026
Chicago Manual of Style (16th Edition):
Kopta, Daniel. “Ray tracing from a data movement perspective.” 2016. Doctoral Dissertation, University of Utah. Accessed April 12, 2021.
http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/4083/rec/2026.
MLA Handbook (7th Edition):
Kopta, Daniel. “Ray tracing from a data movement perspective.” 2016. Web. 12 Apr 2021.
Vancouver:
Kopta D. Ray tracing from a data movement perspective. [Internet] [Doctoral dissertation]. University of Utah; 2016. [cited 2021 Apr 12].
Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/4083/rec/2026.
Council of Science Editors:
Kopta D. Ray tracing from a data movement perspective. [Doctoral Dissertation]. University of Utah; 2016. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/4083/rec/2026
Texas A&M University
21.
Stenner, Jack Eric.
Critical reflection in a digital media artwork. Playas| Homeland Mirage.
Degree: 2007, Texas A&M University
URL: http://pqdtopen.proquest.com/#viewpdf?dispub=3281007
► The introduction of digital media into the working practice of artists has produced challenges previously unknown to the field of art. This inquiry follows…
(more)
▼ The introduction of digital media into the working practice of artists has produced challenges previously unknown to the field of art. This inquiry follows an atypical model of artist-driven research derived from disciplines such as social science and education. Here, an artwork functions as a model that is self-reflective, integrating methodologies in a form that benefits art and science. Using Naturalistic Inquiry, including semi-structured interviews of fifteen participants, the work illustrates a process of creation, analysis and evaluation that places the values of the artist on equal footing with the needs of science. Recently, artists have begun using video game engines as a tool to produce 3D navigable spaces. Using the hybrid video game/installation <i>Playas: Homeland Mirage</i> as a case study, this research examines the impact of technology on the artwork and identifies a number of key issues related to the function of critical reflection in this environment. Rules-of-play were a fundamental pre-requisite to the stimulation of critically reflective experience. The human interface with software and hardware was also a primary factor in reflective experience. Based on participant evaluation and observation, the interface was altered in response to its effect on critical reflection, illustrating how choices in this area impact aesthetic experience. Those with experience in visual art were more likely to engage the work in a critically reflective manner than seasoned video game players who tended to be more interested in scoring and winning. These findings and others inform our understanding of the stimulation of critical reflection in immersive environments and show how we can sensitively integrate technology with meaningful evaluative methods. By repurposing a video game in this manner, we learn about the nature of the video game and the nature of art. This research enables artists to gain a better understanding of the medium to more fully integrate technology within a meaningful practice. Conversely, other fields will benefit from a better understanding of the stimulation of meaning in immersive spaces and gain a comprehensive view of a work that strives to contribute to our culture on a deeper level than as simple entertainment. Ultimately, more fully understanding critical reflection in virtual environments will enable us to create enriched experiences that transcend space to create “real” or “virtual” place.
Subjects/Keywords: Fine Arts; Architecture; Computer Science
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APA (6th Edition):
Stenner, J. E. (2007). Critical reflection in a digital media artwork. Playas| Homeland Mirage. (Thesis). Texas A&M University. Retrieved from http://pqdtopen.proquest.com/#viewpdf?dispub=3281007
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Stenner, Jack Eric. “Critical reflection in a digital media artwork. Playas| Homeland Mirage.” 2007. Thesis, Texas A&M University. Accessed April 12, 2021.
http://pqdtopen.proquest.com/#viewpdf?dispub=3281007.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Stenner, Jack Eric. “Critical reflection in a digital media artwork. Playas| Homeland Mirage.” 2007. Web. 12 Apr 2021.
Vancouver:
Stenner JE. Critical reflection in a digital media artwork. Playas| Homeland Mirage. [Internet] [Thesis]. Texas A&M University; 2007. [cited 2021 Apr 12].
Available from: http://pqdtopen.proquest.com/#viewpdf?dispub=3281007.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Stenner JE. Critical reflection in a digital media artwork. Playas| Homeland Mirage. [Thesis]. Texas A&M University; 2007. Available from: http://pqdtopen.proquest.com/#viewpdf?dispub=3281007
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Nelson Mandela Metropolitan University
22.
Saunders, Evan.
A framework for mobile SOA using compression.
Degree: Faculty of Science, 2010, Nelson Mandela Metropolitan University
URL: http://hdl.handle.net/10948/1500
► The widely accepted standards of Service-Oriented Architecture (SOA) have changed the way many organisations conduct their everyday business. The significant popularity of mobile devices has…
(more)
▼ The widely accepted standards of Service-Oriented Architecture (SOA) have changed the way many organisations conduct their everyday business. The significant popularity of mobile devices has seen a rapid increase in the rate of mobile technology enhancements, which have become widely used for communication, as well as conducting everyday tasks. An increased requirement in many businesses is for staff not to be tied down to the office. Consequently, mobile devices play an important role in achieving the mobility and information access that people desire. Due to the popularity and increasing use of SOA and mobile devices, Mobile Service-Oriented Architecture (Mobile SOA) has become a new industry catch-phrase. Many challenges, however, exist within the Mobile SOA environment. These issues include limitations on mobile devices, such as a reduced screen size, lack of processing power, insufficient processing memory, limited battery life, poor storage capacity, unreliable network connections, limited bandwidth available and high transfer costs. This research aimed to provide an elegant solution to the issues of a mobile device, which hinders the performance of Mobile SOA. The main objective of this research was to improve the effectiveness and efficiency of Mobile SOA. In order to achieve this goal, a framework was proposed, which supported intelligent compression of files used within a Web Service. The proposed framework provided a set of guidelines that facilitate the quick development of a system. A proof-of-concept prototype was developed, based on these guidelines and the framework design principles. The prototype provided practical evidence of the effectiveness of implementing a system based on the proposed framework. An analytical evaluation was conducted to determine the effectiveness of the prototype within the Mobile SOA environment. A performance evaluation was conducted to determine efficiency it provides. Additionally, the performance evaluation highlighted the decrease in file transfer time, as well as the significant reduction in transfer costs. The analytical and performance evaluations demonstrated that the prototype optimises the effectiveness and efficiency of Mobile SOA. The framework could, thus, be used to facilitate efficient file transfer between a Server and (Mobile) Client.
Subjects/Keywords: Service-oriented architecture (Computer science)
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APA (6th Edition):
Saunders, E. (2010). A framework for mobile SOA using compression. (Thesis). Nelson Mandela Metropolitan University. Retrieved from http://hdl.handle.net/10948/1500
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Saunders, Evan. “A framework for mobile SOA using compression.” 2010. Thesis, Nelson Mandela Metropolitan University. Accessed April 12, 2021.
http://hdl.handle.net/10948/1500.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Saunders, Evan. “A framework for mobile SOA using compression.” 2010. Web. 12 Apr 2021.
Vancouver:
Saunders E. A framework for mobile SOA using compression. [Internet] [Thesis]. Nelson Mandela Metropolitan University; 2010. [cited 2021 Apr 12].
Available from: http://hdl.handle.net/10948/1500.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Saunders E. A framework for mobile SOA using compression. [Thesis]. Nelson Mandela Metropolitan University; 2010. Available from: http://hdl.handle.net/10948/1500
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
23.
Virmani, Deepali.
Design and analysis for sensor network architecture with
new features; -.
Degree: Computer Science, 2012, University of Delhi
URL: http://shodhganga.inflibnet.ac.in/handle/10603/13619
► Wireless sensor networks can provide low cost solution to a variety of real-world problems. Sensors are low cost tiny devices with limited storage, computational capability…
(more)
▼ Wireless sensor networks can provide low cost
solution to a variety of real-world problems. Sensors are low cost
tiny devices with limited storage, computational capability and
power. The large scale deployment of wireless sensor networks is
expected to guarantee real time communication. Devices in sensor
networks have a much smaller memory, constrained energy supply,
less process and communication bandwidth. Topologies of the sensor
networks are constantly changing due to a high node failure rate,
occasional shutdown and abrupt communication interferences. Due to
the nature of the applications supported, sensor networks need to
be densely deployed and have anywhere from thousands to millions of
sensing devices, which are the orders of magnitude larger than
traditional ad hoc mobile networks. In addition, energy
conservation becomes the center of focus due to the limited battery
capacity and the impossibility of recharge in the hostile
environment. With such a vast difference between traditional
networks and sensor networks, it is not appropriate and inefficient
to port previous solutions for ad hoc networks into sensor networks
with only incremental modifications. In this thesis we studied the
existing architecture of wireless sensor networks and came up with
its limitations. To overcome the limitations of existing
architecture and to improve the functionalities of sensor networks,
we propose a new network architecture, which has a set of
indispensable layers specially tailored to the characteristics of
sensor networks. The layers of the proposed architecture are as
follows: Physical layer with power management, Robust and
self-stabilized MAC layer, Application independent data
aggregation, Differentiated packet scheduling, Real time routing
layer, Transport layer and Application layer. This proposed
architecture will be an integrated solution and efficiently address
the following important issues: _ Real-time communication _ Network
congestion reduction and control
Bibliography p.188-197
Advisors/Committee Members: Jain, Satbir, Senani, Raj.
Subjects/Keywords: Computer Science; sensor network architecture
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Manager
APA (6th Edition):
Virmani, D. (2012). Design and analysis for sensor network architecture with
new features; -. (Thesis). University of Delhi. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/13619
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Virmani, Deepali. “Design and analysis for sensor network architecture with
new features; -.” 2012. Thesis, University of Delhi. Accessed April 12, 2021.
http://shodhganga.inflibnet.ac.in/handle/10603/13619.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Virmani, Deepali. “Design and analysis for sensor network architecture with
new features; -.” 2012. Web. 12 Apr 2021.
Vancouver:
Virmani D. Design and analysis for sensor network architecture with
new features; -. [Internet] [Thesis]. University of Delhi; 2012. [cited 2021 Apr 12].
Available from: http://shodhganga.inflibnet.ac.in/handle/10603/13619.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Virmani D. Design and analysis for sensor network architecture with
new features; -. [Thesis]. University of Delhi; 2012. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/13619
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Wisconsin – Milwaukee
24.
ROEHL, NATHAN.
Cloud Based IoT Architecture.
Degree: MS, Computer Science, 2019, University of Wisconsin – Milwaukee
URL: https://dc.uwm.edu/etd/2333
► The Internet of Things (IoT) and cloud computing have grown in popularity over the past decade as the internet becomes faster and more ubiquitous.…
(more)
▼ The Internet of Things (IoT) and cloud computing have grown in popularity over the past decade as the internet becomes faster and more ubiquitous. Cloud platforms are well suited to handle IoT systems as they are accessible and resilient, and they provide a scalable solution to store and analyze large amounts of IoT data. IoT applications are complex software systems and software developers need to have a thorough understanding of the capabilities, limitations,
architecture, and design patterns of cloud platforms and cloud-based IoT tools to build an efficient, maintainable, and customizable IoT application. As the IoT landscape is constantly changing, research into cloud-based IoT platforms is either lacking or out of date. The goal of this thesis is to describe the basic components and requirements for a cloud-based IoT platform, to provide useful insights and experiences in implementing a cloud-based IoT solution using Microsoft Azure, and to discuss some of the shortcomings when combining IoT with a cloud platform.
Advisors/Committee Members: Tian Zhao.
Subjects/Keywords: architecture; cloud; IoT; Computer Sciences
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to Zotero / EndNote / Reference
Manager
APA (6th Edition):
ROEHL, N. (2019). Cloud Based IoT Architecture. (Thesis). University of Wisconsin – Milwaukee. Retrieved from https://dc.uwm.edu/etd/2333
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
ROEHL, NATHAN. “Cloud Based IoT Architecture.” 2019. Thesis, University of Wisconsin – Milwaukee. Accessed April 12, 2021.
https://dc.uwm.edu/etd/2333.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
ROEHL, NATHAN. “Cloud Based IoT Architecture.” 2019. Web. 12 Apr 2021.
Vancouver:
ROEHL N. Cloud Based IoT Architecture. [Internet] [Thesis]. University of Wisconsin – Milwaukee; 2019. [cited 2021 Apr 12].
Available from: https://dc.uwm.edu/etd/2333.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
ROEHL N. Cloud Based IoT Architecture. [Thesis]. University of Wisconsin – Milwaukee; 2019. Available from: https://dc.uwm.edu/etd/2333
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
North Carolina State University
25.
Cui, Hanyu.
Extending Data Prefetching to Cope with Context Switch Misses.
Degree: PhD, Computer Engineering, 2009, North Carolina State University
URL: http://www.lib.ncsu.edu/resolver/1840.16/3328
► Among the various costs of a context switch, its impact on the performance of L2 caches is the most significant because of the resulting high…
(more)
▼ Among the various costs of a context switch, its impact on the performance
of L2 caches is the most significant because of the resulting high miss
penalty. To mitigate the impact of context switches, several OS approaches
have been proposed to reduce the number of context switches. Nevertheless,
frequent context switches are inevitable in certain cases and result in
severe L2 cache performance degradation. Moreover, traditional prefetching
techniques are ineffective in the face of context switches as their
prediction tables are also
subject to loss of content during a context
switch.
To reduce the impact of frequent context switches, we propose restoring a
program's locality by prefetching into the L2 cache the data a program was
using before it was swapped out. A Global History List is used to record a
process' L2 read accesses in LRU order. These accesses are saved along
with the process' context when the process is swapped out and loaded to
guide prefetching when it is swapped in. We also propose a feedback
mechanism that greatly reduces memory traffic incurred by our prefetching
scheme. A phase guided prefetching scheme was also proposed to complement GHL
prefetching. Experiments show significant speedup over baseline architectures
with and without traditional prefetching in the presence of frequent
context switches.
Advisors/Committee Members: Edward Gehringer, Committee Member (advisor), Eric Rotenberg, Committee Member (advisor), Yan Solihin, Committee Member (advisor), Suleyman Sair, Committee Chair (advisor).
Subjects/Keywords: computer architecture; prefetching; context switching
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APA (6th Edition):
Cui, H. (2009). Extending Data Prefetching to Cope with Context Switch Misses. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/3328
Chicago Manual of Style (16th Edition):
Cui, Hanyu. “Extending Data Prefetching to Cope with Context Switch Misses.” 2009. Doctoral Dissertation, North Carolina State University. Accessed April 12, 2021.
http://www.lib.ncsu.edu/resolver/1840.16/3328.
MLA Handbook (7th Edition):
Cui, Hanyu. “Extending Data Prefetching to Cope with Context Switch Misses.” 2009. Web. 12 Apr 2021.
Vancouver:
Cui H. Extending Data Prefetching to Cope with Context Switch Misses. [Internet] [Doctoral dissertation]. North Carolina State University; 2009. [cited 2021 Apr 12].
Available from: http://www.lib.ncsu.edu/resolver/1840.16/3328.
Council of Science Editors:
Cui H. Extending Data Prefetching to Cope with Context Switch Misses. [Doctoral Dissertation]. North Carolina State University; 2009. Available from: http://www.lib.ncsu.edu/resolver/1840.16/3328
Harvard University
26.
Bitton, Joelle.
Measure of Abstraction: Embodied Fabrication and the Materiality of Intimacy.
Degree: DDes, 2016, Harvard University
URL: http://nrs.harvard.edu/urn-3:HUL.InstRepos:30499026
► This thesis presents a theoretical and practical research conducted for the last 4 years on interactive fabrication. Interactive fabrication is an emerging field and takes…
(more)
▼ This thesis presents a theoretical and practical research conducted for the last 4 years on interactive fabrication.
Interactive fabrication is an emerging field and takes as a starting point with the numerical control of digital fabrication machines, modulated with parameters of interactivity.
I approach digital fabrication as an ambiguous technology in the ways it articulates the digital with the material, the shapeless with the finite, the abstract with the concrete. As the realm of digital fabrication expands into mainstream culture and maverick machines rise again, there is an opportunity to tamper with expectations of precision and proficiency.
Interactivity is the modus operandi for such experimentation: embracing time, latency, distance and the “decor of everyday life” as conditions. Personal data such as emails, text messages or sleeping data can turn into parameters of control of a CNC-machine, supplanting the typical predetermined file. This is the premise for a human-machine companionship or ‘embodied fabrication’.
3 art projects, Twipology, Rabota and Streamline have been prototyped to enact these possibilities. The fabricated outcomes move beyond functional or ornamental categories, inspiring a mutating and odd materiality, one of intimacy. These objects are objects of a third kind, “born witness” of a moment of interaction with the material world.
This thesis is an ‘undisciplinary’ endeavor, proposing a research method involving art, design, ontology and HCI considerations.
Advisors/Committee Members: Picon, Antoine (committee member), Ackermann, Edith (committee member), Witt, Andrew (committee member).
Subjects/Keywords: Architecture; Information Science; Computer Science
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APA (6th Edition):
Bitton, J. (2016). Measure of Abstraction: Embodied Fabrication and the Materiality of Intimacy. (Doctoral Dissertation). Harvard University. Retrieved from http://nrs.harvard.edu/urn-3:HUL.InstRepos:30499026
Chicago Manual of Style (16th Edition):
Bitton, Joelle. “Measure of Abstraction: Embodied Fabrication and the Materiality of Intimacy.” 2016. Doctoral Dissertation, Harvard University. Accessed April 12, 2021.
http://nrs.harvard.edu/urn-3:HUL.InstRepos:30499026.
MLA Handbook (7th Edition):
Bitton, Joelle. “Measure of Abstraction: Embodied Fabrication and the Materiality of Intimacy.” 2016. Web. 12 Apr 2021.
Vancouver:
Bitton J. Measure of Abstraction: Embodied Fabrication and the Materiality of Intimacy. [Internet] [Doctoral dissertation]. Harvard University; 2016. [cited 2021 Apr 12].
Available from: http://nrs.harvard.edu/urn-3:HUL.InstRepos:30499026.
Council of Science Editors:
Bitton J. Measure of Abstraction: Embodied Fabrication and the Materiality of Intimacy. [Doctoral Dissertation]. Harvard University; 2016. Available from: http://nrs.harvard.edu/urn-3:HUL.InstRepos:30499026
Oregon State University
27.
Raisinghani, Manoj H.
Allocation of SISAL program graphs to processors using BLAS.
Degree: MS, Electrical and Computer Engineering, 1994, Oregon State University
URL: http://hdl.handle.net/1957/35764
► There are a number of well known techniques for extracting parallelism from a given program. They range from hardware implementations, building restructuring compilers or reorganizing…
(more)
▼ There are a number of well known techniques for extracting parallelism from a
given program. They range from hardware implementations, building restructuring
compilers or reorganizing of programs so as to specify all the available parallelism. The
success rate of any of the known techniques is rather poor over all types of programs.
This has pushed the research community to explore new languages and design different
architectures to exploit program parallelism.
The principles of dataflow architectures have addressed the problem of exploiting
parallelism in systems by executing dataflow graphs. These graphs or programs represent
data dependencies among instructions and execution of the graph proceeds in a data-driven
manner. That is, an instruction is executed as soon as all its operands are
available, without waiting for any program counter to sequence its execution, as is the
case in conventional von Neumann architectures.
In this thesis, data flow graphs are generated during the intermediate compilation of
a functional language called SISAL (Streams and Iterations in a Single Assignment
Language). The Intermediate Form (IFl) is a graphical language consisting of multiple
acyclic function graphs that represent a given program. Each graph consists of a
sequence of nodes and edges. The nodes specify the operation and the edges indicate the
dependencies between the nodes. The graphs are further connected to each other by
means of implicit dependencies.
The Automator package developed in this project, preprocesses these multiple IF1
graphs and translates them into a single connected graph. It converts all implicit
dependencies into actual ones. Additionally, complex language constructs like For All,
loops and if-then-else are treated in special ways together with their nested levels by the
Automator. There is virtually no limit to the number of nested levels that can be
translated by this package.
The Automator's prime contribution is in translating real programs written in SISAL
into a specified format required by an allocation algorithm called the Balanced Layered
Allocation Scheme (BLAS).
BLAS partitions a connected graph into independent tasks and assigns them to
processors in a multicomputer system. The problem of program allocation lies in
maximizing parallelism while minimizing interprocessor communication costs. Hence,
allocation is based on the best choice of communication to execution ratio for each task.
BLAS utilizes heuristic rules to find a balance between computation and communication
costs in the target system. Here the target
architecture is a simulated nCUBE 3E
computer, having a hypercube topology.
Simulations show that, BLAS is effective in reducing the overall execution time of
a program by considering the communication costs on the execution times. The results
will help in understanding the effects in packing nodes (grain-packing), routing issues in
the network and in general, the allocation problem to any processor in a network. In
addition, tasks have also…
Advisors/Committee Members: Lee, Ben (advisor), Coakley, James (committee member).
Subjects/Keywords: Computer architecture
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APA (6th Edition):
Raisinghani, M. H. (1994). Allocation of SISAL program graphs to processors using BLAS. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/35764
Chicago Manual of Style (16th Edition):
Raisinghani, Manoj H. “Allocation of SISAL program graphs to processors using BLAS.” 1994. Masters Thesis, Oregon State University. Accessed April 12, 2021.
http://hdl.handle.net/1957/35764.
MLA Handbook (7th Edition):
Raisinghani, Manoj H. “Allocation of SISAL program graphs to processors using BLAS.” 1994. Web. 12 Apr 2021.
Vancouver:
Raisinghani MH. Allocation of SISAL program graphs to processors using BLAS. [Internet] [Masters thesis]. Oregon State University; 1994. [cited 2021 Apr 12].
Available from: http://hdl.handle.net/1957/35764.
Council of Science Editors:
Raisinghani MH. Allocation of SISAL program graphs to processors using BLAS. [Masters Thesis]. Oregon State University; 1994. Available from: http://hdl.handle.net/1957/35764
University of Toronto
28.
Chin, Stephen Alexander.
Reusable OpenCL FPGA Infrastructure.
Degree: 2012, University of Toronto
URL: http://hdl.handle.net/1807/32567
► OpenCL has emerged as a standard programming model for heterogeneous systems. Recent work combining OpenCL and FPGAs has focused on high-level synthesis. Building a complete…
(more)
▼ OpenCL has emerged as a standard programming model for heterogeneous systems. Recent work combining OpenCL and FPGAs has focused on high-level synthesis. Building a complete OpenCL FPGA system requires more than just high-level synthesis. This work introduces a reusable OpenCL infrastructure for FPGAs that complements previous work and specifically targets a key architectural element - the memory interface. An Aggregating Memory Controller that aims to maximize bandwidth to external, large, high-latency, high-bandwidth memories and a template Processing Array with soft-processor and hand-coded hardware elements are designed, simulated, and implemented on an FPGA. Two micro-benchmarks were run on both the soft-processor elements and the hand-coded hardware elements to exercise the Aggregating Memory Controller. The micro-benchmarks were simulated as well as implemented in a hardware prototype. Memory bandwidth results for the system show that the external memory interface can be saturated and the high-latency can be effectively hidden using the Aggregating Memory Controller.
MAST
Advisors/Committee Members: Chow, Paul, Electrical and Computer Engineering.
Subjects/Keywords: FPGA; OpenCL; SDRAM; computer architecture
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APA (6th Edition):
Chin, S. A. (2012). Reusable OpenCL FPGA Infrastructure. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/32567
Chicago Manual of Style (16th Edition):
Chin, Stephen Alexander. “Reusable OpenCL FPGA Infrastructure.” 2012. Masters Thesis, University of Toronto. Accessed April 12, 2021.
http://hdl.handle.net/1807/32567.
MLA Handbook (7th Edition):
Chin, Stephen Alexander. “Reusable OpenCL FPGA Infrastructure.” 2012. Web. 12 Apr 2021.
Vancouver:
Chin SA. Reusable OpenCL FPGA Infrastructure. [Internet] [Masters thesis]. University of Toronto; 2012. [cited 2021 Apr 12].
Available from: http://hdl.handle.net/1807/32567.
Council of Science Editors:
Chin SA. Reusable OpenCL FPGA Infrastructure. [Masters Thesis]. University of Toronto; 2012. Available from: http://hdl.handle.net/1807/32567
California State University – San Bernardino
29.
Chanamolu, Charitha.
REVIEWS TO RATING CONVERSION AND ANALYSIS USING MACHINE LEARNING TECHNIQUES.
Degree: MSin Computer Science, School of Computer Science and Engineering, 2019, California State University – San Bernardino
URL: https://scholarworks.lib.csusb.edu/etd/792
► With the advent of technology in recent years, people depend more on online reviews to purchase a product. It is hard to determine whether…
(more)
▼ With the advent of technology in recent years, people depend more on online reviews to purchase a product. It is hard to determine whether the product is good or bad from hundreds of mixed reviews. Also, it is very time-consuming to read many reviews. So, opinion mining of reviews is necessary.
The main aim of this project is to convert the reviews of a product into a rating and to evaluate the ratings using machine learning algorithms such as Naïve Bayes and Support Vector Machine. In the process of converting the reviews to a rating, score words are created using SentiWordNet and transformed into seven categories from highly positive to highly negative.
Advisors/Committee Members: Murphy,Owen..
Subjects/Keywords: Reviews; Computer and Systems Architecture
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APA (6th Edition):
Chanamolu, C. (2019). REVIEWS TO RATING CONVERSION AND ANALYSIS USING MACHINE LEARNING TECHNIQUES. (Thesis). California State University – San Bernardino. Retrieved from https://scholarworks.lib.csusb.edu/etd/792
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Chanamolu, Charitha. “REVIEWS TO RATING CONVERSION AND ANALYSIS USING MACHINE LEARNING TECHNIQUES.” 2019. Thesis, California State University – San Bernardino. Accessed April 12, 2021.
https://scholarworks.lib.csusb.edu/etd/792.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Chanamolu, Charitha. “REVIEWS TO RATING CONVERSION AND ANALYSIS USING MACHINE LEARNING TECHNIQUES.” 2019. Web. 12 Apr 2021.
Vancouver:
Chanamolu C. REVIEWS TO RATING CONVERSION AND ANALYSIS USING MACHINE LEARNING TECHNIQUES. [Internet] [Thesis]. California State University – San Bernardino; 2019. [cited 2021 Apr 12].
Available from: https://scholarworks.lib.csusb.edu/etd/792.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Chanamolu C. REVIEWS TO RATING CONVERSION AND ANALYSIS USING MACHINE LEARNING TECHNIQUES. [Thesis]. California State University – San Bernardino; 2019. Available from: https://scholarworks.lib.csusb.edu/etd/792
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Hong Kong University of Science and Technology
30.
Vivas Maeda, Rafael Kioji ECE.
Fast and accurate statistical simulation of shared-memory applications on multicore systems.
Degree: 2019, Hong Kong University of Science and Technology
URL: http://repository.ust.hk/ir/Record/1783.1-102360
;
https://doi.org/10.14711/thesis-991012762568003412
;
http://repository.ust.hk/ir/bitstream/1783.1-102360/1/th_redirect.html
► The default method to study application-architecture interactions is cycle-accurate simulation. Statistical simulation is an alternative method that approaches these interactions from a different angle than…
(more)
▼ The default method to study application-architecture interactions is cycle-accurate simulation. Statistical simulation is an alternative method that approaches these interactions from a different angle than time. It has been demonstrated that statistical simulation offers new possibilities to substantially speed up the simulation. The common way to build statistical simulation is using the reuse distance (RD) memory locality model. Unfortunately, the RD model can capture only a single locality granularity, such as the cache-line locality. This limitation leads to a considerably high error when evaluating multi-level caches. In addition, RD alone is only suitable to model single-core applications. Therefore, existing statistical simulators lack effective memory locality models for multiprocessor applications and often neglect data-sharing between threads. Moreover, the typical method to speed up statistical simulations is to blindly reduce the trace length to be synthesized. While this gives good control over the speedup, it leaves the simulation error unbounded. In this thesis, we address these issues. We first introduce a generalization to the RD that can capture the locality seen at multiple granularities. We refer to it as hierarchical reuse distance (HRD). Our results show that HRD is 4X more accurate than RD when simulating single-core systems with multi-level caches. HRD also converges three orders of magnitude faster than RD. The second contribution is a novel s̲h̲a̲ring-l̲o̲cality m̲odel (Shalom). Shalom can capture and reproduce data-sharing in multithread applications. Lastly, the third contribution is a method to bound the statistical simulation error for a particular metric while maximizing the speedup. We achieve this by monitoring the convergence of the statistical synthesis. We name it c̲o̲n̲vergence-d̲e̲termiṉistic s̱imulation (Condens). In a set of experiments, the combination of Shalom and Condens is on average 234X faster than cycle-accurate simulations, with simulation error of 15.4%. Our approach is also 48X faster than state-of-the-art sampling simulation under the same accuracy level. Compared to statistical simulators ignoring sharing, our technique is 3x more accurate for performance metrics and 5x more accurate for cache miss estimations.
Subjects/Keywords: Computer architecture
; Evaluation
; Statistical methods
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APA ·
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APA (6th Edition):
Vivas Maeda, R. K. E. (2019). Fast and accurate statistical simulation of shared-memory applications on multicore systems. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-102360 ; https://doi.org/10.14711/thesis-991012762568003412 ; http://repository.ust.hk/ir/bitstream/1783.1-102360/1/th_redirect.html
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Vivas Maeda, Rafael Kioji ECE. “Fast and accurate statistical simulation of shared-memory applications on multicore systems.” 2019. Thesis, Hong Kong University of Science and Technology. Accessed April 12, 2021.
http://repository.ust.hk/ir/Record/1783.1-102360 ; https://doi.org/10.14711/thesis-991012762568003412 ; http://repository.ust.hk/ir/bitstream/1783.1-102360/1/th_redirect.html.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Vivas Maeda, Rafael Kioji ECE. “Fast and accurate statistical simulation of shared-memory applications on multicore systems.” 2019. Web. 12 Apr 2021.
Vancouver:
Vivas Maeda RKE. Fast and accurate statistical simulation of shared-memory applications on multicore systems. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2019. [cited 2021 Apr 12].
Available from: http://repository.ust.hk/ir/Record/1783.1-102360 ; https://doi.org/10.14711/thesis-991012762568003412 ; http://repository.ust.hk/ir/bitstream/1783.1-102360/1/th_redirect.html.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Vivas Maeda RKE. Fast and accurate statistical simulation of shared-memory applications on multicore systems. [Thesis]. Hong Kong University of Science and Technology; 2019. Available from: http://repository.ust.hk/ir/Record/1783.1-102360 ; https://doi.org/10.14711/thesis-991012762568003412 ; http://repository.ust.hk/ir/bitstream/1783.1-102360/1/th_redirect.html
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
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Open Access Theses and Dissertations
