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You searched for subject:(Complementary Metal Oxide Semiconductor CMOS ). Showing records 1 – 30 of 22032 total matches.

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University of Illinois – Urbana-Champaign

1. Graham, Sean R. Distributed scalable model for CMOS FET power amplifier.

Degree: MS, 1200, 2011, University of Illinois – Urbana-Champaign

 Integrated circuits are very popular for understandable reasons. A circuit implemented within an IC is more cost effective and reliable. A vast majority of ICs… (more)

Subjects/Keywords: Radio Frequency (RF)+; Complementary metal???oxide???semiconductor (CMOS); Power Amplifier

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Graham, S. R. (2011). Distributed scalable model for CMOS FET power amplifier. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18454

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Graham, Sean R. “Distributed scalable model for CMOS FET power amplifier.” 2011. Thesis, University of Illinois – Urbana-Champaign. Accessed January 22, 2020. http://hdl.handle.net/2142/18454.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Graham, Sean R. “Distributed scalable model for CMOS FET power amplifier.” 2011. Web. 22 Jan 2020.

Vancouver:

Graham SR. Distributed scalable model for CMOS FET power amplifier. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2011. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/2142/18454.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Graham SR. Distributed scalable model for CMOS FET power amplifier. [Thesis]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18454

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Limerick

2. Zaidi, Muhaned Ali Hussein. Design and evaluation of high-speed operational amplifier designs using the negative Miller capacitance design technique.

Degree: 2018, University of Limerick

 The operational amplifier (op-amp) is one of the most commonly used analogue circuits for analogue and mixed-signal Integrated Circuit (IC) designs. The op-amp is widely… (more)

Subjects/Keywords: operational amplifier (op-amp); analogue circuits; complementary metal-oxide-semiconductor (CMOS)

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APA (6th Edition):

Zaidi, M. A. H. (2018). Design and evaluation of high-speed operational amplifier designs using the negative Miller capacitance design technique. (Thesis). University of Limerick. Retrieved from http://hdl.handle.net/10344/7599

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zaidi, Muhaned Ali Hussein. “Design and evaluation of high-speed operational amplifier designs using the negative Miller capacitance design technique.” 2018. Thesis, University of Limerick. Accessed January 22, 2020. http://hdl.handle.net/10344/7599.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zaidi, Muhaned Ali Hussein. “Design and evaluation of high-speed operational amplifier designs using the negative Miller capacitance design technique.” 2018. Web. 22 Jan 2020.

Vancouver:

Zaidi MAH. Design and evaluation of high-speed operational amplifier designs using the negative Miller capacitance design technique. [Internet] [Thesis]. University of Limerick; 2018. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/10344/7599.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zaidi MAH. Design and evaluation of high-speed operational amplifier designs using the negative Miller capacitance design technique. [Thesis]. University of Limerick; 2018. Available from: http://hdl.handle.net/10344/7599

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

3. Ding, Hao. Key concepts for implementing SoC-Holter : Les concepts clés pour la réalisation d'un Holter intégré sur puce.

Degree: Docteur es, Informatique, 2011, Université Blaise-Pascale, Clermont-Ferrand II

En dépit du développement rapide de la médecine, les maladies cardiovasculaires restent la première cause de mortalité dans le monde. En France, chaque année, plus… (more)

Subjects/Keywords: Électrocardiographie (ECG); Complementary Metal Oxide Semiconductor (CMOS); Acquisition Comprimée (CS); Arythmies cardiaques; Vectocardiographie (VCG); Electrocardiography (ECG); Complementary Metal Oxide Semiconductor (CMOS); Compressed Sensing (CS); Cardiac arrhythmias; Vectorcardiography (VCG)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ding, H. (2011). Key concepts for implementing SoC-Holter : Les concepts clés pour la réalisation d'un Holter intégré sur puce. (Doctoral Dissertation). Université Blaise-Pascale, Clermont-Ferrand II. Retrieved from http://www.theses.fr/2011CLF22166

Chicago Manual of Style (16th Edition):

Ding, Hao. “Key concepts for implementing SoC-Holter : Les concepts clés pour la réalisation d'un Holter intégré sur puce.” 2011. Doctoral Dissertation, Université Blaise-Pascale, Clermont-Ferrand II. Accessed January 22, 2020. http://www.theses.fr/2011CLF22166.

MLA Handbook (7th Edition):

Ding, Hao. “Key concepts for implementing SoC-Holter : Les concepts clés pour la réalisation d'un Holter intégré sur puce.” 2011. Web. 22 Jan 2020.

Vancouver:

Ding H. Key concepts for implementing SoC-Holter : Les concepts clés pour la réalisation d'un Holter intégré sur puce. [Internet] [Doctoral dissertation]. Université Blaise-Pascale, Clermont-Ferrand II; 2011. [cited 2020 Jan 22]. Available from: http://www.theses.fr/2011CLF22166.

Council of Science Editors:

Ding H. Key concepts for implementing SoC-Holter : Les concepts clés pour la réalisation d'un Holter intégré sur puce. [Doctoral Dissertation]. Université Blaise-Pascale, Clermont-Ferrand II; 2011. Available from: http://www.theses.fr/2011CLF22166

4. Morais, Paulo Sérgio Nogueira. Circuitos digitais em modo de corrente .

Degree: 2010, Universidade de Aveiro

 Este trabalho de dissertação insere-se na área da electrónica digital, e consiste no projecto, construção e caracterização de circuitos digitais em Modo de Corrente, empregando… (more)

Subjects/Keywords: Engenharia electrónica; Electrónica digital; Circuitos integrados; Semicondutores de óxidos metálicos; CMOS (Complementary metal-oxide-semiconductor)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Morais, P. S. N. (2010). Circuitos digitais em modo de corrente . (Thesis). Universidade de Aveiro. Retrieved from http://hdl.handle.net/10773/3710

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Morais, Paulo Sérgio Nogueira. “Circuitos digitais em modo de corrente .” 2010. Thesis, Universidade de Aveiro. Accessed January 22, 2020. http://hdl.handle.net/10773/3710.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Morais, Paulo Sérgio Nogueira. “Circuitos digitais em modo de corrente .” 2010. Web. 22 Jan 2020.

Vancouver:

Morais PSN. Circuitos digitais em modo de corrente . [Internet] [Thesis]. Universidade de Aveiro; 2010. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/10773/3710.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Morais PSN. Circuitos digitais em modo de corrente . [Thesis]. Universidade de Aveiro; 2010. Available from: http://hdl.handle.net/10773/3710

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Edinburgh

5. Walker, Richard John. Fully digital, phase-domain ΔΣ 3D range image sensor in 130nm CMOS imaging technology.

Degree: PhD, 2012, University of Edinburgh

 Three-Dimensional (3D) optical range-imaging is a field experiencing rapid growth, expanding into a wide variety of machine vision applications, most recently including consumer gaming. Time… (more)

Subjects/Keywords: 621.3; 3D camera; 3D imaging; CMOS; ?S; sigma-delta; Complementary Metal Oxide semiconductor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Walker, R. J. (2012). Fully digital, phase-domain ΔΣ 3D range image sensor in 130nm CMOS imaging technology. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/6214

Chicago Manual of Style (16th Edition):

Walker, Richard John. “Fully digital, phase-domain ΔΣ 3D range image sensor in 130nm CMOS imaging technology.” 2012. Doctoral Dissertation, University of Edinburgh. Accessed January 22, 2020. http://hdl.handle.net/1842/6214.

MLA Handbook (7th Edition):

Walker, Richard John. “Fully digital, phase-domain ΔΣ 3D range image sensor in 130nm CMOS imaging technology.” 2012. Web. 22 Jan 2020.

Vancouver:

Walker RJ. Fully digital, phase-domain ΔΣ 3D range image sensor in 130nm CMOS imaging technology. [Internet] [Doctoral dissertation]. University of Edinburgh; 2012. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1842/6214.

Council of Science Editors:

Walker RJ. Fully digital, phase-domain ΔΣ 3D range image sensor in 130nm CMOS imaging technology. [Doctoral Dissertation]. University of Edinburgh; 2012. Available from: http://hdl.handle.net/1842/6214


University of Illinois – Urbana-Champaign

6. Almulla, Saoud A E A. Absorption and fluorescence spectroscopic analysis using compact, linear variable filter based, detection platforms.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 Spectroscopic analysis is an integral part of biological and chemical sensing. However, most spectroscopic equipment is relegated to laboratories. Compact and portable alternatives to conventional… (more)

Subjects/Keywords: Linear variable filter; Spectroscopy; Colorimetry; Fluorometry; Complementary metal-oxide semiconductor (CMOS) sensor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Almulla, S. A. E. A. (2017). Absorption and fluorescence spectroscopic analysis using compact, linear variable filter based, detection platforms. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/98318

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Almulla, Saoud A E A. “Absorption and fluorescence spectroscopic analysis using compact, linear variable filter based, detection platforms.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed January 22, 2020. http://hdl.handle.net/2142/98318.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Almulla, Saoud A E A. “Absorption and fluorescence spectroscopic analysis using compact, linear variable filter based, detection platforms.” 2017. Web. 22 Jan 2020.

Vancouver:

Almulla SAEA. Absorption and fluorescence spectroscopic analysis using compact, linear variable filter based, detection platforms. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/2142/98318.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Almulla SAEA. Absorption and fluorescence spectroscopic analysis using compact, linear variable filter based, detection platforms. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/98318

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Dalhousie University

7. Yu, Haoran. Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology.

Degree: PhD, Department of Electrical & Computer Engineering, 2014, Dalhousie University

 Bulk-driven (BD) technique has been proposed to remedy the voltage swing limitation problem in modern CMOS technology. However, challenges exist when the CMOS technologies move… (more)

Subjects/Keywords: CMOS; bulk-driven; Metal oxide semiconductors, Complementary; Metal oxide semiconductors, Complementary

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yu, H. (2014). Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology. (Doctoral Dissertation). Dalhousie University. Retrieved from http://hdl.handle.net/10222/55992

Chicago Manual of Style (16th Edition):

Yu, Haoran. “Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology.” 2014. Doctoral Dissertation, Dalhousie University. Accessed January 22, 2020. http://hdl.handle.net/10222/55992.

MLA Handbook (7th Edition):

Yu, Haoran. “Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology.” 2014. Web. 22 Jan 2020.

Vancouver:

Yu H. Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology. [Internet] [Doctoral dissertation]. Dalhousie University; 2014. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/10222/55992.

Council of Science Editors:

Yu H. Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology. [Doctoral Dissertation]. Dalhousie University; 2014. Available from: http://hdl.handle.net/10222/55992


Georgia Tech

8. Zahorian, Jaime S. Fabrication technology and design for CMUTS on CMOS for IVUS catheters.

Degree: PhD, Electrical and Computer Engineering, 2013, Georgia Tech

 The objective of this research is to develop novel capacitive micromachined ultrasonic transducer (CMUT) arrays for intravascular ultrasonic (IVUS) imaging along with the fabrication processes… (more)

Subjects/Keywords: Intravascular ultrasonic (IVUS); Capacitive micromachined ultrasonic transducer (CMUT); Complementary metal oxide semiconductor (CMOS); Metal oxide semiconductors, Complementary; Ultrasonic transducer; Diagnostic ultrasonic imaging; Intravascular ultrasonography

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zahorian, J. S. (2013). Fabrication technology and design for CMUTS on CMOS for IVUS catheters. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/51730

Chicago Manual of Style (16th Edition):

Zahorian, Jaime S. “Fabrication technology and design for CMUTS on CMOS for IVUS catheters.” 2013. Doctoral Dissertation, Georgia Tech. Accessed January 22, 2020. http://hdl.handle.net/1853/51730.

MLA Handbook (7th Edition):

Zahorian, Jaime S. “Fabrication technology and design for CMUTS on CMOS for IVUS catheters.” 2013. Web. 22 Jan 2020.

Vancouver:

Zahorian JS. Fabrication technology and design for CMUTS on CMOS for IVUS catheters. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/1853/51730.

Council of Science Editors:

Zahorian JS. Fabrication technology and design for CMUTS on CMOS for IVUS catheters. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/51730


University of Illinois – Urbana-Champaign

9. Ho, Aaron Daniel. Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails.

Degree: MS, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign

 Recent years have seen the proliferation of electronic devices that require multi-phase power converters to provide heterogeneous power rails to different systems. Typical systems will… (more)

Subjects/Keywords: complementary metal–oxide–semiconductor (CMOS) integrated circuits; digital control; low-power electronics; power convertors; asymmetric interleaving; digital control; heterogeneous power rails; low voltage complementary metal–oxide–semiconductor (CMOS) power management; multiphase (complementary metal–oxide–semiconductor) CMOS power management IC system; multiphase power converters; multiple supply rails; reduced input current ripple; size 180 nm; Hardware; Mathematical model; Prototypes; Table lookup; Time-domain analysis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ho, A. D. (2015). Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/88219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ho, Aaron Daniel. “Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed January 22, 2020. http://hdl.handle.net/2142/88219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ho, Aaron Daniel. “Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails.” 2015. Web. 22 Jan 2020.

Vancouver:

Ho AD. Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/2142/88219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ho AD. Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/88219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

10. Chan, Doris A. CMOS Power Device Modeling and Amplifier Circuits.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

 A power amplifier (PA) is a key part of the RF front-end in transmitters for a local broadband network. Today, commercial PAs are made of… (more)

Subjects/Keywords: Complementary Metal Oxide Semiconductor (CMOS); millimeter-wave; coplanar waveguide; Worldwide Interoperability for Microwave Access (WiMAX); power divider/combiner; power amplifier

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APA (6th Edition):

Chan, D. A. (2011). CMOS Power Device Modeling and Amplifier Circuits. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18249

Chicago Manual of Style (16th Edition):

Chan, Doris A. “CMOS Power Device Modeling and Amplifier Circuits.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed January 22, 2020. http://hdl.handle.net/2142/18249.

MLA Handbook (7th Edition):

Chan, Doris A. “CMOS Power Device Modeling and Amplifier Circuits.” 2011. Web. 22 Jan 2020.

Vancouver:

Chan DA. CMOS Power Device Modeling and Amplifier Circuits. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/2142/18249.

Council of Science Editors:

Chan DA. CMOS Power Device Modeling and Amplifier Circuits. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18249


Brunel University

11. Greig, Thomas Alexander. Development of CMOS active pixel sensors.

Degree: 2008, Brunel University

 This thesis describes an investigation into the suitability of complementary metal oxide semiconductor (CMOS) active pixel sensor (APS) devices for scientific imaging applications. CMOS APS… (more)

Subjects/Keywords: 681.25; Complementary metal oxide semiconductor (CMOS); Charge-coupled device (CCD); Quantum efficiency (QE); Charge conversion gain (responsivity); Pixel capacitance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Greig, T. A. (2008). Development of CMOS active pixel sensors. (Doctoral Dissertation). Brunel University. Retrieved from http://bura.brunel.ac.uk/handle/2438/5345 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.445925

Chicago Manual of Style (16th Edition):

Greig, Thomas Alexander. “Development of CMOS active pixel sensors.” 2008. Doctoral Dissertation, Brunel University. Accessed January 22, 2020. http://bura.brunel.ac.uk/handle/2438/5345 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.445925.

MLA Handbook (7th Edition):

Greig, Thomas Alexander. “Development of CMOS active pixel sensors.” 2008. Web. 22 Jan 2020.

Vancouver:

Greig TA. Development of CMOS active pixel sensors. [Internet] [Doctoral dissertation]. Brunel University; 2008. [cited 2020 Jan 22]. Available from: http://bura.brunel.ac.uk/handle/2438/5345 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.445925.

Council of Science Editors:

Greig TA. Development of CMOS active pixel sensors. [Doctoral Dissertation]. Brunel University; 2008. Available from: http://bura.brunel.ac.uk/handle/2438/5345 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.445925


NSYSU

12. Chung, Chun-lin. Back-contact photovoltaic device realized by standard CMOS foundry process and its application.

Degree: Master, Electro-Optical Engineering, 2015, NSYSU

 In this thesis, an interdigitated back-contact photovoltaic device is realized by high-resolution doping and multi-layer interconnections provided by standard bulk CMOS processes. Since the device… (more)

Subjects/Keywords: complementary metal-oxide-semiconductor (CMOS); interdigitated back-contact solar cell; integrated passive device; implantable device; surface texture

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APA (6th Edition):

Chung, C. (2015). Back-contact photovoltaic device realized by standard CMOS foundry process and its application. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628115-150138

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chung, Chun-lin. “Back-contact photovoltaic device realized by standard CMOS foundry process and its application.” 2015. Thesis, NSYSU. Accessed January 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628115-150138.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chung, Chun-lin. “Back-contact photovoltaic device realized by standard CMOS foundry process and its application.” 2015. Web. 22 Jan 2020.

Vancouver:

Chung C. Back-contact photovoltaic device realized by standard CMOS foundry process and its application. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Jan 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628115-150138.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chung C. Back-contact photovoltaic device realized by standard CMOS foundry process and its application. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628115-150138

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. Anek Wuthayavanich. Small implantable CMOS fluorescence imaging device with compact processing system for the detection of nitric oxide : 生体内一酸化窒素測定のための小型埋植型CMOS蛍光イメージングデバイス及びポータブル制御システムに関する研究; セイタイナイ イッサンカ チッソ ソクテイ ノ タメノ コガタ マイショクガタ CMOS ケイコウ イメージング デバイス オヨビ ポータブル セイギョ システム ニ カンスル ケンキュウ.

Degree: 博士(工学), 2017, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: Complementary metal-oxide semiconductor (CMOS) image sensor

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APA (6th Edition):

Wuthayavanich, A. (2017). Small implantable CMOS fluorescence imaging device with compact processing system for the detection of nitric oxide : 生体内一酸化窒素測定のための小型埋植型CMOS蛍光イメージングデバイス及びポータブル制御システムに関する研究; セイタイナイ イッサンカ チッソ ソクテイ ノ タメノ コガタ マイショクガタ CMOS ケイコウ イメージング デバイス オヨビ ポータブル セイギョ システム ニ カンスル ケンキュウ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/11710

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wuthayavanich, Anek. “Small implantable CMOS fluorescence imaging device with compact processing system for the detection of nitric oxide : 生体内一酸化窒素測定のための小型埋植型CMOS蛍光イメージングデバイス及びポータブル制御システムに関する研究; セイタイナイ イッサンカ チッソ ソクテイ ノ タメノ コガタ マイショクガタ CMOS ケイコウ イメージング デバイス オヨビ ポータブル セイギョ システム ニ カンスル ケンキュウ.” 2017. Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed January 22, 2020. http://hdl.handle.net/10061/11710.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wuthayavanich, Anek. “Small implantable CMOS fluorescence imaging device with compact processing system for the detection of nitric oxide : 生体内一酸化窒素測定のための小型埋植型CMOS蛍光イメージングデバイス及びポータブル制御システムに関する研究; セイタイナイ イッサンカ チッソ ソクテイ ノ タメノ コガタ マイショクガタ CMOS ケイコウ イメージング デバイス オヨビ ポータブル セイギョ システム ニ カンスル ケンキュウ.” 2017. Web. 22 Jan 2020.

Vancouver:

Wuthayavanich A. Small implantable CMOS fluorescence imaging device with compact processing system for the detection of nitric oxide : 生体内一酸化窒素測定のための小型埋植型CMOS蛍光イメージングデバイス及びポータブル制御システムに関する研究; セイタイナイ イッサンカ チッソ ソクテイ ノ タメノ コガタ マイショクガタ CMOS ケイコウ イメージング デバイス オヨビ ポータブル セイギョ システム ニ カンスル ケンキュウ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; 2017. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/10061/11710.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wuthayavanich A. Small implantable CMOS fluorescence imaging device with compact processing system for the detection of nitric oxide : 生体内一酸化窒素測定のための小型埋植型CMOS蛍光イメージングデバイス及びポータブル制御システムに関する研究; セイタイナイ イッサンカ チッソ ソクテイ ノ タメノ コガタ マイショクガタ CMOS ケイコウ イメージング デバイス オヨビ ポータブル セイギョ システム ニ カンスル ケンキュウ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; 2017. Available from: http://hdl.handle.net/10061/11710

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

14. Carlson, John Anthony. Scalable designs and methods for heterogeneous electronic-photonic integrated circuitry.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 A set of semiconductor designs shown to be capable of facilitating scalable and reconfigurable layouts for electronic-photonic integrated circuitry is presented. Three emphases are established… (more)

Subjects/Keywords: Photonic integration; III-V on silicon; Gallium nitride; Complementary metal–oxide–semiconductor (CMOS) compatibility; Scalable processes

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Carlson, J. A. (2017). Scalable designs and methods for heterogeneous electronic-photonic integrated circuitry. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97634

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Carlson, John Anthony. “Scalable designs and methods for heterogeneous electronic-photonic integrated circuitry.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed January 22, 2020. http://hdl.handle.net/2142/97634.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Carlson, John Anthony. “Scalable designs and methods for heterogeneous electronic-photonic integrated circuitry.” 2017. Web. 22 Jan 2020.

Vancouver:

Carlson JA. Scalable designs and methods for heterogeneous electronic-photonic integrated circuitry. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/2142/97634.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Carlson JA. Scalable designs and methods for heterogeneous electronic-photonic integrated circuitry. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97634

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

15. Garbi, Ahmed. Développement de nouveaux procédés d’isolation électrique par anodisation localisée du silicium : Development of a new process for electrical isolation of ULSI CMOS ciruits based on local anodization of silicium.

Degree: Docteur es, Dispositifs de l'électronique intégrée, 2011, INSA Lyon

L’industrie microélectronique est régie depuis plusieurs années par la loi de miniaturisation. En particulier, en technologie CMOS, les procédés de fabrication de l’oxyde permettant l’isolation… (more)

Subjects/Keywords: Microélectronique; Circuit intégré Complementary Metal Oxide SemiConductor - CMOS; Isolation électrique; Silicium poreux; Anodisation électrochimique; Anodisation locale; Spectrométrie de masse des ions secondaires; Recuit oxydant; Micro Electronics; CMOS - Complementary Metal Oxide SemiConductor; Electric Insulation; Silicium poreux; Anodisation électrochimique; Secondary-ion mass Spectrometry; Oxidative annealing; 621.381 620 107 2

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Garbi, A. (2011). Développement de nouveaux procédés d’isolation électrique par anodisation localisée du silicium : Development of a new process for electrical isolation of ULSI CMOS ciruits based on local anodization of silicium. (Doctoral Dissertation). INSA Lyon. Retrieved from http://www.theses.fr/2011ISAL0072

Chicago Manual of Style (16th Edition):

Garbi, Ahmed. “Développement de nouveaux procédés d’isolation électrique par anodisation localisée du silicium : Development of a new process for electrical isolation of ULSI CMOS ciruits based on local anodization of silicium.” 2011. Doctoral Dissertation, INSA Lyon. Accessed January 22, 2020. http://www.theses.fr/2011ISAL0072.

MLA Handbook (7th Edition):

Garbi, Ahmed. “Développement de nouveaux procédés d’isolation électrique par anodisation localisée du silicium : Development of a new process for electrical isolation of ULSI CMOS ciruits based on local anodization of silicium.” 2011. Web. 22 Jan 2020.

Vancouver:

Garbi A. Développement de nouveaux procédés d’isolation électrique par anodisation localisée du silicium : Development of a new process for electrical isolation of ULSI CMOS ciruits based on local anodization of silicium. [Internet] [Doctoral dissertation]. INSA Lyon; 2011. [cited 2020 Jan 22]. Available from: http://www.theses.fr/2011ISAL0072.

Council of Science Editors:

Garbi A. Développement de nouveaux procédés d’isolation électrique par anodisation localisée du silicium : Development of a new process for electrical isolation of ULSI CMOS ciruits based on local anodization of silicium. [Doctoral Dissertation]. INSA Lyon; 2011. Available from: http://www.theses.fr/2011ISAL0072


Indian Institute of Science

16. Ajayan, K R. Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology.

Degree: 2014, Indian Institute of Science

 Process variability is a major challenge for the design of nano scale MOSFETs due to fundamental physical limits as well as process control limitations. As… (more)

Subjects/Keywords: Metal Oxide Semiconductors (MOS); Digital Integrated Circuits; Complementary Metal Oxide Semiconductors (CMOS); N-type Metal-Oxide Semiconductors (NMOS); P-type Metal-Oxide Semiconductors (PMOS); Metal Oxode Semiconductor Device Modeling; Look Up Table Model (LUT); Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET); MOSFET Models; BSIM Models; Variability Aware Device Modeling; Integrated Circuit Modeling; Circuit Design; 45nm Analog CMOS Technology; Electrical Communication Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ajayan, K. R. (2014). Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ajayan, K R. “Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology.” 2014. Thesis, Indian Institute of Science. Accessed January 22, 2020. http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ajayan, K R. “Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology.” 2014. Web. 22 Jan 2020.

Vancouver:

Ajayan KR. Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology. [Internet] [Thesis]. Indian Institute of Science; 2014. [cited 2020 Jan 22]. Available from: http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ajayan KR. Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology. [Thesis]. Indian Institute of Science; 2014. Available from: http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Neveu, Florian. Design and implementation of high frequency 3D DC-DC converter : Conception et implémentation d'un convertisseur 3D DC-DC à haute fréquence.

Degree: Docteur es, Génie électrique, 2015, INSA Lyon

L’intégration ultime de convertisseurs à découpage repose sur deux axes de recherche. Le premier axe est de développer les convertisseurs à capacités commutées. Cette approche… (more)

Subjects/Keywords: Electronique de puissance; Convertisseur DC-DC; Haute fréquence; Système embarqué; Circuit intégré Complementary Metal Oxide SemiConductor - CMOS; Power Electronics; DC-DC converters; High fraquency; Integrated circuit; CMOS circuit; 621.317 072

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Neveu, F. (2015). Design and implementation of high frequency 3D DC-DC converter : Conception et implémentation d'un convertisseur 3D DC-DC à haute fréquence. (Doctoral Dissertation). INSA Lyon. Retrieved from http://www.theses.fr/2015ISAL0133

Chicago Manual of Style (16th Edition):

Neveu, Florian. “Design and implementation of high frequency 3D DC-DC converter : Conception et implémentation d'un convertisseur 3D DC-DC à haute fréquence.” 2015. Doctoral Dissertation, INSA Lyon. Accessed January 22, 2020. http://www.theses.fr/2015ISAL0133.

MLA Handbook (7th Edition):

Neveu, Florian. “Design and implementation of high frequency 3D DC-DC converter : Conception et implémentation d'un convertisseur 3D DC-DC à haute fréquence.” 2015. Web. 22 Jan 2020.

Vancouver:

Neveu F. Design and implementation of high frequency 3D DC-DC converter : Conception et implémentation d'un convertisseur 3D DC-DC à haute fréquence. [Internet] [Doctoral dissertation]. INSA Lyon; 2015. [cited 2020 Jan 22]. Available from: http://www.theses.fr/2015ISAL0133.

Council of Science Editors:

Neveu F. Design and implementation of high frequency 3D DC-DC converter : Conception et implémentation d'un convertisseur 3D DC-DC à haute fréquence. [Doctoral Dissertation]. INSA Lyon; 2015. Available from: http://www.theses.fr/2015ISAL0133

18. Sciancalepore, Corrado. Intégration hétérogène III-V sur silicium de microlasers à émission par la surface à base de cristaux photoniques : Modélisation et conception de circuits intégrés tridimensionnels.

Degree: Docteur es, Dispositifs photoniques et optoélectroniques, 2012, Ecully, Ecole centrale de Lyon

La croissance continue et rapide du trafic de données dans les infrastructures de télécommunications, impose des niveaux de débit de transmission ainsi que de puissance… (more)

Subjects/Keywords: Technologie CMOS (ou Complementary Metal Oxide Semiconductor); Cristaux photoniques (CPs); Intégration hétérogène III-V sur silicium; Laser à semiconducteur; Modes de Bloch lents; Laser à émission par la surface; Complementary metal-oxide-semiconductor (CMOS); III-V on Si heterogeneous integration; Photonic crystal (PhC); Semiconductor laser; Slow Bloch mode (SBM); Vertical-cavity surface-emitting laser (VCSEL)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sciancalepore, C. (2012). Intégration hétérogène III-V sur silicium de microlasers à émission par la surface à base de cristaux photoniques : Modélisation et conception de circuits intégrés tridimensionnels. (Doctoral Dissertation). Ecully, Ecole centrale de Lyon. Retrieved from http://www.theses.fr/2012ECDL0050

Chicago Manual of Style (16th Edition):

Sciancalepore, Corrado. “Intégration hétérogène III-V sur silicium de microlasers à émission par la surface à base de cristaux photoniques : Modélisation et conception de circuits intégrés tridimensionnels.” 2012. Doctoral Dissertation, Ecully, Ecole centrale de Lyon. Accessed January 22, 2020. http://www.theses.fr/2012ECDL0050.

MLA Handbook (7th Edition):

Sciancalepore, Corrado. “Intégration hétérogène III-V sur silicium de microlasers à émission par la surface à base de cristaux photoniques : Modélisation et conception de circuits intégrés tridimensionnels.” 2012. Web. 22 Jan 2020.

Vancouver:

Sciancalepore C. Intégration hétérogène III-V sur silicium de microlasers à émission par la surface à base de cristaux photoniques : Modélisation et conception de circuits intégrés tridimensionnels. [Internet] [Doctoral dissertation]. Ecully, Ecole centrale de Lyon; 2012. [cited 2020 Jan 22]. Available from: http://www.theses.fr/2012ECDL0050.

Council of Science Editors:

Sciancalepore C. Intégration hétérogène III-V sur silicium de microlasers à émission par la surface à base de cristaux photoniques : Modélisation et conception de circuits intégrés tridimensionnels. [Doctoral Dissertation]. Ecully, Ecole centrale de Lyon; 2012. Available from: http://www.theses.fr/2012ECDL0050


Indian Institute of Science

19. Jajala, Bujjamma. Ion Assisted Deposition Of HfO2 Thin Films For CMOS Gate Dielectric Applications.

Degree: 2010, Indian Institute of Science

 The scaling down of Complementary Metal Oxide Semiconductor (CMOS) transistors to sub-100nm requires replacement of conventional Silicon dioxide layer with high dielectric constant (K) material… (more)

Subjects/Keywords: Thin Films -; Dielecrtics; Complementary Metal Oxide Semiconductor (CMOS); Thin Film Deposition; Hafnium Dioxide Thin Films; HfO2 Thin Films; high-K Dielectrics; Ion Assisted Deposition (IAD); Condensed Matter Physics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jajala, B. (2010). Ion Assisted Deposition Of HfO2 Thin Films For CMOS Gate Dielectric Applications. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2241

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jajala, Bujjamma. “Ion Assisted Deposition Of HfO2 Thin Films For CMOS Gate Dielectric Applications.” 2010. Thesis, Indian Institute of Science. Accessed January 22, 2020. http://hdl.handle.net/2005/2241.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jajala, Bujjamma. “Ion Assisted Deposition Of HfO2 Thin Films For CMOS Gate Dielectric Applications.” 2010. Web. 22 Jan 2020.

Vancouver:

Jajala B. Ion Assisted Deposition Of HfO2 Thin Films For CMOS Gate Dielectric Applications. [Internet] [Thesis]. Indian Institute of Science; 2010. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/2005/2241.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jajala B. Ion Assisted Deposition Of HfO2 Thin Films For CMOS Gate Dielectric Applications. [Thesis]. Indian Institute of Science; 2010. Available from: http://hdl.handle.net/2005/2241

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

20. Duarte Guevara, Carlos. Multiplexed label-free electrical detection of DNA amplification using field effect transistors.

Degree: PhD, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 The objective of this research project was to develop a miniaturized DNA amplification biosensor for the detection and identification of pathogenic bacteria. Using tailored loop-mediated… (more)

Subjects/Keywords: Field effect transistors (FET) biosensor; Complementary metal-oxide semiconductor (CMOS)-compatible; Ion-sensitive field effect transistors (ISFET); Loop-mediated isothermal amplification; Food safety

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APA (6th Edition):

Duarte Guevara, C. (2016). Multiplexed label-free electrical detection of DNA amplification using field effect transistors. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/90717

Chicago Manual of Style (16th Edition):

Duarte Guevara, Carlos. “Multiplexed label-free electrical detection of DNA amplification using field effect transistors.” 2016. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed January 22, 2020. http://hdl.handle.net/2142/90717.

MLA Handbook (7th Edition):

Duarte Guevara, Carlos. “Multiplexed label-free electrical detection of DNA amplification using field effect transistors.” 2016. Web. 22 Jan 2020.

Vancouver:

Duarte Guevara C. Multiplexed label-free electrical detection of DNA amplification using field effect transistors. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2016. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/2142/90717.

Council of Science Editors:

Duarte Guevara C. Multiplexed label-free electrical detection of DNA amplification using field effect transistors. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/90717


Rochester Institute of Technology

21. Becker, Harvey. The Design of Fail-Safe Logic.

Degree: Microelectronic Engineering, 1977, Rochester Institute of Technology

 This paper examines the behavior of digital logic families, specifically identifying the properties and characteristics of digital fail-safe logic. Fail-safe digital design is examined utilizing… (more)

Subjects/Keywords: Circuit failure; CMOS; Complementary Metal Oxide Semiconductor; Logic gates; Ternary logic

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APA (6th Edition):

Becker, H. (1977). The Design of Fail-Safe Logic. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/7411

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Becker, Harvey. “The Design of Fail-Safe Logic.” 1977. Thesis, Rochester Institute of Technology. Accessed January 22, 2020. https://scholarworks.rit.edu/theses/7411.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Becker, Harvey. “The Design of Fail-Safe Logic.” 1977. Web. 22 Jan 2020.

Vancouver:

Becker H. The Design of Fail-Safe Logic. [Internet] [Thesis]. Rochester Institute of Technology; 1977. [cited 2020 Jan 22]. Available from: https://scholarworks.rit.edu/theses/7411.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Becker H. The Design of Fail-Safe Logic. [Thesis]. Rochester Institute of Technology; 1977. Available from: https://scholarworks.rit.edu/theses/7411

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

22. Jajala, Bujjamma. Ion Assisted Deposition Of HfO2 Thin Films For CMOS Gate Dielectric Applications.

Degree: 2010, Indian Institute of Science

 The scaling down of Complementary Metal Oxide Semiconductor (CMOS) transistors to sub-100nm requires replacement of conventional Silicon dioxide layer with high dielectric constant (K) material… (more)

Subjects/Keywords: Thin Films -; Dielecrtics; Complementary Metal Oxide Semiconductor (CMOS); Thin Film Deposition; Hafnium Dioxide Thin Films; HfO2 Thin Films; high-K Dielectrics; Ion Assisted Deposition (IAD); Condensed Matter Physics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jajala, B. (2010). Ion Assisted Deposition Of HfO2 Thin Films For CMOS Gate Dielectric Applications. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2241 ; http://etd.ncsi.iisc.ernet.in/abstracts/2855/G24418-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jajala, Bujjamma. “Ion Assisted Deposition Of HfO2 Thin Films For CMOS Gate Dielectric Applications.” 2010. Thesis, Indian Institute of Science. Accessed January 22, 2020. http://etd.iisc.ernet.in/handle/2005/2241 ; http://etd.ncsi.iisc.ernet.in/abstracts/2855/G24418-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jajala, Bujjamma. “Ion Assisted Deposition Of HfO2 Thin Films For CMOS Gate Dielectric Applications.” 2010. Web. 22 Jan 2020.

Vancouver:

Jajala B. Ion Assisted Deposition Of HfO2 Thin Films For CMOS Gate Dielectric Applications. [Internet] [Thesis]. Indian Institute of Science; 2010. [cited 2020 Jan 22]. Available from: http://etd.iisc.ernet.in/handle/2005/2241 ; http://etd.ncsi.iisc.ernet.in/abstracts/2855/G24418-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jajala B. Ion Assisted Deposition Of HfO2 Thin Films For CMOS Gate Dielectric Applications. [Thesis]. Indian Institute of Science; 2010. Available from: http://etd.iisc.ernet.in/handle/2005/2241 ; http://etd.ncsi.iisc.ernet.in/abstracts/2855/G24418-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Manchester

23. Chung, Manloeng Andrew. Stochastic Optical Reconstruction Microscopy of the Endoplasmic Reticulum.

Degree: 2018, University of Manchester

 Super-resolution techniques have opened many new possibilities for scientists. With greater resolution, subcellular structures are better defined, which provides more details to probe structure/ functions… (more)

Subjects/Keywords: STORM; Stochastic optical reconstruction microscopy; klc3; Endoplasmic reticulum; E.R; Medical Research Council cell strain 5; MRC5; Complementary metal oxide semiconductor; CMOS; Rab5; EEA1

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APA (6th Edition):

Chung, M. A. (2018). Stochastic Optical Reconstruction Microscopy of the Endoplasmic Reticulum. (Doctoral Dissertation). University of Manchester. Retrieved from http://www.manchester.ac.uk/escholar/uk-ac-man-scw:314439

Chicago Manual of Style (16th Edition):

Chung, Manloeng Andrew. “Stochastic Optical Reconstruction Microscopy of the Endoplasmic Reticulum.” 2018. Doctoral Dissertation, University of Manchester. Accessed January 22, 2020. http://www.manchester.ac.uk/escholar/uk-ac-man-scw:314439.

MLA Handbook (7th Edition):

Chung, Manloeng Andrew. “Stochastic Optical Reconstruction Microscopy of the Endoplasmic Reticulum.” 2018. Web. 22 Jan 2020.

Vancouver:

Chung MA. Stochastic Optical Reconstruction Microscopy of the Endoplasmic Reticulum. [Internet] [Doctoral dissertation]. University of Manchester; 2018. [cited 2020 Jan 22]. Available from: http://www.manchester.ac.uk/escholar/uk-ac-man-scw:314439.

Council of Science Editors:

Chung MA. Stochastic Optical Reconstruction Microscopy of the Endoplasmic Reticulum. [Doctoral Dissertation]. University of Manchester; 2018. Available from: http://www.manchester.ac.uk/escholar/uk-ac-man-scw:314439


Universidade Nova

24. Carvalho, João Pedro Leal Abalada De Matos. Design of a Transimpedance Amplifier for an Optical Receiver.

Degree: 2017, Universidade Nova

 In today’s world, technology is so developed that it is possible to transmit huge amounts of data in a short time. In the experiments with… (more)

Subjects/Keywords: Fiber optics; Transimpedance amplifiers; Amplifier gain; Bandwidth; Input reffered noise; Complementary metal-oxide-semiconductor (CMOS); Domínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Carvalho, J. P. L. A. D. M. (2017). Design of a Transimpedance Amplifier for an Optical Receiver. (Thesis). Universidade Nova. Retrieved from https://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/34375

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Carvalho, João Pedro Leal Abalada De Matos. “Design of a Transimpedance Amplifier for an Optical Receiver.” 2017. Thesis, Universidade Nova. Accessed January 22, 2020. https://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/34375.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Carvalho, João Pedro Leal Abalada De Matos. “Design of a Transimpedance Amplifier for an Optical Receiver.” 2017. Web. 22 Jan 2020.

Vancouver:

Carvalho JPLADM. Design of a Transimpedance Amplifier for an Optical Receiver. [Internet] [Thesis]. Universidade Nova; 2017. [cited 2020 Jan 22]. Available from: https://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/34375.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Carvalho JPLADM. Design of a Transimpedance Amplifier for an Optical Receiver. [Thesis]. Universidade Nova; 2017. Available from: https://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/34375

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


McMaster University

25. Alayed, Mrwan. Development of Time-Resolved Diffuse Optical Systems Using SPAD Detectors and an Efficient Image Reconstruction Algorithm.

Degree: PhD, 2019, McMaster University

Time-Resolved diffuse optics is a powerful and safe technique to quantify the optical properties (OP) for highly scattering media such as biological tissues. The OP… (more)

Subjects/Keywords: Time-Resolved Diffuse Optical Spectroscopy; Time-Resolved Near-Infrared Spectroscopy; Single-Photon Avalanche Diode (SPAD); Time-Correlated Single-Photon Counting; Time-Resolved Diffuse Optical Tomography; Complementary Metal-Oxide-Semiconductor (CMOS)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Alayed, M. (2019). Development of Time-Resolved Diffuse Optical Systems Using SPAD Detectors and an Efficient Image Reconstruction Algorithm. (Doctoral Dissertation). McMaster University. Retrieved from http://hdl.handle.net/11375/24336

Chicago Manual of Style (16th Edition):

Alayed, Mrwan. “Development of Time-Resolved Diffuse Optical Systems Using SPAD Detectors and an Efficient Image Reconstruction Algorithm.” 2019. Doctoral Dissertation, McMaster University. Accessed January 22, 2020. http://hdl.handle.net/11375/24336.

MLA Handbook (7th Edition):

Alayed, Mrwan. “Development of Time-Resolved Diffuse Optical Systems Using SPAD Detectors and an Efficient Image Reconstruction Algorithm.” 2019. Web. 22 Jan 2020.

Vancouver:

Alayed M. Development of Time-Resolved Diffuse Optical Systems Using SPAD Detectors and an Efficient Image Reconstruction Algorithm. [Internet] [Doctoral dissertation]. McMaster University; 2019. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/11375/24336.

Council of Science Editors:

Alayed M. Development of Time-Resolved Diffuse Optical Systems Using SPAD Detectors and an Efficient Image Reconstruction Algorithm. [Doctoral Dissertation]. McMaster University; 2019. Available from: http://hdl.handle.net/11375/24336


University of Illinois – Urbana-Champaign

26. Kwon, Dae Hyun. Digitally enhanced CMOS RF transmitter with integrated power amplifier.

Degree: PhD, 1200, 2010, University of Illinois – Urbana-Champaign

 An energy-efficient, 3.5 GHz, direct-conversion RF transmitter with integrated 23 dBm, Class-B power amplifier (PA) is fabricated in a 0.13 μm CMOS process. The TX… (more)

Subjects/Keywords: Adaptive equalizer; AM-AM; AM-PM; Class-B power amplifier; Complementary metal-oxide semiconductor radio frequency (CMOS RF) transmitter; digital equalization; drain efficiency; error-vector magnitude; look-up table; memoryless nonlinearities; orthogonal frequency-division multiplexing (OFDM); peak-to-average power ratio; power-added efficiency; power amplifier; predistortion; Complementary metal–oxide–semiconductor (CMOS); Radio frequency (RF)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kwon, D. H. (2010). Digitally enhanced CMOS RF transmitter with integrated power amplifier. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/15601

Chicago Manual of Style (16th Edition):

Kwon, Dae Hyun. “Digitally enhanced CMOS RF transmitter with integrated power amplifier.” 2010. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed January 22, 2020. http://hdl.handle.net/2142/15601.

MLA Handbook (7th Edition):

Kwon, Dae Hyun. “Digitally enhanced CMOS RF transmitter with integrated power amplifier.” 2010. Web. 22 Jan 2020.

Vancouver:

Kwon DH. Digitally enhanced CMOS RF transmitter with integrated power amplifier. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2010. [cited 2020 Jan 22]. Available from: http://hdl.handle.net/2142/15601.

Council of Science Editors:

Kwon DH. Digitally enhanced CMOS RF transmitter with integrated power amplifier. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2010. Available from: http://hdl.handle.net/2142/15601


Anna University

27. Suveetha dhanaselvam P. Analytical modeling and simulation Of fully depleted triple material Surrounding gate mosfets Considering short channel effects;.

Degree: Analytical modeling and simulation Of fully depleted triple material Surrounding gate mosfets Considering short channel effects, 2015, Anna University

The steady down scaling of complementary metal oxide newlinesemiconductor CMOS device dimensions have lifted the era of micro newlineelectronics and computer aided ultra large scale… (more)

Subjects/Keywords: Complementary metal oxide semiconductor; Ultra large scale integration

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APA (6th Edition):

P, S. d. (2015). Analytical modeling and simulation Of fully depleted triple material Surrounding gate mosfets Considering short channel effects;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/43541

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

P, Suveetha dhanaselvam. “Analytical modeling and simulation Of fully depleted triple material Surrounding gate mosfets Considering short channel effects;.” 2015. Thesis, Anna University. Accessed January 22, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/43541.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

P, Suveetha dhanaselvam. “Analytical modeling and simulation Of fully depleted triple material Surrounding gate mosfets Considering short channel effects;.” 2015. Web. 22 Jan 2020.

Vancouver:

P Sd. Analytical modeling and simulation Of fully depleted triple material Surrounding gate mosfets Considering short channel effects;. [Internet] [Thesis]. Anna University; 2015. [cited 2020 Jan 22]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/43541.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

P Sd. Analytical modeling and simulation Of fully depleted triple material Surrounding gate mosfets Considering short channel effects;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/43541

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

28. Hsieh, Min-chun. Implementation of Polysilicon Subwavelength Grating Reflectors in Standard Bulk CMOS Foundry Process.

Degree: Master, Electro-Optical Engineering, 2016, NSYSU

 We have successfully demonstrated HCG reflectors in standard bulk CMOS by simply employing polysilicon gate as the high-index grating layer to reflect the 1310-nm and… (more)

Subjects/Keywords: complementary metal oxide semiconductor; polysilicon; High-index-contrast grating

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APA (6th Edition):

Hsieh, M. (2016). Implementation of Polysilicon Subwavelength Grating Reflectors in Standard Bulk CMOS Foundry Process. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0103116-005316

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsieh, Min-chun. “Implementation of Polysilicon Subwavelength Grating Reflectors in Standard Bulk CMOS Foundry Process.” 2016. Thesis, NSYSU. Accessed January 22, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0103116-005316.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsieh, Min-chun. “Implementation of Polysilicon Subwavelength Grating Reflectors in Standard Bulk CMOS Foundry Process.” 2016. Web. 22 Jan 2020.

Vancouver:

Hsieh M. Implementation of Polysilicon Subwavelength Grating Reflectors in Standard Bulk CMOS Foundry Process. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Jan 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0103116-005316.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsieh M. Implementation of Polysilicon Subwavelength Grating Reflectors in Standard Bulk CMOS Foundry Process. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0103116-005316

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


New Jersey Institute of Technology

29. Wang, Gang. Three-dimensional magnetic field sensor in IBM 0.18μm CMOS technology.

Degree: MSin Electrical Engineering - (M.S.), Electrical and Computer Engineering, 2012, New Jersey Institute of Technology

  This work presents a compact three-dimensional Magnetic Field Sensor (MFS) designed in standard Complementary Metal-Oxide-Semiconductor (CMOS) technology. A circular Vertical Hall Device (VHD) for… (more)

Subjects/Keywords: 3D magnetic field sensor; Complementary metal-oxide-semiconductor; Electrical and Electronics

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APA (6th Edition):

Wang, G. (2012). Three-dimensional magnetic field sensor in IBM 0.18μm CMOS technology. (Thesis). New Jersey Institute of Technology. Retrieved from https://digitalcommons.njit.edu/theses/128

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Gang. “Three-dimensional magnetic field sensor in IBM 0.18μm CMOS technology.” 2012. Thesis, New Jersey Institute of Technology. Accessed January 22, 2020. https://digitalcommons.njit.edu/theses/128.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Gang. “Three-dimensional magnetic field sensor in IBM 0.18μm CMOS technology.” 2012. Web. 22 Jan 2020.

Vancouver:

Wang G. Three-dimensional magnetic field sensor in IBM 0.18μm CMOS technology. [Internet] [Thesis]. New Jersey Institute of Technology; 2012. [cited 2020 Jan 22]. Available from: https://digitalcommons.njit.edu/theses/128.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang G. Three-dimensional magnetic field sensor in IBM 0.18μm CMOS technology. [Thesis]. New Jersey Institute of Technology; 2012. Available from: https://digitalcommons.njit.edu/theses/128

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Queensland University of Technology

30. Fu, Qiang. Advanced numerical characterization of silicon with defect by nanoindentation.

Degree: 2012, Queensland University of Technology

 Nano silicon is widely used as the essential element of complementary metal–oxide–semiconductor (CMOS) and solar cells. It is recognized that today, large portion of world… (more)

Subjects/Keywords: Nano silicon; metal–oxide–semiconductor (CMOS); solar cells

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APA (6th Edition):

Fu, Q. (2012). Advanced numerical characterization of silicon with defect by nanoindentation. (Thesis). Queensland University of Technology. Retrieved from https://eprints.qut.edu.au/54621/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fu, Qiang. “Advanced numerical characterization of silicon with defect by nanoindentation.” 2012. Thesis, Queensland University of Technology. Accessed January 22, 2020. https://eprints.qut.edu.au/54621/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fu, Qiang. “Advanced numerical characterization of silicon with defect by nanoindentation.” 2012. Web. 22 Jan 2020.

Vancouver:

Fu Q. Advanced numerical characterization of silicon with defect by nanoindentation. [Internet] [Thesis]. Queensland University of Technology; 2012. [cited 2020 Jan 22]. Available from: https://eprints.qut.edu.au/54621/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fu Q. Advanced numerical characterization of silicon with defect by nanoindentation. [Thesis]. Queensland University of Technology; 2012. Available from: https://eprints.qut.edu.au/54621/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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