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You searched for subject:(Compiler). Showing records 1 – 30 of 490 total matches.

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University of Waterloo

1. Selby, Jason W. A. Unconventional Applications of Compiler Analysis.

Degree: 2011, University of Waterloo

 Previously, compiler transformations have primarily focused on minimizing program execution time. This thesis explores some examples of applying compiler technology outside of its original scope.… (more)

Subjects/Keywords: Compiler Analysis; Compiler Optimization

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APA (6th Edition):

Selby, J. W. A. (2011). Unconventional Applications of Compiler Analysis. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/6184

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Selby, Jason W A. “Unconventional Applications of Compiler Analysis.” 2011. Thesis, University of Waterloo. Accessed October 16, 2019. http://hdl.handle.net/10012/6184.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Selby, Jason W A. “Unconventional Applications of Compiler Analysis.” 2011. Web. 16 Oct 2019.

Vancouver:

Selby JWA. Unconventional Applications of Compiler Analysis. [Internet] [Thesis]. University of Waterloo; 2011. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/10012/6184.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Selby JWA. Unconventional Applications of Compiler Analysis. [Thesis]. University of Waterloo; 2011. Available from: http://hdl.handle.net/10012/6184

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Georgia

2. Li, Nan. Energy-efficient program layout for multi-bank architectures.

Degree: MS, Computer Science, 2003, University of Georgia

 Energy conservation is an important problem for battery-powered embedded or portable systems. New technology such as RDRAM enables memory to operate at different power levels.… (more)

Subjects/Keywords: Compiler

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APA (6th Edition):

Li, N. (2003). Energy-efficient program layout for multi-bank architectures. (Masters Thesis). University of Georgia. Retrieved from http://purl.galileo.usg.edu/uga_etd/li_nan_200312_ms

Chicago Manual of Style (16th Edition):

Li, Nan. “Energy-efficient program layout for multi-bank architectures.” 2003. Masters Thesis, University of Georgia. Accessed October 16, 2019. http://purl.galileo.usg.edu/uga_etd/li_nan_200312_ms.

MLA Handbook (7th Edition):

Li, Nan. “Energy-efficient program layout for multi-bank architectures.” 2003. Web. 16 Oct 2019.

Vancouver:

Li N. Energy-efficient program layout for multi-bank architectures. [Internet] [Masters thesis]. University of Georgia; 2003. [cited 2019 Oct 16]. Available from: http://purl.galileo.usg.edu/uga_etd/li_nan_200312_ms.

Council of Science Editors:

Li N. Energy-efficient program layout for multi-bank architectures. [Masters Thesis]. University of Georgia; 2003. Available from: http://purl.galileo.usg.edu/uga_etd/li_nan_200312_ms


University of Alberta

3. Garg, Rahul. A compiler for parallel execution of numerical Python programs on graphics processing units.

Degree: MS, Department of Computing Science, 2009, University of Alberta

 Modern Graphics Processing Units (GPUs) are providing breakthrough performance for numerical computing at the cost of increased programming complexity. Current programming models for GPUs require… (more)

Subjects/Keywords: gpgpu; compiler

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APA (6th Edition):

Garg, R. (2009). A compiler for parallel execution of numerical Python programs on graphics processing units. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/4j03d0630

Chicago Manual of Style (16th Edition):

Garg, Rahul. “A compiler for parallel execution of numerical Python programs on graphics processing units.” 2009. Masters Thesis, University of Alberta. Accessed October 16, 2019. https://era.library.ualberta.ca/files/4j03d0630.

MLA Handbook (7th Edition):

Garg, Rahul. “A compiler for parallel execution of numerical Python programs on graphics processing units.” 2009. Web. 16 Oct 2019.

Vancouver:

Garg R. A compiler for parallel execution of numerical Python programs on graphics processing units. [Internet] [Masters thesis]. University of Alberta; 2009. [cited 2019 Oct 16]. Available from: https://era.library.ualberta.ca/files/4j03d0630.

Council of Science Editors:

Garg R. A compiler for parallel execution of numerical Python programs on graphics processing units. [Masters Thesis]. University of Alberta; 2009. Available from: https://era.library.ualberta.ca/files/4j03d0630


University of Alberta

4. Xunhao, Li. Jit4OpenCL: a compiler from Python to OpenCL.

Degree: MS, Department of Computing Science, 2010, University of Alberta

 Heterogeneous computing platforms that use GPUs and CPUs in tandem for computation have become an important choice to build low-cost high-performance computing platforms. The computing… (more)

Subjects/Keywords: Python; compiler; OpenCL

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APA (6th Edition):

Xunhao, L. (2010). Jit4OpenCL: a compiler from Python to OpenCL. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/1v53jx087

Chicago Manual of Style (16th Edition):

Xunhao, Li. “Jit4OpenCL: a compiler from Python to OpenCL.” 2010. Masters Thesis, University of Alberta. Accessed October 16, 2019. https://era.library.ualberta.ca/files/1v53jx087.

MLA Handbook (7th Edition):

Xunhao, Li. “Jit4OpenCL: a compiler from Python to OpenCL.” 2010. Web. 16 Oct 2019.

Vancouver:

Xunhao L. Jit4OpenCL: a compiler from Python to OpenCL. [Internet] [Masters thesis]. University of Alberta; 2010. [cited 2019 Oct 16]. Available from: https://era.library.ualberta.ca/files/1v53jx087.

Council of Science Editors:

Xunhao L. Jit4OpenCL: a compiler from Python to OpenCL. [Masters Thesis]. University of Alberta; 2010. Available from: https://era.library.ualberta.ca/files/1v53jx087

5. Mitropoulou, Konstantina. Performance optimizations for compiler-based error detection.

Degree: PhD, 2015, University of Edinburgh

 The trend towards smaller transistor technologies and lower operating voltages stresses the hardware and makes transistors more susceptible to transient errors. In future systems, performance… (more)

Subjects/Keywords: 005.75; fault tolerance; compiler

Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7

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APA (6th Edition):

Mitropoulou, K. (2015). Performance optimizations for compiler-based error detection. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/10473

Chicago Manual of Style (16th Edition):

Mitropoulou, Konstantina. “Performance optimizations for compiler-based error detection.” 2015. Doctoral Dissertation, University of Edinburgh. Accessed October 16, 2019. http://hdl.handle.net/1842/10473.

MLA Handbook (7th Edition):

Mitropoulou, Konstantina. “Performance optimizations for compiler-based error detection.” 2015. Web. 16 Oct 2019.

Vancouver:

Mitropoulou K. Performance optimizations for compiler-based error detection. [Internet] [Doctoral dissertation]. University of Edinburgh; 2015. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/1842/10473.

Council of Science Editors:

Mitropoulou K. Performance optimizations for compiler-based error detection. [Doctoral Dissertation]. University of Edinburgh; 2015. Available from: http://hdl.handle.net/1842/10473


Georgia Tech

6. Gupta, Meghana. Code generation and adaptive control divergence management for light weight SIMT processors.

Degree: MS, Computer Science, 2016, Georgia Tech

 The energy costs of data movement are limiting the performance scaling of future generations of high performance computing architectures targeted to data intensive applications. The… (more)

Subjects/Keywords: Compiler; SIMT; Control divergence

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APA (6th Edition):

Gupta, M. (2016). Code generation and adaptive control divergence management for light weight SIMT processors. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55044

Chicago Manual of Style (16th Edition):

Gupta, Meghana. “Code generation and adaptive control divergence management for light weight SIMT processors.” 2016. Masters Thesis, Georgia Tech. Accessed October 16, 2019. http://hdl.handle.net/1853/55044.

MLA Handbook (7th Edition):

Gupta, Meghana. “Code generation and adaptive control divergence management for light weight SIMT processors.” 2016. Web. 16 Oct 2019.

Vancouver:

Gupta M. Code generation and adaptive control divergence management for light weight SIMT processors. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/1853/55044.

Council of Science Editors:

Gupta M. Code generation and adaptive control divergence management for light weight SIMT processors. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55044


Louisiana State University

7. Hanagodimath, Pratik Prabhu. Performance Comparison Between Patus and Pluto Compilers on Stencils.

Degree: MSEE, Electrical and Computer Engineering, 2014, Louisiana State University

Comparing the performances of Patus and Pluto compilers on stencil applications. Stencils are written in Jacobi and Seidel style of coding and performances of both these compilers are analysed based on these coding styles.

Subjects/Keywords: Compiler optimization; parallel execution.

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APA (6th Edition):

Hanagodimath, P. P. (2014). Performance Comparison Between Patus and Pluto Compilers on Stencils. (Masters Thesis). Louisiana State University. Retrieved from etd-04142014-090546 ; https://digitalcommons.lsu.edu/gradschool_theses/2636

Chicago Manual of Style (16th Edition):

Hanagodimath, Pratik Prabhu. “Performance Comparison Between Patus and Pluto Compilers on Stencils.” 2014. Masters Thesis, Louisiana State University. Accessed October 16, 2019. etd-04142014-090546 ; https://digitalcommons.lsu.edu/gradschool_theses/2636.

MLA Handbook (7th Edition):

Hanagodimath, Pratik Prabhu. “Performance Comparison Between Patus and Pluto Compilers on Stencils.” 2014. Web. 16 Oct 2019.

Vancouver:

Hanagodimath PP. Performance Comparison Between Patus and Pluto Compilers on Stencils. [Internet] [Masters thesis]. Louisiana State University; 2014. [cited 2019 Oct 16]. Available from: etd-04142014-090546 ; https://digitalcommons.lsu.edu/gradschool_theses/2636.

Council of Science Editors:

Hanagodimath PP. Performance Comparison Between Patus and Pluto Compilers on Stencils. [Masters Thesis]. Louisiana State University; 2014. Available from: etd-04142014-090546 ; https://digitalcommons.lsu.edu/gradschool_theses/2636


University of California – Santa Cruz

8. Zhu, Yuxiong. The Live Graph.

Degree: Computer Engineering, 2017, University of California – Santa Cruz

 Live Graph (lgraph) is a graph optimized for live synthesis (Live Synthesize Graph orlgraph for short). By live, we mean that small changes in the… (more)

Subjects/Keywords: Computer engineering; Compiler; Graph; Synthesis

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APA (6th Edition):

Zhu, Y. (2017). The Live Graph. (Thesis). University of California – Santa Cruz. Retrieved from http://www.escholarship.org/uc/item/1zs153c6

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhu, Yuxiong. “The Live Graph.” 2017. Thesis, University of California – Santa Cruz. Accessed October 16, 2019. http://www.escholarship.org/uc/item/1zs153c6.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhu, Yuxiong. “The Live Graph.” 2017. Web. 16 Oct 2019.

Vancouver:

Zhu Y. The Live Graph. [Internet] [Thesis]. University of California – Santa Cruz; 2017. [cited 2019 Oct 16]. Available from: http://www.escholarship.org/uc/item/1zs153c6.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhu Y. The Live Graph. [Thesis]. University of California – Santa Cruz; 2017. Available from: http://www.escholarship.org/uc/item/1zs153c6

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Kansas

9. Smith, Adam R. Compiler Transformations to Generate Reentrant C Programs to Assist Software Parallelization.

Degree: MS, Electrical Engineering & Computer Science, 2009, University of Kansas

 As we move through the multi-core era into the many-core era it becomes obvi- ous that thread-based programming is here to stay. This trend in… (more)

Subjects/Keywords: Computer science; Compiler; Parallel; Reentrant

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APA (6th Edition):

Smith, A. R. (2009). Compiler Transformations to Generate Reentrant C Programs to Assist Software Parallelization. (Masters Thesis). University of Kansas. Retrieved from http://hdl.handle.net/1808/5314

Chicago Manual of Style (16th Edition):

Smith, Adam R. “Compiler Transformations to Generate Reentrant C Programs to Assist Software Parallelization.” 2009. Masters Thesis, University of Kansas. Accessed October 16, 2019. http://hdl.handle.net/1808/5314.

MLA Handbook (7th Edition):

Smith, Adam R. “Compiler Transformations to Generate Reentrant C Programs to Assist Software Parallelization.” 2009. Web. 16 Oct 2019.

Vancouver:

Smith AR. Compiler Transformations to Generate Reentrant C Programs to Assist Software Parallelization. [Internet] [Masters thesis]. University of Kansas; 2009. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/1808/5314.

Council of Science Editors:

Smith AR. Compiler Transformations to Generate Reentrant C Programs to Assist Software Parallelization. [Masters Thesis]. University of Kansas; 2009. Available from: http://hdl.handle.net/1808/5314


University of Illinois – Chicago

10. Casula, Dario. Witnessing Control Flow Graph Optimizations.

Degree: 2016, University of Illinois – Chicago

 Proving the correctness of a program transformation, and specifically, of a compiler op- timization, is a long-standing research problem. Trusting the compiler requires to guarantee… (more)

Subjects/Keywords: llvm; witness; z3; CFG; compiler

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APA (6th Edition):

Casula, D. (2016). Witnessing Control Flow Graph Optimizations. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/20974

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Casula, Dario. “Witnessing Control Flow Graph Optimizations.” 2016. Thesis, University of Illinois – Chicago. Accessed October 16, 2019. http://hdl.handle.net/10027/20974.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Casula, Dario. “Witnessing Control Flow Graph Optimizations.” 2016. Web. 16 Oct 2019.

Vancouver:

Casula D. Witnessing Control Flow Graph Optimizations. [Internet] [Thesis]. University of Illinois – Chicago; 2016. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/10027/20974.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Casula D. Witnessing Control Flow Graph Optimizations. [Thesis]. University of Illinois – Chicago; 2016. Available from: http://hdl.handle.net/10027/20974

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

11. Liu, Qingrui. Compiler-Directed Error Resilience for Reliable Computing.

Degree: PhD, Electrical and Computer Engineering, 2018, Virginia Tech

 Error resilience has become as important as power and performance in modern computing architecture. There are various sources of errors that can paralyze real-world computing… (more)

Subjects/Keywords: Reliability; Compiler Optimization; Computer Architecture

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APA (6th Edition):

Liu, Q. (2018). Compiler-Directed Error Resilience for Reliable Computing. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/84526

Chicago Manual of Style (16th Edition):

Liu, Qingrui. “Compiler-Directed Error Resilience for Reliable Computing.” 2018. Doctoral Dissertation, Virginia Tech. Accessed October 16, 2019. http://hdl.handle.net/10919/84526.

MLA Handbook (7th Edition):

Liu, Qingrui. “Compiler-Directed Error Resilience for Reliable Computing.” 2018. Web. 16 Oct 2019.

Vancouver:

Liu Q. Compiler-Directed Error Resilience for Reliable Computing. [Internet] [Doctoral dissertation]. Virginia Tech; 2018. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/10919/84526.

Council of Science Editors:

Liu Q. Compiler-Directed Error Resilience for Reliable Computing. [Doctoral Dissertation]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/84526


Halmstad University

12. Muellegger, Markus. Evaluation of Compilers for MATLAB- to C-Code Translation.

Degree: Computer and Electrical Engineering (IDE), 2008, Halmstad University

  MATLAB to C code translation is of increasing interest for science and industry. In detail two MATLAB to C compilers denoted as Matlab to… (more)

Subjects/Keywords: MATLAB; C; Automatic Translation; Compiler

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APA (6th Edition):

Muellegger, M. (2008). Evaluation of Compilers for MATLAB- to C-Code Translation. (Thesis). Halmstad University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-1149

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Muellegger, Markus. “Evaluation of Compilers for MATLAB- to C-Code Translation.” 2008. Thesis, Halmstad University. Accessed October 16, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-1149.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Muellegger, Markus. “Evaluation of Compilers for MATLAB- to C-Code Translation.” 2008. Web. 16 Oct 2019.

Vancouver:

Muellegger M. Evaluation of Compilers for MATLAB- to C-Code Translation. [Internet] [Thesis]. Halmstad University; 2008. [cited 2019 Oct 16]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-1149.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Muellegger M. Evaluation of Compilers for MATLAB- to C-Code Translation. [Thesis]. Halmstad University; 2008. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-1149

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

13. De Smalen, S. A solution to misaligned data access in a vectorizing compiler framework:.

Degree: 2009, Delft University of Technology

 Vectorizing code for short vector architectures as employed by today’s multimedia extensions comes with a number of issues. The responsibilities of these issues are moved… (more)

Subjects/Keywords: SIMD; vectorization; compiler; alignment

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APA (6th Edition):

De Smalen, S. (2009). A solution to misaligned data access in a vectorizing compiler framework:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:ee641d0f-b8c2-4194-bc46-a3e5326bea5f

Chicago Manual of Style (16th Edition):

De Smalen, S. “A solution to misaligned data access in a vectorizing compiler framework:.” 2009. Masters Thesis, Delft University of Technology. Accessed October 16, 2019. http://resolver.tudelft.nl/uuid:ee641d0f-b8c2-4194-bc46-a3e5326bea5f.

MLA Handbook (7th Edition):

De Smalen, S. “A solution to misaligned data access in a vectorizing compiler framework:.” 2009. Web. 16 Oct 2019.

Vancouver:

De Smalen S. A solution to misaligned data access in a vectorizing compiler framework:. [Internet] [Masters thesis]. Delft University of Technology; 2009. [cited 2019 Oct 16]. Available from: http://resolver.tudelft.nl/uuid:ee641d0f-b8c2-4194-bc46-a3e5326bea5f.

Council of Science Editors:

De Smalen S. A solution to misaligned data access in a vectorizing compiler framework:. [Masters Thesis]. Delft University of Technology; 2009. Available from: http://resolver.tudelft.nl/uuid:ee641d0f-b8c2-4194-bc46-a3e5326bea5f


Delft University of Technology

14. Schoneveld, G.J. VHDL to SystemC: The Design of a Translator:.

Degree: 2009, Delft University of Technology

 VHDL and SystemC are both languages to describe or model circuits and systems. Reasons could exist for wanting to translate a model in VHDL to… (more)

Subjects/Keywords: VHDL; SystemC; translator; converter; compiler

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APA (6th Edition):

Schoneveld, G. J. (2009). VHDL to SystemC: The Design of a Translator:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:f2ecf719-d8d4-4197-be07-1822e84f6968

Chicago Manual of Style (16th Edition):

Schoneveld, G J. “VHDL to SystemC: The Design of a Translator:.” 2009. Masters Thesis, Delft University of Technology. Accessed October 16, 2019. http://resolver.tudelft.nl/uuid:f2ecf719-d8d4-4197-be07-1822e84f6968.

MLA Handbook (7th Edition):

Schoneveld, G J. “VHDL to SystemC: The Design of a Translator:.” 2009. Web. 16 Oct 2019.

Vancouver:

Schoneveld GJ. VHDL to SystemC: The Design of a Translator:. [Internet] [Masters thesis]. Delft University of Technology; 2009. [cited 2019 Oct 16]. Available from: http://resolver.tudelft.nl/uuid:f2ecf719-d8d4-4197-be07-1822e84f6968.

Council of Science Editors:

Schoneveld GJ. VHDL to SystemC: The Design of a Translator:. [Masters Thesis]. Delft University of Technology; 2009. Available from: http://resolver.tudelft.nl/uuid:f2ecf719-d8d4-4197-be07-1822e84f6968


Delft University of Technology

15. Vielvoije, E. SPIN's Promela to Java Compiler: with help from Stratego:.

Degree: Electrical Engineering, Mathematics and Computer Science, Computer Science, 2008, Delft University of Technology

 In model checking a formal model of a software system is constructed. That model is verified against a set of properties expressed in some logic.… (more)

Subjects/Keywords: promela; java; compiler; stratego

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APA (6th Edition):

Vielvoije, E. (2008). SPIN's Promela to Java Compiler: with help from Stratego:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:c7106f0b-5b8f-44fe-bca7-421653ec76c5

Chicago Manual of Style (16th Edition):

Vielvoije, E. “SPIN's Promela to Java Compiler: with help from Stratego:.” 2008. Masters Thesis, Delft University of Technology. Accessed October 16, 2019. http://resolver.tudelft.nl/uuid:c7106f0b-5b8f-44fe-bca7-421653ec76c5.

MLA Handbook (7th Edition):

Vielvoije, E. “SPIN's Promela to Java Compiler: with help from Stratego:.” 2008. Web. 16 Oct 2019.

Vancouver:

Vielvoije E. SPIN's Promela to Java Compiler: with help from Stratego:. [Internet] [Masters thesis]. Delft University of Technology; 2008. [cited 2019 Oct 16]. Available from: http://resolver.tudelft.nl/uuid:c7106f0b-5b8f-44fe-bca7-421653ec76c5.

Council of Science Editors:

Vielvoije E. SPIN's Promela to Java Compiler: with help from Stratego:. [Masters Thesis]. Delft University of Technology; 2008. Available from: http://resolver.tudelft.nl/uuid:c7106f0b-5b8f-44fe-bca7-421653ec76c5


University of Oregon

16. Clauson, Aran. Search-based Optimization for Compiler Machine-code Generation.

Degree: 2013, University of Oregon

 Compilation encompasses many steps. Parsing turns the input program into a more manageable syntax tree. Verification ensures that the program makes some semblance of sense.… (more)

Subjects/Keywords: Code-generation; Compiler; Search

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APA (6th Edition):

Clauson, A. (2013). Search-based Optimization for Compiler Machine-code Generation. (Thesis). University of Oregon. Retrieved from http://hdl.handle.net/1794/13433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Clauson, Aran. “Search-based Optimization for Compiler Machine-code Generation.” 2013. Thesis, University of Oregon. Accessed October 16, 2019. http://hdl.handle.net/1794/13433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Clauson, Aran. “Search-based Optimization for Compiler Machine-code Generation.” 2013. Web. 16 Oct 2019.

Vancouver:

Clauson A. Search-based Optimization for Compiler Machine-code Generation. [Internet] [Thesis]. University of Oregon; 2013. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/1794/13433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Clauson A. Search-based Optimization for Compiler Machine-code Generation. [Thesis]. University of Oregon; 2013. Available from: http://hdl.handle.net/1794/13433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oklahoma State University

17. Sundararajan, Gopalakrishnan. Osuspram: Design of a Single Port Sram Compiler in Ncsu FreePDK45 Process.

Degree: School of Electrical & Computer Engineering, 2010, Oklahoma State University

 The main focus of this thesis is to design a Static Random Access Memory (SRAM) Compiler that could generate memories of required configurations. The layout… (more)

Subjects/Keywords: compiler; freepdk45; memory; skill; sram

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sundararajan, G. (2010). Osuspram: Design of a Single Port Sram Compiler in Ncsu FreePDK45 Process. (Thesis). Oklahoma State University. Retrieved from http://hdl.handle.net/11244/10280

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sundararajan, Gopalakrishnan. “Osuspram: Design of a Single Port Sram Compiler in Ncsu FreePDK45 Process.” 2010. Thesis, Oklahoma State University. Accessed October 16, 2019. http://hdl.handle.net/11244/10280.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sundararajan, Gopalakrishnan. “Osuspram: Design of a Single Port Sram Compiler in Ncsu FreePDK45 Process.” 2010. Web. 16 Oct 2019.

Vancouver:

Sundararajan G. Osuspram: Design of a Single Port Sram Compiler in Ncsu FreePDK45 Process. [Internet] [Thesis]. Oklahoma State University; 2010. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/11244/10280.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sundararajan G. Osuspram: Design of a Single Port Sram Compiler in Ncsu FreePDK45 Process. [Thesis]. Oklahoma State University; 2010. Available from: http://hdl.handle.net/11244/10280

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. Hebert, Chris. Inferring Types to Eliminate Ownership Checks in an Intentional JavaScript Compiler.

Degree: MS, 2015, University of New Hampshire

 Concurrent programs are notoriously difficult to develop due to the non-deterministic nature of thread scheduling. It is desirable to have a programming language to make… (more)

Subjects/Keywords: compiler; javascript; optimization; Computer science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hebert, C. (2015). Inferring Types to Eliminate Ownership Checks in an Intentional JavaScript Compiler. (Thesis). University of New Hampshire. Retrieved from https://scholars.unh.edu/thesis/1021

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hebert, Chris. “Inferring Types to Eliminate Ownership Checks in an Intentional JavaScript Compiler.” 2015. Thesis, University of New Hampshire. Accessed October 16, 2019. https://scholars.unh.edu/thesis/1021.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hebert, Chris. “Inferring Types to Eliminate Ownership Checks in an Intentional JavaScript Compiler.” 2015. Web. 16 Oct 2019.

Vancouver:

Hebert C. Inferring Types to Eliminate Ownership Checks in an Intentional JavaScript Compiler. [Internet] [Thesis]. University of New Hampshire; 2015. [cited 2019 Oct 16]. Available from: https://scholars.unh.edu/thesis/1021.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hebert C. Inferring Types to Eliminate Ownership Checks in an Intentional JavaScript Compiler. [Thesis]. University of New Hampshire; 2015. Available from: https://scholars.unh.edu/thesis/1021

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Edinburgh

19. Chandramohan, Kiran. Mapping parallelism to heterogeneous processors.

Degree: PhD, 2016, University of Edinburgh

 Most embedded devices are based on heterogeneous Multiprocessor System on Chips (MPSoCs). These contain a variety of processors like CPUs, micro-controllers, DSPs, GPUs and specialised… (more)

Subjects/Keywords: 004; heterogeneous processors; compiler

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chandramohan, K. (2016). Mapping parallelism to heterogeneous processors. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/22028

Chicago Manual of Style (16th Edition):

Chandramohan, Kiran. “Mapping parallelism to heterogeneous processors.” 2016. Doctoral Dissertation, University of Edinburgh. Accessed October 16, 2019. http://hdl.handle.net/1842/22028.

MLA Handbook (7th Edition):

Chandramohan, Kiran. “Mapping parallelism to heterogeneous processors.” 2016. Web. 16 Oct 2019.

Vancouver:

Chandramohan K. Mapping parallelism to heterogeneous processors. [Internet] [Doctoral dissertation]. University of Edinburgh; 2016. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/1842/22028.

Council of Science Editors:

Chandramohan K. Mapping parallelism to heterogeneous processors. [Doctoral Dissertation]. University of Edinburgh; 2016. Available from: http://hdl.handle.net/1842/22028


University of New South Wales

20. Ye, Ding. Accelerating Dynamic Detection of Memory Errors for C Programs via Static Analysis.

Degree: Computer Science & Engineering, 2015, University of New South Wales

 Memory errors in C programs are the root causes of many defects and vulnerabilitiesin software engineering. Among the available error detection techniques,dynamic analysis is widely… (more)

Subjects/Keywords: C programs; LLVM Compiler architecture

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ye, D. (2015). Accelerating Dynamic Detection of Memory Errors for C Programs via Static Analysis. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/54507 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:35127/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Ye, Ding. “Accelerating Dynamic Detection of Memory Errors for C Programs via Static Analysis.” 2015. Doctoral Dissertation, University of New South Wales. Accessed October 16, 2019. http://handle.unsw.edu.au/1959.4/54507 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:35127/SOURCE02?view=true.

MLA Handbook (7th Edition):

Ye, Ding. “Accelerating Dynamic Detection of Memory Errors for C Programs via Static Analysis.” 2015. Web. 16 Oct 2019.

Vancouver:

Ye D. Accelerating Dynamic Detection of Memory Errors for C Programs via Static Analysis. [Internet] [Doctoral dissertation]. University of New South Wales; 2015. [cited 2019 Oct 16]. Available from: http://handle.unsw.edu.au/1959.4/54507 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:35127/SOURCE02?view=true.

Council of Science Editors:

Ye D. Accelerating Dynamic Detection of Memory Errors for C Programs via Static Analysis. [Doctoral Dissertation]. University of New South Wales; 2015. Available from: http://handle.unsw.edu.au/1959.4/54507 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:35127/SOURCE02?view=true


University of Delaware

21. Chen, Yuanfang. Software simultaneous multithreading through compilation .

Degree: 2018, University of Delaware

 With the Dennard Scaling law break for a long time, the computer architecture design progress towards the wider rather than deeper organization. There are three… (more)

Subjects/Keywords: Applied sciences; Compiler; LLVM; SMT

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, Y. (2018). Software simultaneous multithreading through compilation . (Doctoral Dissertation). University of Delaware. Retrieved from http://udspace.udel.edu/handle/19716/23594

Chicago Manual of Style (16th Edition):

Chen, Yuanfang. “Software simultaneous multithreading through compilation .” 2018. Doctoral Dissertation, University of Delaware. Accessed October 16, 2019. http://udspace.udel.edu/handle/19716/23594.

MLA Handbook (7th Edition):

Chen, Yuanfang. “Software simultaneous multithreading through compilation .” 2018. Web. 16 Oct 2019.

Vancouver:

Chen Y. Software simultaneous multithreading through compilation . [Internet] [Doctoral dissertation]. University of Delaware; 2018. [cited 2019 Oct 16]. Available from: http://udspace.udel.edu/handle/19716/23594.

Council of Science Editors:

Chen Y. Software simultaneous multithreading through compilation . [Doctoral Dissertation]. University of Delaware; 2018. Available from: http://udspace.udel.edu/handle/19716/23594


University of Notre Dame

22. Peter James Bui. A Compiler Toolchain for Distributed Data Intensive Scientific Workflows</h1>.

Degree: PhD, Computer Science and Engineering, 2012, University of Notre Dame

  With the growing amount of computational resources available to researchers today and the explosion of scientific data in modern research, it is imperative that… (more)

Subjects/Keywords: compiler; distributed systems; workflows; python

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bui, P. J. (2012). A Compiler Toolchain for Distributed Data Intensive Scientific Workflows</h1>. (Doctoral Dissertation). University of Notre Dame. Retrieved from https://curate.nd.edu/show/pk02c823v2f

Chicago Manual of Style (16th Edition):

Bui, Peter James. “A Compiler Toolchain for Distributed Data Intensive Scientific Workflows</h1>.” 2012. Doctoral Dissertation, University of Notre Dame. Accessed October 16, 2019. https://curate.nd.edu/show/pk02c823v2f.

MLA Handbook (7th Edition):

Bui, Peter James. “A Compiler Toolchain for Distributed Data Intensive Scientific Workflows</h1>.” 2012. Web. 16 Oct 2019.

Vancouver:

Bui PJ. A Compiler Toolchain for Distributed Data Intensive Scientific Workflows</h1>. [Internet] [Doctoral dissertation]. University of Notre Dame; 2012. [cited 2019 Oct 16]. Available from: https://curate.nd.edu/show/pk02c823v2f.

Council of Science Editors:

Bui PJ. A Compiler Toolchain for Distributed Data Intensive Scientific Workflows</h1>. [Doctoral Dissertation]. University of Notre Dame; 2012. Available from: https://curate.nd.edu/show/pk02c823v2f


University of New South Wales

23. Sewell, Thomas. Translation validation for verified, efficient and timely operating systems.

Degree: Computer Science & Engineering, 2017, University of New South Wales

 Computer software is typically written in one language and then translatedout of that language into the native binary languages of the machines thesoftware will run… (more)

Subjects/Keywords: Compiler; Translation Validation; Operating System

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sewell, T. (2017). Translation validation for verified, efficient and timely operating systems. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/58861 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:47819/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Sewell, Thomas. “Translation validation for verified, efficient and timely operating systems.” 2017. Doctoral Dissertation, University of New South Wales. Accessed October 16, 2019. http://handle.unsw.edu.au/1959.4/58861 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:47819/SOURCE02?view=true.

MLA Handbook (7th Edition):

Sewell, Thomas. “Translation validation for verified, efficient and timely operating systems.” 2017. Web. 16 Oct 2019.

Vancouver:

Sewell T. Translation validation for verified, efficient and timely operating systems. [Internet] [Doctoral dissertation]. University of New South Wales; 2017. [cited 2019 Oct 16]. Available from: http://handle.unsw.edu.au/1959.4/58861 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:47819/SOURCE02?view=true.

Council of Science Editors:

Sewell T. Translation validation for verified, efficient and timely operating systems. [Doctoral Dissertation]. University of New South Wales; 2017. Available from: http://handle.unsw.edu.au/1959.4/58861 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:47819/SOURCE02?view=true


Northeastern University

24. Gong, Xiang. Improving GPU performance through instruction redistribution and diversification.

Degree: PhD, Department of Electrical and Computer Engineering, 2018, Northeastern University

 As throughput-oriented accelerators, GPUs provide tremendous processing power by executing a massive number of threads in parallel. However, exploiting high degrees of thread-level parallelism (TLP)… (more)

Subjects/Keywords: compiler; GPU; performance; simulator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gong, X. (2018). Improving GPU performance through instruction redistribution and diversification. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/D20294182

Chicago Manual of Style (16th Edition):

Gong, Xiang. “Improving GPU performance through instruction redistribution and diversification.” 2018. Doctoral Dissertation, Northeastern University. Accessed October 16, 2019. http://hdl.handle.net/2047/D20294182.

MLA Handbook (7th Edition):

Gong, Xiang. “Improving GPU performance through instruction redistribution and diversification.” 2018. Web. 16 Oct 2019.

Vancouver:

Gong X. Improving GPU performance through instruction redistribution and diversification. [Internet] [Doctoral dissertation]. Northeastern University; 2018. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/2047/D20294182.

Council of Science Editors:

Gong X. Improving GPU performance through instruction redistribution and diversification. [Doctoral Dissertation]. Northeastern University; 2018. Available from: http://hdl.handle.net/2047/D20294182


NSYSU

25. HSU, CHUN-TO. Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Read-only memory (ROM) plays an important role In modern System-on-Chip (SoC) designs. Due to the regularity of ROM structure, ROM components are usually generated through… (more)

Subjects/Keywords: RTL Compiler; ROM generator; Programmable Logic Array (PLA); ROM Compiler

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

HSU, C. (2014). Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726114-101438

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

HSU, CHUN-TO. “Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM.” 2014. Thesis, NSYSU. Accessed October 16, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726114-101438.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

HSU, CHUN-TO. “Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM.” 2014. Web. 16 Oct 2019.

Vancouver:

HSU C. Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Oct 16]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726114-101438.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

HSU C. Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726114-101438

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

26. Horník, Jakub. Zadní část překladače podmnožiny jazyka C pro 8-bitový procesor .

Degree: 2011, Brno University of Technology

 Překladač umožňuje programátorovi popisovat algoritmus ve vysokoúrovňovém programovacím jazyce s vyšší mírou abstrakce a strukturovaností, než poskytuje nízkoúrovňový strojový kód. Tato práce se týká návrhu… (more)

Subjects/Keywords: kompilátor; Low Level Virtual Machine Compiler; mezikód; překladač; PicoBlaze; PicoBlaze C Compiler; Small Device C Compiler; zadní část překladače; back-end; compiler; intermediate code; Low Level Virtual Machine Compiler; PicoBlaze; PicoBlaze C Compiler; Small Device C Compiler

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Horník, J. (2011). Zadní část překladače podmnožiny jazyka C pro 8-bitový procesor . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/54208

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Horník, Jakub. “Zadní část překladače podmnožiny jazyka C pro 8-bitový procesor .” 2011. Thesis, Brno University of Technology. Accessed October 16, 2019. http://hdl.handle.net/11012/54208.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Horník, Jakub. “Zadní část překladače podmnožiny jazyka C pro 8-bitový procesor .” 2011. Web. 16 Oct 2019.

Vancouver:

Horník J. Zadní část překladače podmnožiny jazyka C pro 8-bitový procesor . [Internet] [Thesis]. Brno University of Technology; 2011. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/11012/54208.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Horník J. Zadní část překladače podmnožiny jazyka C pro 8-bitový procesor . [Thesis]. Brno University of Technology; 2011. Available from: http://hdl.handle.net/11012/54208

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


EPFL

27. Petrashko, Dmytro. Design and implementation of an optimizing type-centric compiler for a high-level language.

Degree: 2017, EPFL

 Production compilers for programming languages face multiple requirements. They should be correct, as we rely on them to produce code. They should be fast, in… (more)

Subjects/Keywords: compiler design; optimizing compiler; compiler performance; tree traversal fusion; cache locality; call graphs; parametric polymorphism; static analysis; Scala

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Petrashko, D. (2017). Design and implementation of an optimizing type-centric compiler for a high-level language. (Thesis). EPFL. Retrieved from http://infoscience.epfl.ch/record/232671

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Petrashko, Dmytro. “Design and implementation of an optimizing type-centric compiler for a high-level language.” 2017. Thesis, EPFL. Accessed October 16, 2019. http://infoscience.epfl.ch/record/232671.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Petrashko, Dmytro. “Design and implementation of an optimizing type-centric compiler for a high-level language.” 2017. Web. 16 Oct 2019.

Vancouver:

Petrashko D. Design and implementation of an optimizing type-centric compiler for a high-level language. [Internet] [Thesis]. EPFL; 2017. [cited 2019 Oct 16]. Available from: http://infoscience.epfl.ch/record/232671.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Petrashko D. Design and implementation of an optimizing type-centric compiler for a high-level language. [Thesis]. EPFL; 2017. Available from: http://infoscience.epfl.ch/record/232671

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Utah

28. Pagariya, Rohit. Direct equivalence testing of embedded software.

Degree: MS, School of Computing, 2011, University of Utah

 Direct equivalence testing is a framework for detecting errors in C compilers and application programs that exploits the fact that program semantics should be preserved… (more)

Subjects/Keywords: Compiler testing; Embedded software; Equivalence testing; Verification

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pagariya, R. (2011). Direct equivalence testing of embedded software. (Masters Thesis). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/48/rec/740

Chicago Manual of Style (16th Edition):

Pagariya, Rohit. “Direct equivalence testing of embedded software.” 2011. Masters Thesis, University of Utah. Accessed October 16, 2019. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/48/rec/740.

MLA Handbook (7th Edition):

Pagariya, Rohit. “Direct equivalence testing of embedded software.” 2011. Web. 16 Oct 2019.

Vancouver:

Pagariya R. Direct equivalence testing of embedded software. [Internet] [Masters thesis]. University of Utah; 2011. [cited 2019 Oct 16]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/48/rec/740.

Council of Science Editors:

Pagariya R. Direct equivalence testing of embedded software. [Masters Thesis]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/48/rec/740


University of Edinburgh

29. Tournavitis, Georgios. Profile-driven parallelisation of sequential programs.

Degree: 2011, University of Edinburgh

 Traditional parallelism detection in compilers is performed by means of static analysis and more specifically data and control dependence analysis. The information that is available… (more)

Subjects/Keywords: 005.3; compiler; multi-core; parallelisation; pipeline

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tournavitis, G. (2011). Profile-driven parallelisation of sequential programs. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/5287

Chicago Manual of Style (16th Edition):

Tournavitis, Georgios. “Profile-driven parallelisation of sequential programs.” 2011. Doctoral Dissertation, University of Edinburgh. Accessed October 16, 2019. http://hdl.handle.net/1842/5287.

MLA Handbook (7th Edition):

Tournavitis, Georgios. “Profile-driven parallelisation of sequential programs.” 2011. Web. 16 Oct 2019.

Vancouver:

Tournavitis G. Profile-driven parallelisation of sequential programs. [Internet] [Doctoral dissertation]. University of Edinburgh; 2011. [cited 2019 Oct 16]. Available from: http://hdl.handle.net/1842/5287.

Council of Science Editors:

Tournavitis G. Profile-driven parallelisation of sequential programs. [Doctoral Dissertation]. University of Edinburgh; 2011. Available from: http://hdl.handle.net/1842/5287


Penn State University

30. Ding, Wei. A Fresh Look At Data Locality On Emerging Multicores And Manycores.

Degree: PhD, Computer Science and Engineering, 2014, Penn State University

 The emergence of multicore platforms offers several opportunities for boosting ap- plication performance. These opportunities, which include parallelism and data locality benefits, require strong support… (more)

Subjects/Keywords: Data Locality; Multicore; Manycore; Compiler; Loop

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ding, W. (2014). A Fresh Look At Data Locality On Emerging Multicores And Manycores. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/22506

Chicago Manual of Style (16th Edition):

Ding, Wei. “A Fresh Look At Data Locality On Emerging Multicores And Manycores.” 2014. Doctoral Dissertation, Penn State University. Accessed October 16, 2019. https://etda.libraries.psu.edu/catalog/22506.

MLA Handbook (7th Edition):

Ding, Wei. “A Fresh Look At Data Locality On Emerging Multicores And Manycores.” 2014. Web. 16 Oct 2019.

Vancouver:

Ding W. A Fresh Look At Data Locality On Emerging Multicores And Manycores. [Internet] [Doctoral dissertation]. Penn State University; 2014. [cited 2019 Oct 16]. Available from: https://etda.libraries.psu.edu/catalog/22506.

Council of Science Editors:

Ding W. A Fresh Look At Data Locality On Emerging Multicores And Manycores. [Doctoral Dissertation]. Penn State University; 2014. Available from: https://etda.libraries.psu.edu/catalog/22506

[1] [2] [3] [4] [5] … [17]

.