subject:(Comparator)

Southern Illinois University

1. West, Paul Martin. TECHNIQUES FOR DIGITAL LOW DROPOUT REGULATOR MODELING AND TRANSIENT RESPONSE ENHANCEMENT.

Degree: MS, Electrical and Computer Engineering, 2016, Southern Illinois University

URL: https://opensiuc.lib.siu.edu/theses/1878

► Low dropout regulators (LDOs) are important components for power management in modern integrated circuits. With the continued scaling down of power supply voltage, digital… (more)

Subjects/Keywords: Comparator; LDO; Modeling; Transient Response; Voltage Regulator

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APA (6^th Edition):

West, P. M. (2016). TECHNIQUES FOR DIGITAL LOW DROPOUT REGULATOR MODELING AND TRANSIENT RESPONSE ENHANCEMENT. (Masters Thesis). Southern Illinois University. Retrieved from https://opensiuc.lib.siu.edu/theses/1878

Chicago Manual of Style (16^th Edition):

West, Paul Martin. “TECHNIQUES FOR DIGITAL LOW DROPOUT REGULATOR MODELING AND TRANSIENT RESPONSE ENHANCEMENT.” 2016. Masters Thesis, Southern Illinois University. Accessed March 07, 2021. https://opensiuc.lib.siu.edu/theses/1878.

MLA Handbook (7^th Edition):

West, Paul Martin. “TECHNIQUES FOR DIGITAL LOW DROPOUT REGULATOR MODELING AND TRANSIENT RESPONSE ENHANCEMENT.” 2016. Web. 07 Mar 2021.

Vancouver:

West PM. TECHNIQUES FOR DIGITAL LOW DROPOUT REGULATOR MODELING AND TRANSIENT RESPONSE ENHANCEMENT. [Internet] [Masters thesis]. Southern Illinois University; 2016. [cited 2021 Mar 07]. Available from: https://opensiuc.lib.siu.edu/theses/1878.

Council of Science Editors:

West PM. TECHNIQUES FOR DIGITAL LOW DROPOUT REGULATOR MODELING AND TRANSIENT RESPONSE ENHANCEMENT. [Masters Thesis]. Southern Illinois University; 2016. Available from: https://opensiuc.lib.siu.edu/theses/1878

NSYSU

2. Chen , Hsin-cheng. Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0616115-104146

► A high speed and low power Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter is proposed in this thesis. Using only two stage in the proposed ADC… (more)

Subjects/Keywords: Successive Approximation ADC; Error correction; Dynamic comparator; Pipelined ADC; Additional comparator for MSB

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Chen , H. (2015). Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0616115-104146

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chen , Hsin-cheng. “Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter.” 2015. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0616115-104146.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chen , Hsin-cheng. “Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter.” 2015. Web. 07 Mar 2021.

Vancouver:

Chen H. Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter. [Internet] [Thesis]. NSYSU; 2015. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0616115-104146.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen H. Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0616115-104146

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

3. Chen, Yen-yu. On the design and evaluation of a programmable frequency generator ASIC for acoustic-wave sensor application.

Degree: Master, Electrical Engineering, 2011, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0822111-163935

► In recent years, due to advances in semiconductor technology and mature integrated circuit design, complex signal processing equipment is beginning to be replaced by the… (more)

Subjects/Keywords: piezoelectric crystal; programmable frequency generator; resonance frequency; amplitude detector; latch comparator

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APA (6^th Edition):

Chen, Y. (2011). On the design and evaluation of a programmable frequency generator ASIC for acoustic-wave sensor application. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0822111-163935

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chen, Yen-yu. “On the design and evaluation of a programmable frequency generator ASIC for acoustic-wave sensor application.” 2011. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0822111-163935.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chen, Yen-yu. “On the design and evaluation of a programmable frequency generator ASIC for acoustic-wave sensor application.” 2011. Web. 07 Mar 2021.

Vancouver:

Chen Y. On the design and evaluation of a programmable frequency generator ASIC for acoustic-wave sensor application. [Internet] [Thesis]. NSYSU; 2011. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0822111-163935.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Y. On the design and evaluation of a programmable frequency generator ASIC for acoustic-wave sensor application. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0822111-163935

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

4. Kang, Ruei-Gen. Third Order Continuous-Time Sigma-Delta Modulator with 1.5bit Quantizer.

Degree: Master, Electrical Engineering, 2011, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830111-145845

► The thesis proposes a third order continuous-time sigma delta modulator used in GSM. We used a special 1.5bit quantizer, and to use its three different… (more)

Subjects/Keywords: 1.5bit quantizer; continuous-time; sigma-delta modulator; comparator

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APA (6^th Edition):

Kang, R. (2011). Third Order Continuous-Time Sigma-Delta Modulator with 1.5bit Quantizer. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830111-145845

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Kang, Ruei-Gen. “Third Order Continuous-Time Sigma-Delta Modulator with 1.5bit Quantizer.” 2011. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830111-145845.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Kang, Ruei-Gen. “Third Order Continuous-Time Sigma-Delta Modulator with 1.5bit Quantizer.” 2011. Web. 07 Mar 2021.

Vancouver:

Kang R. Third Order Continuous-Time Sigma-Delta Modulator with 1.5bit Quantizer. [Internet] [Thesis]. NSYSU; 2011. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830111-145845.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kang R. Third Order Continuous-Time Sigma-Delta Modulator with 1.5bit Quantizer. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0830111-145845

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

5. Huang, Hui-wen. A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824

► This thesis presents the architecture of a 10-bit 250-MS/s two-step pipelined analog-to-digital converter for reducing power consumption in TSMC 90nm CMOS technology. The first stage… (more)

Subjects/Keywords: Dynamic Comparator; Bootstrapped Switch; Successive Approximation ADC; Binary Search ADC

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APA (6^th Edition):

Huang, H. (2015). A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Huang, Hui-wen. “A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Huang, Hui-wen. “A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Web. 07 Mar 2021.

Vancouver:

Huang H. A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Internet] [Thesis]. NSYSU; 2015. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang H. A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Texas A&M University

6. Kim, Yongtae. Energy Efficient and Error Resilient Neuromorphic Computing in VLSI.

Degree: PhD, Electrical Engineering, 2013, Texas A&M University

URL: http://hdl.handle.net/1969.1/151721

► Realization of the conventional Von Neumann architecture faces increasing challenges due to growing process variations, device reliability and power consumption. As an appealing architectural solution,… (more)

▼ Realization of the conventional Von Neumann architecture faces increasing challenges due to growing process variations, device reliability and power consumption. As an appealing architectural solution, brain-inspired neuromorphic computing has drawn a great deal of research interest due to its potential improved scalability and power efficiency, and better suitability in processing complex tasks. Moreover, inherit error resilience in neuromorphic computing allows remarkable power and energy savings by exploiting approximate computing. This dissertation focuses on a scalable and energy efficient neurocomputing architecture which leverages emerging memristor nanodevices and a novel approximate arithmetic for cognitive computing. First, brain-inspired digital neuromorphic processor (DNP) architecture with memristive synaptic crossbar is presented for large scale spiking neural networks. We leverage memristor nanodevices to build an N ×N crossbar array to store not only multibit synaptic weight values but also the network configuration data with significantly reduced area cost. Additionally, the crossbar array is accessible both column- and row-wise to significantly expedite the synaptic weight update process for on-chip learning. The proposed digital pulse width modulator (PWM) readily creates a binary pulse with various durations to read and write the multilevel memristors with low cost. Our design integrates N digital leaky integrate-and-fire (LIF) silicon neurons to mimic their biological counterparts and the respective on-chip learning circuits for implementing spike timing dependent plasticity (STDP) learning rules. The proposed column based analog-to-digital conversion (ADC) scheme accumulates the pre-synaptic weights of a neuron efficiently and reduces silicon area by using only one shared arithmetic unit for processing LIF operations of all N neurons. With 256 silicon neurons, the learning circuits and 64K synapses, the power dissipation and area of our design are evaluated as 6.45 mW and 1.86 mm2, respectively, in a 90 nm CMOS technology. Furthermore, arithmetic computations contribute significantly to the overall processing time and power of the proposed architecture. In particular, addition and comparison operations represent 88.5% and 42.9% of processing time and power for digital LIF computation, respectively. Hence, by exploiting the built-in resilience of the presented neuromorphic architecture, we propose novel approximate adder and comparator designs to significantly reduce energy consumption with a very low er- ror rate. The significantly improved error rate and critical path delay stem from a novel carry prediction technique that leverages the information from less significant input bits in a parallel manner. An error magnitude reduction scheme is proposed to further reduce amount of error once detected with low cost in the proposed adder design. Implemented in a commercial 90 nm CMOS process, it is shown that the proposed adder is up to 2.4× faster and 43% more energy efficient over traditional… Advisors/Committee Members: Li, Peng (advisor), Choi, Gwan (committee member), Silva-Martinez, Jose (committee member), Mahapatra, Rabi (committee member).

Subjects/Keywords: neuromorphic computing; approximate computing; neuromorphic processor; approximate adder; approximate comparator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Kim, Y. (2013). Energy Efficient and Error Resilient Neuromorphic Computing in VLSI. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/151721

Chicago Manual of Style (16^th Edition):

Kim, Yongtae. “Energy Efficient and Error Resilient Neuromorphic Computing in VLSI.” 2013. Doctoral Dissertation, Texas A&M University. Accessed March 07, 2021. http://hdl.handle.net/1969.1/151721.

MLA Handbook (7^th Edition):

Kim, Yongtae. “Energy Efficient and Error Resilient Neuromorphic Computing in VLSI.” 2013. Web. 07 Mar 2021.

Vancouver:

Kim Y. Energy Efficient and Error Resilient Neuromorphic Computing in VLSI. [Internet] [Doctoral dissertation]. Texas A&M University; 2013. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1969.1/151721.

Council of Science Editors:

Kim Y. Energy Efficient and Error Resilient Neuromorphic Computing in VLSI. [Doctoral Dissertation]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/151721

Texas A&M University

7. Gao, Yang. An Energy Efficient Asynchronous Time-Domain Comparator.

Degree: MS, Electrical Engineering, 2013, Texas A&M University

URL: http://hdl.handle.net/1969.1/149314

► In energy-limited applications, such as wearable battery powered systems and implantable circuits for biological applications, ultra-low power analog-to-digital converters (ADCs) are essential for sustaining long… (more)

Subjects/Keywords: Analog-to-digital converter; asynchronous circuits; comparator; successive approximation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Gao, Y. (2013). An Energy Efficient Asynchronous Time-Domain Comparator. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149314

Chicago Manual of Style (16^th Edition):

Gao, Yang. “An Energy Efficient Asynchronous Time-Domain Comparator.” 2013. Masters Thesis, Texas A&M University. Accessed March 07, 2021. http://hdl.handle.net/1969.1/149314.

MLA Handbook (7^th Edition):

Gao, Yang. “An Energy Efficient Asynchronous Time-Domain Comparator.” 2013. Web. 07 Mar 2021.

Vancouver:

Gao Y. An Energy Efficient Asynchronous Time-Domain Comparator. [Internet] [Masters thesis]. Texas A&M University; 2013. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1969.1/149314.

Council of Science Editors:

Gao Y. An Energy Efficient Asynchronous Time-Domain Comparator. [Masters Thesis]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149314

Penn State University

8. Park, Jun Hyuk. IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS.

Degree: 2017, Penn State University

URL: https://submit-etda.libraries.psu.edu/catalog/14332jzp152

► Integral nonlinearity and differential nonlinearity are the two main performance parameters for a high speed flash analog-to-digital converter, which determine the accuracy of the converter.… (more)

Subjects/Keywords: TIQ Flash ADC; TIQ Voltage Comparator; Nonlinearity; DNL; INL; Process Variation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Park, J. H. (2017). IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/14332jzp152

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Park, Jun Hyuk. “IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS.” 2017. Thesis, Penn State University. Accessed March 07, 2021. https://submit-etda.libraries.psu.edu/catalog/14332jzp152.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Park, Jun Hyuk. “IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS.” 2017. Web. 07 Mar 2021.

Vancouver:

Park JH. IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS. [Internet] [Thesis]. Penn State University; 2017. [cited 2021 Mar 07]. Available from: https://submit-etda.libraries.psu.edu/catalog/14332jzp152.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Park JH. IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS. [Thesis]. Penn State University; 2017. Available from: https://submit-etda.libraries.psu.edu/catalog/14332jzp152

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

UCLA

9. Xu, Hao. Mixed-Signal Circuit Design Driven by Analysis: ADCs, Comparators, and PLLs.

Degree: Electrical Engineering, 2018, UCLA

URL: http://www.escholarship.org/uc/item/88h8b5t3

► Mixed signal circuit design often involves circuits that are time-varying or highly non-linear, which further results in systems that are difficult to characterize using established… (more)

Subjects/Keywords: Electrical engineering; ADC; Analog; comparator; Integrated circuits; mixed signal; PLL

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Xu, H. (2018). Mixed-Signal Circuit Design Driven by Analysis: ADCs, Comparators, and PLLs. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/88h8b5t3

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Xu, Hao. “Mixed-Signal Circuit Design Driven by Analysis: ADCs, Comparators, and PLLs.” 2018. Thesis, UCLA. Accessed March 07, 2021. http://www.escholarship.org/uc/item/88h8b5t3.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Xu, Hao. “Mixed-Signal Circuit Design Driven by Analysis: ADCs, Comparators, and PLLs.” 2018. Web. 07 Mar 2021.

Vancouver:

Xu H. Mixed-Signal Circuit Design Driven by Analysis: ADCs, Comparators, and PLLs. [Internet] [Thesis]. UCLA; 2018. [cited 2021 Mar 07]. Available from: http://www.escholarship.org/uc/item/88h8b5t3.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xu H. Mixed-Signal Circuit Design Driven by Analysis: ADCs, Comparators, and PLLs. [Thesis]. UCLA; 2018. Available from: http://www.escholarship.org/uc/item/88h8b5t3

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

10. Sarmento, Joaquim Miranda. Do public private partnerships create value for money to the public sector? A financial analysis using the Portuguese experience.

Degree: 2009, RCAAP

URL: https://www.rcaap.pt/detail.jsp?id=oai:repositorio.iscte-iul.pt:10071/1826

►

JEL Classification System: G38 - Government Policy and Regulation; H54 - Infrastructures; Other Public Investment and Capital Stock

Over the last few decades, public-private partnerships… (more)

▼

JEL Classification System: G38 - Government Policy and Regulation; H54 - Infrastructures; Other Public Investment and Capital Stock

Over the last few decades, public-private partnerships have been increasable used by governments all around the world to finance and manage complex operations. However, doubts about if their efficiency have been raised. Criticism over public-private partnerships reflects the fact that governments tend to use it just as an “off-budget” operation, to avoid fiscal constraints. Literature is less than unanimous if they generate Value for Money to the public sector. How to assess Value for Money in this type of arrangements has became extremely important for public managers. We believe that the best way to evaluate that is by doing a public sector comparator prior to the bid. Therefore, it is necessary to account for the costs if the decision is to make it by a public procurement versus the public-private partnerships payments, and what discount rates to use in order to find the net present value of the two options, in order to compare and decide which the best decision for taxpayers is. One of the most important costs to include in a public sector comparator is the risk transfer to the private sector, which is the ultimate motive for a greater level of efficiency. Having a notoptimal risk allocation will reduce the probability of a good decision from public managers. However, the scope of this work is not if the public investment should or should not be realized. The cost-benefit analysis of the investment vs. other options should be made prior to the analysis we describe here.

Nas últimas décadas tem-se assistido a um aumento da utilização de parcerias público – privadas em todo o mundo, permitindo aos governos financiar e gerir projectos complexos com o apoio do sector privado. Contudo, tem sido bastante discutido se este tipo de acordos gera eficiência para o sector público. Críticos tendem a referir que as parcerias públicas – privadas são usadas com o intuito exclusivo de desorçamentação, não havendo qualquer preocupação se geram valor acrescentado para o sector público. Como medir o Value for Money tornou-se crucial para os gestores públicos. Consideramos que a melhor forma de o fazer é utilizar um comparador do sector público anterior à negociação. Assim, é necessário apurar todos os custos da alternativa pelo sector público versus os pagamentos à parceria público – privada. Estes valores devem ser apurados em termos de valor actual líquido, a taxas de desconto apropriadas. Um dos custos mais importante a incluir será o dos riscos alocados ao sector privado, que é a principal motivação para maiores níveis de eficiência por parte dos privados. Se o contrato for feito sem uma alocação óptima desses riscos, a probabilidade de os gestores públicos terem tomado a melhor decisão é bastante reduzida. Contudo, é importante compreender que o objectivo deste trabalho não é se aquele é o melhor investimento público face às alternativas, mas sim qual a melhor opção para a sua implementação.…

Advisors/Committee Members: Inácio, Pedro.

Subjects/Keywords: Public private partnerships; Value for money; Public sector comparator; Discount rate

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APA (6^th Edition):

Sarmento, J. M. (2009). Do public private partnerships create value for money to the public sector? A financial analysis using the Portuguese experience. (Thesis). RCAAP. Retrieved from https://www.rcaap.pt/detail.jsp?id=oai:repositorio.iscte-iul.pt:10071/1826

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Sarmento, Joaquim Miranda. “Do public private partnerships create value for money to the public sector? A financial analysis using the Portuguese experience.” 2009. Thesis, RCAAP. Accessed March 07, 2021. https://www.rcaap.pt/detail.jsp?id=oai:repositorio.iscte-iul.pt:10071/1826.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Sarmento, Joaquim Miranda. “Do public private partnerships create value for money to the public sector? A financial analysis using the Portuguese experience.” 2009. Web. 07 Mar 2021.

Vancouver:

Sarmento JM. Do public private partnerships create value for money to the public sector? A financial analysis using the Portuguese experience. [Internet] [Thesis]. RCAAP; 2009. [cited 2021 Mar 07]. Available from: https://www.rcaap.pt/detail.jsp?id=oai:repositorio.iscte-iul.pt:10071/1826.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sarmento JM. Do public private partnerships create value for money to the public sector? A financial analysis using the Portuguese experience. [Thesis]. RCAAP; 2009. Available from: https://www.rcaap.pt/detail.jsp?id=oai:repositorio.iscte-iul.pt:10071/1826

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Univerzitet u Beogradu

11. Zubić, Siniša Ј., 1982-. Алгоритми за дистантне заштите на бази дигиталне фазне компарације.

Degree: Elektrotehnički fakultet, 2016, Univerzitet u Beogradu

URL: https://fedorabg.bg.ac.rs/fedora/get/o:12468/bdef:Content/get

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Техничке науке - Електротехника - Електроенергетски системи / Technical science – Electrical engineering - Power Systems

У дисертацији су презентовани нови алгоритми дистантних заштита базирани… (more)

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Техничке науке - Електротехника - Електроенергетски системи / Technical science – Electrical engineering - Power Systems

У дисертацији су презентовани нови алгоритми дистантних заштита базирани на фазној компарацији у временском домену. Представљени алгоритми су поређени са алгоритмима на бази дискретне Фуријеове трансформације (DFT) који се најчешће користе у пракси и представљају класично рјешење у овој области. Основна разлика између наших и класичних рјешења је у томе што не рачунамо фазоре, него сигнале остављамо у временском домену гдје уз мали број рачунских операција одређујемо да ли је квар лоциран унутар подешене зоне реаговања. Основна предност овог приступа је у томе што значајно редукује број рачунских операција које алгоритам извршава у сваком периоду одабирања. Зависно од облика карактеристике реаговања, предложени алгоритми захтијевају између 30 и 70% мање рачунских операција у односу на класично рјешење базирано на DFT. Предложени приступ има двије потенцијално слабе тачке. Прва је да истовремено присуство виших хармоника истог реда у улазним сигналима може узроковати грешке у детекцији квара. Детаљном анализом и тестирањем смо показали да је и при условима који су много строжији од реалних услова у мрежи, поменута грешка незнатна, тако да практично нема утицаја на тачност детекције квара. Други потенцијални недостатак предложених алгоритама је неопходност уношења додатних временских кашњења у сигнале како би биле реализоване жељене карактеристике реаговања. То би теоретски требало довести до тога да предложени алгоритми буду у свакој ситуацији спорији од контролних. Тестирања показују да то није тачно и да су неки предложени алгоритми у просјеку чак и бржи од класичних...

Advisors/Committee Members: Đurić, Milenko, 1948-.

Subjects/Keywords: relay protection; distance relays; time-domain phase comparator

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APA (6^th Edition):

Zubić, Siniša Ј., 1. (2016). Алгоритми за дистантне заштите на бази дигиталне фазне компарације. (Thesis). Univerzitet u Beogradu. Retrieved from https://fedorabg.bg.ac.rs/fedora/get/o:12468/bdef:Content/get

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Zubić, Siniša Ј., 1982-. “Алгоритми за дистантне заштите на бази дигиталне фазне компарације.” 2016. Thesis, Univerzitet u Beogradu. Accessed March 07, 2021. https://fedorabg.bg.ac.rs/fedora/get/o:12468/bdef:Content/get.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Zubić, Siniša Ј., 1982-. “Алгоритми за дистантне заштите на бази дигиталне фазне компарације.” 2016. Web. 07 Mar 2021.

Vancouver:

Zubić, Siniša Ј. 1. Алгоритми за дистантне заштите на бази дигиталне фазне компарације. [Internet] [Thesis]. Univerzitet u Beogradu; 2016. [cited 2021 Mar 07]. Available from: https://fedorabg.bg.ac.rs/fedora/get/o:12468/bdef:Content/get.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zubić, Siniša Ј. 1. Алгоритми за дистантне заштите на бази дигиталне фазне компарације. [Thesis]. Univerzitet u Beogradu; 2016. Available from: https://fedorabg.bg.ac.rs/fedora/get/o:12468/bdef:Content/get

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Dundee

12. Mohamad Ali, Norfadhilah. Appropriate comparator in national treatment under international investment law : relevance of GATT/WTO, EU and international human rights jurisprudences.

Degree: PhD, 2014, University of Dundee

URL: https://discovery.dundee.ac.uk/en/studentTheses/59a3f88c-8750-4f0b-a04b-7edfe15a477d ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.600768

► The minimalist state of the national treatment provision in the investment treaties has provided limited guidance for the tribunals for interpretation. As a result, there… (more)

Subjects/Keywords: 346.07; National treatment; International investment law; Non-discrimination; Likeness; Relevant comparator

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APA (6^th Edition):

Mohamad Ali, N. (2014). Appropriate comparator in national treatment under international investment law : relevance of GATT/WTO, EU and international human rights jurisprudences. (Doctoral Dissertation). University of Dundee. Retrieved from https://discovery.dundee.ac.uk/en/studentTheses/59a3f88c-8750-4f0b-a04b-7edfe15a477d ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.600768

Chicago Manual of Style (16^th Edition):

Mohamad Ali, Norfadhilah. “Appropriate comparator in national treatment under international investment law : relevance of GATT/WTO, EU and international human rights jurisprudences.” 2014. Doctoral Dissertation, University of Dundee. Accessed March 07, 2021. https://discovery.dundee.ac.uk/en/studentTheses/59a3f88c-8750-4f0b-a04b-7edfe15a477d ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.600768.

MLA Handbook (7^th Edition):

Mohamad Ali, Norfadhilah. “Appropriate comparator in national treatment under international investment law : relevance of GATT/WTO, EU and international human rights jurisprudences.” 2014. Web. 07 Mar 2021.

Vancouver:

Mohamad Ali N. Appropriate comparator in national treatment under international investment law : relevance of GATT/WTO, EU and international human rights jurisprudences. [Internet] [Doctoral dissertation]. University of Dundee; 2014. [cited 2021 Mar 07]. Available from: https://discovery.dundee.ac.uk/en/studentTheses/59a3f88c-8750-4f0b-a04b-7edfe15a477d ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.600768.

Council of Science Editors:

Mohamad Ali N. Appropriate comparator in national treatment under international investment law : relevance of GATT/WTO, EU and international human rights jurisprudences. [Doctoral Dissertation]. University of Dundee; 2014. Available from: https://discovery.dundee.ac.uk/en/studentTheses/59a3f88c-8750-4f0b-a04b-7edfe15a477d ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.600768

13. Nisar, Kashif. DC to DC converter for smart dust.

Degree: The Institute of Technology, 2012, Linköping UniversityLinköping University

URL: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-77247

► This work describes the implementation of DC to DC converter for Smart Dust in 65 nm CMOS technology. The purpose of a DC to… (more)

Subjects/Keywords: Comparator; DC to DC converter; PWM; Op-amp; Voltage regulator

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APA (6^th Edition):

Nisar, K. (2012). DC to DC converter for smart dust. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-77247

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Nisar, Kashif. “DC to DC converter for smart dust.” 2012. Thesis, Linköping UniversityLinköping University. Accessed March 07, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-77247.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Nisar, Kashif. “DC to DC converter for smart dust.” 2012. Web. 07 Mar 2021.

Vancouver:

Nisar K. DC to DC converter for smart dust. [Internet] [Thesis]. Linköping UniversityLinköping University; 2012. [cited 2021 Mar 07]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-77247.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nisar K. DC to DC converter for smart dust. [Thesis]. Linköping UniversityLinköping University; 2012. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-77247

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Linköping University

14. Hedayati, Raheleh. A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology.

Degree: Electronic Devices, 2011, Linköping University

URL: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72767

► In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to-Digital Converter in medical application such as pacemaker. The demand… (more)

Subjects/Keywords: SAR ADC; SAR Logic; Dynamic Comparator; Low Power

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APA (6^th Edition):

Hedayati, R. (2011). A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72767

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hedayati, Raheleh. “A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology.” 2011. Thesis, Linköping University. Accessed March 07, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72767.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hedayati, Raheleh. “A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology.” 2011. Web. 07 Mar 2021.

Vancouver:

Hedayati R. A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology. [Internet] [Thesis]. Linköping University; 2011. [cited 2021 Mar 07]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72767.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hedayati R. A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology. [Thesis]. Linköping University; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72767

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

15. Zhang, R. (author). A 1-Mega Pixels HDR and UV Sensitive Image Sensor With Interleaved 14-bit 64Ms/s SAR ADC.

Degree: 2015, Delft University of Technology

URL: http://resolver.tudelft.nl/uuid:26cd1922-1ecc-4f7e-b8bc-46c5c00f8846

►

This thesis presents a 1-Mega pixels high-dynamic range and UV sensitive image sensor in 0.18 µm technology with 14-bit interleaved 64Ms/s SAR ADC. It can… (more)

Subjects/Keywords: UV sensitive; interleaved SAR ADC; comparator; offset calibration; high dynamic range

10 more images…

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APA (6^th Edition):

Zhang, R. (. (2015). A 1-Mega Pixels HDR and UV Sensitive Image Sensor With Interleaved 14-bit 64Ms/s SAR ADC. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:26cd1922-1ecc-4f7e-b8bc-46c5c00f8846

Chicago Manual of Style (16^th Edition):

Zhang, R (author). “A 1-Mega Pixels HDR and UV Sensitive Image Sensor With Interleaved 14-bit 64Ms/s SAR ADC.” 2015. Masters Thesis, Delft University of Technology. Accessed March 07, 2021. http://resolver.tudelft.nl/uuid:26cd1922-1ecc-4f7e-b8bc-46c5c00f8846.

MLA Handbook (7^th Edition):

Zhang, R (author). “A 1-Mega Pixels HDR and UV Sensitive Image Sensor With Interleaved 14-bit 64Ms/s SAR ADC.” 2015. Web. 07 Mar 2021.

Vancouver:

Zhang R(. A 1-Mega Pixels HDR and UV Sensitive Image Sensor With Interleaved 14-bit 64Ms/s SAR ADC. [Internet] [Masters thesis]. Delft University of Technology; 2015. [cited 2021 Mar 07]. Available from: http://resolver.tudelft.nl/uuid:26cd1922-1ecc-4f7e-b8bc-46c5c00f8846.

Council of Science Editors:

Zhang R(. A 1-Mega Pixels HDR and UV Sensitive Image Sensor With Interleaved 14-bit 64Ms/s SAR ADC. [Masters Thesis]. Delft University of Technology; 2015. Available from: http://resolver.tudelft.nl/uuid:26cd1922-1ecc-4f7e-b8bc-46c5c00f8846

Brno University of Technology

16. Hylský, Josef. Návrh komparátoru s kompenzací napěťové nesymetrie v technologii CMOS: Design of a comparator with offset compensation in CMOS technology.

Degree: 2019, Brno University of Technology

URL: http://hdl.handle.net/11012/14714

► This work contains basic knowledge about comparators and its design in the CMOS technology. The first chapter deals with a wide use of a comparator,… (more)

Subjects/Keywords: Komparátor; technologie CMOS; napěťová nesymetrie.; Comparator; CMOS technology; offset.

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APA (6^th Edition):

Hylský, J. (2019). Návrh komparátoru s kompenzací napěťové nesymetrie v technologii CMOS: Design of a comparator with offset compensation in CMOS technology. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/14714

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Hylský, Josef. “Návrh komparátoru s kompenzací napěťové nesymetrie v technologii CMOS: Design of a comparator with offset compensation in CMOS technology.” 2019. Thesis, Brno University of Technology. Accessed March 07, 2021. http://hdl.handle.net/11012/14714.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Hylský, Josef. “Návrh komparátoru s kompenzací napěťové nesymetrie v technologii CMOS: Design of a comparator with offset compensation in CMOS technology.” 2019. Web. 07 Mar 2021.

Vancouver:

Hylský J. Návrh komparátoru s kompenzací napěťové nesymetrie v technologii CMOS: Design of a comparator with offset compensation in CMOS technology. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/11012/14714.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hylský J. Návrh komparátoru s kompenzací napěťové nesymetrie v technologii CMOS: Design of a comparator with offset compensation in CMOS technology. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/14714

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Polavarapu, Sai Praneeth. Design of a fully-differential charge pump for an integrated dynamic offset test bench.

Degree: MS, Electrical and Electronic Engineering, 2014, California State University – Sacramento

URL: http://hdl.handle.net/10211.3/131276

► Comparators are one of the most important building blocks used in analog and mixed-signal integrated circuits. As the input offset voltage is the basic specification… (more)

Subjects/Keywords: Comparator; DOTB; Offset error

…LIST OF FIGURES Page Figures 1. Figure 1 Schematic of a Latching Comparator… …2 2. Figure 2 Schematic of Comparator used in Dynamic Offset Test Bench… …Many applications require a comparator which compares the unknown input signal to a… …classic paper by Yin, Op’t Eynde & Sansen [1]. This paper describes the comparator… …shown in Figure 1, which compares the given input voltage to a “zero”. That is, the comparator…

11 more images…

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APA (6^th Edition):

Polavarapu, S. P. (2014). Design of a fully-differential charge pump for an integrated dynamic offset test bench. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/131276

Chicago Manual of Style (16^th Edition):

Polavarapu, Sai Praneeth. “Design of a fully-differential charge pump for an integrated dynamic offset test bench.” 2014. Masters Thesis, California State University – Sacramento. Accessed March 07, 2021. http://hdl.handle.net/10211.3/131276.

MLA Handbook (7^th Edition):

Polavarapu, Sai Praneeth. “Design of a fully-differential charge pump for an integrated dynamic offset test bench.” 2014. Web. 07 Mar 2021.

Vancouver:

Polavarapu SP. Design of a fully-differential charge pump for an integrated dynamic offset test bench. [Internet] [Masters thesis]. California State University – Sacramento; 2014. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/10211.3/131276.

Council of Science Editors:

Polavarapu SP. Design of a fully-differential charge pump for an integrated dynamic offset test bench. [Masters Thesis]. California State University – Sacramento; 2014. Available from: http://hdl.handle.net/10211.3/131276

University of Pennsylvania

18. Mianno, Todd Anthony. Drug-Drug Interactions And Kidney Disease In Hospitalized Patients.

Degree: 2019, University of Pennsylvania

URL: https://repository.upenn.edu/edissertations/3395

► As polypharmacy becomes increasingly common in patients with kidney disease, drug-drug interactions (DDIs), the phenomenon of one drug altering the effect of another drug, grow… (more)

Subjects/Keywords: active comparator designs; acute kidney injury; drug-drug interactions; Epidemiology

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APA (6^th Edition):

Mianno, T. A. (2019). Drug-Drug Interactions And Kidney Disease In Hospitalized Patients. (Thesis). University of Pennsylvania. Retrieved from https://repository.upenn.edu/edissertations/3395

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Mianno, Todd Anthony. “Drug-Drug Interactions And Kidney Disease In Hospitalized Patients.” 2019. Thesis, University of Pennsylvania. Accessed March 07, 2021. https://repository.upenn.edu/edissertations/3395.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Mianno, Todd Anthony. “Drug-Drug Interactions And Kidney Disease In Hospitalized Patients.” 2019. Web. 07 Mar 2021.

Vancouver:

Mianno TA. Drug-Drug Interactions And Kidney Disease In Hospitalized Patients. [Internet] [Thesis]. University of Pennsylvania; 2019. [cited 2021 Mar 07]. Available from: https://repository.upenn.edu/edissertations/3395.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mianno TA. Drug-Drug Interactions And Kidney Disease In Hospitalized Patients. [Thesis]. University of Pennsylvania; 2019. Available from: https://repository.upenn.edu/edissertations/3395

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

19. Chen, Chih-hung. 1MHz Bandwidth Switched-Current Sigma Delta Modulator.

Degree: Master, Electrical Engineering, 2010, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901110-122544

► The thesis proposes an integrator with an OPAMP in the feedback loop to fulfill 1MHz bandwidth SI Sigma Delta modulator. The OPAMP is used to… (more)

Subjects/Keywords: delta-sigma modulator; sigma-delta modulator; switched-current circuit; integrator; sample and hole; current comparator

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APA (6^th Edition):

Chen, C. (2010). 1MHz Bandwidth Switched-Current Sigma Delta Modulator. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901110-122544

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Chen, Chih-hung. “1MHz Bandwidth Switched-Current Sigma Delta Modulator.” 2010. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901110-122544.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Chen, Chih-hung. “1MHz Bandwidth Switched-Current Sigma Delta Modulator.” 2010. Web. 07 Mar 2021.

Vancouver:

Chen C. 1MHz Bandwidth Switched-Current Sigma Delta Modulator. [Internet] [Thesis]. NSYSU; 2010. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901110-122544.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen C. 1MHz Bandwidth Switched-Current Sigma Delta Modulator. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0901110-122544

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

20. Lo, Ching-Wen. High Speed SAR Analog to Digital Converter Design.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004

► In this thesis, the circuits are designing with TSMC 90nm CMOS process and 1.2V of supply voltage. The speed and resolution of ADC are 8-bit… (more)

Subjects/Keywords: Bootstrapped switch; Dynamic Comparator; Successive Approximation; Low power; Analog-to-Digital Converter

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APA (6^th Edition):

Lo, C. (2014). High Speed SAR Analog to Digital Converter Design. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lo, Ching-Wen. “High Speed SAR Analog to Digital Converter Design.” 2014. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lo, Ching-Wen. “High Speed SAR Analog to Digital Converter Design.” 2014. Web. 07 Mar 2021.

Vancouver:

Lo C. High Speed SAR Analog to Digital Converter Design. [Internet] [Thesis]. NSYSU; 2014. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lo C. High Speed SAR Analog to Digital Converter Design. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

NSYSU

21. Liao, Yen-Qun. High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626113-144731

► In this thesis, the circuits are designing with TSMC.18Î¼m CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 100MS/s and… (more)

Subjects/Keywords: Symmetry Bootstrap-switch; Dynamic comparator; Switched-Opamp; Successive Approximation ADC; Pipelined ADC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Liao, Y. (2013). High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626113-144731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Liao, Yen-Qun. “High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter.” 2013. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626113-144731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Liao, Yen-Qun. “High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter.” 2013. Web. 07 Mar 2021.

Vancouver:

Liao Y. High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626113-144731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liao Y. High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626113-144731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

University of Saskatchewan

22. Wang, Binben. Increasing the Performance of the Canadian Hydrological Model using Lookup Tables.

Degree: 2020, University of Saskatchewan

URL: http://hdl.handle.net/10388/12783

► The climate of cold regions is fragile and could be easily threatened by human activities. Hydrological processes play an important role in the climate of… (more)

▼ The climate of cold regions is fragile and could be easily threatened by human activities. Hydrological processes play an important role in the climate of cold regions, and using computational models to simulate cold-region hydrological processes helps people understand past hydrological events and predict future ones. With the need to get more accurate simulation results, more complex computational models are often required. However, the complexity of models is often limited by available computational resources. Therefore, improving the computational eﬃciency of model simulations is an urgent task for hydrological researchers and software developers. The Canadian Hydrological Model (CHM) is a modular software package that is used to simulate cold-region hydrological processes. CHM uses an eﬃcient surface discretization, unstructured triangular meshes, to reduce the number of discretization elements, which in turn decreases the complexity of cold-region hydrological models. CHM also employs parallelization to make models more eﬃcient. By proﬁling the performance of CHM, we ﬁnd that there are some computationally intensive functions inside CHM that are evaluated repeatedly. Lookup tables (LUTs) followed by optional interpolation or Taylor series approximation are common optimizations to replace such direct function evaluations. These optimizations can decrease the complexity of cold-region hydrological models further. The Function Comparator (FunC) is a C++ library that can automatically create one-dimensional LUTs for continuous univariate functions on uniformly spaced grids. In this thesis, we use FunC to implement LUTs for two computationally intensive and repeatedly called functions in CHM, achieving an improvement of around 20% in the performance of CHM in the sense of running time on two cold-region hydrological simulations. In the ﬁrst step, we identify two computationally intensive and repeatedly called functions by proﬁling the performance of CHM, determine the error tolerances and the ranges of inputs for their LUT implementations, and use FunC to implement linear interpolation LUTs for both functions in CHM. In the second step, we run CHM with and without LUT implementations on a coldregion hydrological simulation with a small domain. We verify that CHM with LUT implementations produces correct output and show that there is around an 18% improvement in the performance of CHM. In the third step, we run the same CHM with and without LUT implementations on a cold-region hydrological simulation with a large domain. We again verify that CHM with LUT implementations produces correct output and show that there is around a 21% improvement in the performance of CHM. Advisors/Committee Members: Dutchyn, Christopher, Lee, Roy, Ko, Seok-Bum.

Subjects/Keywords: Lookup tables; cold-region hydrological simulation; Function Comparator (FunC); the Canadian Hydrological Model (CHM)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Wang, B. (2020). Increasing the Performance of the Canadian Hydrological Model using Lookup Tables. (Thesis). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/12783

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Wang, Binben. “Increasing the Performance of the Canadian Hydrological Model using Lookup Tables.” 2020. Thesis, University of Saskatchewan. Accessed March 07, 2021. http://hdl.handle.net/10388/12783.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Wang, Binben. “Increasing the Performance of the Canadian Hydrological Model using Lookup Tables.” 2020. Web. 07 Mar 2021.

Vancouver:

Wang B. Increasing the Performance of the Canadian Hydrological Model using Lookup Tables. [Internet] [Thesis]. University of Saskatchewan; 2020. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/10388/12783.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang B. Increasing the Performance of the Canadian Hydrological Model using Lookup Tables. [Thesis]. University of Saskatchewan; 2020. Available from: http://hdl.handle.net/10388/12783

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Vilnius Gediminas Technical University

23. Kilikevičius, Artūras. Ilgio matavimo mechatroninio komparatoriaus dinaminių paklaidų tyrimas.

Degree: Dissertation, Measurement Engineering, 2009, Vilnius Gediminas Technical University

URL: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2009~D_20090623_110816-03177 ;

►

Reziumė Tikslaus ir greito brūkšninių ilgio matų padalų detektavimo problemos aktualumą ir sprendimo būtinybę pirmiausia sąlygoja sparčiai didėjantys precizinių skalių kalibravimo našumo poreikiai. Vienas pagrindinių… (more)

▼

Reziumė Tikslaus ir greito brūkšninių ilgio matų padalų detektavimo problemos aktualumą ir sprendimo būtinybę pirmiausia sąlygoja sparčiai didėjantys precizinių skalių kalibravimo našumo poreikiai. Vienas pagrindinių tokių sistemų projektavimo kriterijų yra paklaidų biudžetas (sandara). Disertacijoje pagrindinis dėmesys skirtas ištirti aplinkos ir komparatoriaus elementų virpesių įtaką kalibravimo tikslumui ir nustatyti, kokią paklaidų biudžeto dalį sudaro paklaida, atsirandanti dėl virpesių poveikio. Darbe sprendžiami keli pagrindiniai uždaviniai: virpesių įtakos komparatoriaus kalibravimo tikslumui nustatymas bei virpesių matavimo priemonių patikimumo tyrimas. Pirmasis uždavinys suformuluotas, nes atlikus literatūros apžvalgą nustatyta, kad kalibravimo sistemų dinaminiams tyrimams buvo skirta mažai dėmesio. Antrasis siejasi su pirmojo uždavinio spendimu, nes kai matuojami dydžiai yra mikrometrų eilės, labai svarbu įvertinti virpesių matavimo priemonių patikimumą. Disertaciją sudaro įvadas, penki skyriai ir rezultatų apibendrinimas. Įvadiniame skyriuje nagrinėjamas problemos aktualumas, formuluojamas darbo tikslas bei uždaviniai, aprašomas mokslinis darbo naujumas, pristatomi autoriaus pranešimai ir publikacijos, disertacijos struktūra. Pirmasis skyrius skirtas literatūros apžvalgai. Jame pateikta ilgio matų kalibravimo ir virpesių matavimo sistemų bei jų paklaidų analizė. Skyriaus pabaigoje formuluojamos išvados ir tikslinami disertacijos uždaviniai. Antrajame skyriuje... [toliau žr. visą tekstą]

Abstract Actuality and solution necessity of the problem of accurate and fast detection of the length measurement scale divisions determine first of all the quickly increas-ing requirements of the scale calibration productivity. One of the main criterions of design of these systems is the budget (structure) of the errors. The main atten-tion in the dissertation is laid to research the influence of an environment and comparator elements vibration onto accuracy of data reception and what part of an error budget forms the error provoked by the vibration action. Some main tasks are being solved in the work: definition of vibration influ-ence on comparator data reception accuracy and research of reliability of vibra-tion measurement means. The first task was formed for the reason that after sur-vey of literature sources it was defined that there was a small attention to dynamical research of calibration systems. The second is connected with the solution of the first task, because while the values being measured are of a mi-crometer order it is severely necessary to evaluate the reliability of vibration measurement systems. The thesis is divided into five chapters including the con-clusion’s chapter. First chapter is dedicated for an introduction to the problem and its topical-ity. There are also formulated purposes and tasks of the work; the used methods and novelty of solutions are described; author‘s publications and structure of the thesis are presented. In the second section... [to full text]

Advisors/Committee Members: Vekteris, Vladas (Doctoral dissertation supervisor), Kasparaitis, Albinas (Doctoral dissertation advisor), Giniotis, Vytautas (Doctoral dissertation committee chair), Kažys, Rymantas Jonas (Doctoral dissertation committee member), Paršeliūnas, Eimuntas Kazimieras (Doctoral dissertation committee member), Sirutkaitis, Valdas (Doctoral dissertation committee member), Skeivalas, Jonas (Doctoral dissertation committee member), Bakšys, Bronius (Doctoral dissertation opponent), Šukys, Arūnas Mindaugas (Doctoral dissertation opponent).

Subjects/Keywords: Mechatroninis komparatorius; Kalibravimo tikslumas; Virpesių poveikis; Mechatronical comparator; Calibration accuracy; Vibration action

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Kilikevičius, A. (2009). Ilgio matavimo mechatroninio komparatoriaus dinaminių paklaidų tyrimas. (Doctoral Dissertation). Vilnius Gediminas Technical University. Retrieved from http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2009~D_20090623_110816-03177 ;

Chicago Manual of Style (16^th Edition):

Kilikevičius, Artūras. “Ilgio matavimo mechatroninio komparatoriaus dinaminių paklaidų tyrimas.” 2009. Doctoral Dissertation, Vilnius Gediminas Technical University. Accessed March 07, 2021. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2009~D_20090623_110816-03177 ;.

MLA Handbook (7^th Edition):

Kilikevičius, Artūras. “Ilgio matavimo mechatroninio komparatoriaus dinaminių paklaidų tyrimas.” 2009. Web. 07 Mar 2021.

Vancouver:

Kilikevičius A. Ilgio matavimo mechatroninio komparatoriaus dinaminių paklaidų tyrimas. [Internet] [Doctoral dissertation]. Vilnius Gediminas Technical University; 2009. [cited 2021 Mar 07]. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2009~D_20090623_110816-03177 ;.

Council of Science Editors:

Kilikevičius A. Ilgio matavimo mechatroninio komparatoriaus dinaminių paklaidų tyrimas. [Doctoral Dissertation]. Vilnius Gediminas Technical University; 2009. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2009~D_20090623_110816-03177 ;

NSYSU

24. Lee, Yao-Lun. A Programmable Gain Amplifier with Auto Gain Control Mechanism for the CMOS Image Sensor.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-121128

► In this thesis, a programmable gain amplifier for the CMOS image sensor is implemented by using the TSMC 0.18 ïm process technology. The main circuit… (more)

Subjects/Keywords: programmable gain amplifier; dynamic comparator; switch capacitor amplifier; bandgap reference circuit; folded cascade operational amplifier

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lee, Y. (2018). A Programmable Gain Amplifier with Auto Gain Control Mechanism for the CMOS Image Sensor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-121128

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Lee, Yao-Lun. “A Programmable Gain Amplifier with Auto Gain Control Mechanism for the CMOS Image Sensor.” 2018. Thesis, NSYSU. Accessed March 07, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-121128.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Lee, Yao-Lun. “A Programmable Gain Amplifier with Auto Gain Control Mechanism for the CMOS Image Sensor.” 2018. Web. 07 Mar 2021.

Vancouver:

Lee Y. A Programmable Gain Amplifier with Auto Gain Control Mechanism for the CMOS Image Sensor. [Internet] [Thesis]. NSYSU; 2018. [cited 2021 Mar 07]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-121128.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee Y. A Programmable Gain Amplifier with Auto Gain Control Mechanism for the CMOS Image Sensor. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-121128

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Univerzitet u Beogradu

25. Stojanović, Zoran, 1979-. Usmereni releji bazirani na digitalnom faznom komparatoru.

Degree: Elektrotehnički fakultet, 2013, Univerzitet u Beogradu

URL: https://fedorabg.bg.ac.rs/fedora/get/o:5473/bdef:Content/get

►

Elektrotehnika - Elektroenergetski sistemi / Electrical engineering - Power Systems

U ovoj doktorskoj disertaciji predstavljen je nov algoritam za usmereni relej baziran na digitalnoj faznoj… (more)

▼

Elektrotehnika - Elektroenergetski sistemi / Electrical engineering - Power Systems

U ovoj doktorskoj disertaciji predstavljen je nov algoritam za usmereni relej baziran na digitalnoj faznoj komparaciji. Za realizaciju digitalnog faznog komparatora pošlo se od ideje da se ne računa fazni pomeraj između struje i referentnog napona, već energija odnosno integral trenutne snage signala na intervalu dužine polovine osnovne periode napona ili struje. Interval integracije je polovina osnovne periode jer je frekvencija trenutne snage dva puta veća u odnosu na frekvenciju ulaznih signala. Algoritam usmerenog releja koji se bazira na integralu trenutne snage signala ima osobine faznog komparatora. Podešavanje maksimalne osetljivosti releja vrši se direktno iz naponskog ili strujnog registra. U odnosu na dosadašnja rešenja, ovakvim pristupom eliminisana je potreba za impedansom modela voda Zm. Izlaz koji generiše usmereni relej ograničen je na intervalu ±1, deljenjem srednje snage signala prividnom snagom. Na taj način omogućeno je jednostavno zadavanje praga reagovanja ili blokiranja releja, koji je različit od nule. Opisani postupak u proračunima koristi samo jednostavne matematičke operacije (sabiranje, množenje i deljenje) zbog čega u maloj meri koristi procesorsko vreme. Zbog postojanja viših harmonika i jednosmerne komponente u ulaznim signalima algoritam je u nastavku proširen digitalnim Fourierovim filtrom. To je otvorilo mogućnost regulacije osetljivosti releja korišćenjem sinusne i kosinusne komponente Fourierovog reda. Brzina reagovanja releja zavisi od režima koji je prethodio kvaru i podešenog praga reagovanja. Kreće se od trenutnog dejstva do 10 ms, što relej svrstava u one sa brzim odzivom. Opisani algoritam može umesto trenutnih vrednosti signala da koristi njihove priraštaje čime se dobija ultrabrzi usmereni relej. Vreme odziva ovog releja je manje od 5 ms i nema zonu neosetljivosti. U nastavku disertacije izloženo je nekoliko specifičnih primena digitalnog faznog komparatora na realnim problemima. Svaki od algoritama detaljno je testiran serijom računarski generisanih signala...

Advisors/Committee Members: Đurić, Milenko, 1948-.

Subjects/Keywords: relay protection; digital relaying; directional element; phase comparator; directional earth-fault protection

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Stojanović, Zoran, 1. (2013). Usmereni releji bazirani na digitalnom faznom komparatoru. (Thesis). Univerzitet u Beogradu. Retrieved from https://fedorabg.bg.ac.rs/fedora/get/o:5473/bdef:Content/get

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Stojanović, Zoran, 1979-. “Usmereni releji bazirani na digitalnom faznom komparatoru.” 2013. Thesis, Univerzitet u Beogradu. Accessed March 07, 2021. https://fedorabg.bg.ac.rs/fedora/get/o:5473/bdef:Content/get.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Stojanović, Zoran, 1979-. “Usmereni releji bazirani na digitalnom faznom komparatoru.” 2013. Web. 07 Mar 2021.

Vancouver:

Stojanović, Zoran 1. Usmereni releji bazirani na digitalnom faznom komparatoru. [Internet] [Thesis]. Univerzitet u Beogradu; 2013. [cited 2021 Mar 07]. Available from: https://fedorabg.bg.ac.rs/fedora/get/o:5473/bdef:Content/get.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Stojanović, Zoran 1. Usmereni releji bazirani na digitalnom faznom komparatoru. [Thesis]. Univerzitet u Beogradu; 2013. Available from: https://fedorabg.bg.ac.rs/fedora/get/o:5473/bdef:Content/get

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Univerzitet u Beogradu

26. Krstivojević, Jelisaveta P., 1982-. Digitalna zaštita energetskih transformatora od unutrašnjih kvarova.

Degree: Elektrotehnički fakultet, 2016, Univerzitet u Beogradu

URL: https://fedorabg.bg.ac.rs/fedora/get/o:11571/bdef:Content/get

►

Tehničke nauke, Elektrotehnika - Elektroenergetski sistemi / Technical science, Electrical engineering - Power Systems

U ovoj doktorskoj disertaciji predstavljeni su algoritmi za digitalnu zaštitu energetskih… (more)

▼

Tehničke nauke, Elektrotehnika - Elektroenergetski sistemi / Technical science, Electrical engineering - Power Systems

U ovoj doktorskoj disertaciji predstavljeni su algoritmi za digitalnu zaštitu energetskih transformatora (ET-a) od unutrašnjih kvarova. Predstavljeni algoritmi za zaštitu od kratkih spojeva namotaja ET-a i za zaštitu ET-a od zemljospojeva baziraju se na primeni digitalne fazne komparacije u vremenskom domenu. Digitalni fazni komparator ne računa direktno fazni pomeraj između signala koje poredi, već proračunava integral proizvoda dva signala na intervalu dužine polovine osnovne periode signala. Ispitana je mogućnost primene fazne komparacije primarne i sekundarne struje za detekciju unutrašnjih kratkih spojeva u ET-u. U normalnom režimu rada i tokom kvarova van zone zaštite struje primara i sekundara su u fazi, dok se u slučaju unutrašnjih kratkih spojeva pojavljuje fazni pomeraj između ove dve struje. U disertaciji je pokazano da fazni pomeraj između struja primara i sekundara tokom unutrašnjih kratkih spojeva zavisi kako od procenta kratkospojenih navojaka, tako i od parametara mreže i radnog režima koji je prethodio kvaru. Korišćenjem fazne komparacije primarne i sekundarne struje mogu se detektovati unutrašnji kratki spojevi. Zbog postojanja opadajuće jednosmerne komponente u struji kvara algoritam je proširen digitalnim filterom opadajuće jednosmerne komponente, a zbog postojanja viših harmonika digitalnim Fourier-ovim filterom. Na ovaj način poboljšane su performanse algoritma. Zatim je predstavljen algoritam koji koristi novi pristup u rešavanju problema nepotrebnog reagovanja diferencijalne zaštite ET-a usled kvarova van štićene zone praćenih zasićenjem strujnih transformatora (ST-a). Novi pristup se zasniva na faznoj komparaciji primarne i sekundarne struje i služi za indikaciju prisustva kvara van štićene zone. Prikazani rezultati potvrđuju da algoritam može da identifikuje prisustvo spoljašnjeg kvara i aktivira signal za blokadu pre nego što ST-i uđu u zasićenje. Njegovom primenom uspešno bi se moglo eliminisati nepotrebno delovanje diferencijalne zaštite i na taj način povećala njena sigurnost u radu. U nastavku je predstavljen algoritam za zemljospojnu zaštitu energetskog transformatora koji se bazira na faznoj komparaciji sume struja na priključcima ET-a i struje neutralnog provodnika. Prikazani algoritam predstavlja novo rešenje za realizaciju zemljospojne zaštite energetskog transformatora. Primenom predstavljenog algoritma eliminisalo bi se nepotrebno reagovanje konvencionalne zemljospojne zaštite ET-a bazirane na diferencijalnom principu tokom spoljašnjih kvarova i uključenja neopterećenog ET-a praćenih zasićenjem ST-a. Algoritam koristi signale koji se ne filtriraju digitalnom Fourier-ovom transformacijom. Takođe, algoritam ne koristi blokadu po drugom harmoniku što ima prednost u brzini formiranja signala reagovanja. Prikazano je da se dodatnim usrednjavanjem vrednosti indeksa usmerenosti povećava otpornost algoritma na oscilacije indeksa koje nastaju usled zasićenja ST-a. Svi…

Advisors/Committee Members: Đurić, Milenko.

Subjects/Keywords: relay protection; digital relaying; power transformer protection; power transformer ground fault protection; phase comparator

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❌

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Krstivojević, Jelisaveta P., 1. (2016). Digitalna zaštita energetskih transformatora od unutrašnjih kvarova. (Thesis). Univerzitet u Beogradu. Retrieved from https://fedorabg.bg.ac.rs/fedora/get/o:11571/bdef:Content/get

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Krstivojević, Jelisaveta P., 1982-. “Digitalna zaštita energetskih transformatora od unutrašnjih kvarova.” 2016. Thesis, Univerzitet u Beogradu. Accessed March 07, 2021. https://fedorabg.bg.ac.rs/fedora/get/o:11571/bdef:Content/get.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Krstivojević, Jelisaveta P., 1982-. “Digitalna zaštita energetskih transformatora od unutrašnjih kvarova.” 2016. Web. 07 Mar 2021.

Vancouver:

Krstivojević, Jelisaveta P. 1. Digitalna zaštita energetskih transformatora od unutrašnjih kvarova. [Internet] [Thesis]. Univerzitet u Beogradu; 2016. [cited 2021 Mar 07]. Available from: https://fedorabg.bg.ac.rs/fedora/get/o:11571/bdef:Content/get.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Krstivojević, Jelisaveta P. 1. Digitalna zaštita energetskih transformatora od unutrašnjih kvarova. [Thesis]. Univerzitet u Beogradu; 2016. Available from: https://fedorabg.bg.ac.rs/fedora/get/o:11571/bdef:Content/get

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Boston University

27. Ranjan, Nikhil. Design of a 5-bit algorithmic A/D converter for potential use in a wireless neural recorder application.

Degree: MS, Electrical & Computer Engineering, 2019, Boston University

URL: http://hdl.handle.net/2144/36043

► The constant endeavor to measure and record neural signals from the human brain and anticipate the results to figure out the mechanism which governs the… (more)

Subjects/Keywords: Electrical engineering; Analogue adder; Comparator; Multiply by 2(voltage) circuit; Pre-amplifier

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APA (6^th Edition):

Ranjan, N. (2019). Design of a 5-bit algorithmic A/D converter for potential use in a wireless neural recorder application. (Masters Thesis). Boston University. Retrieved from http://hdl.handle.net/2144/36043

Chicago Manual of Style (16^th Edition):

Ranjan, Nikhil. “Design of a 5-bit algorithmic A/D converter for potential use in a wireless neural recorder application.” 2019. Masters Thesis, Boston University. Accessed March 07, 2021. http://hdl.handle.net/2144/36043.

MLA Handbook (7^th Edition):

Ranjan, Nikhil. “Design of a 5-bit algorithmic A/D converter for potential use in a wireless neural recorder application.” 2019. Web. 07 Mar 2021.

Vancouver:

Ranjan N. Design of a 5-bit algorithmic A/D converter for potential use in a wireless neural recorder application. [Internet] [Masters thesis]. Boston University; 2019. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/2144/36043.

Council of Science Editors:

Ranjan N. Design of a 5-bit algorithmic A/D converter for potential use in a wireless neural recorder application. [Masters Thesis]. Boston University; 2019. Available from: http://hdl.handle.net/2144/36043

Hong Kong University of Science and Technology

28. Choi, Ricky Yiu-kee. An ultra-low energy SAR ADC design with ultra-low-offset pre-amplifier-less comparator latch.

Degree: 2012, Hong Kong University of Science and Technology

URL: http://repository.ust.hk/ir/Record/1783.1-7774 ; https://doi.org/10.14711/thesis-b1197967 ; http://repository.ust.hk/ir/bitstream/1783.1-7774/1/th_redirect.html

► Successive-approximation (SA) ADC is one of the most popular architectures for data-acquisition applications, especially when high-resolution, low power and medium speed are required. In some… (more)

▼ Successive-approximation (SA) ADC is one of the most popular architectures for data-acquisition applications, especially when high-resolution, low power and medium speed are required. In some applications, such as wireless sensor nodes, designing a low power and low energy ADC is one of the major challenges. For an SA-ADC, the dominant power dissipation sources are the comparator and the switching in the DAC capacitor array. We propose a new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC. By separating the decoding of the most significant and the least significant bits, and using two different capacitor arrays with unequal sizes to determine their values, respectively, the average switching energy of the capacitor arrays is dramatically reduced compared to the traditional switching methods. Experiments were carried out on a 10-bit SAR-ADC, designed using a TSMC 0.18μm CMOS process. HSPICE simulations show that a significant reduction in energy consumption is achieved using the proposed design. We also demonstrated the operation in a pipelined architecture to achieve higher throughput without the need of duplication of the DAC capacitor arrays. We also propose a novel architecture of an ultra-low offset comparator latch using on-chip calibration to compensate the process variation. The proposed technique compensates the variation in process parameters such as W/L, μCOX and threshold voltage independently by considering the intrinsic behavior of the MOS transistors without using power-hungry complicated circuits for measuring the transistor characteristics. Monte Carlo post-layout HSPICE simulations were carried out with 100 samples to evaluate the performance of the comparator latch. Experimental results show that when compared with state-of-the-art pre-amplifier-less architectures, the standard deviation of the input voltage offset is reduced by more than 75% over a range of 400mV difference in the common mode input voltage.

Subjects/Keywords: Analog-to-digital converters – Design and construction ; Electric filters ; Comparator circuits – Design and construction

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APA (6^th Edition):

Choi, R. Y. (2012). An ultra-low energy SAR ADC design with ultra-low-offset pre-amplifier-less comparator latch. (Thesis). Hong Kong University of Science and Technology. Retrieved from http://repository.ust.hk/ir/Record/1783.1-7774 ; https://doi.org/10.14711/thesis-b1197967 ; http://repository.ust.hk/ir/bitstream/1783.1-7774/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Choi, Ricky Yiu-kee. “An ultra-low energy SAR ADC design with ultra-low-offset pre-amplifier-less comparator latch.” 2012. Thesis, Hong Kong University of Science and Technology. Accessed March 07, 2021. http://repository.ust.hk/ir/Record/1783.1-7774 ; https://doi.org/10.14711/thesis-b1197967 ; http://repository.ust.hk/ir/bitstream/1783.1-7774/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Choi, Ricky Yiu-kee. “An ultra-low energy SAR ADC design with ultra-low-offset pre-amplifier-less comparator latch.” 2012. Web. 07 Mar 2021.

Vancouver:

Choi RY. An ultra-low energy SAR ADC design with ultra-low-offset pre-amplifier-less comparator latch. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2012. [cited 2021 Mar 07]. Available from: http://repository.ust.hk/ir/Record/1783.1-7774 ; https://doi.org/10.14711/thesis-b1197967 ; http://repository.ust.hk/ir/bitstream/1783.1-7774/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Choi RY. An ultra-low energy SAR ADC design with ultra-low-offset pre-amplifier-less comparator latch. [Thesis]. Hong Kong University of Science and Technology; 2012. Available from: http://repository.ust.hk/ir/Record/1783.1-7774 ; https://doi.org/10.14711/thesis-b1197967 ; http://repository.ust.hk/ir/bitstream/1783.1-7774/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

IUPUI

29. Balasubramanian, Linknath Surya. ASIC implemented MicroBlaze-based Coprocessor for Data Stream Management Systems.

Degree: 2020, IUPUI

URL: http://hdl.handle.net/1805/22696

►

Indiana University-Purdue University Indianapolis (IUPUI)

The drastic increase in Internet usage demands the need for processing data in real time with higher efficiency than ever… (more)

Subjects/Keywords: Symbiote Coprocessor Unit; ACG/OCG; sequential comparator; D-word multiplier/divider; FPGA

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APA (6^th Edition):

Balasubramanian, L. S. (2020). ASIC implemented MicroBlaze-based Coprocessor for Data Stream Management Systems. (Thesis). IUPUI. Retrieved from http://hdl.handle.net/1805/22696

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Balasubramanian, Linknath Surya. “ASIC implemented MicroBlaze-based Coprocessor for Data Stream Management Systems.” 2020. Thesis, IUPUI. Accessed March 07, 2021. http://hdl.handle.net/1805/22696.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Balasubramanian, Linknath Surya. “ASIC implemented MicroBlaze-based Coprocessor for Data Stream Management Systems.” 2020. Web. 07 Mar 2021.

Vancouver:

Balasubramanian LS. ASIC implemented MicroBlaze-based Coprocessor for Data Stream Management Systems. [Internet] [Thesis]. IUPUI; 2020. [cited 2021 Mar 07]. Available from: http://hdl.handle.net/1805/22696.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Balasubramanian LS. ASIC implemented MicroBlaze-based Coprocessor for Data Stream Management Systems. [Thesis]. IUPUI; 2020. Available from: http://hdl.handle.net/1805/22696

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Univerzitet u Beogradu

30. Ostojić, Mladen, 1985-, 33531751. Дигитална заштита синхроних генератора и мотора од испада из синхронизма и уласка генератора у моторни режим.

Degree: Elektrotehnički fakultet, 2020, Univerzitet u Beogradu

URL: https://fedorabg.bg.ac.rs/fedora/get/o:22838/bdef:Content/get

Техничке науке – Електротехника-Електроенергетски системи / Technical sciences – Electrical engineering-Power systems

У овој докторској дисертацији представљена су три алгоритма који заједно чине комплетну заштиту синхроног генератора од губитка синхронизма и уласка у моторни режим рада...

Advisors/Committee Members: Mikulović, Jovan, 1968-, 12766311.

Subjects/Keywords: relay protection; synchronous generator; phase comparator; loss of excitation; out of step; islanding operation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Ostojić, Mladen, 1985-, 3. (2020). Дигитална заштита синхроних генератора и мотора од испада из синхронизма и уласка генератора у моторни режим. (Thesis). Univerzitet u Beogradu. Retrieved from https://fedorabg.bg.ac.rs/fedora/get/o:22838/bdef:Content/get

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Ostojić, Mladen, 1985-, 33531751. “Дигитална заштита синхроних генератора и мотора од испада из синхронизма и уласка генератора у моторни режим.” 2020. Thesis, Univerzitet u Beogradu. Accessed March 07, 2021. https://fedorabg.bg.ac.rs/fedora/get/o:22838/bdef:Content/get.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Ostojić, Mladen, 1985-, 33531751. “Дигитална заштита синхроних генератора и мотора од испада из синхронизма и уласка генератора у моторни режим.” 2020. Web. 07 Mar 2021.

Vancouver:

Ostojić, Mladen, 1985- 3. Дигитална заштита синхроних генератора и мотора од испада из синхронизма и уласка генератора у моторни режим. [Internet] [Thesis]. Univerzitet u Beogradu; 2020. [cited 2021 Mar 07]. Available from: https://fedorabg.bg.ac.rs/fedora/get/o:22838/bdef:Content/get.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ostojić, Mladen, 1985- 3. Дигитална заштита синхроних генератора и мотора од испада из синхронизма и уласка генератора у моторни режим. [Thesis]. Univerzitet u Beogradu; 2020. Available from: https://fedorabg.bg.ac.rs/fedora/get/o:22838/bdef:Content/get

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Open Access Theses and Dissertations