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You searched for subject:(Circuits). Showing records 1 – 30 of 4124 total matches.

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1. Madi, Saida. Analytical study of the application of the maximum power transfer theorem to electrical circuits and systems.

Degree: 2010, Université M'Hamed Bougara Boumerdès

120 p. : ill. ; 30 cm

The present study analyses the application of the Maximum Power Transfer Theorem (MPTT) to the electrical circuits and… (more)

Subjects/Keywords: Electric circuits; Circuits électriques; Electromécanique

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Madi, S. (2010). Analytical study of the application of the maximum power transfer theorem to electrical circuits and systems. (Thesis). Université M'Hamed Bougara Boumerdès. Retrieved from http://dlibrary.univ-boumerdes.dz:8080123456789/1503

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Madi, Saida. “Analytical study of the application of the maximum power transfer theorem to electrical circuits and systems.” 2010. Thesis, Université M'Hamed Bougara Boumerdès. Accessed October 28, 2020. http://dlibrary.univ-boumerdes.dz:8080123456789/1503.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Madi, Saida. “Analytical study of the application of the maximum power transfer theorem to electrical circuits and systems.” 2010. Web. 28 Oct 2020.

Vancouver:

Madi S. Analytical study of the application of the maximum power transfer theorem to electrical circuits and systems. [Internet] [Thesis]. Université M'Hamed Bougara Boumerdès; 2010. [cited 2020 Oct 28]. Available from: http://dlibrary.univ-boumerdes.dz:8080123456789/1503.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Madi S. Analytical study of the application of the maximum power transfer theorem to electrical circuits and systems. [Thesis]. Université M'Hamed Bougara Boumerdès; 2010. Available from: http://dlibrary.univ-boumerdes.dz:8080123456789/1503

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. Madi, Saida. Analytical study of the application of the maximum power transfer theorem to electrical circuits and systems.

Degree: 2010, Université M'Hamed Bougara Boumerdès

120 p. ; ill. ; 30 cm

The present study analyses the application of the Maximum Power Transfer Theorem (MPTT) to the electrical circuits and… (more)

Subjects/Keywords: Electric circuits; Circuits électriques; Electromécanique

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APA (6th Edition):

Madi, S. (2010). Analytical study of the application of the maximum power transfer theorem to electrical circuits and systems. (Thesis). Université M'Hamed Bougara Boumerdès. Retrieved from http://dlibrary.univ-boumerdes.dz:8080/jspui/handle/123456789/1022

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Madi, Saida. “Analytical study of the application of the maximum power transfer theorem to electrical circuits and systems.” 2010. Thesis, Université M'Hamed Bougara Boumerdès. Accessed October 28, 2020. http://dlibrary.univ-boumerdes.dz:8080/jspui/handle/123456789/1022.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Madi, Saida. “Analytical study of the application of the maximum power transfer theorem to electrical circuits and systems.” 2010. Web. 28 Oct 2020.

Vancouver:

Madi S. Analytical study of the application of the maximum power transfer theorem to electrical circuits and systems. [Internet] [Thesis]. Université M'Hamed Bougara Boumerdès; 2010. [cited 2020 Oct 28]. Available from: http://dlibrary.univ-boumerdes.dz:8080/jspui/handle/123456789/1022.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Madi S. Analytical study of the application of the maximum power transfer theorem to electrical circuits and systems. [Thesis]. Université M'Hamed Bougara Boumerdès; 2010. Available from: http://dlibrary.univ-boumerdes.dz:8080/jspui/handle/123456789/1022

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Utah

3. Lodder, Michael Alan. Biologically motivated predictions for dynamic power in VLSI circuits.

Degree: MS;, Electrical & Computer Engineering;, 2008, University of Utah

 As Very Large Scale Integrated (VLSI) circuits continue to shrink in size and increase in complexity, device design is increasingly power constrained. Currently, engineers must… (more)

Subjects/Keywords: Integrated circuits

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APA (6th Edition):

Lodder, M. A. (2008). Biologically motivated predictions for dynamic power in VLSI circuits. (Masters Thesis). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1552/rec/158

Chicago Manual of Style (16th Edition):

Lodder, Michael Alan. “Biologically motivated predictions for dynamic power in VLSI circuits.” 2008. Masters Thesis, University of Utah. Accessed October 28, 2020. http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1552/rec/158.

MLA Handbook (7th Edition):

Lodder, Michael Alan. “Biologically motivated predictions for dynamic power in VLSI circuits.” 2008. Web. 28 Oct 2020.

Vancouver:

Lodder MA. Biologically motivated predictions for dynamic power in VLSI circuits. [Internet] [Masters thesis]. University of Utah; 2008. [cited 2020 Oct 28]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1552/rec/158.

Council of Science Editors:

Lodder MA. Biologically motivated predictions for dynamic power in VLSI circuits. [Masters Thesis]. University of Utah; 2008. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1552/rec/158


University of Utah

4. Sai, Santosh Varanasi Naga. Performance analysis of four-phase untimed asynchronous handshake protocols.

Degree: MS;, Electrical & Computer Engineering;, 2009, University of Utah

 This thesis presents the trade-offs between concurrency reduction, energy and performance across a four-phase untimed asynchronous protocol family. The formal understanding of the handshake protocols… (more)

Subjects/Keywords: Asynchronous circuits

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APA (6th Edition):

Sai, S. V. N. (2009). Performance analysis of four-phase untimed asynchronous handshake protocols. (Masters Thesis). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1043/rec/873

Chicago Manual of Style (16th Edition):

Sai, Santosh Varanasi Naga. “Performance analysis of four-phase untimed asynchronous handshake protocols.” 2009. Masters Thesis, University of Utah. Accessed October 28, 2020. http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1043/rec/873.

MLA Handbook (7th Edition):

Sai, Santosh Varanasi Naga. “Performance analysis of four-phase untimed asynchronous handshake protocols.” 2009. Web. 28 Oct 2020.

Vancouver:

Sai SVN. Performance analysis of four-phase untimed asynchronous handshake protocols. [Internet] [Masters thesis]. University of Utah; 2009. [cited 2020 Oct 28]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1043/rec/873.

Council of Science Editors:

Sai SVN. Performance analysis of four-phase untimed asynchronous handshake protocols. [Masters Thesis]. University of Utah; 2009. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1043/rec/873


Ryerson University

5. Al-Obaidy, Furat. IC testing using thermal image based on intelligent classification methods.

Degree: 2016, Ryerson University

 The goal of this thesis is to propose an algorithm which would can locate the defect IC on the PCB during their manufacturing phase based… (more)

Subjects/Keywords: Integrated circuits  – Thermal properties  – Testing  – Thermographic methods; Integrated circuits  – Testing; Integrated circuits  – Fault tolerance; Integrated circuits; Printed circuits  – Testing; Printed circuits

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APA (6th Edition):

Al-Obaidy, F. (2016). IC testing using thermal image based on intelligent classification methods. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A5822

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Al-Obaidy, Furat. “IC testing using thermal image based on intelligent classification methods.” 2016. Thesis, Ryerson University. Accessed October 28, 2020. https://digital.library.ryerson.ca/islandora/object/RULA%3A5822.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Al-Obaidy, Furat. “IC testing using thermal image based on intelligent classification methods.” 2016. Web. 28 Oct 2020.

Vancouver:

Al-Obaidy F. IC testing using thermal image based on intelligent classification methods. [Internet] [Thesis]. Ryerson University; 2016. [cited 2020 Oct 28]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5822.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Al-Obaidy F. IC testing using thermal image based on intelligent classification methods. [Thesis]. Ryerson University; 2016. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A5822

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

6. Patwary, Md. Ataur R. Low-power dynamic CMOS circuits in high-performance memory arrays.

Degree: PhD, Electrical and Computer Engineering, 2009, Oregon State University

 Dynamic CMOS circuits are commonly used in high-performance memory arrays to implement wide-NOR logic functions for their read and search operations. This is because dynamic… (more)

Subjects/Keywords: Dynamic circuits; Low voltage integrated circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Patwary, M. A. R. (2009). Low-power dynamic CMOS circuits in high-performance memory arrays. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/10906

Chicago Manual of Style (16th Edition):

Patwary, Md Ataur R. “Low-power dynamic CMOS circuits in high-performance memory arrays.” 2009. Doctoral Dissertation, Oregon State University. Accessed October 28, 2020. http://hdl.handle.net/1957/10906.

MLA Handbook (7th Edition):

Patwary, Md Ataur R. “Low-power dynamic CMOS circuits in high-performance memory arrays.” 2009. Web. 28 Oct 2020.

Vancouver:

Patwary MAR. Low-power dynamic CMOS circuits in high-performance memory arrays. [Internet] [Doctoral dissertation]. Oregon State University; 2009. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1957/10906.

Council of Science Editors:

Patwary MAR. Low-power dynamic CMOS circuits in high-performance memory arrays. [Doctoral Dissertation]. Oregon State University; 2009. Available from: http://hdl.handle.net/1957/10906


Drexel University

7. Lu, Jianchao. High performance IC clock networks with grid and tree topologies.

Degree: 2011, Drexel University

In this dissertation, an essential step in the integrated circuit (IC) physical design flow—the clock network design—is investigated. Clock network design entailsa series of computationally… (more)

Subjects/Keywords: Electric engineering; Integrated circuits; Timing circuits

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APA (6th Edition):

Lu, J. (2011). High performance IC clock networks with grid and tree topologies. (Thesis). Drexel University. Retrieved from http://hdl.handle.net/1860/3526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lu, Jianchao. “High performance IC clock networks with grid and tree topologies.” 2011. Thesis, Drexel University. Accessed October 28, 2020. http://hdl.handle.net/1860/3526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lu, Jianchao. “High performance IC clock networks with grid and tree topologies.” 2011. Web. 28 Oct 2020.

Vancouver:

Lu J. High performance IC clock networks with grid and tree topologies. [Internet] [Thesis]. Drexel University; 2011. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1860/3526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lu J. High performance IC clock networks with grid and tree topologies. [Thesis]. Drexel University; 2011. Available from: http://hdl.handle.net/1860/3526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Duke University

8. Barrett, John. Design of Functional Active RF Metamaterials with Embedded Transistor-Based Circuits and Devices .

Degree: 2015, Duke University

  Recent advances in electromagnetics introduced tools that enable the creation of arti- cial electromagnetic structures with exotic properties such as negative material pa- rameters.… (more)

Subjects/Keywords: Engineering; Active Circuits; Active Metamaterials; Transistor Circuits

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APA (6th Edition):

Barrett, J. (2015). Design of Functional Active RF Metamaterials with Embedded Transistor-Based Circuits and Devices . (Thesis). Duke University. Retrieved from http://hdl.handle.net/10161/9912

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Barrett, John. “Design of Functional Active RF Metamaterials with Embedded Transistor-Based Circuits and Devices .” 2015. Thesis, Duke University. Accessed October 28, 2020. http://hdl.handle.net/10161/9912.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Barrett, John. “Design of Functional Active RF Metamaterials with Embedded Transistor-Based Circuits and Devices .” 2015. Web. 28 Oct 2020.

Vancouver:

Barrett J. Design of Functional Active RF Metamaterials with Embedded Transistor-Based Circuits and Devices . [Internet] [Thesis]. Duke University; 2015. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/10161/9912.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Barrett J. Design of Functional Active RF Metamaterials with Embedded Transistor-Based Circuits and Devices . [Thesis]. Duke University; 2015. Available from: http://hdl.handle.net/10161/9912

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Johannesburg

9. Lacquet, Beatrys Margaretha. Schottky-Hek veldeffektransistortegnologie met ioonplant en verstuifets.

Degree: 2014, University of Johannesburg

M.Ing. (Electrical & Electronic Engineering Science)

Please refer to full text to view abstract

Subjects/Keywords: Integrated circuits; Semiconductors

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lacquet, B. M. (2014). Schottky-Hek veldeffektransistortegnologie met ioonplant en verstuifets. (Thesis). University of Johannesburg. Retrieved from http://hdl.handle.net/10210/12197

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lacquet, Beatrys Margaretha. “Schottky-Hek veldeffektransistortegnologie met ioonplant en verstuifets.” 2014. Thesis, University of Johannesburg. Accessed October 28, 2020. http://hdl.handle.net/10210/12197.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lacquet, Beatrys Margaretha. “Schottky-Hek veldeffektransistortegnologie met ioonplant en verstuifets.” 2014. Web. 28 Oct 2020.

Vancouver:

Lacquet BM. Schottky-Hek veldeffektransistortegnologie met ioonplant en verstuifets. [Internet] [Thesis]. University of Johannesburg; 2014. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/10210/12197.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lacquet BM. Schottky-Hek veldeffektransistortegnologie met ioonplant en verstuifets. [Thesis]. University of Johannesburg; 2014. Available from: http://hdl.handle.net/10210/12197

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Queens University

10. He, Shan. Design of Low-Voltage and Low-Distortion CMOS RF Integrated Circuits Using Volterra Analysis .

Degree: Electrical and Computer Engineering, 2011, Queens University

 Analog circuits that operate with low voltage supply headroom generally suffer from poor linearity performance, poor noise performance, etc. However, with the aggressive scaling of… (more)

Subjects/Keywords: Linearity ; Integrated Circuits

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APA (6th Edition):

He, S. (2011). Design of Low-Voltage and Low-Distortion CMOS RF Integrated Circuits Using Volterra Analysis . (Thesis). Queens University. Retrieved from http://hdl.handle.net/1974/6746

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

He, Shan. “Design of Low-Voltage and Low-Distortion CMOS RF Integrated Circuits Using Volterra Analysis .” 2011. Thesis, Queens University. Accessed October 28, 2020. http://hdl.handle.net/1974/6746.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

He, Shan. “Design of Low-Voltage and Low-Distortion CMOS RF Integrated Circuits Using Volterra Analysis .” 2011. Web. 28 Oct 2020.

Vancouver:

He S. Design of Low-Voltage and Low-Distortion CMOS RF Integrated Circuits Using Volterra Analysis . [Internet] [Thesis]. Queens University; 2011. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1974/6746.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

He S. Design of Low-Voltage and Low-Distortion CMOS RF Integrated Circuits Using Volterra Analysis . [Thesis]. Queens University; 2011. Available from: http://hdl.handle.net/1974/6746

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Latrobe University

11. Radfar, Mohsen. Method to address performance decline due to process, voltage, and temperature variations in integrated circuits.

Degree: PhD, 2013, Latrobe University

Thesis (Ph.D.) - La Trobe University, 2013

Submission note: "A thesis submitted in total fulfilment of the requirements for the degree of Doctor of Philosophy… (more)

Subjects/Keywords: Integrated circuits.; Integrated circuits  – Design and construction.; Low voltage integrated circuits.

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APA (6th Edition):

Radfar, M. (2013). Method to address performance decline due to process, voltage, and temperature variations in integrated circuits. (Doctoral Dissertation). Latrobe University. Retrieved from http://hdl.handle.net/1959.9/513567

Chicago Manual of Style (16th Edition):

Radfar, Mohsen. “Method to address performance decline due to process, voltage, and temperature variations in integrated circuits.” 2013. Doctoral Dissertation, Latrobe University. Accessed October 28, 2020. http://hdl.handle.net/1959.9/513567.

MLA Handbook (7th Edition):

Radfar, Mohsen. “Method to address performance decline due to process, voltage, and temperature variations in integrated circuits.” 2013. Web. 28 Oct 2020.

Vancouver:

Radfar M. Method to address performance decline due to process, voltage, and temperature variations in integrated circuits. [Internet] [Doctoral dissertation]. Latrobe University; 2013. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1959.9/513567.

Council of Science Editors:

Radfar M. Method to address performance decline due to process, voltage, and temperature variations in integrated circuits. [Doctoral Dissertation]. Latrobe University; 2013. Available from: http://hdl.handle.net/1959.9/513567


University of Johannesburg

12. Kirschner, Nikolaus. Modelling of I2l unit cell.

Degree: PhD, 2015, University of Johannesburg

Please refer to full text to view abstract

Subjects/Keywords: Integrated circuits; Transistor circuits; Electric circuits

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APA (6th Edition):

Kirschner, N. (2015). Modelling of I2l unit cell. (Doctoral Dissertation). University of Johannesburg. Retrieved from http://hdl.handle.net/10210/14482

Chicago Manual of Style (16th Edition):

Kirschner, Nikolaus. “Modelling of I2l unit cell.” 2015. Doctoral Dissertation, University of Johannesburg. Accessed October 28, 2020. http://hdl.handle.net/10210/14482.

MLA Handbook (7th Edition):

Kirschner, Nikolaus. “Modelling of I2l unit cell.” 2015. Web. 28 Oct 2020.

Vancouver:

Kirschner N. Modelling of I2l unit cell. [Internet] [Doctoral dissertation]. University of Johannesburg; 2015. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/10210/14482.

Council of Science Editors:

Kirschner N. Modelling of I2l unit cell. [Doctoral Dissertation]. University of Johannesburg; 2015. Available from: http://hdl.handle.net/10210/14482

13. Tan, Zhou. Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing.

Degree: 2011, North Dakota State University

 This paper presents the design of a reconfigurable asynchronous unit, called the pulsed quad-cell (PQ-cell), for conformal computing. The conformal computing vision is to create… (more)

Subjects/Keywords: Cellular automata.; Asynchronous circuits.; Pulse circuits.; Field programmable gate arrays.; Gate array circuits.

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APA (6th Edition):

Tan, Z. (2011). Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing. (Thesis). North Dakota State University. Retrieved from http://hdl.handle.net/10365/29176

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tan, Zhou. “Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing.” 2011. Thesis, North Dakota State University. Accessed October 28, 2020. http://hdl.handle.net/10365/29176.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tan, Zhou. “Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing.” 2011. Web. 28 Oct 2020.

Vancouver:

Tan Z. Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing. [Internet] [Thesis]. North Dakota State University; 2011. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/10365/29176.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tan Z. Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing. [Thesis]. North Dakota State University; 2011. Available from: http://hdl.handle.net/10365/29176

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

14. Mettala Gilla, Swetha. Silicon Compilation and Test for Dataflow Implementations in GasP and Click.

Degree: PhD, Electrical and Computer Engineering, 2018, Portland State University

  Many modern computer systems are distributed over space. Well-known examples are the Internet of Things and IBM's TrueNorth for deep learning applications. At the… (more)

Subjects/Keywords: Data flow computing; Electrical engineering; Integrated circuits; Asynchronous circuits; Digital Circuits; Electrical and Computer Engineering

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APA (6th Edition):

Mettala Gilla, S. (2018). Silicon Compilation and Test for Dataflow Implementations in GasP and Click. (Doctoral Dissertation). Portland State University. Retrieved from https://pdxscholar.library.pdx.edu/open_access_etds/4237

Chicago Manual of Style (16th Edition):

Mettala Gilla, Swetha. “Silicon Compilation and Test for Dataflow Implementations in GasP and Click.” 2018. Doctoral Dissertation, Portland State University. Accessed October 28, 2020. https://pdxscholar.library.pdx.edu/open_access_etds/4237.

MLA Handbook (7th Edition):

Mettala Gilla, Swetha. “Silicon Compilation and Test for Dataflow Implementations in GasP and Click.” 2018. Web. 28 Oct 2020.

Vancouver:

Mettala Gilla S. Silicon Compilation and Test for Dataflow Implementations in GasP and Click. [Internet] [Doctoral dissertation]. Portland State University; 2018. [cited 2020 Oct 28]. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/4237.

Council of Science Editors:

Mettala Gilla S. Silicon Compilation and Test for Dataflow Implementations in GasP and Click. [Doctoral Dissertation]. Portland State University; 2018. Available from: https://pdxscholar.library.pdx.edu/open_access_etds/4237


Oregon State University

15. Jacob, Michael E. Ultra low capacitance RFIC probe.

Degree: MS, Electrical and Computer Engineering, 2009, Oregon State University

 In Radio Frequency Integrated Circuits (RFIC) or high frequency digital ICs, there is a demand to probe the internal nodes for testing. The ultra low… (more)

Subjects/Keywords: Radio frequency integrated circuits  – Testing

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APA (6th Edition):

Jacob, M. E. (2009). Ultra low capacitance RFIC probe. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/11868

Chicago Manual of Style (16th Edition):

Jacob, Michael E. “Ultra low capacitance RFIC probe.” 2009. Masters Thesis, Oregon State University. Accessed October 28, 2020. http://hdl.handle.net/1957/11868.

MLA Handbook (7th Edition):

Jacob, Michael E. “Ultra low capacitance RFIC probe.” 2009. Web. 28 Oct 2020.

Vancouver:

Jacob ME. Ultra low capacitance RFIC probe. [Internet] [Masters thesis]. Oregon State University; 2009. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1957/11868.

Council of Science Editors:

Jacob ME. Ultra low capacitance RFIC probe. [Masters Thesis]. Oregon State University; 2009. Available from: http://hdl.handle.net/1957/11868

16. Nagami, Koichi. Parallel Algorithms for Formal Logic Design Verification Based on Binary Decision Diagrams : 二分決定グラフを用いた形式的論理設計検証における並列処理; ニブン ケッテイ グラフ オ モチイタ ケイシキテキ ロンリ セッケイ ケンショウ ニオケル ヘイレツ ショリ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: Logic Circuits

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APA (6th Edition):

Nagami, K. (n.d.). Parallel Algorithms for Formal Logic Design Verification Based on Binary Decision Diagrams : 二分決定グラフを用いた形式的論理設計検証における並列処理; ニブン ケッテイ グラフ オ モチイタ ケイシキテキ ロンリ セッケイ ケンショウ ニオケル ヘイレツ ショリ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/2508

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nagami, Koichi. “Parallel Algorithms for Formal Logic Design Verification Based on Binary Decision Diagrams : 二分決定グラフを用いた形式的論理設計検証における並列処理; ニブン ケッテイ グラフ オ モチイタ ケイシキテキ ロンリ セッケイ ケンショウ ニオケル ヘイレツ ショリ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed October 28, 2020. http://hdl.handle.net/10061/2508.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nagami, Koichi. “Parallel Algorithms for Formal Logic Design Verification Based on Binary Decision Diagrams : 二分決定グラフを用いた形式的論理設計検証における並列処理; ニブン ケッテイ グラフ オ モチイタ ケイシキテキ ロンリ セッケイ ケンショウ ニオケル ヘイレツ ショリ.” Web. 28 Oct 2020.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Nagami K. Parallel Algorithms for Formal Logic Design Verification Based on Binary Decision Diagrams : 二分決定グラフを用いた形式的論理設計検証における並列処理; ニブン ケッテイ グラフ オ モチイタ ケイシキテキ ロンリ セッケイ ケンショウ ニオケル ヘイレツ ショリ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2020 Oct 28]. Available from: http://hdl.handle.net/10061/2508.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Nagami K. Parallel Algorithms for Formal Logic Design Verification Based on Binary Decision Diagrams : 二分決定グラフを用いた形式的論理設計検証における並列処理; ニブン ケッテイ グラフ オ モチイタ ケイシキテキ ロンリ セッケイ ケンショウ ニオケル ヘイレツ ショリ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/2508

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


Rochester Institute of Technology

17. Ting, Goodwin. An Integrated BiCMOS driver chip for medium power applications.

Degree: Electrical Engineering, 1991, Rochester Institute of Technology

 The development of an integrated driver circuit intended for medium power switching applications is presented. The device contains, on one chip, CMOS digital control logic… (more)

Subjects/Keywords: Integrated circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ting, G. (1991). An Integrated BiCMOS driver chip for medium power applications. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/5569

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ting, Goodwin. “An Integrated BiCMOS driver chip for medium power applications.” 1991. Thesis, Rochester Institute of Technology. Accessed October 28, 2020. https://scholarworks.rit.edu/theses/5569.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ting, Goodwin. “An Integrated BiCMOS driver chip for medium power applications.” 1991. Web. 28 Oct 2020.

Vancouver:

Ting G. An Integrated BiCMOS driver chip for medium power applications. [Internet] [Thesis]. Rochester Institute of Technology; 1991. [cited 2020 Oct 28]. Available from: https://scholarworks.rit.edu/theses/5569.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ting G. An Integrated BiCMOS driver chip for medium power applications. [Thesis]. Rochester Institute of Technology; 1991. Available from: https://scholarworks.rit.edu/theses/5569

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

18. Price, David T. N-Well CMOS process integration.

Degree: Electrical Engineering, 1992, Rochester Institute of Technology

 The predominant integrated circuit fabrication technologies used for VLSI devices are CMOS, and BiCMOS. The goal of this work was to develop a CMOS process… (more)

Subjects/Keywords: Integrated circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Price, D. T. (1992). N-Well CMOS process integration. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/5574

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Price, David T. “N-Well CMOS process integration.” 1992. Thesis, Rochester Institute of Technology. Accessed October 28, 2020. https://scholarworks.rit.edu/theses/5574.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Price, David T. “N-Well CMOS process integration.” 1992. Web. 28 Oct 2020.

Vancouver:

Price DT. N-Well CMOS process integration. [Internet] [Thesis]. Rochester Institute of Technology; 1992. [cited 2020 Oct 28]. Available from: https://scholarworks.rit.edu/theses/5574.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Price DT. N-Well CMOS process integration. [Thesis]. Rochester Institute of Technology; 1992. Available from: https://scholarworks.rit.edu/theses/5574

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Utah

19. Maxwell, John Nathan. Design and fabrication of an actuation module using integrated pneumatic technology.

Degree: MS;, Mechanical Engineering;, 2007, University of Utah

 In this thesis, xurography techniques are used to create an integrated pneumatic card (IPC) by integrating fluidic channels inside the electronic circuitry of their control… (more)

Subjects/Keywords: Pneumatic control; Actuators; Printed circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Maxwell, J. N. (2007). Design and fabrication of an actuation module using integrated pneumatic technology. (Masters Thesis). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1594/rec/299

Chicago Manual of Style (16th Edition):

Maxwell, John Nathan. “Design and fabrication of an actuation module using integrated pneumatic technology.” 2007. Masters Thesis, University of Utah. Accessed October 28, 2020. http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1594/rec/299.

MLA Handbook (7th Edition):

Maxwell, John Nathan. “Design and fabrication of an actuation module using integrated pneumatic technology.” 2007. Web. 28 Oct 2020.

Vancouver:

Maxwell JN. Design and fabrication of an actuation module using integrated pneumatic technology. [Internet] [Masters thesis]. University of Utah; 2007. [cited 2020 Oct 28]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1594/rec/299.

Council of Science Editors:

Maxwell JN. Design and fabrication of an actuation module using integrated pneumatic technology. [Masters Thesis]. University of Utah; 2007. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/1594/rec/299


University of Alberta

20. Holmes, Stephen Michael. High-speed configurable analog block design for a field-programmable analog array.

Degree: MS, Department of Electrical and Computer Engineering, 2011, University of Alberta

 This thesis is an exploration into the design of configurable analog block (CAB) for field programmable analog arrays (FPAAs) designed in modern complementary metal-oxide-semiconductor (CMOS)… (more)

Subjects/Keywords: OTA; CAB; FPAA; circuits; Analog

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Holmes, S. M. (2011). High-speed configurable analog block design for a field-programmable analog array. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/0k225b288

Chicago Manual of Style (16th Edition):

Holmes, Stephen Michael. “High-speed configurable analog block design for a field-programmable analog array.” 2011. Masters Thesis, University of Alberta. Accessed October 28, 2020. https://era.library.ualberta.ca/files/0k225b288.

MLA Handbook (7th Edition):

Holmes, Stephen Michael. “High-speed configurable analog block design for a field-programmable analog array.” 2011. Web. 28 Oct 2020.

Vancouver:

Holmes SM. High-speed configurable analog block design for a field-programmable analog array. [Internet] [Masters thesis]. University of Alberta; 2011. [cited 2020 Oct 28]. Available from: https://era.library.ualberta.ca/files/0k225b288.

Council of Science Editors:

Holmes SM. High-speed configurable analog block design for a field-programmable analog array. [Masters Thesis]. University of Alberta; 2011. Available from: https://era.library.ualberta.ca/files/0k225b288


Oregon State University

21. Fasang, Patrick Pad, 1941-. Design of a mini-computer controlled digital integrated circuit tester.

Degree: PhD, Electrical and Computer Engineering, 1973, Oregon State University

 The purpose of the thesis is to design, construct, program, and test an automatic integrated circuit test system. The class of integrated circuits tested was… (more)

Subjects/Keywords: Integrated circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fasang, Patrick Pad, 1. (1973). Design of a mini-computer controlled digital integrated circuit tester. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/46097

Chicago Manual of Style (16th Edition):

Fasang, Patrick Pad, 1941-. “Design of a mini-computer controlled digital integrated circuit tester.” 1973. Doctoral Dissertation, Oregon State University. Accessed October 28, 2020. http://hdl.handle.net/1957/46097.

MLA Handbook (7th Edition):

Fasang, Patrick Pad, 1941-. “Design of a mini-computer controlled digital integrated circuit tester.” 1973. Web. 28 Oct 2020.

Vancouver:

Fasang, Patrick Pad 1. Design of a mini-computer controlled digital integrated circuit tester. [Internet] [Doctoral dissertation]. Oregon State University; 1973. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1957/46097.

Council of Science Editors:

Fasang, Patrick Pad 1. Design of a mini-computer controlled digital integrated circuit tester. [Doctoral Dissertation]. Oregon State University; 1973. Available from: http://hdl.handle.net/1957/46097


Oregon State University

22. Chang, Ki Suk. An integrated MOS addressing circuit.

Degree: MS, Electrical and Electronics Engineering, 1969, Oregon State University

 This paper is a study of the design of an integrated MOS addressing circuit by using the modified two-phase dynamic shift register. This modified circuit… (more)

Subjects/Keywords: Transistor circuits

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APA (6th Edition):

Chang, K. S. (1969). An integrated MOS addressing circuit. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/46148

Chicago Manual of Style (16th Edition):

Chang, Ki Suk. “An integrated MOS addressing circuit.” 1969. Masters Thesis, Oregon State University. Accessed October 28, 2020. http://hdl.handle.net/1957/46148.

MLA Handbook (7th Edition):

Chang, Ki Suk. “An integrated MOS addressing circuit.” 1969. Web. 28 Oct 2020.

Vancouver:

Chang KS. An integrated MOS addressing circuit. [Internet] [Masters thesis]. Oregon State University; 1969. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1957/46148.

Council of Science Editors:

Chang KS. An integrated MOS addressing circuit. [Masters Thesis]. Oregon State University; 1969. Available from: http://hdl.handle.net/1957/46148


Oregon State University

23. Chiang, Ching Hwa. Active network synthesis using operational amplifiers.

Degree: MS, Electrical and Electronics Engineering, 1967, Oregon State University

 Three synthesis methods for the realization of the voltage transfer function by means of RC elements and three different active devices are presented. These three… (more)

Subjects/Keywords: Electric circuits

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APA (6th Edition):

Chiang, C. H. (1967). Active network synthesis using operational amplifiers. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/47010

Chicago Manual of Style (16th Edition):

Chiang, Ching Hwa. “Active network synthesis using operational amplifiers.” 1967. Masters Thesis, Oregon State University. Accessed October 28, 2020. http://hdl.handle.net/1957/47010.

MLA Handbook (7th Edition):

Chiang, Ching Hwa. “Active network synthesis using operational amplifiers.” 1967. Web. 28 Oct 2020.

Vancouver:

Chiang CH. Active network synthesis using operational amplifiers. [Internet] [Masters thesis]. Oregon State University; 1967. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1957/47010.

Council of Science Editors:

Chiang CH. Active network synthesis using operational amplifiers. [Masters Thesis]. Oregon State University; 1967. Available from: http://hdl.handle.net/1957/47010


Oregon State University

24. Hung, Shih-chuan. The design of a single chip logic state analyzer.

Degree: MS, Electrical and Computer Engineering, 1988, Oregon State University

 This thesis describes the design of a single-chip logic analyzer. The utility of such a chip in measuring and recording digital system parameters is illustrated.… (more)

Subjects/Keywords: Logic circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hung, S. (1988). The design of a single chip logic state analyzer. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/39857

Chicago Manual of Style (16th Edition):

Hung, Shih-chuan. “The design of a single chip logic state analyzer.” 1988. Masters Thesis, Oregon State University. Accessed October 28, 2020. http://hdl.handle.net/1957/39857.

MLA Handbook (7th Edition):

Hung, Shih-chuan. “The design of a single chip logic state analyzer.” 1988. Web. 28 Oct 2020.

Vancouver:

Hung S. The design of a single chip logic state analyzer. [Internet] [Masters thesis]. Oregon State University; 1988. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1957/39857.

Council of Science Editors:

Hung S. The design of a single chip logic state analyzer. [Masters Thesis]. Oregon State University; 1988. Available from: http://hdl.handle.net/1957/39857


Oregon State University

25. Wilkerson, John Lee. Transistor circuit design for optimum noise performance.

Degree: MS, Electrical Engineering, 1962, Oregon State University

Subjects/Keywords: Transistor circuits

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APA (6th Edition):

Wilkerson, J. L. (1962). Transistor circuit design for optimum noise performance. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/51566

Chicago Manual of Style (16th Edition):

Wilkerson, John Lee. “Transistor circuit design for optimum noise performance.” 1962. Masters Thesis, Oregon State University. Accessed October 28, 2020. http://hdl.handle.net/1957/51566.

MLA Handbook (7th Edition):

Wilkerson, John Lee. “Transistor circuit design for optimum noise performance.” 1962. Web. 28 Oct 2020.

Vancouver:

Wilkerson JL. Transistor circuit design for optimum noise performance. [Internet] [Masters thesis]. Oregon State University; 1962. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1957/51566.

Council of Science Editors:

Wilkerson JL. Transistor circuit design for optimum noise performance. [Masters Thesis]. Oregon State University; 1962. Available from: http://hdl.handle.net/1957/51566


Oregon State University

26. Kazmi, Saeed A. Integrated injection logic alarm system.

Degree: MS, Electrical Engineering, 1976, Oregon State University

 The object of this work was to design and fabricate an integrated circuit using Integrated Injection Logic. Integrated Injection Logic (I[superscript 2] L) is a… (more)

Subjects/Keywords: Integrated circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kazmi, S. A. (1976). Integrated injection logic alarm system. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/43395

Chicago Manual of Style (16th Edition):

Kazmi, Saeed A. “Integrated injection logic alarm system.” 1976. Masters Thesis, Oregon State University. Accessed October 28, 2020. http://hdl.handle.net/1957/43395.

MLA Handbook (7th Edition):

Kazmi, Saeed A. “Integrated injection logic alarm system.” 1976. Web. 28 Oct 2020.

Vancouver:

Kazmi SA. Integrated injection logic alarm system. [Internet] [Masters thesis]. Oregon State University; 1976. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1957/43395.

Council of Science Editors:

Kazmi SA. Integrated injection logic alarm system. [Masters Thesis]. Oregon State University; 1976. Available from: http://hdl.handle.net/1957/43395


Oregon State University

27. Hoei, Jung-sheng. High accuracy CMOS switched-current ladder filters.

Degree: MS, Electrical and Computer Engineering, 1991, Oregon State University

 Clock-feedthrough effects, channel-length modulation and device mismatch are the main causes of the inaccuracy of Switched-Current (SI) circuits. In this paper, these non-ideal effects are… (more)

Subjects/Keywords: Switching circuits

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APA (6th Edition):

Hoei, J. (1991). High accuracy CMOS switched-current ladder filters. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/37000

Chicago Manual of Style (16th Edition):

Hoei, Jung-sheng. “High accuracy CMOS switched-current ladder filters.” 1991. Masters Thesis, Oregon State University. Accessed October 28, 2020. http://hdl.handle.net/1957/37000.

MLA Handbook (7th Edition):

Hoei, Jung-sheng. “High accuracy CMOS switched-current ladder filters.” 1991. Web. 28 Oct 2020.

Vancouver:

Hoei J. High accuracy CMOS switched-current ladder filters. [Internet] [Masters thesis]. Oregon State University; 1991. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1957/37000.

Council of Science Editors:

Hoei J. High accuracy CMOS switched-current ladder filters. [Masters Thesis]. Oregon State University; 1991. Available from: http://hdl.handle.net/1957/37000


Cornell University

28. Lee, Wooram. Nonlinear Circuits For Signal Generation And Processing In Cmos.

Degree: PhD, Electrical Engineering, 2012, Cornell University

 As Moore's law predicted, transistor scaling has continued unabated for more than half a century, resulting in significant improvement in speed, efficiency, and integration level.… (more)

Subjects/Keywords: Integrated Circuits; Nonlinear; cmos

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APA (6th Edition):

Lee, W. (2012). Nonlinear Circuits For Signal Generation And Processing In Cmos. (Doctoral Dissertation). Cornell University. Retrieved from http://hdl.handle.net/1813/31174

Chicago Manual of Style (16th Edition):

Lee, Wooram. “Nonlinear Circuits For Signal Generation And Processing In Cmos.” 2012. Doctoral Dissertation, Cornell University. Accessed October 28, 2020. http://hdl.handle.net/1813/31174.

MLA Handbook (7th Edition):

Lee, Wooram. “Nonlinear Circuits For Signal Generation And Processing In Cmos.” 2012. Web. 28 Oct 2020.

Vancouver:

Lee W. Nonlinear Circuits For Signal Generation And Processing In Cmos. [Internet] [Doctoral dissertation]. Cornell University; 2012. [cited 2020 Oct 28]. Available from: http://hdl.handle.net/1813/31174.

Council of Science Editors:

Lee W. Nonlinear Circuits For Signal Generation And Processing In Cmos. [Doctoral Dissertation]. Cornell University; 2012. Available from: http://hdl.handle.net/1813/31174


University College London (University of London)

29. Sehmbi, Jatinder Singh. The dynamics of friction oscillators.

Degree: PhD, 2001, University College London (University of London)

 The aim of this thesis is to investigate the nonsmooth dynamical behaviour of a mechanical system, which undergoes self-sustained oscillations and chaotic motion induced by… (more)

Subjects/Keywords: 621; Circuits

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APA (6th Edition):

Sehmbi, J. S. (2001). The dynamics of friction oscillators. (Doctoral Dissertation). University College London (University of London). Retrieved from https://discovery.ucl.ac.uk/id/eprint/10102282/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.248042

Chicago Manual of Style (16th Edition):

Sehmbi, Jatinder Singh. “The dynamics of friction oscillators.” 2001. Doctoral Dissertation, University College London (University of London). Accessed October 28, 2020. https://discovery.ucl.ac.uk/id/eprint/10102282/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.248042.

MLA Handbook (7th Edition):

Sehmbi, Jatinder Singh. “The dynamics of friction oscillators.” 2001. Web. 28 Oct 2020.

Vancouver:

Sehmbi JS. The dynamics of friction oscillators. [Internet] [Doctoral dissertation]. University College London (University of London); 2001. [cited 2020 Oct 28]. Available from: https://discovery.ucl.ac.uk/id/eprint/10102282/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.248042.

Council of Science Editors:

Sehmbi JS. The dynamics of friction oscillators. [Doctoral Dissertation]. University College London (University of London); 2001. Available from: https://discovery.ucl.ac.uk/id/eprint/10102282/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.248042


University College London (University of London)

30. Blake, Richard Spencer. Novel architectures for forward error control at very high bit rates.

Degree: PhD, 1997, University College London (University of London)

 This thesis is concerned with the design and assessment of novel architectures for the implementation of forward error correction (FEC) coding systems for very high… (more)

Subjects/Keywords: 621.3192; Circuits

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APA (6th Edition):

Blake, R. S. (1997). Novel architectures for forward error control at very high bit rates. (Doctoral Dissertation). University College London (University of London). Retrieved from https://discovery.ucl.ac.uk/id/eprint/10104542/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.267819

Chicago Manual of Style (16th Edition):

Blake, Richard Spencer. “Novel architectures for forward error control at very high bit rates.” 1997. Doctoral Dissertation, University College London (University of London). Accessed October 28, 2020. https://discovery.ucl.ac.uk/id/eprint/10104542/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.267819.

MLA Handbook (7th Edition):

Blake, Richard Spencer. “Novel architectures for forward error control at very high bit rates.” 1997. Web. 28 Oct 2020.

Vancouver:

Blake RS. Novel architectures for forward error control at very high bit rates. [Internet] [Doctoral dissertation]. University College London (University of London); 1997. [cited 2020 Oct 28]. Available from: https://discovery.ucl.ac.uk/id/eprint/10104542/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.267819.

Council of Science Editors:

Blake RS. Novel architectures for forward error control at very high bit rates. [Doctoral Dissertation]. University College London (University of London); 1997. Available from: https://discovery.ucl.ac.uk/id/eprint/10104542/ ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.267819

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