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You searched for subject:(Circuit Sizing). Showing records 1 – 16 of 16 total matches.

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Iowa State University

1. Sharma, Ankur. Lagrangian relaxation-based multi-threaded discrete gate sizer.

Degree: 2018, Iowa State University

 In integrated circuit design gate sizing is one of the key optimization techniques which is repeatedly invoked to trade-off delays for area and/or power of… (more)

Subjects/Keywords: Circuit optimization; Gate sizing; Lagrangian relaxation; Multithreading; Computer Engineering

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APA (6th Edition):

Sharma, A. (2018). Lagrangian relaxation-based multi-threaded discrete gate sizer. (Thesis). Iowa State University. Retrieved from https://lib.dr.iastate.edu/etd/16763

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sharma, Ankur. “Lagrangian relaxation-based multi-threaded discrete gate sizer.” 2018. Thesis, Iowa State University. Accessed January 20, 2021. https://lib.dr.iastate.edu/etd/16763.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sharma, Ankur. “Lagrangian relaxation-based multi-threaded discrete gate sizer.” 2018. Web. 20 Jan 2021.

Vancouver:

Sharma A. Lagrangian relaxation-based multi-threaded discrete gate sizer. [Internet] [Thesis]. Iowa State University; 2018. [cited 2021 Jan 20]. Available from: https://lib.dr.iastate.edu/etd/16763.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sharma A. Lagrangian relaxation-based multi-threaded discrete gate sizer. [Thesis]. Iowa State University; 2018. Available from: https://lib.dr.iastate.edu/etd/16763

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

2. Chiasson, Charles. Optimization and Modeling of FPGA Circuitry in Advanced Process Technology.

Degree: 2013, University of Toronto

We develop a new fully-automated transistor sizing tool for FPGAs that features area, delay and wire load modeling enhancements over prior work to improve its… (more)

Subjects/Keywords: FPGA; circuit design; advanced process technology; optimization; modeling; transistor sizing; transmission gate FPGA; 0544

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APA (6th Edition):

Chiasson, C. (2013). Optimization and Modeling of FPGA Circuitry in Advanced Process Technology. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/42733

Chicago Manual of Style (16th Edition):

Chiasson, Charles. “Optimization and Modeling of FPGA Circuitry in Advanced Process Technology.” 2013. Masters Thesis, University of Toronto. Accessed January 20, 2021. http://hdl.handle.net/1807/42733.

MLA Handbook (7th Edition):

Chiasson, Charles. “Optimization and Modeling of FPGA Circuitry in Advanced Process Technology.” 2013. Web. 20 Jan 2021.

Vancouver:

Chiasson C. Optimization and Modeling of FPGA Circuitry in Advanced Process Technology. [Internet] [Masters thesis]. University of Toronto; 2013. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/1807/42733.

Council of Science Editors:

Chiasson C. Optimization and Modeling of FPGA Circuitry in Advanced Process Technology. [Masters Thesis]. University of Toronto; 2013. Available from: http://hdl.handle.net/1807/42733


UCLA

3. Conos, Nathaniel Alcala. Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques.

Degree: Computer Science, 2014, UCLA

 Energy minimization is one of the premiere design objectives in modern inte-grated circuits (ICs). Currently, there is a pressing need to reduce energy con-sumption in… (more)

Subjects/Keywords: Computer science; Computer engineering; Dynamic Voltage Scaling; Energy Minimization; Gate Sizing; Integrated Circuit Synthesis; Power Gating; Threshold Voltage Selection

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APA (6th Edition):

Conos, N. A. (2014). Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/0m13d0wq

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Conos, Nathaniel Alcala. “Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques.” 2014. Thesis, UCLA. Accessed January 20, 2021. http://www.escholarship.org/uc/item/0m13d0wq.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Conos, Nathaniel Alcala. “Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques.” 2014. Web. 20 Jan 2021.

Vancouver:

Conos NA. Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques. [Internet] [Thesis]. UCLA; 2014. [cited 2021 Jan 20]. Available from: http://www.escholarship.org/uc/item/0m13d0wq.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Conos NA. Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques. [Thesis]. UCLA; 2014. Available from: http://www.escholarship.org/uc/item/0m13d0wq

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. Huang, Yi-Le. An Improved Lagrangian Relaxation Method for VLSI Combinational Circuit Optimization.

Degree: MS, Electrical Engineering, 2012, Texas A&M University

 Gate sizing and threshold voltage (Vt) assignment are very popular and useful techniques in current very large scale integration (VLSI) design flow for timing and… (more)

Subjects/Keywords: VLSI; gate sizing; circuit optimization; low power

…total chip area subject to circuit timing constraints. Gate sizing [1] is one of the… …power becomes the dominant concern as we try to combat the increase in the overall circuit… …circuit performance and power consumption becomes a big issue in current design flow. In the… …for circuit designs. In recent years, leakage power becomes more and more important due to… …leakage power and try to optimize combinational circuit for leakage power reduction by using… 

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APA (6th Edition):

Huang, Y. (2012). An Improved Lagrangian Relaxation Method for VLSI Combinational Circuit Optimization. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8684

Chicago Manual of Style (16th Edition):

Huang, Yi-Le. “An Improved Lagrangian Relaxation Method for VLSI Combinational Circuit Optimization.” 2012. Masters Thesis, Texas A&M University. Accessed January 20, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8684.

MLA Handbook (7th Edition):

Huang, Yi-Le. “An Improved Lagrangian Relaxation Method for VLSI Combinational Circuit Optimization.” 2012. Web. 20 Jan 2021.

Vancouver:

Huang Y. An Improved Lagrangian Relaxation Method for VLSI Combinational Circuit Optimization. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8684.

Council of Science Editors:

Huang Y. An Improved Lagrangian Relaxation Method for VLSI Combinational Circuit Optimization. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8684


University of Texas – Austin

5. Lok, Mario Chichun. Process variation aware low power buffer design.

Degree: MSin Engineering, Electrical and Computer Engineering, 2010, University of Texas – Austin

 In many digital designs there is a need to use multi-stage tapered buffers to drive large capacitive loads. These buffers contribute a significant percentage of… (more)

Subjects/Keywords: Low power design; Adaptive circuit; Statistical sizing; Tunable circuit; Adaptable optimization

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APA (6th Edition):

Lok, M. C. (2010). Process variation aware low power buffer design. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/ETD-UT-2010-05-1167

Chicago Manual of Style (16th Edition):

Lok, Mario Chichun. “Process variation aware low power buffer design.” 2010. Masters Thesis, University of Texas – Austin. Accessed January 20, 2021. http://hdl.handle.net/2152/ETD-UT-2010-05-1167.

MLA Handbook (7th Edition):

Lok, Mario Chichun. “Process variation aware low power buffer design.” 2010. Web. 20 Jan 2021.

Vancouver:

Lok MC. Process variation aware low power buffer design. [Internet] [Masters thesis]. University of Texas – Austin; 2010. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/2152/ETD-UT-2010-05-1167.

Council of Science Editors:

Lok MC. Process variation aware low power buffer design. [Masters Thesis]. University of Texas – Austin; 2010. Available from: http://hdl.handle.net/2152/ETD-UT-2010-05-1167


University of Michigan

6. Gao, Feng. Gate-level techniques for low power and reliable circuit design.

Degree: PhD, Electrical engineering, 2005, University of Michigan

 The continuous scaling down of transistor feature size poses several challenges to integrated circuit (IC) design. First, both dynamic and leakage power consumption keep increasing.… (more)

Subjects/Keywords: Circuit; Design; Gate Sizing; Level; Low; Power Consumption; Reliable; Techniques

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APA (6th Edition):

Gao, F. (2005). Gate-level techniques for low power and reliable circuit design. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/125363

Chicago Manual of Style (16th Edition):

Gao, Feng. “Gate-level techniques for low power and reliable circuit design.” 2005. Doctoral Dissertation, University of Michigan. Accessed January 20, 2021. http://hdl.handle.net/2027.42/125363.

MLA Handbook (7th Edition):

Gao, Feng. “Gate-level techniques for low power and reliable circuit design.” 2005. Web. 20 Jan 2021.

Vancouver:

Gao F. Gate-level techniques for low power and reliable circuit design. [Internet] [Doctoral dissertation]. University of Michigan; 2005. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/2027.42/125363.

Council of Science Editors:

Gao F. Gate-level techniques for low power and reliable circuit design. [Doctoral Dissertation]. University of Michigan; 2005. Available from: http://hdl.handle.net/2027.42/125363


Georgia Tech

7. Dhillon, Yuvraj Singh. Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability.

Degree: PhD, Electrical and Computer Engineering, 2005, Georgia Tech

 Power consumption and soft-error tolerance have become major constraints in the design of DSM CMOS circuits. With continued technology scaling, the impact of these parameters… (more)

Subjects/Keywords: Dual threshold voltages; Multiple supply voltages; Low-power; Sizing; Circuit optimization; Soft error

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APA (6th Edition):

Dhillon, Y. S. (2005). Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/6935

Chicago Manual of Style (16th Edition):

Dhillon, Yuvraj Singh. “Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability.” 2005. Doctoral Dissertation, Georgia Tech. Accessed January 20, 2021. http://hdl.handle.net/1853/6935.

MLA Handbook (7th Edition):

Dhillon, Yuvraj Singh. “Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability.” 2005. Web. 20 Jan 2021.

Vancouver:

Dhillon YS. Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability. [Internet] [Doctoral dissertation]. Georgia Tech; 2005. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/1853/6935.

Council of Science Editors:

Dhillon YS. Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability. [Doctoral Dissertation]. Georgia Tech; 2005. Available from: http://hdl.handle.net/1853/6935


University of Cincinnati

8. DING, MENGMENG. REGRESSION BASED ANALOG PERFORMANCE MACROMODELING: TECHNIQUES AND APPLICATIONS.

Degree: PhD, Engineering : Computer Science and Engineering, 2006, University of Cincinnati

 Optimization based analog circuit sizing opens a new page for computer aided design of analog integrated circuits. While differing in implementation details, the sizing tools… (more)

Subjects/Keywords: analog performance macromodeling; analog circuit sizing; adaptive sampling; active learning; regression; classification

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APA (6th Edition):

DING, M. (2006). REGRESSION BASED ANALOG PERFORMANCE MACROMODELING: TECHNIQUES AND APPLICATIONS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1146145102

Chicago Manual of Style (16th Edition):

DING, MENGMENG. “REGRESSION BASED ANALOG PERFORMANCE MACROMODELING: TECHNIQUES AND APPLICATIONS.” 2006. Doctoral Dissertation, University of Cincinnati. Accessed January 20, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1146145102.

MLA Handbook (7th Edition):

DING, MENGMENG. “REGRESSION BASED ANALOG PERFORMANCE MACROMODELING: TECHNIQUES AND APPLICATIONS.” 2006. Web. 20 Jan 2021.

Vancouver:

DING M. REGRESSION BASED ANALOG PERFORMANCE MACROMODELING: TECHNIQUES AND APPLICATIONS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2006. [cited 2021 Jan 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1146145102.

Council of Science Editors:

DING M. REGRESSION BASED ANALOG PERFORMANCE MACROMODELING: TECHNIQUES AND APPLICATIONS. [Doctoral Dissertation]. University of Cincinnati; 2006. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1146145102


University of Cincinnati

9. AGARWAL, ANURADHA. ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS.

Degree: PhD, Engineering : Computer Science and Engineering, 2005, University of Cincinnati

 With the ever increasing complexity of integrated circuits and constantly shrinking device sizes, the need to develop entire dystems on chip (SoC) has received a… (more)

Subjects/Keywords: Analog; Radio-frequency; Circuit Synthesis; Layout Parasitics; Performance Modeling; Parasitic Estimation and Modeling; Layout-Aware Synthesis; Circuit sizing; Parasitic Corners; Yield Optimization; Parasitic Capacitances; Dynamic Performance Macromodel

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APA (6th Edition):

AGARWAL, A. (2005). ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454

Chicago Manual of Style (16th Edition):

AGARWAL, ANURADHA. “ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS.” 2005. Doctoral Dissertation, University of Cincinnati. Accessed January 20, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454.

MLA Handbook (7th Edition):

AGARWAL, ANURADHA. “ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS.” 2005. Web. 20 Jan 2021.

Vancouver:

AGARWAL A. ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2005. [cited 2021 Jan 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454.

Council of Science Editors:

AGARWAL A. ALGORITHMS FOR LAYOUT-AWARE AND PERFORMANCE MODEL DRIVEN SYNTHESIS OF ANALOG CIRCUITS. [Doctoral Dissertation]. University of Cincinnati; 2005. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132259454


Université de Bordeaux I

10. Nguyen, Huy Cuong. Modélisation électrothermique de système électrique électronique automobile et pilotage de mosfet intelligents pour protéger les faisceaux, éviter les courts circuits aggravés et diminuer la masse de câblage : The experience of the visit and construction of knowledge : the case of science museums and scientific cultural centers.

Degree: Docteur es, Automatique et productique, signal et image, 2013, Université de Bordeaux I

Sur les différents calculateurs du véhicule, de plus en plus d'organes sont commandés par un interrupteur en silicium (circuit MOSFET) au lieu d'un relais. En… (more)

Subjects/Keywords: Mosfet; Câblage; Modélisation électrothermique; Protection; Court-circuits; Dérivation non-entière; Estimateurs; Dimensionnement de système électrique; Electronique automobile; Contrôle/commande; Electrothermique; Fusibles; Mosfet; Harness; Thermal electrical modeling; Protection; Short circuit; Estimation; Fractional derivative; Sizing electric; Car electronic system; Control; Smart fuse; Mosfet

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APA (6th Edition):

Nguyen, H. C. (2013). Modélisation électrothermique de système électrique électronique automobile et pilotage de mosfet intelligents pour protéger les faisceaux, éviter les courts circuits aggravés et diminuer la masse de câblage : The experience of the visit and construction of knowledge : the case of science museums and scientific cultural centers. (Doctoral Dissertation). Université de Bordeaux I. Retrieved from http://www.theses.fr/2013BOR14776

Chicago Manual of Style (16th Edition):

Nguyen, Huy Cuong. “Modélisation électrothermique de système électrique électronique automobile et pilotage de mosfet intelligents pour protéger les faisceaux, éviter les courts circuits aggravés et diminuer la masse de câblage : The experience of the visit and construction of knowledge : the case of science museums and scientific cultural centers.” 2013. Doctoral Dissertation, Université de Bordeaux I. Accessed January 20, 2021. http://www.theses.fr/2013BOR14776.

MLA Handbook (7th Edition):

Nguyen, Huy Cuong. “Modélisation électrothermique de système électrique électronique automobile et pilotage de mosfet intelligents pour protéger les faisceaux, éviter les courts circuits aggravés et diminuer la masse de câblage : The experience of the visit and construction of knowledge : the case of science museums and scientific cultural centers.” 2013. Web. 20 Jan 2021.

Vancouver:

Nguyen HC. Modélisation électrothermique de système électrique électronique automobile et pilotage de mosfet intelligents pour protéger les faisceaux, éviter les courts circuits aggravés et diminuer la masse de câblage : The experience of the visit and construction of knowledge : the case of science museums and scientific cultural centers. [Internet] [Doctoral dissertation]. Université de Bordeaux I; 2013. [cited 2021 Jan 20]. Available from: http://www.theses.fr/2013BOR14776.

Council of Science Editors:

Nguyen HC. Modélisation électrothermique de système électrique électronique automobile et pilotage de mosfet intelligents pour protéger les faisceaux, éviter les courts circuits aggravés et diminuer la masse de câblage : The experience of the visit and construction of knowledge : the case of science museums and scientific cultural centers. [Doctoral Dissertation]. Université de Bordeaux I; 2013. Available from: http://www.theses.fr/2013BOR14776

11. Xie, Jiani. Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization.

Degree: PhD, Electrical Engineering and Computer Science, 2014, Syracuse University

  The modeling of an individual gate and the optimization of circuit performance has long been a critical issue in the VLSI industry. In this… (more)

Subjects/Keywords: Circuit optimization; Delay minimization; Discrete gate sizing; Gate and delay model; Power optimization; Engineering

…3 Table 2. 1. Minimum Circuit Delay comparison of discrete sizing algorithm (DS)… …improving circuit performance. Researchers have been working on the gate sizing problems for more… …sizing problem, including the models that researchers have applied for circuit performance… …circuit delay, layout area or power consumption, etc. Gate sizing is a flexible and powerful… …circuit has been efficient in solving sizing problems, especially for continuous gate sizing… 

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APA (6th Edition):

Xie, J. (2014). Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization. (Doctoral Dissertation). Syracuse University. Retrieved from https://surface.syr.edu/etd/201

Chicago Manual of Style (16th Edition):

Xie, Jiani. “Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization.” 2014. Doctoral Dissertation, Syracuse University. Accessed January 20, 2021. https://surface.syr.edu/etd/201.

MLA Handbook (7th Edition):

Xie, Jiani. “Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization.” 2014. Web. 20 Jan 2021.

Vancouver:

Xie J. Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization. [Internet] [Doctoral dissertation]. Syracuse University; 2014. [cited 2021 Jan 20]. Available from: https://surface.syr.edu/etd/201.

Council of Science Editors:

Xie J. Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization. [Doctoral Dissertation]. Syracuse University; 2014. Available from: https://surface.syr.edu/etd/201

12. Jug, Marjan. Analiza internega omrežja podjetja unior ter rekonstrukcija transformatorske postaje TP UNIOR 1.

Degree: 2020, Univerza v Mariboru

Magistrska naloga prikazuje analizo kratkostičnih razmer industrijske cone UNIOR-ja v Zrečah pri različnih obratovalnih razmerah ter izdelavo rekonstrukcije transformatorske postaje TP UNIOR 1. V prvem… (more)

Subjects/Keywords: Elektroenergetsko omrežje; transformatorska postaja; stikališče; NEPLAN,kratki stik; dimenzioniranje opreme; izbira stikalne opreme; Power network; transformer substation; substation; NEPLAN; short circuit; sizing and selecting switchgear.; info:eu-repo/classification/udc/621.311.42.064(043.2)

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APA (6th Edition):

Jug, M. (2020). Analiza internega omrežja podjetja unior ter rekonstrukcija transformatorske postaje TP UNIOR 1. (Masters Thesis). Univerza v Mariboru. Retrieved from https://dk.um.si/IzpisGradiva.php?id=76634 ; https://dk.um.si/Dokument.php?id=143192&dn= ; https://plus.si.cobiss.net/opac7/bib/27340291?lang=sl

Chicago Manual of Style (16th Edition):

Jug, Marjan. “Analiza internega omrežja podjetja unior ter rekonstrukcija transformatorske postaje TP UNIOR 1.” 2020. Masters Thesis, Univerza v Mariboru. Accessed January 20, 2021. https://dk.um.si/IzpisGradiva.php?id=76634 ; https://dk.um.si/Dokument.php?id=143192&dn= ; https://plus.si.cobiss.net/opac7/bib/27340291?lang=sl.

MLA Handbook (7th Edition):

Jug, Marjan. “Analiza internega omrežja podjetja unior ter rekonstrukcija transformatorske postaje TP UNIOR 1.” 2020. Web. 20 Jan 2021.

Vancouver:

Jug M. Analiza internega omrežja podjetja unior ter rekonstrukcija transformatorske postaje TP UNIOR 1. [Internet] [Masters thesis]. Univerza v Mariboru; 2020. [cited 2021 Jan 20]. Available from: https://dk.um.si/IzpisGradiva.php?id=76634 ; https://dk.um.si/Dokument.php?id=143192&dn= ; https://plus.si.cobiss.net/opac7/bib/27340291?lang=sl.

Council of Science Editors:

Jug M. Analiza internega omrežja podjetja unior ter rekonstrukcija transformatorske postaje TP UNIOR 1. [Masters Thesis]. Univerza v Mariboru; 2020. Available from: https://dk.um.si/IzpisGradiva.php?id=76634 ; https://dk.um.si/Dokument.php?id=143192&dn= ; https://plus.si.cobiss.net/opac7/bib/27340291?lang=sl


University of South Florida

13. Venkataraman, Mahalingam. Techniques for VLSI Circuit Optimization Considering Process Variations.

Degree: 2009, University of South Florida

 Technology scaling has increased the transistor's susceptibility to process variations in nanometer very large scale integrated (VLSI) circuits. The effects of such variations are having… (more)

Subjects/Keywords: Variation Awareness; Circuit Design; Gate Sizing; Incremental Timing Placement; Buffer Insertion; Clock Stretching; Fuzzy Programming; Logic Level; Layout Level; American Studies; Arts and Humanities

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APA (6th Edition):

Venkataraman, M. (2009). Techniques for VLSI Circuit Optimization Considering Process Variations. (Thesis). University of South Florida. Retrieved from https://scholarcommons.usf.edu/etd/66

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Venkataraman, Mahalingam. “Techniques for VLSI Circuit Optimization Considering Process Variations.” 2009. Thesis, University of South Florida. Accessed January 20, 2021. https://scholarcommons.usf.edu/etd/66.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Venkataraman, Mahalingam. “Techniques for VLSI Circuit Optimization Considering Process Variations.” 2009. Web. 20 Jan 2021.

Vancouver:

Venkataraman M. Techniques for VLSI Circuit Optimization Considering Process Variations. [Internet] [Thesis]. University of South Florida; 2009. [cited 2021 Jan 20]. Available from: https://scholarcommons.usf.edu/etd/66.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Venkataraman M. Techniques for VLSI Circuit Optimization Considering Process Variations. [Thesis]. University of South Florida; 2009. Available from: https://scholarcommons.usf.edu/etd/66

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

14. Mukherjee, Souvik. Layout-level Circuit Sizing and Design-for-manufacturability Methods for Embedded RF Passive Circuits.

Degree: PhD, Electrical and Computer Engineering, 2007, Georgia Tech

 The emergence of multi-band communications standards, and the fast pace of the consumer electronics markets for wireless/cellular applications emphasize the need for fast design closure.… (more)

Subjects/Keywords: Layout-level; Circuit sizing; Liquid crystalline polymer; Design-for-manufacturability; Yield optimization; Statistical analysis; Radio frequency integrated circuits Design and construction; Mathematical optimization; Manufacturing processes; Electronic circuits Design and construction

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APA (6th Edition):

Mukherjee, S. (2007). Layout-level Circuit Sizing and Design-for-manufacturability Methods for Embedded RF Passive Circuits. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/16131

Chicago Manual of Style (16th Edition):

Mukherjee, Souvik. “Layout-level Circuit Sizing and Design-for-manufacturability Methods for Embedded RF Passive Circuits.” 2007. Doctoral Dissertation, Georgia Tech. Accessed January 20, 2021. http://hdl.handle.net/1853/16131.

MLA Handbook (7th Edition):

Mukherjee, Souvik. “Layout-level Circuit Sizing and Design-for-manufacturability Methods for Embedded RF Passive Circuits.” 2007. Web. 20 Jan 2021.

Vancouver:

Mukherjee S. Layout-level Circuit Sizing and Design-for-manufacturability Methods for Embedded RF Passive Circuits. [Internet] [Doctoral dissertation]. Georgia Tech; 2007. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/1853/16131.

Council of Science Editors:

Mukherjee S. Layout-level Circuit Sizing and Design-for-manufacturability Methods for Embedded RF Passive Circuits. [Doctoral Dissertation]. Georgia Tech; 2007. Available from: http://hdl.handle.net/1853/16131


University of Cincinnati

15. VIJAY, VIKAS. A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS.

Degree: MS, Engineering : Computer Engineering, 2004, University of Cincinnati

 This thesis presents automated techniques for synthesis of high performance RF circuits. The top-down methodology developed encompasses all stages of RF design from circuit sizing,… (more)

Subjects/Keywords: Radio Frequency; Synthesis; Optimization; Automation; Layout Generation; RF; Analog; High Frequency; Module Generation; C++; SKILL; Extraction; Performance Analysis; Circuit Sizing; Radio Receiver; LNA; Mixer; VCO; Phase Frequency Detector

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APA (6th Edition):

VIJAY, V. (2004). A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283

Chicago Manual of Style (16th Edition):

VIJAY, VIKAS. “A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS.” 2004. Masters Thesis, University of Cincinnati. Accessed January 20, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283.

MLA Handbook (7th Edition):

VIJAY, VIKAS. “A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS.” 2004. Web. 20 Jan 2021.

Vancouver:

VIJAY V. A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS. [Internet] [Masters thesis]. University of Cincinnati; 2004. [cited 2021 Jan 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283.

Council of Science Editors:

VIJAY V. A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS. [Masters Thesis]. University of Cincinnati; 2004. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283

16. Rafiq, Moosa. Velocity control of single-rod hydrostatic actuators: component sizing and controller design.

Degree: Mechanical Engineering, 2018, University of Manitoba

 Pump-controlled hydraulic actuation of single-rod actuators is more challenging than double-rod actuators due to difference in areas on two sides of single-rod actuators and a… (more)

Subjects/Keywords: Hydraulic circuit; Optimization; Optimisation; Parameter; Control; Pilot operated check valve; Counterbalance valve; Valve; PSO; MNM; Nelder; Ten parameters; Hydrostatic; Pump; Pump Control; Algorithm; Simulation; Experiment; Cracking pressure; Optimal; Novel; Design; Methodology; Criteria; Particle; Swarm; Hydraulic design; Optimal design; Validation; Component sizing; Sizing; Sizing hydraulic circuits; Monika; Vibrations; Undesirable region; Multistep; Multistep polynomial; Single rod; Double rod; Single-rod; Double-rod; QFT; Quantitative Feedback Theory; Velocity control; Velocity; Component; Hydraulic component; Jerk; Objective; Objective function; ten parameter; Quadrants; System identification; Chirp; Chirp signal; Transfer function; Uncertainities; Feedback; Frequency; Gain margin; Phase margin

…system; (b) single-rod system....... 5 Figure 2.2 Hydraulic circuit configurations… …x28;a) hydraulic circuit using 3-way 2-position shuttle valve; (b) hydraulic… …circuit using 3-way 3-position shuttle valve with two regulating valves; (c) two pump… …control of a single-rod actuator shown; (d) hydraulic circuit using pilot check… …operated valves; (e) hydraulic circuit using counterbalance valves… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rafiq, M. (2018). Velocity control of single-rod hydrostatic actuators: component sizing and controller design. (Masters Thesis). University of Manitoba. Retrieved from http://hdl.handle.net/1993/32886

Chicago Manual of Style (16th Edition):

Rafiq, Moosa. “Velocity control of single-rod hydrostatic actuators: component sizing and controller design.” 2018. Masters Thesis, University of Manitoba. Accessed January 20, 2021. http://hdl.handle.net/1993/32886.

MLA Handbook (7th Edition):

Rafiq, Moosa. “Velocity control of single-rod hydrostatic actuators: component sizing and controller design.” 2018. Web. 20 Jan 2021.

Vancouver:

Rafiq M. Velocity control of single-rod hydrostatic actuators: component sizing and controller design. [Internet] [Masters thesis]. University of Manitoba; 2018. [cited 2021 Jan 20]. Available from: http://hdl.handle.net/1993/32886.

Council of Science Editors:

Rafiq M. Velocity control of single-rod hydrostatic actuators: component sizing and controller design. [Masters Thesis]. University of Manitoba; 2018. Available from: http://hdl.handle.net/1993/32886

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