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You searched for subject:(Chip to chip). Showing records 1 – 30 of 43 total matches.

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University of Arizona

1. Baniya, Prabhat. Switched-Beam 60 GHz Endfire Circular Patch Planar Array With Integrated 2-D Butler Matrix for Chip-to-Chip Space-Surface Wave Communications .

Degree: 2019, University of Arizona

 The complexity of chip interconnection on a multicore multichip (MCMC) module using the traditional wired interconnects increases with the chip count. The global wired interconnects… (more)

Subjects/Keywords: antenna; Butler; chip-to-chip; endfire; surface; switched-beam

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APA (6th Edition):

Baniya, P. (2019). Switched-Beam 60 GHz Endfire Circular Patch Planar Array With Integrated 2-D Butler Matrix for Chip-to-Chip Space-Surface Wave Communications . (Doctoral Dissertation). University of Arizona. Retrieved from http://hdl.handle.net/10150/633157

Chicago Manual of Style (16th Edition):

Baniya, Prabhat. “Switched-Beam 60 GHz Endfire Circular Patch Planar Array With Integrated 2-D Butler Matrix for Chip-to-Chip Space-Surface Wave Communications .” 2019. Doctoral Dissertation, University of Arizona. Accessed February 29, 2020. http://hdl.handle.net/10150/633157.

MLA Handbook (7th Edition):

Baniya, Prabhat. “Switched-Beam 60 GHz Endfire Circular Patch Planar Array With Integrated 2-D Butler Matrix for Chip-to-Chip Space-Surface Wave Communications .” 2019. Web. 29 Feb 2020.

Vancouver:

Baniya P. Switched-Beam 60 GHz Endfire Circular Patch Planar Array With Integrated 2-D Butler Matrix for Chip-to-Chip Space-Surface Wave Communications . [Internet] [Doctoral dissertation]. University of Arizona; 2019. [cited 2020 Feb 29]. Available from: http://hdl.handle.net/10150/633157.

Council of Science Editors:

Baniya P. Switched-Beam 60 GHz Endfire Circular Patch Planar Array With Integrated 2-D Butler Matrix for Chip-to-Chip Space-Surface Wave Communications . [Doctoral Dissertation]. University of Arizona; 2019. Available from: http://hdl.handle.net/10150/633157


New Jersey Institute of Technology

2. Kim, Hansin. Micro pipes – a portable integrated platform for electrochemical sensing using essence architecture.

Degree: MSin Biomedical Engineering - (M.S.), Biomedical Engineering, 2019, New Jersey Institute of Technology

  The field of microfluidics and lab-on-chip (LOC) technology has the potential to have a truly transformative effect in biological engineering. This includes areas such… (more)

Subjects/Keywords: Chip-to-world interface; Improved integration; Lab-on-chip; Biomedical Engineering and Bioengineering

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APA (6th Edition):

Kim, H. (2019). Micro pipes – a portable integrated platform for electrochemical sensing using essence architecture. (Thesis). New Jersey Institute of Technology. Retrieved from https://digitalcommons.njit.edu/theses/1741

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kim, Hansin. “Micro pipes – a portable integrated platform for electrochemical sensing using essence architecture.” 2019. Thesis, New Jersey Institute of Technology. Accessed February 29, 2020. https://digitalcommons.njit.edu/theses/1741.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kim, Hansin. “Micro pipes – a portable integrated platform for electrochemical sensing using essence architecture.” 2019. Web. 29 Feb 2020.

Vancouver:

Kim H. Micro pipes – a portable integrated platform for electrochemical sensing using essence architecture. [Internet] [Thesis]. New Jersey Institute of Technology; 2019. [cited 2020 Feb 29]. Available from: https://digitalcommons.njit.edu/theses/1741.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim H. Micro pipes – a portable integrated platform for electrochemical sensing using essence architecture. [Thesis]. New Jersey Institute of Technology; 2019. Available from: https://digitalcommons.njit.edu/theses/1741

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

3. Yasotharan, Sanjesh. A Microfluidic Platform for the Automated Multimodal Assessment of Small Artery Structure and Function.

Degree: 2012, University of Toronto

In this thesis, I present a microfluidic platform that enables automated image-based assessment of biological structure and function. My work focuses on assessing intact resistance… (more)

Subjects/Keywords: Microfluidics; Resistance Artery; Automation; World to chip interconnect; 0548; 0541

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APA (6th Edition):

Yasotharan, S. (2012). A Microfluidic Platform for the Automated Multimodal Assessment of Small Artery Structure and Function. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/32504

Chicago Manual of Style (16th Edition):

Yasotharan, Sanjesh. “A Microfluidic Platform for the Automated Multimodal Assessment of Small Artery Structure and Function.” 2012. Masters Thesis, University of Toronto. Accessed February 29, 2020. http://hdl.handle.net/1807/32504.

MLA Handbook (7th Edition):

Yasotharan, Sanjesh. “A Microfluidic Platform for the Automated Multimodal Assessment of Small Artery Structure and Function.” 2012. Web. 29 Feb 2020.

Vancouver:

Yasotharan S. A Microfluidic Platform for the Automated Multimodal Assessment of Small Artery Structure and Function. [Internet] [Masters thesis]. University of Toronto; 2012. [cited 2020 Feb 29]. Available from: http://hdl.handle.net/1807/32504.

Council of Science Editors:

Yasotharan S. A Microfluidic Platform for the Automated Multimodal Assessment of Small Artery Structure and Function. [Masters Thesis]. University of Toronto; 2012. Available from: http://hdl.handle.net/1807/32504


University of Toronto

4. Goldvasser, Pavel. Identification of Novel Notch Target Genes in Breast Cancer.

Degree: 2011, University of Toronto

Notch signaling plays a key role in development, tissue homeostasis, and cancer. High expression levels of Notch signaling components are associated with aggressive disease and… (more)

Subjects/Keywords: Notch; HGF-MET; breast cancer; basal-like subtype; epithelial-to-mesenchymal transition; ChIP-on-chip; expression array analysis; 0760

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APA (6th Edition):

Goldvasser, P. (2011). Identification of Novel Notch Target Genes in Breast Cancer. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/30607

Chicago Manual of Style (16th Edition):

Goldvasser, Pavel. “Identification of Novel Notch Target Genes in Breast Cancer.” 2011. Masters Thesis, University of Toronto. Accessed February 29, 2020. http://hdl.handle.net/1807/30607.

MLA Handbook (7th Edition):

Goldvasser, Pavel. “Identification of Novel Notch Target Genes in Breast Cancer.” 2011. Web. 29 Feb 2020.

Vancouver:

Goldvasser P. Identification of Novel Notch Target Genes in Breast Cancer. [Internet] [Masters thesis]. University of Toronto; 2011. [cited 2020 Feb 29]. Available from: http://hdl.handle.net/1807/30607.

Council of Science Editors:

Goldvasser P. Identification of Novel Notch Target Genes in Breast Cancer. [Masters Thesis]. University of Toronto; 2011. Available from: http://hdl.handle.net/1807/30607


Georgia Tech

5. Kim, Seunghwan. THz device-to-device communications: Channel measurements, modelling, simulation, and antenna design.

Degree: PhD, Electrical and Computer Engineering, 2016, Georgia Tech

 As the demand for smaller devices that can offer higher speed wireless communication any time and anywhere is growing relentlessly, the need for higher frequency… (more)

Subjects/Keywords: THz communications; Channel measurement; Channel characterization; Statistical channel modeling; THz antennas; Chip-to-chip wireless channels

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APA (6th Edition):

Kim, S. (2016). THz device-to-device communications: Channel measurements, modelling, simulation, and antenna design. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56324

Chicago Manual of Style (16th Edition):

Kim, Seunghwan. “THz device-to-device communications: Channel measurements, modelling, simulation, and antenna design.” 2016. Doctoral Dissertation, Georgia Tech. Accessed February 29, 2020. http://hdl.handle.net/1853/56324.

MLA Handbook (7th Edition):

Kim, Seunghwan. “THz device-to-device communications: Channel measurements, modelling, simulation, and antenna design.” 2016. Web. 29 Feb 2020.

Vancouver:

Kim S. THz device-to-device communications: Channel measurements, modelling, simulation, and antenna design. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2020 Feb 29]. Available from: http://hdl.handle.net/1853/56324.

Council of Science Editors:

Kim S. THz device-to-device communications: Channel measurements, modelling, simulation, and antenna design. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56324


Rochester Institute of Technology

6. Saxena, Sagar. A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band.

Degree: MS, Computer Engineering, 2017, Rochester Institute of Technology

  Network-on-Chips (NoCs) have emerged as a communication infrastructure for the multi-core System-on-Chips (SoCs). Despite its advantages, due to the multi-hop communication over the metal… (more)

Subjects/Keywords: Chip-to-chip communication; Graphene-based THz-band antennas; Multichip system; Phase based communication protocol; Terahertz band communication; Wireless network-on-chip

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APA (6th Edition):

Saxena, S. (2017). A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/9628

Chicago Manual of Style (16th Edition):

Saxena, Sagar. “A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band.” 2017. Masters Thesis, Rochester Institute of Technology. Accessed February 29, 2020. https://scholarworks.rit.edu/theses/9628.

MLA Handbook (7th Edition):

Saxena, Sagar. “A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band.” 2017. Web. 29 Feb 2020.

Vancouver:

Saxena S. A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band. [Internet] [Masters thesis]. Rochester Institute of Technology; 2017. [cited 2020 Feb 29]. Available from: https://scholarworks.rit.edu/theses/9628.

Council of Science Editors:

Saxena S. A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band. [Masters Thesis]. Rochester Institute of Technology; 2017. Available from: https://scholarworks.rit.edu/theses/9628


Louisiana State University

7. Brown, Christopher Ramsey. A Parametric Investigation of a Novel, Modular, Gasketless, Microfluidic Interconnect Using Parallel Superhydrophobic Surfaces.

Degree: MSME, Mechanical Engineering, 2014, Louisiana State University

 The gasketless microfluidic interconnect has the potential to offer a standardized approach to interconnects between modular microfluidic components. This strategy uses parallel superhydrophobic surfaces (contact… (more)

Subjects/Keywords: microfluidics; fluid interconnect; chip-to-chip; world-to-chip; lab-on-a-chip; modular; meniscus stability; surface tension; surface energy; Laplace force; capillary forces; superhydrophobicity; applications of superhydrophobic surfaces; injection molding

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APA (6th Edition):

Brown, C. R. (2014). A Parametric Investigation of a Novel, Modular, Gasketless, Microfluidic Interconnect Using Parallel Superhydrophobic Surfaces. (Masters Thesis). Louisiana State University. Retrieved from etd-03312014-105753 ; https://digitalcommons.lsu.edu/gradschool_theses/1139

Chicago Manual of Style (16th Edition):

Brown, Christopher Ramsey. “A Parametric Investigation of a Novel, Modular, Gasketless, Microfluidic Interconnect Using Parallel Superhydrophobic Surfaces.” 2014. Masters Thesis, Louisiana State University. Accessed February 29, 2020. etd-03312014-105753 ; https://digitalcommons.lsu.edu/gradschool_theses/1139.

MLA Handbook (7th Edition):

Brown, Christopher Ramsey. “A Parametric Investigation of a Novel, Modular, Gasketless, Microfluidic Interconnect Using Parallel Superhydrophobic Surfaces.” 2014. Web. 29 Feb 2020.

Vancouver:

Brown CR. A Parametric Investigation of a Novel, Modular, Gasketless, Microfluidic Interconnect Using Parallel Superhydrophobic Surfaces. [Internet] [Masters thesis]. Louisiana State University; 2014. [cited 2020 Feb 29]. Available from: etd-03312014-105753 ; https://digitalcommons.lsu.edu/gradschool_theses/1139.

Council of Science Editors:

Brown CR. A Parametric Investigation of a Novel, Modular, Gasketless, Microfluidic Interconnect Using Parallel Superhydrophobic Surfaces. [Masters Thesis]. Louisiana State University; 2014. Available from: etd-03312014-105753 ; https://digitalcommons.lsu.edu/gradschool_theses/1139


University of Arkansas

8. Thian, Ross Josiah. Multi-threshold CMOS Circuit Design Methodology from 2D to 3D.

Degree: MSCmpE, 2010, University of Arkansas

  A new and exciting approach in digital IC design in order to accommodate the Moore's law is 3D chip stacking. Chip stacking offers more… (more)

Subjects/Keywords: 2D to 3D conversion methodology; 3D chip design; Low power chip design; Multi-threshold cmos; Computer Engineering; Digital Circuits; Electrical and Computer Engineering

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APA (6th Edition):

Thian, R. J. (2010). Multi-threshold CMOS Circuit Design Methodology from 2D to 3D. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/52

Chicago Manual of Style (16th Edition):

Thian, Ross Josiah. “Multi-threshold CMOS Circuit Design Methodology from 2D to 3D.” 2010. Masters Thesis, University of Arkansas. Accessed February 29, 2020. https://scholarworks.uark.edu/etd/52.

MLA Handbook (7th Edition):

Thian, Ross Josiah. “Multi-threshold CMOS Circuit Design Methodology from 2D to 3D.” 2010. Web. 29 Feb 2020.

Vancouver:

Thian RJ. Multi-threshold CMOS Circuit Design Methodology from 2D to 3D. [Internet] [Masters thesis]. University of Arkansas; 2010. [cited 2020 Feb 29]. Available from: https://scholarworks.uark.edu/etd/52.

Council of Science Editors:

Thian RJ. Multi-threshold CMOS Circuit Design Methodology from 2D to 3D. [Masters Thesis]. University of Arkansas; 2010. Available from: https://scholarworks.uark.edu/etd/52


University of Toronto

9. Tahmoureszadeh, Tina. Analog Front-end Design for 2x Blind ADC-based Receivers.

Degree: 2010, University of Toronto

This thesis presents the design, implementation, and fabrication of an analog front-end (AFE) targeting 2x blind ADC-based receivers. The front-end consists of a combination of… (more)

Subjects/Keywords: High-speed signaling; chip-to-chip communication; analog front-end; equalization; clock and data recovery; feed-forward equalization; receiver; ADC-based receiver; blind receiver; channel; 0544

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APA (6th Edition):

Tahmoureszadeh, T. (2010). Analog Front-end Design for 2x Blind ADC-based Receivers. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/29988

Chicago Manual of Style (16th Edition):

Tahmoureszadeh, Tina. “Analog Front-end Design for 2x Blind ADC-based Receivers.” 2010. Masters Thesis, University of Toronto. Accessed February 29, 2020. http://hdl.handle.net/1807/29988.

MLA Handbook (7th Edition):

Tahmoureszadeh, Tina. “Analog Front-end Design for 2x Blind ADC-based Receivers.” 2010. Web. 29 Feb 2020.

Vancouver:

Tahmoureszadeh T. Analog Front-end Design for 2x Blind ADC-based Receivers. [Internet] [Masters thesis]. University of Toronto; 2010. [cited 2020 Feb 29]. Available from: http://hdl.handle.net/1807/29988.

Council of Science Editors:

Tahmoureszadeh T. Analog Front-end Design for 2x Blind ADC-based Receivers. [Masters Thesis]. University of Toronto; 2010. Available from: http://hdl.handle.net/1807/29988


Arizona State University

10. Javidahmadabadi, Mahdi. Galvanically Isolated On Chip Communication By Resonant Coupling.

Degree: Electrical Engineering, 2015, Arizona State University

Subjects/Keywords: Electrical engineering; chip-to-chip; coupler; galvanic isolation; high-voltage; isolator; resonator

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APA (6th Edition):

Javidahmadabadi, M. (2015). Galvanically Isolated On Chip Communication By Resonant Coupling. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/34898

Chicago Manual of Style (16th Edition):

Javidahmadabadi, Mahdi. “Galvanically Isolated On Chip Communication By Resonant Coupling.” 2015. Masters Thesis, Arizona State University. Accessed February 29, 2020. http://repository.asu.edu/items/34898.

MLA Handbook (7th Edition):

Javidahmadabadi, Mahdi. “Galvanically Isolated On Chip Communication By Resonant Coupling.” 2015. Web. 29 Feb 2020.

Vancouver:

Javidahmadabadi M. Galvanically Isolated On Chip Communication By Resonant Coupling. [Internet] [Masters thesis]. Arizona State University; 2015. [cited 2020 Feb 29]. Available from: http://repository.asu.edu/items/34898.

Council of Science Editors:

Javidahmadabadi M. Galvanically Isolated On Chip Communication By Resonant Coupling. [Masters Thesis]. Arizona State University; 2015. Available from: http://repository.asu.edu/items/34898


University of New South Wales

11. Aluthwala, Pasindu. Digital Harmonic-Cancelling Sinusoidal Signal Synthesis.

Degree: Computer Science & Engineering, 2017, University of New South Wales

 Sinusoidal signal synthesizers are essential modules in a variety of electronic applications, such as communication systems, calibration and verification of analog/mixed-signal integrated circuits (ICs), and… (more)

Subjects/Keywords: digital to analog converter; on chip signal generator; harmonic cancelling; PSK modulation; built in self test

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APA (6th Edition):

Aluthwala, P. (2017). Digital Harmonic-Cancelling Sinusoidal Signal Synthesis. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/58363 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:45849/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Aluthwala, Pasindu. “Digital Harmonic-Cancelling Sinusoidal Signal Synthesis.” 2017. Doctoral Dissertation, University of New South Wales. Accessed February 29, 2020. http://handle.unsw.edu.au/1959.4/58363 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:45849/SOURCE02?view=true.

MLA Handbook (7th Edition):

Aluthwala, Pasindu. “Digital Harmonic-Cancelling Sinusoidal Signal Synthesis.” 2017. Web. 29 Feb 2020.

Vancouver:

Aluthwala P. Digital Harmonic-Cancelling Sinusoidal Signal Synthesis. [Internet] [Doctoral dissertation]. University of New South Wales; 2017. [cited 2020 Feb 29]. Available from: http://handle.unsw.edu.au/1959.4/58363 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:45849/SOURCE02?view=true.

Council of Science Editors:

Aluthwala P. Digital Harmonic-Cancelling Sinusoidal Signal Synthesis. [Doctoral Dissertation]. University of New South Wales; 2017. Available from: http://handle.unsw.edu.au/1959.4/58363 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:45849/SOURCE02?view=true


North Carolina State University

12. Xu, Jian. AC Coupled Interconnect for Inter-chip Communications.

Degree: PhD, Electrical Engineering, 2007, North Carolina State University

 The scaling of integrated circuit (IC) technology demands high-speed, high-density and low-power input/output (I⁄O) for inter-chip communications. As an alternative scheme for conductive interconnects, AC… (more)

Subjects/Keywords: chip-to-chip communication; inter-chip communication; capacitive coupling; AC coupled interconnect; inductive coupling; three dimensional IC; transceiver circuit; high-speed I/O

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APA (6th Edition):

Xu, J. (2007). AC Coupled Interconnect for Inter-chip Communications. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/5774

Chicago Manual of Style (16th Edition):

Xu, Jian. “AC Coupled Interconnect for Inter-chip Communications.” 2007. Doctoral Dissertation, North Carolina State University. Accessed February 29, 2020. http://www.lib.ncsu.edu/resolver/1840.16/5774.

MLA Handbook (7th Edition):

Xu, Jian. “AC Coupled Interconnect for Inter-chip Communications.” 2007. Web. 29 Feb 2020.

Vancouver:

Xu J. AC Coupled Interconnect for Inter-chip Communications. [Internet] [Doctoral dissertation]. North Carolina State University; 2007. [cited 2020 Feb 29]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/5774.

Council of Science Editors:

Xu J. AC Coupled Interconnect for Inter-chip Communications. [Doctoral Dissertation]. North Carolina State University; 2007. Available from: http://www.lib.ncsu.edu/resolver/1840.16/5774


North Carolina State University

13. Luo, Lei. Coupled Chip-to-Chip Interconnect Design.

Degree: PhD, Electrical Engineering, 2006, North Carolina State University

 In modern high performance VLSI chips high bandwidth and high throughput are becoming increasingly important. Multi-Tb⁄s throughput is the current trend of high performance VLSI… (more)

Subjects/Keywords: High Speed Link; Transmitter; Capacitive Coupling; Pulse Signaling; Pulse Receiver; Flip Chip; Low Power; Interconnect; Packaging; Serial Link; Transceiver; Receiver; Chip-to-chip communications;

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APA (6th Edition):

Luo, L. (2006). Coupled Chip-to-Chip Interconnect Design. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/5720

Chicago Manual of Style (16th Edition):

Luo, Lei. “Coupled Chip-to-Chip Interconnect Design.” 2006. Doctoral Dissertation, North Carolina State University. Accessed February 29, 2020. http://www.lib.ncsu.edu/resolver/1840.16/5720.

MLA Handbook (7th Edition):

Luo, Lei. “Coupled Chip-to-Chip Interconnect Design.” 2006. Web. 29 Feb 2020.

Vancouver:

Luo L. Coupled Chip-to-Chip Interconnect Design. [Internet] [Doctoral dissertation]. North Carolina State University; 2006. [cited 2020 Feb 29]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/5720.

Council of Science Editors:

Luo L. Coupled Chip-to-Chip Interconnect Design. [Doctoral Dissertation]. North Carolina State University; 2006. Available from: http://www.lib.ncsu.edu/resolver/1840.16/5720

14. Ackermann, Tobias Nils. Living Photonics: Lab-on-a-chip technologies for light coupling into biological cells.

Degree: Departament de Física, 2017, Universitat Autònoma de Barcelona

 This dissertation encompasses our research on Lab-on-a-Chip (LoC) technologies enabling light coupling into biological cell layers like bacterial biofilms or monolayers of eukaryotes, with the… (more)

Subjects/Keywords: Guies d'ona cel·lulars; Guias de ondas celulares; Cell-lightguides; Lab-on-chip fotònic; Lab-on-chip fotónico; Photonic lab-on-a-chip; Interfície chip-usuari; Interfaz chip-usuario; Chip-to-world int; Ciències Experimentals; 53

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APA (6th Edition):

Ackermann, T. N. (2017). Living Photonics: Lab-on-a-chip technologies for light coupling into biological cells. (Thesis). Universitat Autònoma de Barcelona. Retrieved from http://hdl.handle.net/10803/458635

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ackermann, Tobias Nils. “Living Photonics: Lab-on-a-chip technologies for light coupling into biological cells.” 2017. Thesis, Universitat Autònoma de Barcelona. Accessed February 29, 2020. http://hdl.handle.net/10803/458635.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ackermann, Tobias Nils. “Living Photonics: Lab-on-a-chip technologies for light coupling into biological cells.” 2017. Web. 29 Feb 2020.

Vancouver:

Ackermann TN. Living Photonics: Lab-on-a-chip technologies for light coupling into biological cells. [Internet] [Thesis]. Universitat Autònoma de Barcelona; 2017. [cited 2020 Feb 29]. Available from: http://hdl.handle.net/10803/458635.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ackermann TN. Living Photonics: Lab-on-a-chip technologies for light coupling into biological cells. [Thesis]. Universitat Autònoma de Barcelona; 2017. Available from: http://hdl.handle.net/10803/458635

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

15. Lee, Kang Kug. A Sample-to-Answer Polymer Lab-on-a-Chip with Superhydrophilic Surfaces using a Spray Layer-by-Layer Nano-Assembly Method.

Degree: PhD, Engineering and Applied Science: Electrical Engineering, 2013, University of Cincinnati

 In this research, an innovative 'smart' sample-to-answer (S-to-A) polymer lab-on-a-chip (LOC) platform with superhydrophilic surfaces has been proposed, developed, and fully characterized for point-of-care clinical… (more)

Subjects/Keywords: Engineering; Sample to Answer Polymer Lab on a Chip; Superhydrophilic Surfaces; Spray Layer by Layer Nano Assembly Method; On chip Whole Blood Plamsa Separator; Asymmetric Capillary Force; Point of Care Clinical Testing

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APA (6th Edition):

Lee, K. K. (2013). A Sample-to-Answer Polymer Lab-on-a-Chip with Superhydrophilic Surfaces using a Spray Layer-by-Layer Nano-Assembly Method. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1384864905

Chicago Manual of Style (16th Edition):

Lee, Kang Kug. “A Sample-to-Answer Polymer Lab-on-a-Chip with Superhydrophilic Surfaces using a Spray Layer-by-Layer Nano-Assembly Method.” 2013. Doctoral Dissertation, University of Cincinnati. Accessed February 29, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1384864905.

MLA Handbook (7th Edition):

Lee, Kang Kug. “A Sample-to-Answer Polymer Lab-on-a-Chip with Superhydrophilic Surfaces using a Spray Layer-by-Layer Nano-Assembly Method.” 2013. Web. 29 Feb 2020.

Vancouver:

Lee KK. A Sample-to-Answer Polymer Lab-on-a-Chip with Superhydrophilic Surfaces using a Spray Layer-by-Layer Nano-Assembly Method. [Internet] [Doctoral dissertation]. University of Cincinnati; 2013. [cited 2020 Feb 29]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1384864905.

Council of Science Editors:

Lee KK. A Sample-to-Answer Polymer Lab-on-a-Chip with Superhydrophilic Surfaces using a Spray Layer-by-Layer Nano-Assembly Method. [Doctoral Dissertation]. University of Cincinnati; 2013. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1384864905

16. Yeh, Ho-Hsin. Developments of 60 GHz Antenna and Wireless Interconnect inside Multi-Chip Module for Parallel Processor System .

Degree: 2013, University of Arizona

 In order to carry out the complicated computation inside the high performance computing (HPC) systems, tens to hundreds of parallel processor chips and physical wires… (more)

Subjects/Keywords: Chip to Chip Communication; High Speed Circuit; Interconnect; Electrical & Computer Engineering; 60 GHz Antenna

…are required to be integrated inside the multi-chip package module (MCM). The… …on evaluating the antenna’s system performance within the chip to chip wireless… …is required by planar type chip to chip 12 interconnect can be achieved with the design… …the chip. (1.1) is utilized to explain the relation between the power consumption… …data transfer between multiple processor chips. The wired interconnect for a chip to chip… 

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APA (6th Edition):

Yeh, H. (2013). Developments of 60 GHz Antenna and Wireless Interconnect inside Multi-Chip Module for Parallel Processor System . (Doctoral Dissertation). University of Arizona. Retrieved from http://hdl.handle.net/10150/272872

Chicago Manual of Style (16th Edition):

Yeh, Ho-Hsin. “Developments of 60 GHz Antenna and Wireless Interconnect inside Multi-Chip Module for Parallel Processor System .” 2013. Doctoral Dissertation, University of Arizona. Accessed February 29, 2020. http://hdl.handle.net/10150/272872.

MLA Handbook (7th Edition):

Yeh, Ho-Hsin. “Developments of 60 GHz Antenna and Wireless Interconnect inside Multi-Chip Module for Parallel Processor System .” 2013. Web. 29 Feb 2020.

Vancouver:

Yeh H. Developments of 60 GHz Antenna and Wireless Interconnect inside Multi-Chip Module for Parallel Processor System . [Internet] [Doctoral dissertation]. University of Arizona; 2013. [cited 2020 Feb 29]. Available from: http://hdl.handle.net/10150/272872.

Council of Science Editors:

Yeh H. Developments of 60 GHz Antenna and Wireless Interconnect inside Multi-Chip Module for Parallel Processor System . [Doctoral Dissertation]. University of Arizona; 2013. Available from: http://hdl.handle.net/10150/272872


Georgia Tech

17. Spencer, Todd Joseph. Air-gap transmission lines on printed circuit boards for chip-to-chip interconnections.

Degree: PhD, Chemical Engineering, 2010, Georgia Tech

 Low-loss off-chip interconnects are required for energy-efficient communication in dense microprocessors. To meet these needs, air cavity parallel plate and microstrip lines with copper conductors… (more)

Subjects/Keywords: Dielectric; Interconnect; Chip-to-chip; Air gap; Microelectromechanical systems; Microprocessors; Polymers – Deterioration; Polymers Electric properties

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Spencer, T. J. (2010). Air-gap transmission lines on printed circuit boards for chip-to-chip interconnections. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/34754

Chicago Manual of Style (16th Edition):

Spencer, Todd Joseph. “Air-gap transmission lines on printed circuit boards for chip-to-chip interconnections.” 2010. Doctoral Dissertation, Georgia Tech. Accessed February 29, 2020. http://hdl.handle.net/1853/34754.

MLA Handbook (7th Edition):

Spencer, Todd Joseph. “Air-gap transmission lines on printed circuit boards for chip-to-chip interconnections.” 2010. Web. 29 Feb 2020.

Vancouver:

Spencer TJ. Air-gap transmission lines on printed circuit boards for chip-to-chip interconnections. [Internet] [Doctoral dissertation]. Georgia Tech; 2010. [cited 2020 Feb 29]. Available from: http://hdl.handle.net/1853/34754.

Council of Science Editors:

Spencer TJ. Air-gap transmission lines on printed circuit boards for chip-to-chip interconnections. [Doctoral Dissertation]. Georgia Tech; 2010. Available from: http://hdl.handle.net/1853/34754


Georgia Tech

18. Kacker, Karan. Design and fabrication of free-standing structures as off-chip interconnects for microsystems packaging.

Degree: PhD, Mechanical Engineering, 2008, Georgia Tech

 It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) that by the year 2019, with the IC feature… (more)

Subjects/Keywords: Flip chip assembly; Compliant interconnects; First level interconnects; Chip to substrate interconnects; Wafer level packaging; Interconnects (Integrated circuit technology); Microelectronic packaging

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APA (6th Edition):

Kacker, K. (2008). Design and fabrication of free-standing structures as off-chip interconnects for microsystems packaging. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/26464

Chicago Manual of Style (16th Edition):

Kacker, Karan. “Design and fabrication of free-standing structures as off-chip interconnects for microsystems packaging.” 2008. Doctoral Dissertation, Georgia Tech. Accessed February 29, 2020. http://hdl.handle.net/1853/26464.

MLA Handbook (7th Edition):

Kacker, Karan. “Design and fabrication of free-standing structures as off-chip interconnects for microsystems packaging.” 2008. Web. 29 Feb 2020.

Vancouver:

Kacker K. Design and fabrication of free-standing structures as off-chip interconnects for microsystems packaging. [Internet] [Doctoral dissertation]. Georgia Tech; 2008. [cited 2020 Feb 29]. Available from: http://hdl.handle.net/1853/26464.

Council of Science Editors:

Kacker K. Design and fabrication of free-standing structures as off-chip interconnects for microsystems packaging. [Doctoral Dissertation]. Georgia Tech; 2008. Available from: http://hdl.handle.net/1853/26464

19. Mermoz, Sebastien. Auto-assemblage assisté par capillarité et collage direct : Self-assembly assisted by capillarity and direct bonding.

Degree: Docteur es, Mécanique des fluides, procédés, énergétique, 2015, Grenoble Alpes

Parmi les différentes techniques permettant d'assembler à la fois mécaniquement et électriquement les puces empilées, le collage direct de surfaces mixtes Cu-SiO2 représente l'option la… (more)

Subjects/Keywords: Auto-assemblage; Collage direct; Puce-à-plaque; Intégration 3D; Capillarité; Modélisation; Self-assembly; Direct bonding; Chip-to-wafer; 3D integration; Capillarity; Modelisation; 620

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APA (6th Edition):

Mermoz, S. (2015). Auto-assemblage assisté par capillarité et collage direct : Self-assembly assisted by capillarity and direct bonding. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2015GREAI114

Chicago Manual of Style (16th Edition):

Mermoz, Sebastien. “Auto-assemblage assisté par capillarité et collage direct : Self-assembly assisted by capillarity and direct bonding.” 2015. Doctoral Dissertation, Grenoble Alpes. Accessed February 29, 2020. http://www.theses.fr/2015GREAI114.

MLA Handbook (7th Edition):

Mermoz, Sebastien. “Auto-assemblage assisté par capillarité et collage direct : Self-assembly assisted by capillarity and direct bonding.” 2015. Web. 29 Feb 2020.

Vancouver:

Mermoz S. Auto-assemblage assisté par capillarité et collage direct : Self-assembly assisted by capillarity and direct bonding. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2015. [cited 2020 Feb 29]. Available from: http://www.theses.fr/2015GREAI114.

Council of Science Editors:

Mermoz S. Auto-assemblage assisté par capillarité et collage direct : Self-assembly assisted by capillarity and direct bonding. [Doctoral Dissertation]. Grenoble Alpes; 2015. Available from: http://www.theses.fr/2015GREAI114


Universidade do Rio Grande do Sul

20. Aguilera, Carlos Julio González. Avaliação de conversores AD sob efeitos de radiação e mitigação utilizando redundância com diversidade.

Degree: 2018, Universidade do Rio Grande do Sul

Este trabalho aborda um sistema de aquisição de dados (SAD) analógico-digital, baseado em um esquema redundante com diversidade de projeto, que é testado em dois… (more)

Subjects/Keywords: Ionizing radiation; Microeletrônica; Diversity; Radiação; Total ionizing dose; Single event effects; Triple modular redundancy; Mixed signals; Programmable system-on-chip; Analog-to-digital converters

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APA (6th Edition):

Aguilera, C. J. G. (2018). Avaliação de conversores AD sob efeitos de radiação e mitigação utilizando redundância com diversidade. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/179530

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Aguilera, Carlos Julio González. “Avaliação de conversores AD sob efeitos de radiação e mitigação utilizando redundância com diversidade.” 2018. Thesis, Universidade do Rio Grande do Sul. Accessed February 29, 2020. http://hdl.handle.net/10183/179530.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Aguilera, Carlos Julio González. “Avaliação de conversores AD sob efeitos de radiação e mitigação utilizando redundância com diversidade.” 2018. Web. 29 Feb 2020.

Vancouver:

Aguilera CJG. Avaliação de conversores AD sob efeitos de radiação e mitigação utilizando redundância com diversidade. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2018. [cited 2020 Feb 29]. Available from: http://hdl.handle.net/10183/179530.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Aguilera CJG. Avaliação de conversores AD sob efeitos de radiação e mitigação utilizando redundância com diversidade. [Thesis]. Universidade do Rio Grande do Sul; 2018. Available from: http://hdl.handle.net/10183/179530

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université Catholique de Louvain

21. Nuessle, Georg. Development of a novel micro channel cooling system for the NA62 GTK detector.

Degree: 2015, Université Catholique de Louvain

Subjects/Keywords: Silicon tracking detector; NA62; Gigatracker; Micro channel; Chip to tube soldering; Cooling

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APA (6th Edition):

Nuessle, G. (2015). Development of a novel micro channel cooling system for the NA62 GTK detector. (Thesis). Université Catholique de Louvain. Retrieved from http://hdl.handle.net/2078.1/171150

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nuessle, Georg. “Development of a novel micro channel cooling system for the NA62 GTK detector.” 2015. Thesis, Université Catholique de Louvain. Accessed February 29, 2020. http://hdl.handle.net/2078.1/171150.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nuessle, Georg. “Development of a novel micro channel cooling system for the NA62 GTK detector.” 2015. Web. 29 Feb 2020.

Vancouver:

Nuessle G. Development of a novel micro channel cooling system for the NA62 GTK detector. [Internet] [Thesis]. Université Catholique de Louvain; 2015. [cited 2020 Feb 29]. Available from: http://hdl.handle.net/2078.1/171150.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nuessle G. Development of a novel micro channel cooling system for the NA62 GTK detector. [Thesis]. Université Catholique de Louvain; 2015. Available from: http://hdl.handle.net/2078.1/171150

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Northeastern University

22. Jung, Inseok. Self-calibration approach for mixed signal circuits in systems-on-chip.

Degree: PhD, Department of Electrical and Computer Engineering, 2015, Northeastern University

 MOSFET scaling has served industry very well for a few decades by proving improvements in transistor performance, power, and cost. However, they require high test… (more)

Subjects/Keywords: ADC; circuit; Mixed circuit; Electrical and Computer Engineering; Mixed signal circuits; Mixed signal circuits; Systems on a chip; Analog-to-digital converters; Metal oxide semiconductor field-effect transistors

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APA (6th Edition):

Jung, I. (2015). Self-calibration approach for mixed signal circuits in systems-on-chip. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20009298

Chicago Manual of Style (16th Edition):

Jung, Inseok. “Self-calibration approach for mixed signal circuits in systems-on-chip.” 2015. Doctoral Dissertation, Northeastern University. Accessed February 29, 2020. http://hdl.handle.net/2047/d20009298.

MLA Handbook (7th Edition):

Jung, Inseok. “Self-calibration approach for mixed signal circuits in systems-on-chip.” 2015. Web. 29 Feb 2020.

Vancouver:

Jung I. Self-calibration approach for mixed signal circuits in systems-on-chip. [Internet] [Doctoral dissertation]. Northeastern University; 2015. [cited 2020 Feb 29]. Available from: http://hdl.handle.net/2047/d20009298.

Council of Science Editors:

Jung I. Self-calibration approach for mixed signal circuits in systems-on-chip. [Doctoral Dissertation]. Northeastern University; 2015. Available from: http://hdl.handle.net/2047/d20009298


University of Michigan

23. Jung, Wanyeong. Low-Power Energy Efficient Circuit Techniques for Small IoT Systems.

Degree: PhD, Electrical Engineering, 2017, University of Michigan

 Although the improvement in circuit speed has been limited in recent years, there has been increased focus on the internet of things (IoT) as technology… (more)

Subjects/Keywords: Internet of Things; Low-power circuit technique; Switched-capacitor DC-DC Converter; Capacitance sensor; Analog-to-digital converter; On-chip oven control; Electrical Engineering; Engineering

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APA (6th Edition):

Jung, W. (2017). Low-Power Energy Efficient Circuit Techniques for Small IoT Systems. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/138743

Chicago Manual of Style (16th Edition):

Jung, Wanyeong. “Low-Power Energy Efficient Circuit Techniques for Small IoT Systems.” 2017. Doctoral Dissertation, University of Michigan. Accessed February 29, 2020. http://hdl.handle.net/2027.42/138743.

MLA Handbook (7th Edition):

Jung, Wanyeong. “Low-Power Energy Efficient Circuit Techniques for Small IoT Systems.” 2017. Web. 29 Feb 2020.

Vancouver:

Jung W. Low-Power Energy Efficient Circuit Techniques for Small IoT Systems. [Internet] [Doctoral dissertation]. University of Michigan; 2017. [cited 2020 Feb 29]. Available from: http://hdl.handle.net/2027.42/138743.

Council of Science Editors:

Jung W. Low-Power Energy Efficient Circuit Techniques for Small IoT Systems. [Doctoral Dissertation]. University of Michigan; 2017. Available from: http://hdl.handle.net/2027.42/138743


Georgia Tech

24. He, Ate. Fabrication of High Performance Chip-to-Substrate Interconnections.

Degree: PhD, Chemical Engineering, 2007, Georgia Tech

 Novel fabrication technologies for high performance electrical and optical chip-to-substrate input/output (I/O) interconnections were developed. This research is driven by the long term performance and… (more)

Subjects/Keywords: Electroless plating; Assembly; Fabrication; Chip-to-substrate; Interconnect; Copper pillar

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

He, A. (2007). Fabrication of High Performance Chip-to-Substrate Interconnections. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/14483

Chicago Manual of Style (16th Edition):

He, Ate. “Fabrication of High Performance Chip-to-Substrate Interconnections.” 2007. Doctoral Dissertation, Georgia Tech. Accessed February 29, 2020. http://hdl.handle.net/1853/14483.

MLA Handbook (7th Edition):

He, Ate. “Fabrication of High Performance Chip-to-Substrate Interconnections.” 2007. Web. 29 Feb 2020.

Vancouver:

He A. Fabrication of High Performance Chip-to-Substrate Interconnections. [Internet] [Doctoral dissertation]. Georgia Tech; 2007. [cited 2020 Feb 29]. Available from: http://hdl.handle.net/1853/14483.

Council of Science Editors:

He A. Fabrication of High Performance Chip-to-Substrate Interconnections. [Doctoral Dissertation]. Georgia Tech; 2007. Available from: http://hdl.handle.net/1853/14483

25. Zhang, Chaoming, 1980-. Built-in self test of RF subsystems.

Degree: PhD, Electrical and Computer Engineering, 2008, University of Texas – Austin

 With the rapid development of wireless and wireline communications, a variety of new standards and applications are emerging in the marketplace. In order to achieve… (more)

Subjects/Keywords: Built-in self test; RF subsystems; System on Chip; SoC; On-chip detectors; Analog to Digital Converters; CMOS; RF transceivers

…components can be accurately measured. On-chip measurement results need to be collected by Analog… …Prototype Chip Design . . . . . . . . . . . . . . . . . 3.2.1 Voltage to Delay Building Block… …fully investigated. In [8], a high bandwidth on-chip detector was designed to test… …implemented on-chip in a receiver to facilitate specification test for both the system and the… …chip RF test system, an ADC is a necessary component. In order to simplify the control and… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhang, Chaoming, 1. (2008). Built-in self test of RF subsystems. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/21908

Chicago Manual of Style (16th Edition):

Zhang, Chaoming, 1980-. “Built-in self test of RF subsystems.” 2008. Doctoral Dissertation, University of Texas – Austin. Accessed February 29, 2020. http://hdl.handle.net/2152/21908.

MLA Handbook (7th Edition):

Zhang, Chaoming, 1980-. “Built-in self test of RF subsystems.” 2008. Web. 29 Feb 2020.

Vancouver:

Zhang, Chaoming 1. Built-in self test of RF subsystems. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2008. [cited 2020 Feb 29]. Available from: http://hdl.handle.net/2152/21908.

Council of Science Editors:

Zhang, Chaoming 1. Built-in self test of RF subsystems. [Doctoral Dissertation]. University of Texas – Austin; 2008. Available from: http://hdl.handle.net/2152/21908


Indian Institute of Science

26. Vasudevamurthy, Rajath. Time-based All-Digital Technique for Analog Built-in Self Test.

Degree: 2013, Indian Institute of Science

 A scheme for Built-in-Self-Test (BIST) of analog signals with minimal area overhead, for measuring on-chip voltages in an all-digital manner is presented in this thesis.… (more)

Subjects/Keywords: Electronic Circuits; On-Chip Analog Test Voltages; Electronic Circuit Design; Analog Circuits; Built-in Self Test (BIST); Time-to-Digital Converters; Analog Routing; Analog Built-in Self Test; Time Based Analog-to-Digital Converter; Analog-to-Digital Converters; Integrated Circuit; Analog IP Test; Electronic Engineering

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APA (6th Edition):

Vasudevamurthy, R. (2013). Time-based All-Digital Technique for Analog Built-in Self Test. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2841

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vasudevamurthy, Rajath. “Time-based All-Digital Technique for Analog Built-in Self Test.” 2013. Thesis, Indian Institute of Science. Accessed February 29, 2020. http://hdl.handle.net/2005/2841.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vasudevamurthy, Rajath. “Time-based All-Digital Technique for Analog Built-in Self Test.” 2013. Web. 29 Feb 2020.

Vancouver:

Vasudevamurthy R. Time-based All-Digital Technique for Analog Built-in Self Test. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2020 Feb 29]. Available from: http://hdl.handle.net/2005/2841.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vasudevamurthy R. Time-based All-Digital Technique for Analog Built-in Self Test. [Thesis]. Indian Institute of Science; 2013. Available from: http://hdl.handle.net/2005/2841

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

27. Chenet, Cristiano Pegoraro. Análise de soft errors em conversores analógico-digitais e mitigação utilizando redundância e diversidade.

Degree: 2015, Universidade do Rio Grande do Sul

 Este trabalho aborda os soft errors em conversores de dados analógico-digitais e a mitigação usando redundância e diversidade. Nas tecnologias CMOS recentes, os efeitos singulares… (more)

Subjects/Keywords: Conversor analogico/digital; Single event effects (SEE); Soft errors; Circuitos eletrônicos; Cmos; Triple modular redundancy (TMR); Redundância modular tripla; Redundancy and diversity; Programmable system-on-chip (PSoC); Analog-to-digital converters

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APA (6th Edition):

Chenet, C. P. (2015). Análise de soft errors em conversores analógico-digitais e mitigação utilizando redundância e diversidade. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/127693

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chenet, Cristiano Pegoraro. “Análise de soft errors em conversores analógico-digitais e mitigação utilizando redundância e diversidade.” 2015. Thesis, Universidade do Rio Grande do Sul. Accessed February 29, 2020. http://hdl.handle.net/10183/127693.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chenet, Cristiano Pegoraro. “Análise de soft errors em conversores analógico-digitais e mitigação utilizando redundância e diversidade.” 2015. Web. 29 Feb 2020.

Vancouver:

Chenet CP. Análise de soft errors em conversores analógico-digitais e mitigação utilizando redundância e diversidade. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2015. [cited 2020 Feb 29]. Available from: http://hdl.handle.net/10183/127693.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chenet CP. Análise de soft errors em conversores analógico-digitais e mitigação utilizando redundância e diversidade. [Thesis]. Universidade do Rio Grande do Sul; 2015. Available from: http://hdl.handle.net/10183/127693

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

28. Yoo, Jincheol. A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications.

Degree: PhD, Computer Science and Engineering, 2002, Penn State University

 This thesis addresses a Threshold Inverter Quantization (TIQ) based CMOS flash analog-to-digital converter (ADC) for system-on-chip (SoC) applications. The TIQ technique, which uses two cascaded… (more)

Subjects/Keywords: Threshold Inverter Quantization (TIQ); Flash ADC; Analog-to-Digital Converter; System-on-Chip (SoC)

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APA (6th Edition):

Yoo, J. (2002). A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/6040

Chicago Manual of Style (16th Edition):

Yoo, Jincheol. “A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications.” 2002. Doctoral Dissertation, Penn State University. Accessed February 29, 2020. https://etda.libraries.psu.edu/catalog/6040.

MLA Handbook (7th Edition):

Yoo, Jincheol. “A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications.” 2002. Web. 29 Feb 2020.

Vancouver:

Yoo J. A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications. [Internet] [Doctoral dissertation]. Penn State University; 2002. [cited 2020 Feb 29]. Available from: https://etda.libraries.psu.edu/catalog/6040.

Council of Science Editors:

Yoo J. A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications. [Doctoral Dissertation]. Penn State University; 2002. Available from: https://etda.libraries.psu.edu/catalog/6040

29. Dong, Qi. Credit risk measurement of the listed companies in China based on KMV model.

Degree: 2016, RCAAP

Devido à recente crise financeira global que provoca um grande número de defaults de empresas (Moody`s, 2009), bem como a inovação na dívida corporativa e… (more)

Subjects/Keywords: Gestão financeira; Mercado financeiro; Análise de risco; Risco de crédito; Modelos de risco; Credit risk; KMV model; Distance to default; Probability of Default; Default Point; ST&*ST companies; Blue-chip companies; China; Domínio/Área Científica::Ciências Sociais::Economia e Gestão

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dong, Q. (2016). Credit risk measurement of the listed companies in China based on KMV model. (Thesis). RCAAP. Retrieved from https://www.rcaap.pt/detail.jsp?id=oai:repositorio.iscte-iul.pt:10071/13184

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dong, Qi. “Credit risk measurement of the listed companies in China based on KMV model.” 2016. Thesis, RCAAP. Accessed February 29, 2020. https://www.rcaap.pt/detail.jsp?id=oai:repositorio.iscte-iul.pt:10071/13184.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dong, Qi. “Credit risk measurement of the listed companies in China based on KMV model.” 2016. Web. 29 Feb 2020.

Vancouver:

Dong Q. Credit risk measurement of the listed companies in China based on KMV model. [Internet] [Thesis]. RCAAP; 2016. [cited 2020 Feb 29]. Available from: https://www.rcaap.pt/detail.jsp?id=oai:repositorio.iscte-iul.pt:10071/13184.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dong Q. Credit risk measurement of the listed companies in China based on KMV model. [Thesis]. RCAAP; 2016. Available from: https://www.rcaap.pt/detail.jsp?id=oai:repositorio.iscte-iul.pt:10071/13184

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

30. Markov, Petr. Hybrid Silicon-Vanadium Dioxide Modulators and Transformation Optics Couplers for Optical Interconnects.

Degree: PhD, Electrical Engineering, 2015, Vanderbilt University

 The ever-growing demand for more powerful computers has led to the emergence of multicore processors. Due to the nature of parallel processing, additional cores significantly… (more)

Subjects/Keywords: Vanadium dioxide; optical interconnect; electro-optic modulator; transformation optics; fiber-to-chip coupler

to-chip coupler based on two-stage adiabatic evolution from ref. [13]… …2.8 Simulated transmission plot for fiber-to-chip coupling for TO coupler with 50 nm (… …to-rack interconnects, a middle ground between long range and on-chip, can be incredibly… …technology uses on-chip copper electrical interconnects to carry information between cores and… …electrical interconnects can be used on chip. Electrical interconnects are also susceptible to… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Markov, P. (2015). Hybrid Silicon-Vanadium Dioxide Modulators and Transformation Optics Couplers for Optical Interconnects. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03232015-124312/ ;

Chicago Manual of Style (16th Edition):

Markov, Petr. “Hybrid Silicon-Vanadium Dioxide Modulators and Transformation Optics Couplers for Optical Interconnects.” 2015. Doctoral Dissertation, Vanderbilt University. Accessed February 29, 2020. http://etd.library.vanderbilt.edu/available/etd-03232015-124312/ ;.

MLA Handbook (7th Edition):

Markov, Petr. “Hybrid Silicon-Vanadium Dioxide Modulators and Transformation Optics Couplers for Optical Interconnects.” 2015. Web. 29 Feb 2020.

Vancouver:

Markov P. Hybrid Silicon-Vanadium Dioxide Modulators and Transformation Optics Couplers for Optical Interconnects. [Internet] [Doctoral dissertation]. Vanderbilt University; 2015. [cited 2020 Feb 29]. Available from: http://etd.library.vanderbilt.edu/available/etd-03232015-124312/ ;.

Council of Science Editors:

Markov P. Hybrid Silicon-Vanadium Dioxide Modulators and Transformation Optics Couplers for Optical Interconnects. [Doctoral Dissertation]. Vanderbilt University; 2015. Available from: http://etd.library.vanderbilt.edu/available/etd-03232015-124312/ ;

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