Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(Chip Multi Core Processor). Showing records 1 – 30 of 19268 total matches.

[1] [2] [3] [4] [5] … [643]

Search Limiters

Last 2 Years | English Only

Degrees

Languages

Country

▼ Search Limiters


Ohio University

1. Kennedy, Matthew D. Power-Efficient Nanophotonic Architectures for Intra- and Inter-Chip Communication.

Degree: MS, Electrical Engineering (Engineering and Technology), 2016, Ohio University

 As demand for computational processing power continues to rise, chip manufacturers have recently shifted from raising clock rates towards increasing processing core counts, heralding the… (more)

Subjects/Keywords: Computer Engineering; Electrical Engineering; network-on-chip; silicon nanophotonics; power-efficient; intra-chip communication; inter-chip communication; multi-core processor

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kennedy, M. D. (2016). Power-Efficient Nanophotonic Architectures for Intra- and Inter-Chip Communication. (Masters Thesis). Ohio University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1458232838

Chicago Manual of Style (16th Edition):

Kennedy, Matthew D. “Power-Efficient Nanophotonic Architectures for Intra- and Inter-Chip Communication.” 2016. Masters Thesis, Ohio University. Accessed January 23, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1458232838.

MLA Handbook (7th Edition):

Kennedy, Matthew D. “Power-Efficient Nanophotonic Architectures for Intra- and Inter-Chip Communication.” 2016. Web. 23 Jan 2020.

Vancouver:

Kennedy MD. Power-Efficient Nanophotonic Architectures for Intra- and Inter-Chip Communication. [Internet] [Masters thesis]. Ohio University; 2016. [cited 2020 Jan 23]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1458232838.

Council of Science Editors:

Kennedy MD. Power-Efficient Nanophotonic Architectures for Intra- and Inter-Chip Communication. [Masters Thesis]. Ohio University; 2016. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1458232838


University of Illinois – Urbana-Champaign

2. Zhou, Wenjia. A lightweight DSP framework for OMAP3530-driven embedded devices.

Degree: MS, 1200, 2015, University of Illinois – Urbana-Champaign

 This thesis provides a lightweight framework, called MiniDSP, for OMAP3530 heterogeneous dual core SoC to run tasks on its DSP co-processor. This framework is composed… (more)

Subjects/Keywords: Digital signal processor (DSP); Embedded system; Multi-core system on chip (SoC); Device driver

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhou, W. (2015). A lightweight DSP framework for OMAP3530-driven embedded devices. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/73020

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhou, Wenjia. “A lightweight DSP framework for OMAP3530-driven embedded devices.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed January 23, 2020. http://hdl.handle.net/2142/73020.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhou, Wenjia. “A lightweight DSP framework for OMAP3530-driven embedded devices.” 2015. Web. 23 Jan 2020.

Vancouver:

Zhou W. A lightweight DSP framework for OMAP3530-driven embedded devices. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Jan 23]. Available from: http://hdl.handle.net/2142/73020.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhou W. A lightweight DSP framework for OMAP3530-driven embedded devices. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/73020

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

3. Vikas, G. Power Optimal Network-On-Chip Interconnect Design.

Degree: 2010, Indian Institute of Science

 A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power… (more)

Subjects/Keywords: Network On Chip - Design and Construction; Electric Power Networks; Application Specific System On Chip; Routers (Computer Networks); Chip Multi Core Processor; Network-on-Chip Interconnect Design; Computer Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vikas, G. (2010). Power Optimal Network-On-Chip Interconnect Design. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1408

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Thesis, Indian Institute of Science. Accessed January 23, 2020. http://hdl.handle.net/2005/1408.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Web. 23 Jan 2020.

Vancouver:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Internet] [Thesis]. Indian Institute of Science; 2010. [cited 2020 Jan 23]. Available from: http://hdl.handle.net/2005/1408.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Thesis]. Indian Institute of Science; 2010. Available from: http://hdl.handle.net/2005/1408

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

4. Vikas, G. Power Optimal Network-On-Chip Interconnect Design.

Degree: 2010, Indian Institute of Science

 A large part of today's multi-core chips is interconnect. Increasing communication complexity has made new strategies for interconnects essential such as Network on Chip. Power… (more)

Subjects/Keywords: Network On Chip - Design and Construction; Electric Power Networks; Application Specific System On Chip; Routers (Computer Networks); Chip Multi Core Processor; Network-on-Chip Interconnect Design; Computer Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vikas, G. (2010). Power Optimal Network-On-Chip Interconnect Design. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Thesis, Indian Institute of Science. Accessed January 23, 2020. http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vikas, G. “Power Optimal Network-On-Chip Interconnect Design.” 2010. Web. 23 Jan 2020.

Vancouver:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Internet] [Thesis]. Indian Institute of Science; 2010. [cited 2020 Jan 23]. Available from: http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vikas G. Power Optimal Network-On-Chip Interconnect Design. [Thesis]. Indian Institute of Science; 2010. Available from: http://etd.iisc.ernet.in/handle/2005/1408 ; http://etd.ncsi.iisc.ernet.in/abstracts/1817/G23700-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Washington University in St. Louis

5. Wun, Benjamin. High Speed Networking In The Multi-Core Era.

Degree: PhD, Computer Science and Engineering, 2011, Washington University in St. Louis

 High speed networking is a demanding task that has traditionally been performed in dedicated, purpose built hardware or specialized network processors. These platforms sacrifice flexibility… (more)

Subjects/Keywords: Computer engineering; Multi-core; Networking; Network Processor

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wun, B. (2011). High Speed Networking In The Multi-Core Era. (Doctoral Dissertation). Washington University in St. Louis. Retrieved from https://openscholarship.wustl.edu/etd/668

Chicago Manual of Style (16th Edition):

Wun, Benjamin. “High Speed Networking In The Multi-Core Era.” 2011. Doctoral Dissertation, Washington University in St. Louis. Accessed January 23, 2020. https://openscholarship.wustl.edu/etd/668.

MLA Handbook (7th Edition):

Wun, Benjamin. “High Speed Networking In The Multi-Core Era.” 2011. Web. 23 Jan 2020.

Vancouver:

Wun B. High Speed Networking In The Multi-Core Era. [Internet] [Doctoral dissertation]. Washington University in St. Louis; 2011. [cited 2020 Jan 23]. Available from: https://openscholarship.wustl.edu/etd/668.

Council of Science Editors:

Wun B. High Speed Networking In The Multi-Core Era. [Doctoral Dissertation]. Washington University in St. Louis; 2011. Available from: https://openscholarship.wustl.edu/etd/668


Rochester Institute of Technology

6. Sieber, Patrick. Reliability-aware multi-segmented bus architecture for photonic networks-on-chip.

Degree: Computer Engineering, 2013, Rochester Institute of Technology

 Network-on-chip (NoC) has emerged as an enabling platform for connecting hundreds of cores on a single chip, allowing for a structured, scalable system when compared… (more)

Subjects/Keywords: Multi-core; Network-on-chip; Photonic

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sieber, P. (2013). Reliability-aware multi-segmented bus architecture for photonic networks-on-chip. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/3160

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sieber, Patrick. “Reliability-aware multi-segmented bus architecture for photonic networks-on-chip.” 2013. Thesis, Rochester Institute of Technology. Accessed January 23, 2020. https://scholarworks.rit.edu/theses/3160.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sieber, Patrick. “Reliability-aware multi-segmented bus architecture for photonic networks-on-chip.” 2013. Web. 23 Jan 2020.

Vancouver:

Sieber P. Reliability-aware multi-segmented bus architecture for photonic networks-on-chip. [Internet] [Thesis]. Rochester Institute of Technology; 2013. [cited 2020 Jan 23]. Available from: https://scholarworks.rit.edu/theses/3160.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sieber P. Reliability-aware multi-segmented bus architecture for photonic networks-on-chip. [Thesis]. Rochester Institute of Technology; 2013. Available from: https://scholarworks.rit.edu/theses/3160

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

7. Hsu, Chien-te. Design of parallel computing processor based on OpenCL architecture.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 In addition to pursuing more shader cores for better rendering performance, another important trend in the evolution of modern graphic processing units (GPU) is to… (more)

Subjects/Keywords: Scalar Processor; Multi-core; GPU; General Computing; OpenCL

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hsu, C. (2015). Design of parallel computing processor based on OpenCL architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-113525

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsu, Chien-te. “Design of parallel computing processor based on OpenCL architecture.” 2015. Thesis, NSYSU. Accessed January 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-113525.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsu, Chien-te. “Design of parallel computing processor based on OpenCL architecture.” 2015. Web. 23 Jan 2020.

Vancouver:

Hsu C. Design of parallel computing processor based on OpenCL architecture. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Jan 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-113525.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu C. Design of parallel computing processor based on OpenCL architecture. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-113525

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Nova

8. Alves, André Nunes Gomes. Healing replicas in a software component replication system.

Degree: 2013, Universidade Nova

Dissertação para obtenção do Grau de Mestre em Engenharia Informática

Replication is a key technique for improving performance, availability and faulttolerance of systems. Replicated systems… (more)

Subjects/Keywords: Component replication; Fault-tolerance; Performance; Multi-core processor

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Alves, A. N. G. (2013). Healing replicas in a software component replication system. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/11353

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Alves, André Nunes Gomes. “Healing replicas in a software component replication system.” 2013. Thesis, Universidade Nova. Accessed January 23, 2020. http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/11353.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Alves, André Nunes Gomes. “Healing replicas in a software component replication system.” 2013. Web. 23 Jan 2020.

Vancouver:

Alves ANG. Healing replicas in a software component replication system. [Internet] [Thesis]. Universidade Nova; 2013. [cited 2020 Jan 23]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/11353.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Alves ANG. Healing replicas in a software component replication system. [Thesis]. Universidade Nova; 2013. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/11353

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universitat Politècnica de Catalunya

9. Paolieri, Marco. A Multi-core processor for hard real-time systems.

Degree: Departament d'Arquitectura de Computadors, 2011, Universitat Politècnica de Catalunya

 La creciente demanda de nuevas funcionalidades en los sistemas empotrados de tiempo real actuales y futuros en industrias como la automovilística y la de aviación,… (more)

Subjects/Keywords: Real-time; Multi-core; Processor; Embedded systems; Woet; 004

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Paolieri, M. (2011). A Multi-core processor for hard real-time systems. (Thesis). Universitat Politècnica de Catalunya. Retrieved from http://hdl.handle.net/10803/51578

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Paolieri, Marco. “A Multi-core processor for hard real-time systems.” 2011. Thesis, Universitat Politècnica de Catalunya. Accessed January 23, 2020. http://hdl.handle.net/10803/51578.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Paolieri, Marco. “A Multi-core processor for hard real-time systems.” 2011. Web. 23 Jan 2020.

Vancouver:

Paolieri M. A Multi-core processor for hard real-time systems. [Internet] [Thesis]. Universitat Politècnica de Catalunya; 2011. [cited 2020 Jan 23]. Available from: http://hdl.handle.net/10803/51578.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Paolieri M. A Multi-core processor for hard real-time systems. [Thesis]. Universitat Politècnica de Catalunya; 2011. Available from: http://hdl.handle.net/10803/51578

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Massey University

10. Loke, Chun Eng. A two-dimensional extensible bus technology and protocol for VLSI processor core : a thesis presented in partial fulfilment of the requirements for the degree of Master of Engineering in Computer and Electronic Engineering at School of Engineering and Advanced Technology, Massey University, Albany, New Zealand .

Degree: 2011, Massey University

 Intellectual property (IP) core design modularity and reuse in Very-Large-Scale-Integration (VLSI) silicon have been the key focus areas in design productivity improvement in order to… (more)

Subjects/Keywords: Integrated circuits; Systems on a chip; Two-dimensional extensible bus technology; VLSI processor core

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Loke, C. E. (2011). A two-dimensional extensible bus technology and protocol for VLSI processor core : a thesis presented in partial fulfilment of the requirements for the degree of Master of Engineering in Computer and Electronic Engineering at School of Engineering and Advanced Technology, Massey University, Albany, New Zealand . (Thesis). Massey University. Retrieved from http://hdl.handle.net/10179/3511

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Loke, Chun Eng. “A two-dimensional extensible bus technology and protocol for VLSI processor core : a thesis presented in partial fulfilment of the requirements for the degree of Master of Engineering in Computer and Electronic Engineering at School of Engineering and Advanced Technology, Massey University, Albany, New Zealand .” 2011. Thesis, Massey University. Accessed January 23, 2020. http://hdl.handle.net/10179/3511.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Loke, Chun Eng. “A two-dimensional extensible bus technology and protocol for VLSI processor core : a thesis presented in partial fulfilment of the requirements for the degree of Master of Engineering in Computer and Electronic Engineering at School of Engineering and Advanced Technology, Massey University, Albany, New Zealand .” 2011. Web. 23 Jan 2020.

Vancouver:

Loke CE. A two-dimensional extensible bus technology and protocol for VLSI processor core : a thesis presented in partial fulfilment of the requirements for the degree of Master of Engineering in Computer and Electronic Engineering at School of Engineering and Advanced Technology, Massey University, Albany, New Zealand . [Internet] [Thesis]. Massey University; 2011. [cited 2020 Jan 23]. Available from: http://hdl.handle.net/10179/3511.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Loke CE. A two-dimensional extensible bus technology and protocol for VLSI processor core : a thesis presented in partial fulfilment of the requirements for the degree of Master of Engineering in Computer and Electronic Engineering at School of Engineering and Advanced Technology, Massey University, Albany, New Zealand . [Thesis]. Massey University; 2011. Available from: http://hdl.handle.net/10179/3511

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

11. Velayutham, Chandru. A Hybrid Network-on-Chip and Segmented Bus Architecture for Large Caches.

Degree: MS, Engineering : Computer Engineering, 2009, University of Cincinnati

  The continual shrinking of process technologies enables many cores and large caches to be incorporated into future chips. Recent research at Intel suggests that… (more)

Subjects/Keywords: Engineering; Network on Chip; bus; cache; NUCA; multi-core

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Velayutham, C. (2009). A Hybrid Network-on-Chip and Segmented Bus Architecture for Large Caches. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1228444188

Chicago Manual of Style (16th Edition):

Velayutham, Chandru. “A Hybrid Network-on-Chip and Segmented Bus Architecture for Large Caches.” 2009. Masters Thesis, University of Cincinnati. Accessed January 23, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1228444188.

MLA Handbook (7th Edition):

Velayutham, Chandru. “A Hybrid Network-on-Chip and Segmented Bus Architecture for Large Caches.” 2009. Web. 23 Jan 2020.

Vancouver:

Velayutham C. A Hybrid Network-on-Chip and Segmented Bus Architecture for Large Caches. [Internet] [Masters thesis]. University of Cincinnati; 2009. [cited 2020 Jan 23]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1228444188.

Council of Science Editors:

Velayutham C. A Hybrid Network-on-Chip and Segmented Bus Architecture for Large Caches. [Masters Thesis]. University of Cincinnati; 2009. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1228444188


NSYSU

12. Lei, Kin-fong. Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems.

Degree: Master, Electrical Engineering, 2010, NSYSU

 In the multi-core systems, the data transfer between cores becomes a major challenge. The on-chip interconnect networks should be low latency, high throughput, scalability, better… (more)

Subjects/Keywords: On-Chip Interconnect Networks; Asynchronous Ring Bus; Multi-Core Systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lei, K. (2010). Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lei, Kin-fong. “Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems.” 2010. Thesis, NSYSU. Accessed January 23, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lei, Kin-fong. “Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems.” 2010. Web. 23 Jan 2020.

Vancouver:

Lei K. Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Jan 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lei K. Design of an Asynchronous Ring Bus Architecture for Multi-Core Systems. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818110-131743

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

13. Van Kampenhout, J. R. Deterministic Task Transfer in Network-on-Chip Based Multi-Core Processors:.

Degree: 2011, Delft University of Technology

 In this thesis we consider the application of multi-cores in safety critical real-time systems, especially avionics. In our literature study we extract two major challenges.… (more)

Subjects/Keywords: task migration; Networks-on-Chip; real-time; multi-core; avionics

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Van Kampenhout, J. R. (2011). Deterministic Task Transfer in Network-on-Chip Based Multi-Core Processors:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:6fe3398b-a45e-431c-876f-7e778885c454

Chicago Manual of Style (16th Edition):

Van Kampenhout, J R. “Deterministic Task Transfer in Network-on-Chip Based Multi-Core Processors:.” 2011. Masters Thesis, Delft University of Technology. Accessed January 23, 2020. http://resolver.tudelft.nl/uuid:6fe3398b-a45e-431c-876f-7e778885c454.

MLA Handbook (7th Edition):

Van Kampenhout, J R. “Deterministic Task Transfer in Network-on-Chip Based Multi-Core Processors:.” 2011. Web. 23 Jan 2020.

Vancouver:

Van Kampenhout JR. Deterministic Task Transfer in Network-on-Chip Based Multi-Core Processors:. [Internet] [Masters thesis]. Delft University of Technology; 2011. [cited 2020 Jan 23]. Available from: http://resolver.tudelft.nl/uuid:6fe3398b-a45e-431c-876f-7e778885c454.

Council of Science Editors:

Van Kampenhout JR. Deterministic Task Transfer in Network-on-Chip Based Multi-Core Processors:. [Masters Thesis]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:6fe3398b-a45e-431c-876f-7e778885c454


Vanderbilt University

14. Qian, Jianshu. Improved bufferless routing via balanced pipeline stages.

Degree: MS, Electrical Engineering, 2013, Vanderbilt University

 Network-on-chip (NoC) architectures with emerging interconnect technologies have been developed to meet the demand for high-performance computational systems while maintaining energy efficiency. The introduction of… (more)

Subjects/Keywords: On-chip networks; FPGA; Multi-core; Bufferless routing

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Qian, J. (2013). Improved bufferless routing via balanced pipeline stages. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-07072013-145648/ ;

Chicago Manual of Style (16th Edition):

Qian, Jianshu. “Improved bufferless routing via balanced pipeline stages.” 2013. Masters Thesis, Vanderbilt University. Accessed January 23, 2020. http://etd.library.vanderbilt.edu/available/etd-07072013-145648/ ;.

MLA Handbook (7th Edition):

Qian, Jianshu. “Improved bufferless routing via balanced pipeline stages.” 2013. Web. 23 Jan 2020.

Vancouver:

Qian J. Improved bufferless routing via balanced pipeline stages. [Internet] [Masters thesis]. Vanderbilt University; 2013. [cited 2020 Jan 23]. Available from: http://etd.library.vanderbilt.edu/available/etd-07072013-145648/ ;.

Council of Science Editors:

Qian J. Improved bufferless routing via balanced pipeline stages. [Masters Thesis]. Vanderbilt University; 2013. Available from: http://etd.library.vanderbilt.edu/available/etd-07072013-145648/ ;


Universidade do Rio Grande do Sul

15. Barcelos, Daniel. Modelo de migração de tarefas para MPSoCs baseados em redes-em-chip.

Degree: 2008, Universidade do Rio Grande do Sul

Em relação a sistemas multiprocessados integrados em uma única pastilha (MPSoC), tanto a alocação dinâmica quanto a migração de tarefas são áreas de pesquisa recentes… (more)

Subjects/Keywords: Task migration; Microeletrônica; Embedded systems; Network-on-chip; Multi-processor systems; Distributed systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Barcelos, D. (2008). Modelo de migração de tarefas para MPSoCs baseados em redes-em-chip. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/14783

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Barcelos, Daniel. “Modelo de migração de tarefas para MPSoCs baseados em redes-em-chip.” 2008. Thesis, Universidade do Rio Grande do Sul. Accessed January 23, 2020. http://hdl.handle.net/10183/14783.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Barcelos, Daniel. “Modelo de migração de tarefas para MPSoCs baseados em redes-em-chip.” 2008. Web. 23 Jan 2020.

Vancouver:

Barcelos D. Modelo de migração de tarefas para MPSoCs baseados em redes-em-chip. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2008. [cited 2020 Jan 23]. Available from: http://hdl.handle.net/10183/14783.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Barcelos D. Modelo de migração de tarefas para MPSoCs baseados em redes-em-chip. [Thesis]. Universidade do Rio Grande do Sul; 2008. Available from: http://hdl.handle.net/10183/14783

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

16. Psarras, Anastasios. High-performance networks-on-chip.

Degree: 2017, Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ)

 Over the last two decades, we have witnessed a fundamental paradigm shift in digital system design: the transition to the multi-core realm. Naturally, the multi-core(more)

Subjects/Keywords: Δίκτυα σε Ολοκληρωμένα Κυκλώματα; Ολοκληρωμένα κυκλώματα; Πολυπύρηνοι επεξεργαστές; Συστήματα σε Ολοκληρωμένα Κυκλώματα; Networks-on-Chip; VLSI; Multi-core architectures; Chip Multi-Processors; System-on-chip; On-chip Interconnection Networks

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Psarras, A. (2017). High-performance networks-on-chip. (Thesis). Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ). Retrieved from http://hdl.handle.net/10442/hedi/41266

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Psarras, Anastasios. “High-performance networks-on-chip.” 2017. Thesis, Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ). Accessed January 23, 2020. http://hdl.handle.net/10442/hedi/41266.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Psarras, Anastasios. “High-performance networks-on-chip.” 2017. Web. 23 Jan 2020.

Vancouver:

Psarras A. High-performance networks-on-chip. [Internet] [Thesis]. Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ); 2017. [cited 2020 Jan 23]. Available from: http://hdl.handle.net/10442/hedi/41266.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Psarras A. High-performance networks-on-chip. [Thesis]. Democritus University of Thrace (DUTH); Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ); 2017. Available from: http://hdl.handle.net/10442/hedi/41266

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Druyer, Rémy. Réseau sur puce sécurisé pour applications cryptographiques sur FPGA : Secure Network-on-Chip for cryptographic applications on FPGA.

Degree: Docteur es, Systèmes automatiques et micro-électroniques, 2017, Montpellier

Que ce soit au travers des smartphones, des consoles de jeux portables ou bientôt des supercalculateurs, les systèmes sur puce (System-on-chip (SoC)) ont vu leur… (more)

Subjects/Keywords: Fpga; Réseau sur puce; Sécurité; Système multi-Processeur sur puce programmable; Fpga; Network-On-Chip; Security; Multi-Processor system on programmable chip (MPSoPC

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Druyer, R. (2017). Réseau sur puce sécurisé pour applications cryptographiques sur FPGA : Secure Network-on-Chip for cryptographic applications on FPGA. (Doctoral Dissertation). Montpellier. Retrieved from http://www.theses.fr/2017MONTS023

Chicago Manual of Style (16th Edition):

Druyer, Rémy. “Réseau sur puce sécurisé pour applications cryptographiques sur FPGA : Secure Network-on-Chip for cryptographic applications on FPGA.” 2017. Doctoral Dissertation, Montpellier. Accessed January 23, 2020. http://www.theses.fr/2017MONTS023.

MLA Handbook (7th Edition):

Druyer, Rémy. “Réseau sur puce sécurisé pour applications cryptographiques sur FPGA : Secure Network-on-Chip for cryptographic applications on FPGA.” 2017. Web. 23 Jan 2020.

Vancouver:

Druyer R. Réseau sur puce sécurisé pour applications cryptographiques sur FPGA : Secure Network-on-Chip for cryptographic applications on FPGA. [Internet] [Doctoral dissertation]. Montpellier; 2017. [cited 2020 Jan 23]. Available from: http://www.theses.fr/2017MONTS023.

Council of Science Editors:

Druyer R. Réseau sur puce sécurisé pour applications cryptographiques sur FPGA : Secure Network-on-Chip for cryptographic applications on FPGA. [Doctoral Dissertation]. Montpellier; 2017. Available from: http://www.theses.fr/2017MONTS023


Rochester Institute of Technology

18. Muszynski, Jesse. Pond IDE: Machine level program development environment and register transfer level simulator for a massively parallel computer architecture.

Degree: Microelectronic Engineering, 2010, Rochester Institute of Technology

 As computing architectures are being implemented in late and post silicon technologies, fault tolerance and concurrent operation are becoming increasingly important. It is already common… (more)

Subjects/Keywords: Massively parallel; Multi-core; Nano architecture; Network on chip; Post silicon; Register transfer level

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Muszynski, J. (2010). Pond IDE: Machine level program development environment and register transfer level simulator for a massively parallel computer architecture. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/7142

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Muszynski, Jesse. “Pond IDE: Machine level program development environment and register transfer level simulator for a massively parallel computer architecture.” 2010. Thesis, Rochester Institute of Technology. Accessed January 23, 2020. https://scholarworks.rit.edu/theses/7142.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Muszynski, Jesse. “Pond IDE: Machine level program development environment and register transfer level simulator for a massively parallel computer architecture.” 2010. Web. 23 Jan 2020.

Vancouver:

Muszynski J. Pond IDE: Machine level program development environment and register transfer level simulator for a massively parallel computer architecture. [Internet] [Thesis]. Rochester Institute of Technology; 2010. [cited 2020 Jan 23]. Available from: https://scholarworks.rit.edu/theses/7142.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Muszynski J. Pond IDE: Machine level program development environment and register transfer level simulator for a massively parallel computer architecture. [Thesis]. Rochester Institute of Technology; 2010. Available from: https://scholarworks.rit.edu/theses/7142

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Berkeley

19. Markovskiy, Yury. A System-level Approach to Fault and Variation Resilience in Multi-core Die.

Degree: Computer Science, 2009, University of California – Berkeley

 With shrinking transistors and growth in parametric variability, statically managing die yield is no longer possible. Design for Manufacturing (DFM) techniques use increasingly bigger guard-bandsthat… (more)

Subjects/Keywords: Computer Science; fault-tolerance; multi-core; network-on-chip; network routing; reliability; VLSI manufacturing yield

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Markovskiy, Y. (2009). A System-level Approach to Fault and Variation Resilience in Multi-core Die. (Thesis). University of California – Berkeley. Retrieved from http://www.escholarship.org/uc/item/0nd0b98v

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Markovskiy, Yury. “A System-level Approach to Fault and Variation Resilience in Multi-core Die.” 2009. Thesis, University of California – Berkeley. Accessed January 23, 2020. http://www.escholarship.org/uc/item/0nd0b98v.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Markovskiy, Yury. “A System-level Approach to Fault and Variation Resilience in Multi-core Die.” 2009. Web. 23 Jan 2020.

Vancouver:

Markovskiy Y. A System-level Approach to Fault and Variation Resilience in Multi-core Die. [Internet] [Thesis]. University of California – Berkeley; 2009. [cited 2020 Jan 23]. Available from: http://www.escholarship.org/uc/item/0nd0b98v.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Markovskiy Y. A System-level Approach to Fault and Variation Resilience in Multi-core Die. [Thesis]. University of California – Berkeley; 2009. Available from: http://www.escholarship.org/uc/item/0nd0b98v

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Colorado State University

20. Pimpalkhute, Tejasi. Heterogeneous prioritization for network-on-chip based multi-core systems.

Degree: MS(M.S.), Electrical and Computer Engineering, 2007, Colorado State University

 In chip multi-processor (CMP) systems, communication and memory access both play an important role in influencing the performance achievable by the system. The manner in… (more)

Subjects/Keywords: multi-core systems; off-chip memory; network-on-chip

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pimpalkhute, T. (2007). Heterogeneous prioritization for network-on-chip based multi-core systems. (Masters Thesis). Colorado State University. Retrieved from http://hdl.handle.net/10217/81054

Chicago Manual of Style (16th Edition):

Pimpalkhute, Tejasi. “Heterogeneous prioritization for network-on-chip based multi-core systems.” 2007. Masters Thesis, Colorado State University. Accessed January 23, 2020. http://hdl.handle.net/10217/81054.

MLA Handbook (7th Edition):

Pimpalkhute, Tejasi. “Heterogeneous prioritization for network-on-chip based multi-core systems.” 2007. Web. 23 Jan 2020.

Vancouver:

Pimpalkhute T. Heterogeneous prioritization for network-on-chip based multi-core systems. [Internet] [Masters thesis]. Colorado State University; 2007. [cited 2020 Jan 23]. Available from: http://hdl.handle.net/10217/81054.

Council of Science Editors:

Pimpalkhute T. Heterogeneous prioritization for network-on-chip based multi-core systems. [Masters Thesis]. Colorado State University; 2007. Available from: http://hdl.handle.net/10217/81054

21. Dahlberg, Christopher. Speeding up matrix computation kernels by sharing vector coprocessor among multiple cores on chip.

Degree: Computer and Electrical Engineering, 2012, Jönköping University

  Today’s computer systems develop towards less energy consumption while keeping high performance. These are contradictory requirement and pose a great challenge. A good example… (more)

Subjects/Keywords: Coprocessor; Speeding-up; Accelerator; Power efficiency; Shared resources; Vector processor; Multi-core on chip; Matrix algorithm; Matrix computation kernels

…next generation of multi-core systems has a different approach, called heterogeneous system… …Multiprocessors (Parallel and multi-core architectures)) A multicore and multiprocessor… …Software Development Kit MicroBlaze Soft Processor Design Preservation Project Navigator CORE… …Processing Unit VP Vector Processor VL Vector Length CSR Compressed Sparse Row FSB Front… …Processing Laboratory (CAPPL). The research has resulted in a Vector co-processor with… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dahlberg, C. (2012). Speeding up matrix computation kernels by sharing vector coprocessor among multiple cores on chip. (Thesis). Jönköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-19292

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dahlberg, Christopher. “Speeding up matrix computation kernels by sharing vector coprocessor among multiple cores on chip.” 2012. Thesis, Jönköping University. Accessed January 23, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-19292.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dahlberg, Christopher. “Speeding up matrix computation kernels by sharing vector coprocessor among multiple cores on chip.” 2012. Web. 23 Jan 2020.

Vancouver:

Dahlberg C. Speeding up matrix computation kernels by sharing vector coprocessor among multiple cores on chip. [Internet] [Thesis]. Jönköping University; 2012. [cited 2020 Jan 23]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-19292.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dahlberg C. Speeding up matrix computation kernels by sharing vector coprocessor among multiple cores on chip. [Thesis]. Jönköping University; 2012. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-19292

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arizona

22. Yoo, Sungjong. Electromagnetic Modeling of Multi-Dimensional Scale Problems: Nanoscale Solar Materials, RF Electronics, Wearable Antennas .

Degree: 2014, University of Arizona

 The use of full wave electromagnetic modeling and simulation tools allows for accurate performance predictions of unique RF structures that exhibit multi-dimensional scales. Full wave… (more)

Subjects/Keywords: Electromagnetic modeling tool; Input impedance matching; Multi core multi chip; Photovoltaics; Zigzag antenna; Electrical & Computer Engineering; Artificial magnetic layer

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yoo, S. (2014). Electromagnetic Modeling of Multi-Dimensional Scale Problems: Nanoscale Solar Materials, RF Electronics, Wearable Antennas . (Doctoral Dissertation). University of Arizona. Retrieved from http://hdl.handle.net/10150/333484

Chicago Manual of Style (16th Edition):

Yoo, Sungjong. “Electromagnetic Modeling of Multi-Dimensional Scale Problems: Nanoscale Solar Materials, RF Electronics, Wearable Antennas .” 2014. Doctoral Dissertation, University of Arizona. Accessed January 23, 2020. http://hdl.handle.net/10150/333484.

MLA Handbook (7th Edition):

Yoo, Sungjong. “Electromagnetic Modeling of Multi-Dimensional Scale Problems: Nanoscale Solar Materials, RF Electronics, Wearable Antennas .” 2014. Web. 23 Jan 2020.

Vancouver:

Yoo S. Electromagnetic Modeling of Multi-Dimensional Scale Problems: Nanoscale Solar Materials, RF Electronics, Wearable Antennas . [Internet] [Doctoral dissertation]. University of Arizona; 2014. [cited 2020 Jan 23]. Available from: http://hdl.handle.net/10150/333484.

Council of Science Editors:

Yoo S. Electromagnetic Modeling of Multi-Dimensional Scale Problems: Nanoscale Solar Materials, RF Electronics, Wearable Antennas . [Doctoral Dissertation]. University of Arizona; 2014. Available from: http://hdl.handle.net/10150/333484


Universidade do Rio Grande do Sul

23. Alves, Marco Antonio Zanata. Avaliação do compartilhamento das memórias cache no desempenho de arquiteturas multi-core.

Degree: 2009, Universidade do Rio Grande do Sul

No atual contexto de inovações em multi-core, em que as novas tecnologias de integração estão fornecendo um número crescente de transistores por chip, o estudo… (more)

Subjects/Keywords: Processamento paralelo; Cache memory; Desempenho : Computadores; Multi-core processor; Memoria cache; Computer architecture; High performance computing

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Alves, M. A. Z. (2009). Avaliação do compartilhamento das memórias cache no desempenho de arquiteturas multi-core. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/16129

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Alves, Marco Antonio Zanata. “Avaliação do compartilhamento das memórias cache no desempenho de arquiteturas multi-core.” 2009. Thesis, Universidade do Rio Grande do Sul. Accessed January 23, 2020. http://hdl.handle.net/10183/16129.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Alves, Marco Antonio Zanata. “Avaliação do compartilhamento das memórias cache no desempenho de arquiteturas multi-core.” 2009. Web. 23 Jan 2020.

Vancouver:

Alves MAZ. Avaliação do compartilhamento das memórias cache no desempenho de arquiteturas multi-core. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2009. [cited 2020 Jan 23]. Available from: http://hdl.handle.net/10183/16129.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Alves MAZ. Avaliação do compartilhamento das memórias cache no desempenho de arquiteturas multi-core. [Thesis]. Universidade do Rio Grande do Sul; 2009. Available from: http://hdl.handle.net/10183/16129

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

24. Marschner, Alexander R. An FPGA-based Target Acquisition System.

Degree: MS, Electrical and Computer Engineering, 2007, Virginia Tech

 This work describes the development of an image processing algorithm, the implementation of that algorithm as both a strictly hardware design and as a multi-core(more)

Subjects/Keywords: OpenFire; multi-core; soft processor; object tracking; image clipping

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Marschner, A. R. (2007). An FPGA-based Target Acquisition System. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/36002

Chicago Manual of Style (16th Edition):

Marschner, Alexander R. “An FPGA-based Target Acquisition System.” 2007. Masters Thesis, Virginia Tech. Accessed January 23, 2020. http://hdl.handle.net/10919/36002.

MLA Handbook (7th Edition):

Marschner, Alexander R. “An FPGA-based Target Acquisition System.” 2007. Web. 23 Jan 2020.

Vancouver:

Marschner AR. An FPGA-based Target Acquisition System. [Internet] [Masters thesis]. Virginia Tech; 2007. [cited 2020 Jan 23]. Available from: http://hdl.handle.net/10919/36002.

Council of Science Editors:

Marschner AR. An FPGA-based Target Acquisition System. [Masters Thesis]. Virginia Tech; 2007. Available from: http://hdl.handle.net/10919/36002


Brunel University

25. Ferhati, Arben. Single-phase laminar flow heat transfer from confined electron beam enhanced surfaces.

Degree: PhD, 2015, Brunel University

 The continuing requirement for computational processing power, multi-functional devices and component miniaturization have emphasised the need for thermal management systems able to maintain the temperature… (more)

Subjects/Keywords: 621.402; Electronic information management; Single/ multi-core processor architecture; Heat dissipation; Thermoelectric cooling technique; Cooling technologies

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ferhati, A. (2015). Single-phase laminar flow heat transfer from confined electron beam enhanced surfaces. (Doctoral Dissertation). Brunel University. Retrieved from http://bura.brunel.ac.uk/handle/2438/13827 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.701927

Chicago Manual of Style (16th Edition):

Ferhati, Arben. “Single-phase laminar flow heat transfer from confined electron beam enhanced surfaces.” 2015. Doctoral Dissertation, Brunel University. Accessed January 23, 2020. http://bura.brunel.ac.uk/handle/2438/13827 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.701927.

MLA Handbook (7th Edition):

Ferhati, Arben. “Single-phase laminar flow heat transfer from confined electron beam enhanced surfaces.” 2015. Web. 23 Jan 2020.

Vancouver:

Ferhati A. Single-phase laminar flow heat transfer from confined electron beam enhanced surfaces. [Internet] [Doctoral dissertation]. Brunel University; 2015. [cited 2020 Jan 23]. Available from: http://bura.brunel.ac.uk/handle/2438/13827 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.701927.

Council of Science Editors:

Ferhati A. Single-phase laminar flow heat transfer from confined electron beam enhanced surfaces. [Doctoral Dissertation]. Brunel University; 2015. Available from: http://bura.brunel.ac.uk/handle/2438/13827 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.701927


Georgia Tech

26. Park, Junhee. Performance scalability of n-tier application in virtualized cloud environments: Two case studies in vertical and horizontal scaling.

Degree: PhD, Computer Science, 2016, Georgia Tech

 The prevalence of multi-core processors with recent advancement in virtualization technologies has enabled horizontal and vertical scaling within a physical node achieving economical sharing of… (more)

Subjects/Keywords: Virtualization; Consolidation; Multi-Core processor; Performance interference; Memory thrashing; Cloud; Scalability; n-Tier; Hypervisor comparison; RUBBoS

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Park, J. (2016). Performance scalability of n-tier application in virtualized cloud environments: Two case studies in vertical and horizontal scaling. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55018

Chicago Manual of Style (16th Edition):

Park, Junhee. “Performance scalability of n-tier application in virtualized cloud environments: Two case studies in vertical and horizontal scaling.” 2016. Doctoral Dissertation, Georgia Tech. Accessed January 23, 2020. http://hdl.handle.net/1853/55018.

MLA Handbook (7th Edition):

Park, Junhee. “Performance scalability of n-tier application in virtualized cloud environments: Two case studies in vertical and horizontal scaling.” 2016. Web. 23 Jan 2020.

Vancouver:

Park J. Performance scalability of n-tier application in virtualized cloud environments: Two case studies in vertical and horizontal scaling. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2020 Jan 23]. Available from: http://hdl.handle.net/1853/55018.

Council of Science Editors:

Park J. Performance scalability of n-tier application in virtualized cloud environments: Two case studies in vertical and horizontal scaling. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55018


Virginia Tech

27. Newcomb, Jamie David. A Scalable Approach to Multi-core Prototyping.

Degree: MS, Electrical and Computer Engineering, 2008, Virginia Tech

 In recent years, multi-core processors and multi-processor networks have grown in popularity as a solution to the limits on increasing clock speed, rising power consumption,… (more)

Subjects/Keywords: multi-gigabit; Aurora; Xilinx; FPGA; multi-processor array; multi-core

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Newcomb, J. D. (2008). A Scalable Approach to Multi-core Prototyping. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31087

Chicago Manual of Style (16th Edition):

Newcomb, Jamie David. “A Scalable Approach to Multi-core Prototyping.” 2008. Masters Thesis, Virginia Tech. Accessed January 23, 2020. http://hdl.handle.net/10919/31087.

MLA Handbook (7th Edition):

Newcomb, Jamie David. “A Scalable Approach to Multi-core Prototyping.” 2008. Web. 23 Jan 2020.

Vancouver:

Newcomb JD. A Scalable Approach to Multi-core Prototyping. [Internet] [Masters thesis]. Virginia Tech; 2008. [cited 2020 Jan 23]. Available from: http://hdl.handle.net/10919/31087.

Council of Science Editors:

Newcomb JD. A Scalable Approach to Multi-core Prototyping. [Masters Thesis]. Virginia Tech; 2008. Available from: http://hdl.handle.net/10919/31087


University of Waterloo

28. Grant, David. A Lightweight Processor Core for Application Specific Acceleration.

Degree: 2004, University of Waterloo

 Advances in configurable logic technology have permitted the development of low-cost, high-speed configurable devices, allowing one or more soft processor cores to be introduced into… (more)

Subjects/Keywords: Electrical & Computer Engineering; system-on-a-chip; application specific acceleration; processor core; tradeoffs

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Grant, D. (2004). A Lightweight Processor Core for Application Specific Acceleration. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/800

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Grant, David. “A Lightweight Processor Core for Application Specific Acceleration.” 2004. Thesis, University of Waterloo. Accessed January 23, 2020. http://hdl.handle.net/10012/800.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Grant, David. “A Lightweight Processor Core for Application Specific Acceleration.” 2004. Web. 23 Jan 2020.

Vancouver:

Grant D. A Lightweight Processor Core for Application Specific Acceleration. [Internet] [Thesis]. University of Waterloo; 2004. [cited 2020 Jan 23]. Available from: http://hdl.handle.net/10012/800.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Grant D. A Lightweight Processor Core for Application Specific Acceleration. [Thesis]. University of Waterloo; 2004. Available from: http://hdl.handle.net/10012/800

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

29. Dwarakanath, Nagendra Gulur. Multi-Core Memory System Design : Developing and using Analytical Models for Performance Evaluation and Enhancements.

Degree: 2015, Indian Institute of Science

 Memory system design is increasingly influencing modern multi-core architectures from both performance and power perspectives. Both main memory latency and bandwidth have im-proved at a… (more)

Subjects/Keywords: Multi Core Architecture; ANATOMY-Cache; DRAM; Off-chip Memory; Off-chip Bandwidth; On-chip Memory Systems; ANATOMY; Multi-Core Memory System; DRAM Cache; Computer System-performance Evaluation; Memory System Design; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dwarakanath, N. G. (2015). Multi-Core Memory System Design : Developing and using Analytical Models for Performance Evaluation and Enhancements. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3935 ; http://etd.iisc.ernet.in/abstracts/4812/G27186-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dwarakanath, Nagendra Gulur. “Multi-Core Memory System Design : Developing and using Analytical Models for Performance Evaluation and Enhancements.” 2015. Thesis, Indian Institute of Science. Accessed January 23, 2020. http://etd.iisc.ernet.in/2005/3935 ; http://etd.iisc.ernet.in/abstracts/4812/G27186-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dwarakanath, Nagendra Gulur. “Multi-Core Memory System Design : Developing and using Analytical Models for Performance Evaluation and Enhancements.” 2015. Web. 23 Jan 2020.

Vancouver:

Dwarakanath NG. Multi-Core Memory System Design : Developing and using Analytical Models for Performance Evaluation and Enhancements. [Internet] [Thesis]. Indian Institute of Science; 2015. [cited 2020 Jan 23]. Available from: http://etd.iisc.ernet.in/2005/3935 ; http://etd.iisc.ernet.in/abstracts/4812/G27186-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dwarakanath NG. Multi-Core Memory System Design : Developing and using Analytical Models for Performance Evaluation and Enhancements. [Thesis]. Indian Institute of Science; 2015. Available from: http://etd.iisc.ernet.in/2005/3935 ; http://etd.iisc.ernet.in/abstracts/4812/G27186-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

30. Das, Reetuparna. Application-Aware On-Chip Networks.

Degree: PhD, Computer Science and Engineering, 2010, Penn State University

Multi-hop packet-based Network-on-Chip (NoC) architectures are widely viewed as the de facto solution for integrating the nodes in many-core architecture for their scalability and well-controlled… (more)

Subjects/Keywords: On-chip networks; multi-core; arbitration; prioritization; memory systems; packet scheduling; slack; criticality; topology; compression; hierarchical

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Das, R. (2010). Application-Aware On-Chip Networks. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/10863

Chicago Manual of Style (16th Edition):

Das, Reetuparna. “Application-Aware On-Chip Networks.” 2010. Doctoral Dissertation, Penn State University. Accessed January 23, 2020. https://etda.libraries.psu.edu/catalog/10863.

MLA Handbook (7th Edition):

Das, Reetuparna. “Application-Aware On-Chip Networks.” 2010. Web. 23 Jan 2020.

Vancouver:

Das R. Application-Aware On-Chip Networks. [Internet] [Doctoral dissertation]. Penn State University; 2010. [cited 2020 Jan 23]. Available from: https://etda.libraries.psu.edu/catalog/10863.

Council of Science Editors:

Das R. Application-Aware On-Chip Networks. [Doctoral Dissertation]. Penn State University; 2010. Available from: https://etda.libraries.psu.edu/catalog/10863

[1] [2] [3] [4] [5] … [643]

.