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You searched for subject:(Charge Pump Phase Locked Loop PLL ). Showing records 1 – 30 of 17793 total matches.

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University of Illinois – Urbana-Champaign

1. Wei, Da. Clock synthesizer design with analog and digital phase locked loop.

Degree: MS, 1200, 2014, University of Illinois – Urbana-Champaign

 As process technology has aggressively scaled, the demand for fast, robust computing has grown tremendously. With the rise of large scale data centers to handhold… (more)

Subjects/Keywords: All Digital Phase-Locked Loop (PLL); Charge Pump Phase-Locked Loop (PLL); Clock Synthesizer; Phase Locked Loop

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wei, D. (2014). Clock synthesizer design with analog and digital phase locked loop. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/50472

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wei, Da. “Clock synthesizer design with analog and digital phase locked loop.” 2014. Thesis, University of Illinois – Urbana-Champaign. Accessed September 18, 2019. http://hdl.handle.net/2142/50472.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wei, Da. “Clock synthesizer design with analog and digital phase locked loop.” 2014. Web. 18 Sep 2019.

Vancouver:

Wei D. Clock synthesizer design with analog and digital phase locked loop. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2014. [cited 2019 Sep 18]. Available from: http://hdl.handle.net/2142/50472.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wei D. Clock synthesizer design with analog and digital phase locked loop. [Thesis]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/50472

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

2. Raghavendra, R G. Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector.

Degree: 2009, Indian Institute of Science

Phase Locked Loop (PLL) is an integral component of clock generation circuits. A third order Charge Pump PLL (CPPLL) is most widely employed PLL architecture… (more)

Subjects/Keywords: Special Devices (Computer Engineering); Analog Frequency Detector; Charge Pump Phase Locked Loop; Phase Locked Loop (PLL); Phase Locked Loop Filters; Phase Locked Loop Filter Design; Summer-Less Dual Charge Pump Based Loop Filters; Loop Filter Design; Computer Engineering

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APA (6th Edition):

Raghavendra, R. G. (2009). Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1006

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Raghavendra, R G. “Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector.” 2009. Thesis, Indian Institute of Science. Accessed September 18, 2019. http://hdl.handle.net/2005/1006.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Raghavendra, R G. “Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector.” 2009. Web. 18 Sep 2019.

Vancouver:

Raghavendra RG. Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector. [Internet] [Thesis]. Indian Institute of Science; 2009. [cited 2019 Sep 18]. Available from: http://hdl.handle.net/2005/1006.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Raghavendra RG. Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector. [Thesis]. Indian Institute of Science; 2009. Available from: http://hdl.handle.net/2005/1006

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arkansas

3. Joshi, Phaniraj. Design of an 866 MHz On-chip Frequency Synthesizer.

Degree: MSEE, 2011, University of Arkansas

  There is a strong need for stable frequency references with large tuning ranges in today's communication systems. While the crystal oscillators assure good frequency… (more)

Subjects/Keywords: Communication and the arts; Applied sciences; Charge pump; Closed loop; Frequency synthesizer; Phase locked loop; Pll; Tristate phase frequency detector; Electrical and Electronics

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APA (6th Edition):

Joshi, P. (2011). Design of an 866 MHz On-chip Frequency Synthesizer. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/143

Chicago Manual of Style (16th Edition):

Joshi, Phaniraj. “Design of an 866 MHz On-chip Frequency Synthesizer.” 2011. Masters Thesis, University of Arkansas. Accessed September 18, 2019. https://scholarworks.uark.edu/etd/143.

MLA Handbook (7th Edition):

Joshi, Phaniraj. “Design of an 866 MHz On-chip Frequency Synthesizer.” 2011. Web. 18 Sep 2019.

Vancouver:

Joshi P. Design of an 866 MHz On-chip Frequency Synthesizer. [Internet] [Masters thesis]. University of Arkansas; 2011. [cited 2019 Sep 18]. Available from: https://scholarworks.uark.edu/etd/143.

Council of Science Editors:

Joshi P. Design of an 866 MHz On-chip Frequency Synthesizer. [Masters Thesis]. University of Arkansas; 2011. Available from: https://scholarworks.uark.edu/etd/143


Indian Institute of Science

4. Manikandan, R R. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.

Degree: 2015, Indian Institute of Science

 There has been a huge rise in interest in the design of energy efficient wireless sensor networks (WSN) and body area networks (BAN) with the… (more)

Subjects/Keywords: Transmitter Architecture; Radio Frequency (RF) Transmitter Circuits; Energy Efficient Wireless Transmitters; Wireless Sensor Networks; Phase-Locked Loop (PLL); Frequency Synthesizer Circuits; Wireless Communication; Charge Pump Phase-Locked Loop (CP-PLL); Analog Integrated Circuits; Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits; Charge Pump Circuits; Electronic Circuits; Spur Suppression Technique; Energy Efficient Transmitters; Communication Engineering

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APA (6th Edition):

Manikandan, R. R. (2015). Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2656 ; http://etd.ncsi.iisc.ernet.in/abstracts/3467/G26869-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Manikandan, R R. “Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.” 2015. Thesis, Indian Institute of Science. Accessed September 18, 2019. http://etd.iisc.ernet.in/handle/2005/2656 ; http://etd.ncsi.iisc.ernet.in/abstracts/3467/G26869-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Manikandan, R R. “Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.” 2015. Web. 18 Sep 2019.

Vancouver:

Manikandan RR. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. [Internet] [Thesis]. Indian Institute of Science; 2015. [cited 2019 Sep 18]. Available from: http://etd.iisc.ernet.in/handle/2005/2656 ; http://etd.ncsi.iisc.ernet.in/abstracts/3467/G26869-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Manikandan RR. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. [Thesis]. Indian Institute of Science; 2015. Available from: http://etd.iisc.ernet.in/handle/2005/2656 ; http://etd.ncsi.iisc.ernet.in/abstracts/3467/G26869-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

5. Manikandan, R R. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.

Degree: 2015, Indian Institute of Science

 There has been a huge rise in interest in the design of energy efficient wireless sensor networks (WSN) and body area networks (BAN) with the… (more)

Subjects/Keywords: Transmitter Architecture; Radio Frequency (RF) Transmitter Circuits; Energy Efficient Wireless Transmitters; Wireless Sensor Networks; Phase-Locked Loop (PLL); Frequency Synthesizer Circuits; Wireless Communication; Charge Pump Phase-Locked Loop (CP-PLL); Analog Integrated Circuits; Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits; Charge Pump Circuits; Electronic Circuits; Spur Suppression Technique; Energy Efficient Transmitters; Communication Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Manikandan, R. R. (2015). Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2656

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Manikandan, R R. “Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.” 2015. Thesis, Indian Institute of Science. Accessed September 18, 2019. http://hdl.handle.net/2005/2656.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Manikandan, R R. “Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.” 2015. Web. 18 Sep 2019.

Vancouver:

Manikandan RR. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. [Internet] [Thesis]. Indian Institute of Science; 2015. [cited 2019 Sep 18]. Available from: http://hdl.handle.net/2005/2656.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Manikandan RR. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. [Thesis]. Indian Institute of Science; 2015. Available from: http://hdl.handle.net/2005/2656

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

6. Liu, Yubo. Design of all digital phase-locked loop in serial link communication.

Degree: MS, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 The speed of wireline and wireless communication systems has been increasing aggressively over the past decade. Multi-GHz clocks are in demand more than ever. In… (more)

Subjects/Keywords: phase-locked loop (PLL); serial link; all digital phase-locked loop (ADPLL); jitter

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APA (6th Edition):

Liu, Y. (2015). Design of all digital phase-locked loop in serial link communication. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78736

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Yubo. “Design of all digital phase-locked loop in serial link communication.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed September 18, 2019. http://hdl.handle.net/2142/78736.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Yubo. “Design of all digital phase-locked loop in serial link communication.” 2015. Web. 18 Sep 2019.

Vancouver:

Liu Y. Design of all digital phase-locked loop in serial link communication. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2019 Sep 18]. Available from: http://hdl.handle.net/2142/78736.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu Y. Design of all digital phase-locked loop in serial link communication. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78736

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


New Jersey Institute of Technology

7. Gundel, Adnan. Low jitter phase-locked loop clock synthesis with wide locking range.

Degree: PhD, Electrical and Computer Engineering, 2007, New Jersey Institute of Technology

  The fast growing demand of wireless and high speed data communications has driven efforts to increase the levels of integration in many communications applications.… (more)

Subjects/Keywords: Phase locked loop (PLL); Voltage-controlled oscillator (VCO); Jitter; Phase noise; Clock synthesizer; Charge pump (CP); Electrical and Electronics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gundel, A. (2007). Low jitter phase-locked loop clock synthesis with wide locking range. (Doctoral Dissertation). New Jersey Institute of Technology. Retrieved from https://digitalcommons.njit.edu/dissertations/815

Chicago Manual of Style (16th Edition):

Gundel, Adnan. “Low jitter phase-locked loop clock synthesis with wide locking range.” 2007. Doctoral Dissertation, New Jersey Institute of Technology. Accessed September 18, 2019. https://digitalcommons.njit.edu/dissertations/815.

MLA Handbook (7th Edition):

Gundel, Adnan. “Low jitter phase-locked loop clock synthesis with wide locking range.” 2007. Web. 18 Sep 2019.

Vancouver:

Gundel A. Low jitter phase-locked loop clock synthesis with wide locking range. [Internet] [Doctoral dissertation]. New Jersey Institute of Technology; 2007. [cited 2019 Sep 18]. Available from: https://digitalcommons.njit.edu/dissertations/815.

Council of Science Editors:

Gundel A. Low jitter phase-locked loop clock synthesis with wide locking range. [Doctoral Dissertation]. New Jersey Institute of Technology; 2007. Available from: https://digitalcommons.njit.edu/dissertations/815


Anna University

8. Sujatha, V. Design and analysis of high Performance charge pump phase lock Loop with low current mismatch and High output impedance; -.

Degree: Information and Communication Engineering, 2014, Anna University

In a Phase Locked Loop PLL the Charge Pump CP circuit is newlineone of the key elements It receives Up and Down signals from the… (more)

Subjects/Keywords: Channel Metal Oxide Semiconductors; Charge Pump Phase Locked Loop; Complementary Metal Oxide Semiconductors; Gain Boosting Charge Pump; High output impedance; High Performance charge pump phase; Information and Communication engineering; Phase Frequency Detector; Phase Locked Loop; Voltage controlled oscillator

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APA (6th Edition):

Sujatha, V. (2014). Design and analysis of high Performance charge pump phase lock Loop with low current mismatch and High output impedance; -. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/24464

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sujatha, V. “Design and analysis of high Performance charge pump phase lock Loop with low current mismatch and High output impedance; -.” 2014. Thesis, Anna University. Accessed September 18, 2019. http://shodhganga.inflibnet.ac.in/handle/10603/24464.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sujatha, V. “Design and analysis of high Performance charge pump phase lock Loop with low current mismatch and High output impedance; -.” 2014. Web. 18 Sep 2019.

Vancouver:

Sujatha V. Design and analysis of high Performance charge pump phase lock Loop with low current mismatch and High output impedance; -. [Internet] [Thesis]. Anna University; 2014. [cited 2019 Sep 18]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/24464.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sujatha V. Design and analysis of high Performance charge pump phase lock Loop with low current mismatch and High output impedance; -. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/24464

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Wright State University

9. Keregudadhahalli, Rajesh Kumar. Costas PLL Loop System for BPSK Detection.

Degree: MSEgr, Electrical Engineering, 2008, Wright State University

  A 2GHz carrier recovery Costas Loop based BPSK detector is designed using CMOS 0.18µm technology. The designed BPSK detector consists of single to differential… (more)

Subjects/Keywords: Electrical Engineering; Costas Phase Locked Loop; PLL Loop System; BPSK Detection

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APA (6th Edition):

Keregudadhahalli, R. K. (2008). Costas PLL Loop System for BPSK Detection. (Masters Thesis). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1220921515

Chicago Manual of Style (16th Edition):

Keregudadhahalli, Rajesh Kumar. “Costas PLL Loop System for BPSK Detection.” 2008. Masters Thesis, Wright State University. Accessed September 18, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=wright1220921515.

MLA Handbook (7th Edition):

Keregudadhahalli, Rajesh Kumar. “Costas PLL Loop System for BPSK Detection.” 2008. Web. 18 Sep 2019.

Vancouver:

Keregudadhahalli RK. Costas PLL Loop System for BPSK Detection. [Internet] [Masters thesis]. Wright State University; 2008. [cited 2019 Sep 18]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1220921515.

Council of Science Editors:

Keregudadhahalli RK. Costas PLL Loop System for BPSK Detection. [Masters Thesis]. Wright State University; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1220921515


McGill University

10. Martin, Louis V. Phase-Locked Loop Simulation in Transient Stabilities Studies.

Degree: M. Eng., Department of Electrical Engineering, 1989, McGill University

Note:

The objective of this thesis was to develop and validate a phase-locked loop (PLL) model suitable for transient stability studies of power systems. Such… (more)

Subjects/Keywords: Phase-locked loop (PLL)

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APA (6th Edition):

Martin, L. V. (1989). Phase-Locked Loop Simulation in Transient Stabilities Studies. (Masters Thesis). McGill University. Retrieved from http://digitool.library.mcgill.ca/thesisfile156013.pdf

Chicago Manual of Style (16th Edition):

Martin, Louis V. “Phase-Locked Loop Simulation in Transient Stabilities Studies.” 1989. Masters Thesis, McGill University. Accessed September 18, 2019. http://digitool.library.mcgill.ca/thesisfile156013.pdf.

MLA Handbook (7th Edition):

Martin, Louis V. “Phase-Locked Loop Simulation in Transient Stabilities Studies.” 1989. Web. 18 Sep 2019.

Vancouver:

Martin LV. Phase-Locked Loop Simulation in Transient Stabilities Studies. [Internet] [Masters thesis]. McGill University; 1989. [cited 2019 Sep 18]. Available from: http://digitool.library.mcgill.ca/thesisfile156013.pdf.

Council of Science Editors:

Martin LV. Phase-Locked Loop Simulation in Transient Stabilities Studies. [Masters Thesis]. McGill University; 1989. Available from: http://digitool.library.mcgill.ca/thesisfile156013.pdf


Lehigh University

11. Alvarez, Ricardo. Design, Simulation, and Implementation of GmC-based Phase Locked Loop.

Degree: MS, Electrical and Computer Engineering, 2018, Lehigh University

 This study explores the design, simulation, and implementation of a transconductance-based Phase Locked Loop system using GmC filters as main building blocks. The system is… (more)

Subjects/Keywords: GmC; Phase Locked Loop; PLL; Transconductance Amplifier; Electrical and Computer Engineering

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APA (6th Edition):

Alvarez, R. (2018). Design, Simulation, and Implementation of GmC-based Phase Locked Loop. (Thesis). Lehigh University. Retrieved from https://preserve.lehigh.edu/etd/4265

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Alvarez, Ricardo. “Design, Simulation, and Implementation of GmC-based Phase Locked Loop.” 2018. Thesis, Lehigh University. Accessed September 18, 2019. https://preserve.lehigh.edu/etd/4265.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Alvarez, Ricardo. “Design, Simulation, and Implementation of GmC-based Phase Locked Loop.” 2018. Web. 18 Sep 2019.

Vancouver:

Alvarez R. Design, Simulation, and Implementation of GmC-based Phase Locked Loop. [Internet] [Thesis]. Lehigh University; 2018. [cited 2019 Sep 18]. Available from: https://preserve.lehigh.edu/etd/4265.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Alvarez R. Design, Simulation, and Implementation of GmC-based Phase Locked Loop. [Thesis]. Lehigh University; 2018. Available from: https://preserve.lehigh.edu/etd/4265

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Washington State University

12. [No author]. LOW POWER LOW NOISE BODY-ENABLED PHASE LOCKED LOOP FOR WIRELINE AND WIRELESS TRANSCEIVERS .

Degree: 2011, Washington State University

 To meet peoplefs needs in social connection, health care and all areas of our IT-fused society, wireline and wireless communication technologies have been the driving… (more)

Subjects/Keywords: Electrical engineering; Charge Pump; Phase Noise; PLL; Transceiver; VCO

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APA (6th Edition):

author], [. (2011). LOW POWER LOW NOISE BODY-ENABLED PHASE LOCKED LOOP FOR WIRELINE AND WIRELESS TRANSCEIVERS . (Thesis). Washington State University. Retrieved from http://hdl.handle.net/2376/3007

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

author], [No. “LOW POWER LOW NOISE BODY-ENABLED PHASE LOCKED LOOP FOR WIRELINE AND WIRELESS TRANSCEIVERS .” 2011. Thesis, Washington State University. Accessed September 18, 2019. http://hdl.handle.net/2376/3007.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

author], [No. “LOW POWER LOW NOISE BODY-ENABLED PHASE LOCKED LOOP FOR WIRELINE AND WIRELESS TRANSCEIVERS .” 2011. Web. 18 Sep 2019.

Vancouver:

author] [. LOW POWER LOW NOISE BODY-ENABLED PHASE LOCKED LOOP FOR WIRELINE AND WIRELESS TRANSCEIVERS . [Internet] [Thesis]. Washington State University; 2011. [cited 2019 Sep 18]. Available from: http://hdl.handle.net/2376/3007.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. LOW POWER LOW NOISE BODY-ENABLED PHASE LOCKED LOOP FOR WIRELINE AND WIRELESS TRANSCEIVERS . [Thesis]. Washington State University; 2011. Available from: http://hdl.handle.net/2376/3007

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

13. Yin, Wenjing. Design techniques for high-performance digital PLLs and CDRs.

Degree: PhD, Electrical and Computer Engineering, 2010, Oregon State University

Phase-Locked Loops (PLLs) are essential building blocks in many communication systems. Designing high performance analog PLLs in the presence of technology imposed constraints such as… (more)

Subjects/Keywords: digital PLL; Phase-locked loops

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APA (6th Edition):

Yin, W. (2010). Design techniques for high-performance digital PLLs and CDRs. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/19407

Chicago Manual of Style (16th Edition):

Yin, Wenjing. “Design techniques for high-performance digital PLLs and CDRs.” 2010. Doctoral Dissertation, Oregon State University. Accessed September 18, 2019. http://hdl.handle.net/1957/19407.

MLA Handbook (7th Edition):

Yin, Wenjing. “Design techniques for high-performance digital PLLs and CDRs.” 2010. Web. 18 Sep 2019.

Vancouver:

Yin W. Design techniques for high-performance digital PLLs and CDRs. [Internet] [Doctoral dissertation]. Oregon State University; 2010. [cited 2019 Sep 18]. Available from: http://hdl.handle.net/1957/19407.

Council of Science Editors:

Yin W. Design techniques for high-performance digital PLLs and CDRs. [Doctoral Dissertation]. Oregon State University; 2010. Available from: http://hdl.handle.net/1957/19407


University of Manchester

14. Gao, Siyu. Grid synchronisation of VSC-HVDC system.

Degree: PhD, 2015, University of Manchester

 This thesis investigates issues affecting grid synchronisation of VSC-HVDC systems with particular regard to, but not limited to, offshore wind power generation during the complex… (more)

Subjects/Keywords: 621.3815; VSC, HVDC, Power System, Power Electronic, Phase-Locked Loop, PLL, MMC, Converter, Control, Modelling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gao, S. (2015). Grid synchronisation of VSC-HVDC system. (Doctoral Dissertation). University of Manchester. Retrieved from https://www.research.manchester.ac.uk/portal/en/theses/grid-synchronisation-of-vschvdc-system(6de14261-b0cd-4a82-bfb9-2ccaae012c4e).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.634913

Chicago Manual of Style (16th Edition):

Gao, Siyu. “Grid synchronisation of VSC-HVDC system.” 2015. Doctoral Dissertation, University of Manchester. Accessed September 18, 2019. https://www.research.manchester.ac.uk/portal/en/theses/grid-synchronisation-of-vschvdc-system(6de14261-b0cd-4a82-bfb9-2ccaae012c4e).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.634913.

MLA Handbook (7th Edition):

Gao, Siyu. “Grid synchronisation of VSC-HVDC system.” 2015. Web. 18 Sep 2019.

Vancouver:

Gao S. Grid synchronisation of VSC-HVDC system. [Internet] [Doctoral dissertation]. University of Manchester; 2015. [cited 2019 Sep 18]. Available from: https://www.research.manchester.ac.uk/portal/en/theses/grid-synchronisation-of-vschvdc-system(6de14261-b0cd-4a82-bfb9-2ccaae012c4e).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.634913.

Council of Science Editors:

Gao S. Grid synchronisation of VSC-HVDC system. [Doctoral Dissertation]. University of Manchester; 2015. Available from: https://www.research.manchester.ac.uk/portal/en/theses/grid-synchronisation-of-vschvdc-system(6de14261-b0cd-4a82-bfb9-2ccaae012c4e).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.634913


Uppsala University

15. Ögren, Jim. PLL design for inverter grid connection : Simulations for ideal and non-ideal grid conditions.

Degree: Disciplinary Domain of Science and Technology, 2010, Uppsala University

  In this report a phase locked loop (PLL) system for grid voltage phase tracking has been investigated. The grid voltage phase angle contains critical… (more)

Subjects/Keywords: PLL; inverter; Phase locked loop; symmetrical optimum method; Engineering physics; Teknisk fysik

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APA (6th Edition):

Ögren, J. (2010). PLL design for inverter grid connection : Simulations for ideal and non-ideal grid conditions. (Thesis). Uppsala University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-156145

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ögren, Jim. “PLL design for inverter grid connection : Simulations for ideal and non-ideal grid conditions.” 2010. Thesis, Uppsala University. Accessed September 18, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-156145.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ögren, Jim. “PLL design for inverter grid connection : Simulations for ideal and non-ideal grid conditions.” 2010. Web. 18 Sep 2019.

Vancouver:

Ögren J. PLL design for inverter grid connection : Simulations for ideal and non-ideal grid conditions. [Internet] [Thesis]. Uppsala University; 2010. [cited 2019 Sep 18]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-156145.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ögren J. PLL design for inverter grid connection : Simulations for ideal and non-ideal grid conditions. [Thesis]. Uppsala University; 2010. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-156145

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Northeastern University

16. Zhao, Jun. A low power CMOS design of an all digital phase locked loop.

Degree: PhD, Department of Electrical and Computer Engineering, 2011, Northeastern University

 This dissertation presents a proposed all digital phase locked loop and a digitally controlled oscillator with low power consumption for fractional-N frequency synthesis applications. The… (more)

Subjects/Keywords: eElectrical engineering; digital phase locked loop; ADPLL; PLL; Electrical and Computer Engineering

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APA (6th Edition):

Zhao, J. (2011). A low power CMOS design of an all digital phase locked loop. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20001051

Chicago Manual of Style (16th Edition):

Zhao, Jun. “A low power CMOS design of an all digital phase locked loop.” 2011. Doctoral Dissertation, Northeastern University. Accessed September 18, 2019. http://hdl.handle.net/2047/d20001051.

MLA Handbook (7th Edition):

Zhao, Jun. “A low power CMOS design of an all digital phase locked loop.” 2011. Web. 18 Sep 2019.

Vancouver:

Zhao J. A low power CMOS design of an all digital phase locked loop. [Internet] [Doctoral dissertation]. Northeastern University; 2011. [cited 2019 Sep 18]. Available from: http://hdl.handle.net/2047/d20001051.

Council of Science Editors:

Zhao J. A low power CMOS design of an all digital phase locked loop. [Doctoral Dissertation]. Northeastern University; 2011. Available from: http://hdl.handle.net/2047/d20001051


California State University – Sacramento

17. Dabhi, Chirag V. Design of a charge pump for a phase locked loop FM synthesizer in 0.5??m CMOS.

Degree: MS, Electrical and Electronic Engineering, 2011, California State University – Sacramento

 The aim of this project was to design, simulate and layout a charge pump for a phase locked loop (PLL) FM synthesizer in a 0.5um… (more)

Subjects/Keywords: PLL; Charge pump; Differential amplifier

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APA (6th Edition):

Dabhi, C. V. (2011). Design of a charge pump for a phase locked loop FM synthesizer in 0.5??m CMOS. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.9/859

Chicago Manual of Style (16th Edition):

Dabhi, Chirag V. “Design of a charge pump for a phase locked loop FM synthesizer in 0.5??m CMOS.” 2011. Masters Thesis, California State University – Sacramento. Accessed September 18, 2019. http://hdl.handle.net/10211.9/859.

MLA Handbook (7th Edition):

Dabhi, Chirag V. “Design of a charge pump for a phase locked loop FM synthesizer in 0.5??m CMOS.” 2011. Web. 18 Sep 2019.

Vancouver:

Dabhi CV. Design of a charge pump for a phase locked loop FM synthesizer in 0.5??m CMOS. [Internet] [Masters thesis]. California State University – Sacramento; 2011. [cited 2019 Sep 18]. Available from: http://hdl.handle.net/10211.9/859.

Council of Science Editors:

Dabhi CV. Design of a charge pump for a phase locked loop FM synthesizer in 0.5??m CMOS. [Masters Thesis]. California State University – Sacramento; 2011. Available from: http://hdl.handle.net/10211.9/859


Brno University of Technology

18. Konečný, Tomáš. Návrh fázového závěsu .

Degree: 2009, Brno University of Technology

 Práce se zabývá návehem fázového závěsu, který bude použit jako násobička kmitočtu. Je představen plně integrovaný fázový závěs s nábojovou pumpou.; Thesis deals with design… (more)

Subjects/Keywords: CMOS; Fázový závěs; PLL; Nábojová pumpa; Frekvenční syntéza; CMOS; Phase locked loop; PLL Current pump; Frequency synthesis

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APA (6th Edition):

Konečný, T. (2009). Návrh fázového závěsu . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/7426

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Konečný, Tomáš. “Návrh fázového závěsu .” 2009. Thesis, Brno University of Technology. Accessed September 18, 2019. http://hdl.handle.net/11012/7426.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Konečný, Tomáš. “Návrh fázového závěsu .” 2009. Web. 18 Sep 2019.

Vancouver:

Konečný T. Návrh fázového závěsu . [Internet] [Thesis]. Brno University of Technology; 2009. [cited 2019 Sep 18]. Available from: http://hdl.handle.net/11012/7426.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Konečný T. Návrh fázového závěsu . [Thesis]. Brno University of Technology; 2009. Available from: http://hdl.handle.net/11012/7426

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

19. Loveless, Thomas Daniel. A radiation-hardened-by-design charge pump for phase-locked loop circuits.

Degree: MS, Electrical Engineering, 2008, Vanderbilt University

 Single-event transients (SETs) due to terrestrial or space radiation exposure have become a growing concern in modern high-speed analog and mixed-signal electronics. Recent work with… (more)

Subjects/Keywords: charge pump; single-event transients; radiation-hardened-by-design; phase-locked loop

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Loveless, T. D. (2008). A radiation-hardened-by-design charge pump for phase-locked loop circuits. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-01292008-150433/ ;

Chicago Manual of Style (16th Edition):

Loveless, Thomas Daniel. “A radiation-hardened-by-design charge pump for phase-locked loop circuits.” 2008. Masters Thesis, Vanderbilt University. Accessed September 18, 2019. http://etd.library.vanderbilt.edu/available/etd-01292008-150433/ ;.

MLA Handbook (7th Edition):

Loveless, Thomas Daniel. “A radiation-hardened-by-design charge pump for phase-locked loop circuits.” 2008. Web. 18 Sep 2019.

Vancouver:

Loveless TD. A radiation-hardened-by-design charge pump for phase-locked loop circuits. [Internet] [Masters thesis]. Vanderbilt University; 2008. [cited 2019 Sep 18]. Available from: http://etd.library.vanderbilt.edu/available/etd-01292008-150433/ ;.

Council of Science Editors:

Loveless TD. A radiation-hardened-by-design charge pump for phase-locked loop circuits. [Masters Thesis]. Vanderbilt University; 2008. Available from: http://etd.library.vanderbilt.edu/available/etd-01292008-150433/ ;


University of Alberta

20. Wang, Yifei. Grid phase and harmonic detection using cascaded delayed signal cancellation technique.

Degree: MS, Department of Electrical and Computer Engineering, 2011, University of Alberta

 Power converters are indispensable in modern energy conversion and utilization systems. For their control, there are two interesting topics: one is grid phase detection for… (more)

Subjects/Keywords: harmonic detection; delayed signal cancellation (DSC); phase-locked loop (PLL); cascaded delayed signal cancellation (CDSC); grid phase detection

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APA (6th Edition):

Wang, Y. (2011). Grid phase and harmonic detection using cascaded delayed signal cancellation technique. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/gm80hv95v

Chicago Manual of Style (16th Edition):

Wang, Yifei. “Grid phase and harmonic detection using cascaded delayed signal cancellation technique.” 2011. Masters Thesis, University of Alberta. Accessed September 18, 2019. https://era.library.ualberta.ca/files/gm80hv95v.

MLA Handbook (7th Edition):

Wang, Yifei. “Grid phase and harmonic detection using cascaded delayed signal cancellation technique.” 2011. Web. 18 Sep 2019.

Vancouver:

Wang Y. Grid phase and harmonic detection using cascaded delayed signal cancellation technique. [Internet] [Masters thesis]. University of Alberta; 2011. [cited 2019 Sep 18]. Available from: https://era.library.ualberta.ca/files/gm80hv95v.

Council of Science Editors:

Wang Y. Grid phase and harmonic detection using cascaded delayed signal cancellation technique. [Masters Thesis]. University of Alberta; 2011. Available from: https://era.library.ualberta.ca/files/gm80hv95v


Kyoto University / 京都大学

21. Kim, Sinnyoung. Analysis and Design of Radiation-Hardened Phase-Locked Loop : 放射線耐性を持つPLLの解析と設計.

Degree: 博士(情報学), 2014, Kyoto University / 京都大学

新制・課程博士

甲第18413号

情博第528号

Subjects/Keywords: Phase-Locked Loop (PLL); Soft error; Radiation-Hardened PLL (RH-PLL)

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APA (6th Edition):

Kim, S. (2014). Analysis and Design of Radiation-Hardened Phase-Locked Loop : 放射線耐性を持つPLLの解析と設計. (Thesis). Kyoto University / 京都大学. Retrieved from http://hdl.handle.net/2433/188872 ; http://dx.doi.org/10.14989/doctor.k18413

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kim, Sinnyoung. “Analysis and Design of Radiation-Hardened Phase-Locked Loop : 放射線耐性を持つPLLの解析と設計.” 2014. Thesis, Kyoto University / 京都大学. Accessed September 18, 2019. http://hdl.handle.net/2433/188872 ; http://dx.doi.org/10.14989/doctor.k18413.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kim, Sinnyoung. “Analysis and Design of Radiation-Hardened Phase-Locked Loop : 放射線耐性を持つPLLの解析と設計.” 2014. Web. 18 Sep 2019.

Vancouver:

Kim S. Analysis and Design of Radiation-Hardened Phase-Locked Loop : 放射線耐性を持つPLLの解析と設計. [Internet] [Thesis]. Kyoto University / 京都大学; 2014. [cited 2019 Sep 18]. Available from: http://hdl.handle.net/2433/188872 ; http://dx.doi.org/10.14989/doctor.k18413.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim S. Analysis and Design of Radiation-Hardened Phase-Locked Loop : 放射線耐性を持つPLLの解析と設計. [Thesis]. Kyoto University / 京都大学; 2014. Available from: http://hdl.handle.net/2433/188872 ; http://dx.doi.org/10.14989/doctor.k18413

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

22. Daniels, Brian. Analysis and design of high order digital phase locked loops.

Degree: 2008, RIAN

 The Phase Locked Loop (PLL) is an important component of many electronic devices; it can be employed as a frequency synthesizer, for clock data recovery,… (more)

Subjects/Keywords: Electronic Engineering; Phase locked loop (PLL); High order digital phased locked loop(DPLL).

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APA (6th Edition):

Daniels, B. (2008). Analysis and design of high order digital phase locked loops. (Thesis). RIAN. Retrieved from http://eprints.maynoothuniversity.ie/1492/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Daniels, Brian. “Analysis and design of high order digital phase locked loops.” 2008. Thesis, RIAN. Accessed September 18, 2019. http://eprints.maynoothuniversity.ie/1492/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Daniels, Brian. “Analysis and design of high order digital phase locked loops.” 2008. Web. 18 Sep 2019.

Vancouver:

Daniels B. Analysis and design of high order digital phase locked loops. [Internet] [Thesis]. RIAN; 2008. [cited 2019 Sep 18]. Available from: http://eprints.maynoothuniversity.ie/1492/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Daniels B. Analysis and design of high order digital phase locked loops. [Thesis]. RIAN; 2008. Available from: http://eprints.maynoothuniversity.ie/1492/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

23. Jeon, Hyung-Joon. Design of Mixed-mode Adaptive Loop Gain Bang-Bang Clock and Data Recovery and Process-Variation-Resilient Current Mode Logic.

Degree: 2013, Texas A&M University

 As the volume of data processed by computers and telecommunication devices rapidly increases, high speed serial link has been challenged to maximize its I/O bandwidth… (more)

Subjects/Keywords: Integrated circuit; Mixed signal; Serial link; Clock and Data Recovery; CDR; Current Mode Logic; CML; Phase Locked Loop; PLL

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APA (6th Edition):

Jeon, H. (2013). Design of Mixed-mode Adaptive Loop Gain Bang-Bang Clock and Data Recovery and Process-Variation-Resilient Current Mode Logic. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149205

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jeon, Hyung-Joon. “Design of Mixed-mode Adaptive Loop Gain Bang-Bang Clock and Data Recovery and Process-Variation-Resilient Current Mode Logic.” 2013. Thesis, Texas A&M University. Accessed September 18, 2019. http://hdl.handle.net/1969.1/149205.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jeon, Hyung-Joon. “Design of Mixed-mode Adaptive Loop Gain Bang-Bang Clock and Data Recovery and Process-Variation-Resilient Current Mode Logic.” 2013. Web. 18 Sep 2019.

Vancouver:

Jeon H. Design of Mixed-mode Adaptive Loop Gain Bang-Bang Clock and Data Recovery and Process-Variation-Resilient Current Mode Logic. [Internet] [Thesis]. Texas A&M University; 2013. [cited 2019 Sep 18]. Available from: http://hdl.handle.net/1969.1/149205.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jeon H. Design of Mixed-mode Adaptive Loop Gain Bang-Bang Clock and Data Recovery and Process-Variation-Resilient Current Mode Logic. [Thesis]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149205

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Western Ontario

24. Baradarani, Farzam. A Phase-Angle Tracking Method for Synchronization of Single- and Three-Phase Grid-Connected Converters.

Degree: 2014, University of Western Ontario

 This thesis proposes a phase-angle tracking method, i.e., based on discrete Fourier transform for synchronization of three-phase and single-phase power-electronic converters under distorted and variable-frequency… (more)

Subjects/Keywords: Digital synchronization of power-electronic converters; Discrete Fourier transform (DFT); phasor-estimation; phase-locked loop (PLL); Power and Energy; Signal Processing

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APA (6th Edition):

Baradarani, F. (2014). A Phase-Angle Tracking Method for Synchronization of Single- and Three-Phase Grid-Connected Converters. (Thesis). University of Western Ontario. Retrieved from https://ir.lib.uwo.ca/etd/2415

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Baradarani, Farzam. “A Phase-Angle Tracking Method for Synchronization of Single- and Three-Phase Grid-Connected Converters.” 2014. Thesis, University of Western Ontario. Accessed September 18, 2019. https://ir.lib.uwo.ca/etd/2415.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Baradarani, Farzam. “A Phase-Angle Tracking Method for Synchronization of Single- and Three-Phase Grid-Connected Converters.” 2014. Web. 18 Sep 2019.

Vancouver:

Baradarani F. A Phase-Angle Tracking Method for Synchronization of Single- and Three-Phase Grid-Connected Converters. [Internet] [Thesis]. University of Western Ontario; 2014. [cited 2019 Sep 18]. Available from: https://ir.lib.uwo.ca/etd/2415.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Baradarani F. A Phase-Angle Tracking Method for Synchronization of Single- and Three-Phase Grid-Connected Converters. [Thesis]. University of Western Ontario; 2014. Available from: https://ir.lib.uwo.ca/etd/2415

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

25. Wu, Zhengzheng. Microelectromechanical Systems for Wireless Radio Front-ends and Integrated Frequency References.

Degree: PhD, Electrical Engineering, 2014, University of Michigan

 Microelectromechanical systems (MEMS) have great potential in realizing chip-scale integrated devices for energy-efficient analog spectrum processing. This thesis presents the development of a new class… (more)

Subjects/Keywords: MEMS and RF MEMS; Resonator and Oscillator; Radio Frequency (RF); Integrated Circuit (IC); Phase-locked Loop (PLL); Filter; Electrical Engineering; Engineering

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APA (6th Edition):

Wu, Z. (2014). Microelectromechanical Systems for Wireless Radio Front-ends and Integrated Frequency References. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/109069

Chicago Manual of Style (16th Edition):

Wu, Zhengzheng. “Microelectromechanical Systems for Wireless Radio Front-ends and Integrated Frequency References.” 2014. Doctoral Dissertation, University of Michigan. Accessed September 18, 2019. http://hdl.handle.net/2027.42/109069.

MLA Handbook (7th Edition):

Wu, Zhengzheng. “Microelectromechanical Systems for Wireless Radio Front-ends and Integrated Frequency References.” 2014. Web. 18 Sep 2019.

Vancouver:

Wu Z. Microelectromechanical Systems for Wireless Radio Front-ends and Integrated Frequency References. [Internet] [Doctoral dissertation]. University of Michigan; 2014. [cited 2019 Sep 18]. Available from: http://hdl.handle.net/2027.42/109069.

Council of Science Editors:

Wu Z. Microelectromechanical Systems for Wireless Radio Front-ends and Integrated Frequency References. [Doctoral Dissertation]. University of Michigan; 2014. Available from: http://hdl.handle.net/2027.42/109069


Uppsala University

26. Moberg, Caroline. Development of measurement algorithm in an industrial PLC : An evaluation of DSOGI-PLL for real time measurements.

Degree: Engineering Sciences, 2019, Uppsala University

  The aim of this project was to devise an algorithm for three phase AC power grid measurements that could be utilized in an excitation… (more)

Subjects/Keywords: Phase locked loop; DSOGI-PLL; Symmetrical component extraction; Measurement algorithm; Other Electrical Engineering, Electronic Engineering, Information Engineering; Annan elektroteknik och elektronik

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APA (6th Edition):

Moberg, C. (2019). Development of measurement algorithm in an industrial PLC : An evaluation of DSOGI-PLL for real time measurements. (Thesis). Uppsala University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-388490

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Moberg, Caroline. “Development of measurement algorithm in an industrial PLC : An evaluation of DSOGI-PLL for real time measurements.” 2019. Thesis, Uppsala University. Accessed September 18, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-388490.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Moberg, Caroline. “Development of measurement algorithm in an industrial PLC : An evaluation of DSOGI-PLL for real time measurements.” 2019. Web. 18 Sep 2019.

Vancouver:

Moberg C. Development of measurement algorithm in an industrial PLC : An evaluation of DSOGI-PLL for real time measurements. [Internet] [Thesis]. Uppsala University; 2019. [cited 2019 Sep 18]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-388490.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Moberg C. Development of measurement algorithm in an industrial PLC : An evaluation of DSOGI-PLL for real time measurements. [Thesis]. Uppsala University; 2019. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-388490

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

27. Park, Sang Wook. Oscillator Architectures and Enhanced Frequency Synthesizer.

Degree: 2009, Texas A&M University

 A voltage controlled oscillator (VCO), that generates a periodic signal whose frequency is tuned by a voltage, is a key building block in any integrated… (more)

Subjects/Keywords: Oscillator; Phase locked loop

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APA (6th Edition):

Park, S. W. (2009). Oscillator Architectures and Enhanced Frequency Synthesizer. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/148445

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Park, Sang Wook. “Oscillator Architectures and Enhanced Frequency Synthesizer.” 2009. Thesis, Texas A&M University. Accessed September 18, 2019. http://hdl.handle.net/1969.1/148445.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Park, Sang Wook. “Oscillator Architectures and Enhanced Frequency Synthesizer.” 2009. Web. 18 Sep 2019.

Vancouver:

Park SW. Oscillator Architectures and Enhanced Frequency Synthesizer. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2019 Sep 18]. Available from: http://hdl.handle.net/1969.1/148445.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Park SW. Oscillator Architectures and Enhanced Frequency Synthesizer. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/148445

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Nova

28. Leandro, Gonçalo Alexandre Raposeiro. Digital PLL for ISM applications.

Degree: 2017, Universidade Nova

 In modern transceivers, a low power PLL is a key block. It is known that with the evolution of technology, lower power and high performance… (more)

Subjects/Keywords: PLL; VCO; Divider; Charge Pump; Loop Filter; Low Power; Domínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Leandro, G. A. R. (2017). Digital PLL for ISM applications. (Thesis). Universidade Nova. Retrieved from https://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/30818

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Leandro, Gonçalo Alexandre Raposeiro. “Digital PLL for ISM applications.” 2017. Thesis, Universidade Nova. Accessed September 18, 2019. https://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/30818.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Leandro, Gonçalo Alexandre Raposeiro. “Digital PLL for ISM applications.” 2017. Web. 18 Sep 2019.

Vancouver:

Leandro GAR. Digital PLL for ISM applications. [Internet] [Thesis]. Universidade Nova; 2017. [cited 2019 Sep 18]. Available from: https://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/30818.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Leandro GAR. Digital PLL for ISM applications. [Thesis]. Universidade Nova; 2017. Available from: https://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/30818

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

29. Jeon, Hyung-Joon. A 10Gb/s Full On-chip Bang-Bang Clock and Data Recovery System Using an Adaptive Loop Bandwidth Strategy.

Degree: 2010, Texas A&M University

 As demand for higher bandwidth I/O grows, the front end design of serial link becomes significant to overcome stringent timing requirements on noisy and bandwidthlimited… (more)

Subjects/Keywords: CDR; PLL; Clock and Data Recovery; Phase-Locked Loop; Serial Link; SONET; OC-192; Adaptive loop bandwidth; capacitance multiplication; half-rate phase detector

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jeon, H. (2010). A 10Gb/s Full On-chip Bang-Bang Clock and Data Recovery System Using an Adaptive Loop Bandwidth Strategy. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2009-08-7183

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jeon, Hyung-Joon. “A 10Gb/s Full On-chip Bang-Bang Clock and Data Recovery System Using an Adaptive Loop Bandwidth Strategy.” 2010. Thesis, Texas A&M University. Accessed September 18, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2009-08-7183.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jeon, Hyung-Joon. “A 10Gb/s Full On-chip Bang-Bang Clock and Data Recovery System Using an Adaptive Loop Bandwidth Strategy.” 2010. Web. 18 Sep 2019.

Vancouver:

Jeon H. A 10Gb/s Full On-chip Bang-Bang Clock and Data Recovery System Using an Adaptive Loop Bandwidth Strategy. [Internet] [Thesis]. Texas A&M University; 2010. [cited 2019 Sep 18]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-08-7183.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jeon H. A 10Gb/s Full On-chip Bang-Bang Clock and Data Recovery System Using an Adaptive Loop Bandwidth Strategy. [Thesis]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-08-7183

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

30. Cheng, Shanfeng. Design of CMOS integrated phase-locked loops for multi-gigabits serial data links.

Degree: 2007, Texas A&M University

 High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication… (more)

Subjects/Keywords: Phase-locked Loops; PLL; Clock and Data Recovery; CDR; Jitter; Phase Noise; VCO; Charge Pump; Phase Detector; Frequency Detector; Voltage-Controlled Oscillator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cheng, S. (2007). Design of CMOS integrated phase-locked loops for multi-gigabits serial data links. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/4954

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cheng, Shanfeng. “Design of CMOS integrated phase-locked loops for multi-gigabits serial data links.” 2007. Thesis, Texas A&M University. Accessed September 18, 2019. http://hdl.handle.net/1969.1/4954.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cheng, Shanfeng. “Design of CMOS integrated phase-locked loops for multi-gigabits serial data links.” 2007. Web. 18 Sep 2019.

Vancouver:

Cheng S. Design of CMOS integrated phase-locked loops for multi-gigabits serial data links. [Internet] [Thesis]. Texas A&M University; 2007. [cited 2019 Sep 18]. Available from: http://hdl.handle.net/1969.1/4954.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cheng S. Design of CMOS integrated phase-locked loops for multi-gigabits serial data links. [Thesis]. Texas A&M University; 2007. Available from: http://hdl.handle.net/1969.1/4954

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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