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You searched for subject:(Capacitor mismatch). Showing records 1 – 4 of 4 total matches.

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1. 小松, 直樹. ノイズシェーピング構成とミスマッチシェーパーを用いた自己校正型パイプラインADCに関する研究 : A pipelined ADC using background calibration with mismatch shaper and noise shaping architecture.

Degree: 2012, Hosei University / 法政大学

 A novel background calibration technique for capacitor mismatches is proposed in this paper. The capacitor mismatch is one of the non-ideal factors in the pipelined… (more)

Subjects/Keywords: Capacitor mismatch; Digital Calibration; NSDEM; Pipelined ADC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

小松, . (2012). ノイズシェーピング構成とミスマッチシェーパーを用いた自己校正型パイプラインADCに関する研究 : A pipelined ADC using background calibration with mismatch shaper and noise shaping architecture. (Thesis). Hosei University / 法政大学. Retrieved from http://hdl.handle.net/10114/7619

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

小松, 直樹. “ノイズシェーピング構成とミスマッチシェーパーを用いた自己校正型パイプラインADCに関する研究 : A pipelined ADC using background calibration with mismatch shaper and noise shaping architecture.” 2012. Thesis, Hosei University / 法政大学. Accessed September 24, 2020. http://hdl.handle.net/10114/7619.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

小松, 直樹. “ノイズシェーピング構成とミスマッチシェーパーを用いた自己校正型パイプラインADCに関する研究 : A pipelined ADC using background calibration with mismatch shaper and noise shaping architecture.” 2012. Web. 24 Sep 2020.

Vancouver:

小松 . ノイズシェーピング構成とミスマッチシェーパーを用いた自己校正型パイプラインADCに関する研究 : A pipelined ADC using background calibration with mismatch shaper and noise shaping architecture. [Internet] [Thesis]. Hosei University / 法政大学; 2012. [cited 2020 Sep 24]. Available from: http://hdl.handle.net/10114/7619.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

小松 . ノイズシェーピング構成とミスマッチシェーパーを用いた自己校正型パイプラインADCに関する研究 : A pipelined ADC using background calibration with mismatch shaper and noise shaping architecture. [Thesis]. Hosei University / 法政大学; 2012. Available from: http://hdl.handle.net/10114/7619

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. Lindeberg, Johan. Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal Calibration.

Degree: The Institute of Technology, 2014, Linköping UniversityLinköping University

  The objective of this Master's thesis was to design and implement a low power Analog to Digital Converter (ADC) used for sensor measurements. In… (more)

Subjects/Keywords: Analog to Digital Converter (ADC); Cyclic; Algorithmic; Incremental; Capacitor mismatch; Compensation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lindeberg, J. (2014). Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal Calibration. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103229

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lindeberg, Johan. “Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal Calibration.” 2014. Thesis, Linköping UniversityLinköping University. Accessed September 24, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103229.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lindeberg, Johan. “Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal Calibration.” 2014. Web. 24 Sep 2020.

Vancouver:

Lindeberg J. Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal Calibration. [Internet] [Thesis]. Linköping UniversityLinköping University; 2014. [cited 2020 Sep 24]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103229.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lindeberg J. Design and Implementation of a Low-Power SAR-ADC with Flexible Sample-Rate and Internal Calibration. [Thesis]. Linköping UniversityLinköping University; 2014. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103229

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Washington

3. Li, Shuowei. PCAST: A Practical Capacitor Array Synthesizer Targeted for SAR-ADC Implementation.

Degree: 2017, University of Washington

 In this thesis, we introduce PCAST, a practical capacitor array synthesizer targeted for SAR-ADC implementation developed in the SKILL language, which is natively supported by… (more)

Subjects/Keywords: Capacitor array; Layout automation; Mismatch characterization; Parasitics; Electrical engineering; Electrical engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, S. (2017). PCAST: A Practical Capacitor Array Synthesizer Targeted for SAR-ADC Implementation. (Thesis). University of Washington. Retrieved from http://hdl.handle.net/1773/40052

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Shuowei. “PCAST: A Practical Capacitor Array Synthesizer Targeted for SAR-ADC Implementation.” 2017. Thesis, University of Washington. Accessed September 24, 2020. http://hdl.handle.net/1773/40052.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Shuowei. “PCAST: A Practical Capacitor Array Synthesizer Targeted for SAR-ADC Implementation.” 2017. Web. 24 Sep 2020.

Vancouver:

Li S. PCAST: A Practical Capacitor Array Synthesizer Targeted for SAR-ADC Implementation. [Internet] [Thesis]. University of Washington; 2017. [cited 2020 Sep 24]. Available from: http://hdl.handle.net/1773/40052.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li S. PCAST: A Practical Capacitor Array Synthesizer Targeted for SAR-ADC Implementation. [Thesis]. University of Washington; 2017. Available from: http://hdl.handle.net/1773/40052

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

4. Lee, Seungchul. Digital calibration of nonlinear memory errors in sigma-delta ADCs.

Degree: PhD, 1200, 2012, University of Illinois – Urbana-Champaign

 Background digital calibration techniques based on an output-referred error model are proposed to linearize sigma-delta (ΣΔ) modulators. A sequential power series (a special form of… (more)

Subjects/Keywords: Analog-to-digital converter; ΣΔ modulator; low gain amplifier; nonlinear distortion; memory error; quantization noise leakage; digital calibration; correlation; test signal; digital-to-analog converter; capacitor mismatch; piecewise linear model; independent component analysis; multi-stage delta-sigma (MASH) structure

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lee, S. (2012). Digital calibration of nonlinear memory errors in sigma-delta ADCs. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/34543

Chicago Manual of Style (16th Edition):

Lee, Seungchul. “Digital calibration of nonlinear memory errors in sigma-delta ADCs.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 24, 2020. http://hdl.handle.net/2142/34543.

MLA Handbook (7th Edition):

Lee, Seungchul. “Digital calibration of nonlinear memory errors in sigma-delta ADCs.” 2012. Web. 24 Sep 2020.

Vancouver:

Lee S. Digital calibration of nonlinear memory errors in sigma-delta ADCs. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2020 Sep 24]. Available from: http://hdl.handle.net/2142/34543.

Council of Science Editors:

Lee S. Digital calibration of nonlinear memory errors in sigma-delta ADCs. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/34543

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