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You searched for subject:(Caches). Showing records 1 – 30 of 60 total matches.

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Penn State University

1. Muralidhara, Sai Prashanth. Reducing Interference in Memory Hierarchy Resources Using Application Aware Management.

Degree: 2011, Penn State University

 Aggressive technology scaling has resulted in an increase in number of cores being integrated on-chip. While on-chip cores are increasing at a fast rate, the… (more)

Subjects/Keywords: Multicores; memory hierarchy; caches; DRAM

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APA (6th Edition):

Muralidhara, S. P. (2011). Reducing Interference in Memory Hierarchy Resources Using Application Aware Management. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/12150

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Muralidhara, Sai Prashanth. “Reducing Interference in Memory Hierarchy Resources Using Application Aware Management.” 2011. Thesis, Penn State University. Accessed March 06, 2021. https://submit-etda.libraries.psu.edu/catalog/12150.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Muralidhara, Sai Prashanth. “Reducing Interference in Memory Hierarchy Resources Using Application Aware Management.” 2011. Web. 06 Mar 2021.

Vancouver:

Muralidhara SP. Reducing Interference in Memory Hierarchy Resources Using Application Aware Management. [Internet] [Thesis]. Penn State University; 2011. [cited 2021 Mar 06]. Available from: https://submit-etda.libraries.psu.edu/catalog/12150.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Muralidhara SP. Reducing Interference in Memory Hierarchy Resources Using Application Aware Management. [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/12150

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

2. Kim, Soontae. ENERGY-EFFICIENT HIGH PERFORMANCE CACHE ARCHITECTURES.

Degree: 2008, Penn State University

 The demand for high-performance architectures and powerful battery-operated mobile devices has accentuated the need for low-power systems. In many media and embedded applications, the memory… (more)

Subjects/Keywords: energy; performance; caches

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APA (6th Edition):

Kim, S. (2008). ENERGY-EFFICIENT HIGH PERFORMANCE CACHE ARCHITECTURES. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/6183

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kim, Soontae. “ENERGY-EFFICIENT HIGH PERFORMANCE CACHE ARCHITECTURES.” 2008. Thesis, Penn State University. Accessed March 06, 2021. https://submit-etda.libraries.psu.edu/catalog/6183.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kim, Soontae. “ENERGY-EFFICIENT HIGH PERFORMANCE CACHE ARCHITECTURES.” 2008. Web. 06 Mar 2021.

Vancouver:

Kim S. ENERGY-EFFICIENT HIGH PERFORMANCE CACHE ARCHITECTURES. [Internet] [Thesis]. Penn State University; 2008. [cited 2021 Mar 06]. Available from: https://submit-etda.libraries.psu.edu/catalog/6183.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim S. ENERGY-EFFICIENT HIGH PERFORMANCE CACHE ARCHITECTURES. [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/6183

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

3. Soares, Livio. Operating System Techniques for Reducing Processor State Pollution.

Degree: 2012, University of Toronto

Application performance on modern processors has become increasingly dictated by the use of on-chip structures, such as caches and look-aside buffers. The hierarchical (multi-leveled) design… (more)

Subjects/Keywords: Operating Systems; Processors; Processor Caches; Multicore; 0984

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APA (6th Edition):

Soares, L. (2012). Operating System Techniques for Reducing Processor State Pollution. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/32895

Chicago Manual of Style (16th Edition):

Soares, Livio. “Operating System Techniques for Reducing Processor State Pollution.” 2012. Doctoral Dissertation, University of Toronto. Accessed March 06, 2021. http://hdl.handle.net/1807/32895.

MLA Handbook (7th Edition):

Soares, Livio. “Operating System Techniques for Reducing Processor State Pollution.” 2012. Web. 06 Mar 2021.

Vancouver:

Soares L. Operating System Techniques for Reducing Processor State Pollution. [Internet] [Doctoral dissertation]. University of Toronto; 2012. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/1807/32895.

Council of Science Editors:

Soares L. Operating System Techniques for Reducing Processor State Pollution. [Doctoral Dissertation]. University of Toronto; 2012. Available from: http://hdl.handle.net/1807/32895


University of Arizona

4. Gajaria, Dhruv Mayur. DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors .

Degree: 2019, University of Arizona

 Spin-transfer torque RAMs (STT-RAMs) have been studied as a promising alternative to SRAMs in emerging caches and main memories due to their low leakage power… (more)

Subjects/Keywords: Caches; DVFS; Multi-Core Processors; STT-RAM

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APA (6th Edition):

Gajaria, D. M. (2019). DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/633246

Chicago Manual of Style (16th Edition):

Gajaria, Dhruv Mayur. “DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors .” 2019. Masters Thesis, University of Arizona. Accessed March 06, 2021. http://hdl.handle.net/10150/633246.

MLA Handbook (7th Edition):

Gajaria, Dhruv Mayur. “DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors .” 2019. Web. 06 Mar 2021.

Vancouver:

Gajaria DM. DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors . [Internet] [Masters thesis]. University of Arizona; 2019. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/10150/633246.

Council of Science Editors:

Gajaria DM. DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors . [Masters Thesis]. University of Arizona; 2019. Available from: http://hdl.handle.net/10150/633246


University of Texas – Austin

5. -9048-1017. Exploiting long-term behavior for improved memory system performance.

Degree: PhD, Computer science, 2016, University of Texas – Austin

 Memory latency is a key bottleneck for many programs. Caching and prefetching are two popular hardware mechanisms to alleviate the impact of long memory latencies,… (more)

Subjects/Keywords: Caches; Replacement policy; Prefetching; Memory system

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APA (6th Edition):

-9048-1017. (2016). Exploiting long-term behavior for improved memory system performance. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/42015

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

-9048-1017. “Exploiting long-term behavior for improved memory system performance.” 2016. Doctoral Dissertation, University of Texas – Austin. Accessed March 06, 2021. http://hdl.handle.net/2152/42015.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

-9048-1017. “Exploiting long-term behavior for improved memory system performance.” 2016. Web. 06 Mar 2021.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

-9048-1017. Exploiting long-term behavior for improved memory system performance. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2016. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/2152/42015.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

-9048-1017. Exploiting long-term behavior for improved memory system performance. [Doctoral Dissertation]. University of Texas – Austin; 2016. Available from: http://hdl.handle.net/2152/42015

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

6. Oliveira, Jacqueline Augusto de. "Uso de caches na Web - Influência das políticas de substituição de objetos".

Degree: Mestrado, Ciências de Computação e Matemática Computacional, 2004, University of São Paulo

Este trabalho tem como objetivo analisar a influência provocada pelas políticas de substituição de objetos em caches na Web. Isso é feito por meio da… (more)

Subjects/Keywords: caches web; políticas de substituição; replacement policies; web caches

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APA (6th Edition):

Oliveira, J. A. d. (2004). "Uso de caches na Web - Influência das políticas de substituição de objetos". (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/55/55134/tde-26072004-121404/ ;

Chicago Manual of Style (16th Edition):

Oliveira, Jacqueline Augusto de. “"Uso de caches na Web - Influência das políticas de substituição de objetos".” 2004. Masters Thesis, University of São Paulo. Accessed March 06, 2021. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-26072004-121404/ ;.

MLA Handbook (7th Edition):

Oliveira, Jacqueline Augusto de. “"Uso de caches na Web - Influência das políticas de substituição de objetos".” 2004. Web. 06 Mar 2021.

Vancouver:

Oliveira JAd. "Uso de caches na Web - Influência das políticas de substituição de objetos". [Internet] [Masters thesis]. University of São Paulo; 2004. [cited 2021 Mar 06]. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-26072004-121404/ ;.

Council of Science Editors:

Oliveira JAd. "Uso de caches na Web - Influência das políticas de substituição de objetos". [Masters Thesis]. University of São Paulo; 2004. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-26072004-121404/ ;


Universitat Politècnica de València

7. Valero Bresó, Alejandro. Hybrid caches: design and data management .

Degree: 2013, Universitat Politècnica de València

 Cache memories have been usually implemented with Static Random-Access Memory (SRAM) technology since it is the fastest electronic memory technology. However, this technology consumes a… (more)

Subjects/Keywords: Cache memories; EDRAM technology; Energy consumption; Hybrid caches; Last-Level Caches; Macrocell; MRU-Tour; Performance; Replacement algorithms; Selective refresh; SRAM technology

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APA (6th Edition):

Valero Bresó, A. (2013). Hybrid caches: design and data management . (Doctoral Dissertation). Universitat Politècnica de València. Retrieved from http://hdl.handle.net/10251/32663

Chicago Manual of Style (16th Edition):

Valero Bresó, Alejandro. “Hybrid caches: design and data management .” 2013. Doctoral Dissertation, Universitat Politècnica de València. Accessed March 06, 2021. http://hdl.handle.net/10251/32663.

MLA Handbook (7th Edition):

Valero Bresó, Alejandro. “Hybrid caches: design and data management .” 2013. Web. 06 Mar 2021.

Vancouver:

Valero Bresó A. Hybrid caches: design and data management . [Internet] [Doctoral dissertation]. Universitat Politècnica de València; 2013. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/10251/32663.

Council of Science Editors:

Valero Bresó A. Hybrid caches: design and data management . [Doctoral Dissertation]. Universitat Politècnica de València; 2013. Available from: http://hdl.handle.net/10251/32663

8. Péneau, Pierre-Yves. Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique : Integration of emerging non volatile memory technologies in cache hierarchy for improving energy-efficiency.

Degree: Docteur es, Systèmes automatiques et micro-électroniques, 2018, Montpellier

De nos jours, des efforts majeurs pour la conception de systèmes sur puces performants et efficaces énergétiquement sont en cours. Le déclin de la loi… (more)

Subjects/Keywords: Efficacité énergétique; Stt-Mram; Hiérarchie mémoire; Caches; Llc; Energy-Efficiency; Stt-Mram; Memory hierarchy; Caches; Llc

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APA (6th Edition):

Péneau, P. (2018). Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique : Integration of emerging non volatile memory technologies in cache hierarchy for improving energy-efficiency. (Doctoral Dissertation). Montpellier. Retrieved from http://www.theses.fr/2018MONTS108

Chicago Manual of Style (16th Edition):

Péneau, Pierre-Yves. “Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique : Integration of emerging non volatile memory technologies in cache hierarchy for improving energy-efficiency.” 2018. Doctoral Dissertation, Montpellier. Accessed March 06, 2021. http://www.theses.fr/2018MONTS108.

MLA Handbook (7th Edition):

Péneau, Pierre-Yves. “Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique : Integration of emerging non volatile memory technologies in cache hierarchy for improving energy-efficiency.” 2018. Web. 06 Mar 2021.

Vancouver:

Péneau P. Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique : Integration of emerging non volatile memory technologies in cache hierarchy for improving energy-efficiency. [Internet] [Doctoral dissertation]. Montpellier; 2018. [cited 2021 Mar 06]. Available from: http://www.theses.fr/2018MONTS108.

Council of Science Editors:

Péneau P. Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique : Integration of emerging non volatile memory technologies in cache hierarchy for improving energy-efficiency. [Doctoral Dissertation]. Montpellier; 2018. Available from: http://www.theses.fr/2018MONTS108


Penn State University

9. Kotra, Jagadish Babu. HARDWARE SOFTWARE CO-DESIGN FOR OPTIMIZING MEMORY HIERARCHY IN MANY-CORE AND MULTI-SOCKET SYSTEMS.

Degree: 2017, Penn State University

 Thanks to Moore’s law, the number of transistors on a chip have been increasing over time without increasing area of the processing die. The increased… (more)

Subjects/Keywords: Hardware-software co-design; memory hierarchy; manycore processors; memory; caches

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APA (6th Edition):

Kotra, J. B. (2017). HARDWARE SOFTWARE CO-DESIGN FOR OPTIMIZING MEMORY HIERARCHY IN MANY-CORE AND MULTI-SOCKET SYSTEMS. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/14830jbk5155

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kotra, Jagadish Babu. “HARDWARE SOFTWARE CO-DESIGN FOR OPTIMIZING MEMORY HIERARCHY IN MANY-CORE AND MULTI-SOCKET SYSTEMS.” 2017. Thesis, Penn State University. Accessed March 06, 2021. https://submit-etda.libraries.psu.edu/catalog/14830jbk5155.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kotra, Jagadish Babu. “HARDWARE SOFTWARE CO-DESIGN FOR OPTIMIZING MEMORY HIERARCHY IN MANY-CORE AND MULTI-SOCKET SYSTEMS.” 2017. Web. 06 Mar 2021.

Vancouver:

Kotra JB. HARDWARE SOFTWARE CO-DESIGN FOR OPTIMIZING MEMORY HIERARCHY IN MANY-CORE AND MULTI-SOCKET SYSTEMS. [Internet] [Thesis]. Penn State University; 2017. [cited 2021 Mar 06]. Available from: https://submit-etda.libraries.psu.edu/catalog/14830jbk5155.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kotra JB. HARDWARE SOFTWARE CO-DESIGN FOR OPTIMIZING MEMORY HIERARCHY IN MANY-CORE AND MULTI-SOCKET SYSTEMS. [Thesis]. Penn State University; 2017. Available from: https://submit-etda.libraries.psu.edu/catalog/14830jbk5155

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

10. Bhatia, Eshan. Perceptron Learning in Cache Management and Prediction Techniques.

Degree: MS, Computer Engineering, 2019, Texas A&M University

 Hardware prefetching is an effective technique for hiding cache miss latencies in modern processor designs. An efficient prefetcher should identify complex memory access patterns during… (more)

Subjects/Keywords: Computer Architecture; Caches

…pre-load the needed data into the processor’s caches in a timely manner. Memory access… …be stored in, and deciding what data should be evicted from the caches to accommodate the… 

Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7

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APA (6th Edition):

Bhatia, E. (2019). Perceptron Learning in Cache Management and Prediction Techniques. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/185028

Chicago Manual of Style (16th Edition):

Bhatia, Eshan. “Perceptron Learning in Cache Management and Prediction Techniques.” 2019. Masters Thesis, Texas A&M University. Accessed March 06, 2021. http://hdl.handle.net/1969.1/185028.

MLA Handbook (7th Edition):

Bhatia, Eshan. “Perceptron Learning in Cache Management and Prediction Techniques.” 2019. Web. 06 Mar 2021.

Vancouver:

Bhatia E. Perceptron Learning in Cache Management and Prediction Techniques. [Internet] [Masters thesis]. Texas A&M University; 2019. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/1969.1/185028.

Council of Science Editors:

Bhatia E. Perceptron Learning in Cache Management and Prediction Techniques. [Masters Thesis]. Texas A&M University; 2019. Available from: http://hdl.handle.net/1969.1/185028

11. Panda, Reena. A Branch-Directed Data Cache Prefetching Technique for Inorder Processors.

Degree: MS, Computer Engineering, 2012, Texas A&M University

 The increasing gap between processor and main memory speeds has become a serious bottleneck towards further improvement in system performance. Data prefetching techniques have been… (more)

Subjects/Keywords: Caches; Prefetching; Inorder Processors

…growing gap between memory and processor speeds. One such technique is the use of “caches” [… …also been proposed to the cache implementation and handling, like lock-up free caches [2… …control flow sequence of a program. It caches pairs of branch instruction PCs, where the second… 

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APA (6th Edition):

Panda, R. (2012). A Branch-Directed Data Cache Prefetching Technique for Inorder Processors. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10287

Chicago Manual of Style (16th Edition):

Panda, Reena. “A Branch-Directed Data Cache Prefetching Technique for Inorder Processors.” 2012. Masters Thesis, Texas A&M University. Accessed March 06, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10287.

MLA Handbook (7th Edition):

Panda, Reena. “A Branch-Directed Data Cache Prefetching Technique for Inorder Processors.” 2012. Web. 06 Mar 2021.

Vancouver:

Panda R. A Branch-Directed Data Cache Prefetching Technique for Inorder Processors. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10287.

Council of Science Editors:

Panda R. A Branch-Directed Data Cache Prefetching Technique for Inorder Processors. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10287


Brigham Young University

12. Ostler, Michaela Ann. Chiapa de Corzo Mound 3 Revisited: Burials, Caches, and Architecture.

Degree: MA, 2017, Brigham Young University

 Chiapa de Corzo Mound 3 was excavated by Tim Tucker under the direction of the New World Archaeological Foundation in July 1965. Mound 3 is… (more)

Subjects/Keywords: Chiapa de Corzo; burials; caches; architecture; function; NWAF; ceramics

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APA (6th Edition):

Ostler, M. A. (2017). Chiapa de Corzo Mound 3 Revisited: Burials, Caches, and Architecture. (Masters Thesis). Brigham Young University. Retrieved from https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9540&context=etd

Chicago Manual of Style (16th Edition):

Ostler, Michaela Ann. “Chiapa de Corzo Mound 3 Revisited: Burials, Caches, and Architecture.” 2017. Masters Thesis, Brigham Young University. Accessed March 06, 2021. https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9540&context=etd.

MLA Handbook (7th Edition):

Ostler, Michaela Ann. “Chiapa de Corzo Mound 3 Revisited: Burials, Caches, and Architecture.” 2017. Web. 06 Mar 2021.

Vancouver:

Ostler MA. Chiapa de Corzo Mound 3 Revisited: Burials, Caches, and Architecture. [Internet] [Masters thesis]. Brigham Young University; 2017. [cited 2021 Mar 06]. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9540&context=etd.

Council of Science Editors:

Ostler MA. Chiapa de Corzo Mound 3 Revisited: Burials, Caches, and Architecture. [Masters Thesis]. Brigham Young University; 2017. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9540&context=etd


Brigham Young University

13. Ostler, Michaela Ann. Chiapa de Corzo Mound 3 Revisited: Burials, Caches, and Architecture.

Degree: MA, 2017, Brigham Young University

  Chiapa de Corzo Mound 3 was excavated by Tim Tucker under the direction of the New World Archaeological Foundation in July 1965. Mound 3… (more)

Subjects/Keywords: Chiapa de Corzo; burials; caches; architecture; function; NWAF; ceramics; Anthropology

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ostler, M. A. (2017). Chiapa de Corzo Mound 3 Revisited: Burials, Caches, and Architecture. (Masters Thesis). Brigham Young University. Retrieved from https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9538&context=etd

Chicago Manual of Style (16th Edition):

Ostler, Michaela Ann. “Chiapa de Corzo Mound 3 Revisited: Burials, Caches, and Architecture.” 2017. Masters Thesis, Brigham Young University. Accessed March 06, 2021. https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9538&context=etd.

MLA Handbook (7th Edition):

Ostler, Michaela Ann. “Chiapa de Corzo Mound 3 Revisited: Burials, Caches, and Architecture.” 2017. Web. 06 Mar 2021.

Vancouver:

Ostler MA. Chiapa de Corzo Mound 3 Revisited: Burials, Caches, and Architecture. [Internet] [Masters thesis]. Brigham Young University; 2017. [cited 2021 Mar 06]. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9538&context=etd.

Council of Science Editors:

Ostler MA. Chiapa de Corzo Mound 3 Revisited: Burials, Caches, and Architecture. [Masters Thesis]. Brigham Young University; 2017. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=9538&context=etd


University of Toronto

14. Nacouzi, Michel El. On Optimizing Die-stacked DRAM Caches.

Degree: 2013, University of Toronto

Die-stacking is a new technology that allows multiple integrated circuits to be stacked on top of each other while connected with a high-bandwidth and high-speed… (more)

Subjects/Keywords: Die-Stacked DRAM caches; Computer Architecture; 0984; 0544; 0537

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APA (6th Edition):

Nacouzi, M. E. (2013). On Optimizing Die-stacked DRAM Caches. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/42831

Chicago Manual of Style (16th Edition):

Nacouzi, Michel El. “On Optimizing Die-stacked DRAM Caches.” 2013. Masters Thesis, University of Toronto. Accessed March 06, 2021. http://hdl.handle.net/1807/42831.

MLA Handbook (7th Edition):

Nacouzi, Michel El. “On Optimizing Die-stacked DRAM Caches.” 2013. Web. 06 Mar 2021.

Vancouver:

Nacouzi ME. On Optimizing Die-stacked DRAM Caches. [Internet] [Masters thesis]. University of Toronto; 2013. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/1807/42831.

Council of Science Editors:

Nacouzi ME. On Optimizing Die-stacked DRAM Caches. [Masters Thesis]. University of Toronto; 2013. Available from: http://hdl.handle.net/1807/42831


Delft University of Technology

15. De Langen, P.J. Energy reduction techniques for caches and multiprocessors.

Degree: 2009, Delft University of Technology

Subjects/Keywords: energy reduction; caches; multiprocessor scheduling

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APA (6th Edition):

De Langen, P. J. (2009). Energy reduction techniques for caches and multiprocessors. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:4060494b-3725-4abc-aefb-8235fd05871c ; urn:NBN:nl:ui:24-uuid:4060494b-3725-4abc-aefb-8235fd05871c ; urn:NBN:nl:ui:24-uuid:4060494b-3725-4abc-aefb-8235fd05871c ; http://resolver.tudelft.nl/uuid:4060494b-3725-4abc-aefb-8235fd05871c

Chicago Manual of Style (16th Edition):

De Langen, P J. “Energy reduction techniques for caches and multiprocessors.” 2009. Doctoral Dissertation, Delft University of Technology. Accessed March 06, 2021. http://resolver.tudelft.nl/uuid:4060494b-3725-4abc-aefb-8235fd05871c ; urn:NBN:nl:ui:24-uuid:4060494b-3725-4abc-aefb-8235fd05871c ; urn:NBN:nl:ui:24-uuid:4060494b-3725-4abc-aefb-8235fd05871c ; http://resolver.tudelft.nl/uuid:4060494b-3725-4abc-aefb-8235fd05871c.

MLA Handbook (7th Edition):

De Langen, P J. “Energy reduction techniques for caches and multiprocessors.” 2009. Web. 06 Mar 2021.

Vancouver:

De Langen PJ. Energy reduction techniques for caches and multiprocessors. [Internet] [Doctoral dissertation]. Delft University of Technology; 2009. [cited 2021 Mar 06]. Available from: http://resolver.tudelft.nl/uuid:4060494b-3725-4abc-aefb-8235fd05871c ; urn:NBN:nl:ui:24-uuid:4060494b-3725-4abc-aefb-8235fd05871c ; urn:NBN:nl:ui:24-uuid:4060494b-3725-4abc-aefb-8235fd05871c ; http://resolver.tudelft.nl/uuid:4060494b-3725-4abc-aefb-8235fd05871c.

Council of Science Editors:

De Langen PJ. Energy reduction techniques for caches and multiprocessors. [Doctoral Dissertation]. Delft University of Technology; 2009. Available from: http://resolver.tudelft.nl/uuid:4060494b-3725-4abc-aefb-8235fd05871c ; urn:NBN:nl:ui:24-uuid:4060494b-3725-4abc-aefb-8235fd05871c ; urn:NBN:nl:ui:24-uuid:4060494b-3725-4abc-aefb-8235fd05871c ; http://resolver.tudelft.nl/uuid:4060494b-3725-4abc-aefb-8235fd05871c

16. Hamelin, Claire. Couples de spin-orbite en vue d'applications aux mémoires cache : Spin orbit torques for cache memory applications.

Degree: Docteur es, Nanophysique, 2016, Université Grenoble Alpes (ComUE)

Le remplacement des technologies DRAM et SRAM des mémoires caches est un enjeu pour l’industrie microélectronique qui doit faire face à des demandes de miniaturisation,… (more)

Subjects/Keywords: Spintronique; Mémoires caches; Nanomagnétisme; Spintronic; Cache memory; Nanomagnetism; 530

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APA (6th Edition):

Hamelin, C. (2016). Couples de spin-orbite en vue d'applications aux mémoires cache : Spin orbit torques for cache memory applications. (Doctoral Dissertation). Université Grenoble Alpes (ComUE). Retrieved from http://www.theses.fr/2016GREAY061

Chicago Manual of Style (16th Edition):

Hamelin, Claire. “Couples de spin-orbite en vue d'applications aux mémoires cache : Spin orbit torques for cache memory applications.” 2016. Doctoral Dissertation, Université Grenoble Alpes (ComUE). Accessed March 06, 2021. http://www.theses.fr/2016GREAY061.

MLA Handbook (7th Edition):

Hamelin, Claire. “Couples de spin-orbite en vue d'applications aux mémoires cache : Spin orbit torques for cache memory applications.” 2016. Web. 06 Mar 2021.

Vancouver:

Hamelin C. Couples de spin-orbite en vue d'applications aux mémoires cache : Spin orbit torques for cache memory applications. [Internet] [Doctoral dissertation]. Université Grenoble Alpes (ComUE); 2016. [cited 2021 Mar 06]. Available from: http://www.theses.fr/2016GREAY061.

Council of Science Editors:

Hamelin C. Couples de spin-orbite en vue d'applications aux mémoires cache : Spin orbit torques for cache memory applications. [Doctoral Dissertation]. Université Grenoble Alpes (ComUE); 2016. Available from: http://www.theses.fr/2016GREAY061

17. Díaz, Pedro. Mechanisms to improve the efficiency of hardware data prefetchers.

Degree: PhD, 2011, University of Edinburgh

 A well known performance bottleneck in computer architecture is the so-called memory wall. This term refers to the huge disparity between on-chip and off-chip access… (more)

Subjects/Keywords: 004; prefetching; caches; hardware

…sensitivity for 256KB, 512KB and 2MB L2 caches. . . 55 4.2 L2 cache Read Hit Rate for 256KB… …512KB and 2MB L2 caches. . . . 56 4.3 Number of L2 cache accesses per 1K instructions… …instruction caches [19], I/O [20] or the TLB [9]. Moreover, data… …caches higher in the hierarchy, and therefore prefetching is more important for hiding the… …replacement for second level caches. The conclusion of this analysis is that for the benchmarks… 

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APA (6th Edition):

Díaz, P. (2011). Mechanisms to improve the efficiency of hardware data prefetchers. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/5650

Chicago Manual of Style (16th Edition):

Díaz, Pedro. “Mechanisms to improve the efficiency of hardware data prefetchers.” 2011. Doctoral Dissertation, University of Edinburgh. Accessed March 06, 2021. http://hdl.handle.net/1842/5650.

MLA Handbook (7th Edition):

Díaz, Pedro. “Mechanisms to improve the efficiency of hardware data prefetchers.” 2011. Web. 06 Mar 2021.

Vancouver:

Díaz P. Mechanisms to improve the efficiency of hardware data prefetchers. [Internet] [Doctoral dissertation]. University of Edinburgh; 2011. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/1842/5650.

Council of Science Editors:

Díaz P. Mechanisms to improve the efficiency of hardware data prefetchers. [Doctoral Dissertation]. University of Edinburgh; 2011. Available from: http://hdl.handle.net/1842/5650

18. Tian, Yingying. Reducing Waste in Memory Hierarchies.

Degree: PhD, Computer Science, 2015, Texas A&M University

 Memory hierarchies play an important role in microarchitectural design to bridge the performance gap between modern microprocessors and main memory. However, memory hierarchies are inefficient… (more)

Subjects/Keywords: Caches; cache management

…temporal locality and spatial locality, respectively. Caches [106] store instructions… …and data that exhibit locality with low access latencies. Caches are usually small and fast… …compared to the main memory. References to memory locations that are stored in caches can be… …However, in practices caches are often inefficient because they store useless or redundant data… …1.1.1 Waste of Dead Blocks Caches organize data and instructions into fixed-sized blocks of… 

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APA (6th Edition):

Tian, Y. (2015). Reducing Waste in Memory Hierarchies. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/155075

Chicago Manual of Style (16th Edition):

Tian, Yingying. “Reducing Waste in Memory Hierarchies.” 2015. Doctoral Dissertation, Texas A&M University. Accessed March 06, 2021. http://hdl.handle.net/1969.1/155075.

MLA Handbook (7th Edition):

Tian, Yingying. “Reducing Waste in Memory Hierarchies.” 2015. Web. 06 Mar 2021.

Vancouver:

Tian Y. Reducing Waste in Memory Hierarchies. [Internet] [Doctoral dissertation]. Texas A&M University; 2015. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/1969.1/155075.

Council of Science Editors:

Tian Y. Reducing Waste in Memory Hierarchies. [Doctoral Dissertation]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/155075


Virginia Tech

19. Sharma, Niti. Impact of Increased Cache Misses on Runtime Performance of MPX-enabled Programs.

Degree: MS, Computer Science and Applications, 2019, Virginia Tech

 Low level programming languages like C and C++ are primary choices to write low-level systems software such as operating systems, virtual machines, embedded software, and… (more)

Subjects/Keywords: Spatial Security; Memory Protection Extensions; Caches; Benchmarks; Runtime; Overheads; TLB

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sharma, N. (2019). Impact of Increased Cache Misses on Runtime Performance of MPX-enabled Programs. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/89914

Chicago Manual of Style (16th Edition):

Sharma, Niti. “Impact of Increased Cache Misses on Runtime Performance of MPX-enabled Programs.” 2019. Masters Thesis, Virginia Tech. Accessed March 06, 2021. http://hdl.handle.net/10919/89914.

MLA Handbook (7th Edition):

Sharma, Niti. “Impact of Increased Cache Misses on Runtime Performance of MPX-enabled Programs.” 2019. Web. 06 Mar 2021.

Vancouver:

Sharma N. Impact of Increased Cache Misses on Runtime Performance of MPX-enabled Programs. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/10919/89914.

Council of Science Editors:

Sharma N. Impact of Increased Cache Misses on Runtime Performance of MPX-enabled Programs. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/89914

20. Kommanaboina, Kishor Yadav. Auto-Determination of Cache/TLB parameters.

Degree: MS, Computer Science and Engineering, 2013, The Ohio State University

 Modern optimizing compilers are adept at performing transformations like loop tiling, fusion, etc. The improvement in performance achieved by compilers due to these transformations relies… (more)

Subjects/Keywords: Computer Science; Cache; TLB; Microbenchmarks; inclusive caches; exclusive caches

…28 3.4 Determining lower level of caches… …27 Figure 5 : A1 < A2 with exclusive caches… …of the different levels of caches and TLBs. Having accurate information about these… …memory hierarchy like Data caches and TLBs are presented. 1.1 Objective Our objective is to… …Caches hold frequently accessed blocks of main memory. They improve performance by reducing the… 

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APA (6th Edition):

Kommanaboina, K. Y. (2013). Auto-Determination of Cache/TLB parameters. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1367581773

Chicago Manual of Style (16th Edition):

Kommanaboina, Kishor Yadav. “Auto-Determination of Cache/TLB parameters.” 2013. Masters Thesis, The Ohio State University. Accessed March 06, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=osu1367581773.

MLA Handbook (7th Edition):

Kommanaboina, Kishor Yadav. “Auto-Determination of Cache/TLB parameters.” 2013. Web. 06 Mar 2021.

Vancouver:

Kommanaboina KY. Auto-Determination of Cache/TLB parameters. [Internet] [Masters thesis]. The Ohio State University; 2013. [cited 2021 Mar 06]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1367581773.

Council of Science Editors:

Kommanaboina KY. Auto-Determination of Cache/TLB parameters. [Masters Thesis]. The Ohio State University; 2013. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1367581773


University of Rochester

21. Shriraman, Arrvindh. Architectural techniques for memory oversight in multiprocessors.

Degree: PhD, 2011, University of Rochester

 Computer architects have exploited the transistors afforded by Moore’s law to provide software developers with high performance computing resources. Software has translated this growth in… (more)

Subjects/Keywords: Memory hierarchy; Caches; Cache coherence; Monitoring; Isolation; Protection; Transactional memory; RTM; FlexTM; Sentry

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APA (6th Edition):

Shriraman, A. (2011). Architectural techniques for memory oversight in multiprocessors. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/14180

Chicago Manual of Style (16th Edition):

Shriraman, Arrvindh. “Architectural techniques for memory oversight in multiprocessors.” 2011. Doctoral Dissertation, University of Rochester. Accessed March 06, 2021. http://hdl.handle.net/1802/14180.

MLA Handbook (7th Edition):

Shriraman, Arrvindh. “Architectural techniques for memory oversight in multiprocessors.” 2011. Web. 06 Mar 2021.

Vancouver:

Shriraman A. Architectural techniques for memory oversight in multiprocessors. [Internet] [Doctoral dissertation]. University of Rochester; 2011. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/1802/14180.

Council of Science Editors:

Shriraman A. Architectural techniques for memory oversight in multiprocessors. [Doctoral Dissertation]. University of Rochester; 2011. Available from: http://hdl.handle.net/1802/14180


Cornell University

22. Ismail, Mohamed. Hardware-Software Co-optimization for Dynamic Languages.

Degree: PhD, Electrical and Computer Engineering, 2019, Cornell University

 As software becomes more complex and the costs of developing and maintaining code increase, dynamic programming languages such as Python are becoming more desirable alternatives… (more)

Subjects/Keywords: Computer engineering; caches; dynamic languages; JavaScript; memory management; Python; Computer science; Engineering

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APA (6th Edition):

Ismail, M. (2019). Hardware-Software Co-optimization for Dynamic Languages. (Doctoral Dissertation). Cornell University. Retrieved from http://hdl.handle.net/1813/67721

Chicago Manual of Style (16th Edition):

Ismail, Mohamed. “Hardware-Software Co-optimization for Dynamic Languages.” 2019. Doctoral Dissertation, Cornell University. Accessed March 06, 2021. http://hdl.handle.net/1813/67721.

MLA Handbook (7th Edition):

Ismail, Mohamed. “Hardware-Software Co-optimization for Dynamic Languages.” 2019. Web. 06 Mar 2021.

Vancouver:

Ismail M. Hardware-Software Co-optimization for Dynamic Languages. [Internet] [Doctoral dissertation]. Cornell University; 2019. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/1813/67721.

Council of Science Editors:

Ismail M. Hardware-Software Co-optimization for Dynamic Languages. [Doctoral Dissertation]. Cornell University; 2019. Available from: http://hdl.handle.net/1813/67721


Penn State University

23. Shah, Shail Paragbhai. CHARACTERIZING AND OPTIMIZING ON-CHIP SHARED MEMORY RESOURCES USING MARKET-DRIVEN MECHANISMS.

Degree: 2019, Penn State University

 Heterogeneous applications often share memory resources such as last-level caches and memory bandwidth within the many-core system deployed in the IaaS model. The performance of… (more)

Subjects/Keywords: Resource Allocation; last level caches; characterization; memory bandwidth; auction mechanism; game theory

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APA (6th Edition):

Shah, S. P. (2019). CHARACTERIZING AND OPTIMIZING ON-CHIP SHARED MEMORY RESOURCES USING MARKET-DRIVEN MECHANISMS. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/16496sks5698

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shah, Shail Paragbhai. “CHARACTERIZING AND OPTIMIZING ON-CHIP SHARED MEMORY RESOURCES USING MARKET-DRIVEN MECHANISMS.” 2019. Thesis, Penn State University. Accessed March 06, 2021. https://submit-etda.libraries.psu.edu/catalog/16496sks5698.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shah, Shail Paragbhai. “CHARACTERIZING AND OPTIMIZING ON-CHIP SHARED MEMORY RESOURCES USING MARKET-DRIVEN MECHANISMS.” 2019. Web. 06 Mar 2021.

Vancouver:

Shah SP. CHARACTERIZING AND OPTIMIZING ON-CHIP SHARED MEMORY RESOURCES USING MARKET-DRIVEN MECHANISMS. [Internet] [Thesis]. Penn State University; 2019. [cited 2021 Mar 06]. Available from: https://submit-etda.libraries.psu.edu/catalog/16496sks5698.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shah SP. CHARACTERIZING AND OPTIMIZING ON-CHIP SHARED MEMORY RESOURCES USING MARKET-DRIVEN MECHANISMS. [Thesis]. Penn State University; 2019. Available from: https://submit-etda.libraries.psu.edu/catalog/16496sks5698

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

24. Patrick, Christina M. Minimizing End-To-End Interference in I/O Stacks Spanning Shared Multi-Level Buffer Caches .

Degree: 2011, Penn State University

 Service providers and IT solutions generally favor shared resources to avoid excessive cost and over-provisioning. Most applications access shared storage servers through a multi-level buffer… (more)

Subjects/Keywords: storage cache; interference; Multi-level buffer caches; performance; I/O; disk; cache

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APA (6th Edition):

Patrick, C. M. (2011). Minimizing End-To-End Interference in I/O Stacks Spanning Shared Multi-Level Buffer Caches . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/11776

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Patrick, Christina M. “Minimizing End-To-End Interference in I/O Stacks Spanning Shared Multi-Level Buffer Caches .” 2011. Thesis, Penn State University. Accessed March 06, 2021. https://submit-etda.libraries.psu.edu/catalog/11776.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Patrick, Christina M. “Minimizing End-To-End Interference in I/O Stacks Spanning Shared Multi-Level Buffer Caches .” 2011. Web. 06 Mar 2021.

Vancouver:

Patrick CM. Minimizing End-To-End Interference in I/O Stacks Spanning Shared Multi-Level Buffer Caches . [Internet] [Thesis]. Penn State University; 2011. [cited 2021 Mar 06]. Available from: https://submit-etda.libraries.psu.edu/catalog/11776.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Patrick CM. Minimizing End-To-End Interference in I/O Stacks Spanning Shared Multi-Level Buffer Caches . [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/11776

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Michigan Technological University

25. Byrne, Daniel. mPart: Miss Ratio Curve Guided Partitioning in Key-Value Stores.

Degree: MS, Department of Computer Science, 2018, Michigan Technological University

  Web applications employ key-value stores to cache the data that is most commonly accessed. The cache improves an web application’s performance by serving its… (more)

Subjects/Keywords: Cloud Computing; Caches; Multi-tenant Architectures; Key-Value Stores; Miss Ratio Curves; Data Storage Systems

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APA (6th Edition):

Byrne, D. (2018). mPart: Miss Ratio Curve Guided Partitioning in Key-Value Stores. (Masters Thesis). Michigan Technological University. Retrieved from https://digitalcommons.mtu.edu/etdr/653

Chicago Manual of Style (16th Edition):

Byrne, Daniel. “mPart: Miss Ratio Curve Guided Partitioning in Key-Value Stores.” 2018. Masters Thesis, Michigan Technological University. Accessed March 06, 2021. https://digitalcommons.mtu.edu/etdr/653.

MLA Handbook (7th Edition):

Byrne, Daniel. “mPart: Miss Ratio Curve Guided Partitioning in Key-Value Stores.” 2018. Web. 06 Mar 2021.

Vancouver:

Byrne D. mPart: Miss Ratio Curve Guided Partitioning in Key-Value Stores. [Internet] [Masters thesis]. Michigan Technological University; 2018. [cited 2021 Mar 06]. Available from: https://digitalcommons.mtu.edu/etdr/653.

Council of Science Editors:

Byrne D. mPart: Miss Ratio Curve Guided Partitioning in Key-Value Stores. [Masters Thesis]. Michigan Technological University; 2018. Available from: https://digitalcommons.mtu.edu/etdr/653

26. Ramaswamy, Subramanian. Active management of Cache resources.

Degree: PhD, Electrical and Computer Engineering, 2008, Georgia Tech

 This dissertation addresses two sets of challenges facing processor design as the industry enters the deep sub-micron region of semiconductor design. The first set of… (more)

Subjects/Keywords: Efficiency; Customized placement; Reconfigurable caches; Customized caches; Efficient caches; Cache memory; Memory management (Computer science); Energy conservation

…19 Figure 5 Utilization with modern caches . . . . . . . . . . . . . . . . . . . . . . 21… …Figure 6 Performance efficiency with modern caches . . . . . . . . . . . . . . . . 21 Figure… …7 Energy efficiency with modern caches Figure 8 Conflict set construction… …associative caches. . . . . . . . . . . . . . . . 57 Figure 30 Address translation of direct-mapped… …caches - concept . . . . . . . . . . 58 Figure 31 Address decoding for direct-mapped caches… 

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APA (6th Edition):

Ramaswamy, S. (2008). Active management of Cache resources. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/24663

Chicago Manual of Style (16th Edition):

Ramaswamy, Subramanian. “Active management of Cache resources.” 2008. Doctoral Dissertation, Georgia Tech. Accessed March 06, 2021. http://hdl.handle.net/1853/24663.

MLA Handbook (7th Edition):

Ramaswamy, Subramanian. “Active management of Cache resources.” 2008. Web. 06 Mar 2021.

Vancouver:

Ramaswamy S. Active management of Cache resources. [Internet] [Doctoral dissertation]. Georgia Tech; 2008. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/1853/24663.

Council of Science Editors:

Ramaswamy S. Active management of Cache resources. [Doctoral Dissertation]. Georgia Tech; 2008. Available from: http://hdl.handle.net/1853/24663


University of Michigan

27. Ansari, Amin. Overcoming Hard-Faults in High-Performance Microprocessors.

Degree: PhD, Computer Science & Engineering, 2011, University of Michigan

 As device density grows, each transistor gets smaller and more fragile leading to an overall higher susceptibility to hard-faults. These hard-faults result in permanent silicon… (more)

Subjects/Keywords: On-chip Caches, Wearout, Manufacturing Defects, Process Variation, Yield, Heterogeneous Coupled Core Execution; Computer Science; Engineering

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APA (6th Edition):

Ansari, A. (2011). Overcoming Hard-Faults in High-Performance Microprocessors. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/86517

Chicago Manual of Style (16th Edition):

Ansari, Amin. “Overcoming Hard-Faults in High-Performance Microprocessors.” 2011. Doctoral Dissertation, University of Michigan. Accessed March 06, 2021. http://hdl.handle.net/2027.42/86517.

MLA Handbook (7th Edition):

Ansari, Amin. “Overcoming Hard-Faults in High-Performance Microprocessors.” 2011. Web. 06 Mar 2021.

Vancouver:

Ansari A. Overcoming Hard-Faults in High-Performance Microprocessors. [Internet] [Doctoral dissertation]. University of Michigan; 2011. [cited 2021 Mar 06]. Available from: http://hdl.handle.net/2027.42/86517.

Council of Science Editors:

Ansari A. Overcoming Hard-Faults in High-Performance Microprocessors. [Doctoral Dissertation]. University of Michigan; 2011. Available from: http://hdl.handle.net/2027.42/86517

28. Koller, Ricardo. Improving Caches in Consolidated Environments.

Degree: PhD, Computer Science, 2012, Florida International University

  Memory (cache, DRAM, and disk) is in charge of providing data and instructions to a computer’s processor. In order to maximize performance, the speeds… (more)

Subjects/Keywords: Operating systems; storage systems; memory caches; consolidation

…PARTITIONING FOR EXTERNAL MEMORY CACHES 5.1 Background on cache partitioning… …60 61 65 66 66 69 69 70 70 71 71 72 73 74 75 78 6. CONSISTENCY IN WRITE-BACK CACHES 6.1… …ratio for content- and sector- addressed caches for read operations. The total number of pages… …23 3.6 Comparison of ARC and LRU content-addressed caches for pages read only (top… …97 xii CHAPTER 1 INTRODUCTION Memory (CPU caches, DRAM, and disk) has become… 

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APA (6th Edition):

Koller, R. (2012). Improving Caches in Consolidated Environments. (Doctoral Dissertation). Florida International University. Retrieved from https://digitalcommons.fiu.edu/etd/708 ; 10.25148/etd.FI12080801 ; FI12080801

Chicago Manual of Style (16th Edition):

Koller, Ricardo. “Improving Caches in Consolidated Environments.” 2012. Doctoral Dissertation, Florida International University. Accessed March 06, 2021. https://digitalcommons.fiu.edu/etd/708 ; 10.25148/etd.FI12080801 ; FI12080801.

MLA Handbook (7th Edition):

Koller, Ricardo. “Improving Caches in Consolidated Environments.” 2012. Web. 06 Mar 2021.

Vancouver:

Koller R. Improving Caches in Consolidated Environments. [Internet] [Doctoral dissertation]. Florida International University; 2012. [cited 2021 Mar 06]. Available from: https://digitalcommons.fiu.edu/etd/708 ; 10.25148/etd.FI12080801 ; FI12080801.

Council of Science Editors:

Koller R. Improving Caches in Consolidated Environments. [Doctoral Dissertation]. Florida International University; 2012. Available from: https://digitalcommons.fiu.edu/etd/708 ; 10.25148/etd.FI12080801 ; FI12080801


University of Notre Dame

29. Branden James Moore. Exploiting Large Shared On-Chip Caches for Chip Multiprocessors</h1>.

Degree: Computer Science and Engineering, 2005, University of Notre Dame

  Chip multiprocessors are one of several emerging architectures that address the growing processor memory performance gap. At the same time, advances in chip manufacturing… (more)

Subjects/Keywords: chip multiprocessors; shared caches; merged logic and DRAM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Moore, B. J. (2005). Exploiting Large Shared On-Chip Caches for Chip Multiprocessors</h1>. (Thesis). University of Notre Dame. Retrieved from https://curate.nd.edu/show/tb09j388f4p

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Moore, Branden James. “Exploiting Large Shared On-Chip Caches for Chip Multiprocessors</h1>.” 2005. Thesis, University of Notre Dame. Accessed March 06, 2021. https://curate.nd.edu/show/tb09j388f4p.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Moore, Branden James. “Exploiting Large Shared On-Chip Caches for Chip Multiprocessors</h1>.” 2005. Web. 06 Mar 2021.

Vancouver:

Moore BJ. Exploiting Large Shared On-Chip Caches for Chip Multiprocessors</h1>. [Internet] [Thesis]. University of Notre Dame; 2005. [cited 2021 Mar 06]. Available from: https://curate.nd.edu/show/tb09j388f4p.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Moore BJ. Exploiting Large Shared On-Chip Caches for Chip Multiprocessors</h1>. [Thesis]. University of Notre Dame; 2005. Available from: https://curate.nd.edu/show/tb09j388f4p

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

30. Lorrillere, Maxime. Caches collaboratifs noyau adaptés aux environnements virtualisés : A kernel cooperative cache for virtualized environments.

Degree: Docteur es, Informatique, 2016, Université Pierre et Marie Curie – Paris VI

Avec l'avènement du cloud computing, la virtualisation est devenue aujourd'hui incontournable. Elle offre isolation et flexibilité, en revanche elle implique une fragmentation des ressources, et… (more)

Subjects/Keywords: Systèmes d'exploitation; Caches répartis; Virtualisation; Mémoire; Systèmes de fichiers; Linux; Operating system; Cooperative caching; Virtualization; 004

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lorrillere, M. (2016). Caches collaboratifs noyau adaptés aux environnements virtualisés : A kernel cooperative cache for virtualized environments. (Doctoral Dissertation). Université Pierre et Marie Curie – Paris VI. Retrieved from http://www.theses.fr/2016PA066036

Chicago Manual of Style (16th Edition):

Lorrillere, Maxime. “Caches collaboratifs noyau adaptés aux environnements virtualisés : A kernel cooperative cache for virtualized environments.” 2016. Doctoral Dissertation, Université Pierre et Marie Curie – Paris VI. Accessed March 06, 2021. http://www.theses.fr/2016PA066036.

MLA Handbook (7th Edition):

Lorrillere, Maxime. “Caches collaboratifs noyau adaptés aux environnements virtualisés : A kernel cooperative cache for virtualized environments.” 2016. Web. 06 Mar 2021.

Vancouver:

Lorrillere M. Caches collaboratifs noyau adaptés aux environnements virtualisés : A kernel cooperative cache for virtualized environments. [Internet] [Doctoral dissertation]. Université Pierre et Marie Curie – Paris VI; 2016. [cited 2021 Mar 06]. Available from: http://www.theses.fr/2016PA066036.

Council of Science Editors:

Lorrillere M. Caches collaboratifs noyau adaptés aux environnements virtualisés : A kernel cooperative cache for virtualized environments. [Doctoral Dissertation]. Université Pierre et Marie Curie – Paris VI; 2016. Available from: http://www.theses.fr/2016PA066036

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