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You searched for subject:(Cache memory). Showing records 1 – 30 of 252 total matches.

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NSYSU

1. Yang, Yun-Chung. A Reconfigurable Cache for Efficient Usage of the Tag RAM Space.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 In almost every typical SoCs (System-on-Chip) in modern days, the size of cache grows larger as new SoC fabrics enhanced to satisfy the variety of… (more)

Subjects/Keywords: Memory architecture; Cache

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, Y. (2014). A Reconfigurable Cache for Efficient Usage of the Tag RAM Space. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-114613

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Yun-Chung. “A Reconfigurable Cache for Efficient Usage of the Tag RAM Space.” 2014. Thesis, NSYSU. Accessed October 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-114613.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Yun-Chung. “A Reconfigurable Cache for Efficient Usage of the Tag RAM Space.” 2014. Web. 18 Oct 2019.

Vancouver:

Yang Y. A Reconfigurable Cache for Efficient Usage of the Tag RAM Space. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Oct 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-114613.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang Y. A Reconfigurable Cache for Efficient Usage of the Tag RAM Space. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0728114-114613

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of North Texas

2. Nwachukwu, Izuchukwu Udochi. Techniques for Improving Uniformity in Direct Mapped Caches.

Degree: 2011, University of North Texas

 Directly mapped caches are an attractive option for processor designers as they combine fast lookup times with reduced complexity and area. However, directly-mapped caches are… (more)

Subjects/Keywords: cache; memory; indexing

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APA (6th Edition):

Nwachukwu, I. U. (2011). Techniques for Improving Uniformity in Direct Mapped Caches. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc68025/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nwachukwu, Izuchukwu Udochi. “Techniques for Improving Uniformity in Direct Mapped Caches.” 2011. Thesis, University of North Texas. Accessed October 18, 2019. https://digital.library.unt.edu/ark:/67531/metadc68025/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nwachukwu, Izuchukwu Udochi. “Techniques for Improving Uniformity in Direct Mapped Caches.” 2011. Web. 18 Oct 2019.

Vancouver:

Nwachukwu IU. Techniques for Improving Uniformity in Direct Mapped Caches. [Internet] [Thesis]. University of North Texas; 2011. [cited 2019 Oct 18]. Available from: https://digital.library.unt.edu/ark:/67531/metadc68025/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nwachukwu IU. Techniques for Improving Uniformity in Direct Mapped Caches. [Thesis]. University of North Texas; 2011. Available from: https://digital.library.unt.edu/ark:/67531/metadc68025/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

3. Zheng, Tianhao, Ph. D. Efficient fine-grained virtual memory.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin

 Virtual memory in modern computer systems provides a single abstraction of the memory hierarchy. By hiding fragmentation and overlays of physical memory, virtual memory frees… (more)

Subjects/Keywords: Memory; Cache; Metadata

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APA (6th Edition):

Zheng, Tianhao, P. D. (2018). Efficient fine-grained virtual memory. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/68079

Chicago Manual of Style (16th Edition):

Zheng, Tianhao, Ph D. “Efficient fine-grained virtual memory.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed October 18, 2019. http://hdl.handle.net/2152/68079.

MLA Handbook (7th Edition):

Zheng, Tianhao, Ph D. “Efficient fine-grained virtual memory.” 2018. Web. 18 Oct 2019.

Vancouver:

Zheng, Tianhao PD. Efficient fine-grained virtual memory. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/2152/68079.

Council of Science Editors:

Zheng, Tianhao PD. Efficient fine-grained virtual memory. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://hdl.handle.net/2152/68079


Oregon State University

4. Ho, Yui Luen. Processor memory traffic characteristics for on-chip cache.

Degree: MS, xElectrical and Computer Engineering, 1992, Oregon State University

 The motivation of this research is to study different cache designs for on-chip caches that improve processor performance and at the same time minimize the… (more)

Subjects/Keywords: Cache memory

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APA (6th Edition):

Ho, Y. L. (1992). Processor memory traffic characteristics for on-chip cache. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/36922

Chicago Manual of Style (16th Edition):

Ho, Yui Luen. “Processor memory traffic characteristics for on-chip cache.” 1992. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/36922.

MLA Handbook (7th Edition):

Ho, Yui Luen. “Processor memory traffic characteristics for on-chip cache.” 1992. Web. 18 Oct 2019.

Vancouver:

Ho YL. Processor memory traffic characteristics for on-chip cache. [Internet] [Masters thesis]. Oregon State University; 1992. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/36922.

Council of Science Editors:

Ho YL. Processor memory traffic characteristics for on-chip cache. [Masters Thesis]. Oregon State University; 1992. Available from: http://hdl.handle.net/1957/36922


Hong Kong University of Science and Technology

5. Dai, Jie. Collaborative caching in content-oriented networks.

Degree: 2012, Hong Kong University of Science and Technology

 The content-oriented network is becoming a reality with enormous amount of contents such as high-definition videos and software packages being spreading across the entire network… (more)

Subjects/Keywords: Cache memory; Electronic data processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dai, J. (2012). Collaborative caching in content-oriented networks. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1180172 ; http://repository.ust.hk/ir/bitstream/1783.1-7560/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dai, Jie. “Collaborative caching in content-oriented networks.” 2012. Thesis, Hong Kong University of Science and Technology. Accessed October 18, 2019. https://doi.org/10.14711/thesis-b1180172 ; http://repository.ust.hk/ir/bitstream/1783.1-7560/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dai, Jie. “Collaborative caching in content-oriented networks.” 2012. Web. 18 Oct 2019.

Vancouver:

Dai J. Collaborative caching in content-oriented networks. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2012. [cited 2019 Oct 18]. Available from: https://doi.org/10.14711/thesis-b1180172 ; http://repository.ust.hk/ir/bitstream/1783.1-7560/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dai J. Collaborative caching in content-oriented networks. [Thesis]. Hong Kong University of Science and Technology; 2012. Available from: https://doi.org/10.14711/thesis-b1180172 ; http://repository.ust.hk/ir/bitstream/1783.1-7560/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Edinburgh

6. Huang, Cheng-Chieh. Optimizing cache utilization in modern cache hierarchies.

Degree: PhD, 2016, University of Edinburgh

Memory wall is one of the major performance bottlenecks in modern computer systems. SRAM caches have been used to successfully bridge the performance gap between… (more)

Subjects/Keywords: 004.5; cache; DRAM; memory hierarchy

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APA (6th Edition):

Huang, C. (2016). Optimizing cache utilization in modern cache hierarchies. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/19571

Chicago Manual of Style (16th Edition):

Huang, Cheng-Chieh. “Optimizing cache utilization in modern cache hierarchies.” 2016. Doctoral Dissertation, University of Edinburgh. Accessed October 18, 2019. http://hdl.handle.net/1842/19571.

MLA Handbook (7th Edition):

Huang, Cheng-Chieh. “Optimizing cache utilization in modern cache hierarchies.” 2016. Web. 18 Oct 2019.

Vancouver:

Huang C. Optimizing cache utilization in modern cache hierarchies. [Internet] [Doctoral dissertation]. University of Edinburgh; 2016. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1842/19571.

Council of Science Editors:

Huang C. Optimizing cache utilization in modern cache hierarchies. [Doctoral Dissertation]. University of Edinburgh; 2016. Available from: http://hdl.handle.net/1842/19571


Cornell University

7. Bhadauria, Major. High Performance Techniques for Reducing Cache Power .

Degree: 2008, Cornell University

 Minimizing power consumption continues to grow as a critical design issue for many platforms, from embedded systems to chip multiprocessors (CMP) to ultra scale parallel… (more)

Subjects/Keywords: performance; power; cache; memory

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APA (6th Edition):

Bhadauria, M. (2008). High Performance Techniques for Reducing Cache Power . (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/10755

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bhadauria, Major. “High Performance Techniques for Reducing Cache Power .” 2008. Thesis, Cornell University. Accessed October 18, 2019. http://hdl.handle.net/1813/10755.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bhadauria, Major. “High Performance Techniques for Reducing Cache Power .” 2008. Web. 18 Oct 2019.

Vancouver:

Bhadauria M. High Performance Techniques for Reducing Cache Power . [Internet] [Thesis]. Cornell University; 2008. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1813/10755.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bhadauria M. High Performance Techniques for Reducing Cache Power . [Thesis]. Cornell University; 2008. Available from: http://hdl.handle.net/1813/10755

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oklahoma State University

8. Mulia, Wira Damis. Dynamic Cache-Usage Profiler for the Xen Hypervisor.

Degree: School of Electrical & Computer Engineering, 2009, Oklahoma State University

 This study focuses on improving virtualization performance by utilizing existing architectural infrastructures. The system encompasses the profiler that interacts with low-level architecture resources, a data… (more)

Subjects/Keywords: cache memory; dynamic feedback; virtualization

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APA (6th Edition):

Mulia, W. D. (2009). Dynamic Cache-Usage Profiler for the Xen Hypervisor. (Thesis). Oklahoma State University. Retrieved from http://hdl.handle.net/11244/10247

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mulia, Wira Damis. “Dynamic Cache-Usage Profiler for the Xen Hypervisor.” 2009. Thesis, Oklahoma State University. Accessed October 18, 2019. http://hdl.handle.net/11244/10247.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mulia, Wira Damis. “Dynamic Cache-Usage Profiler for the Xen Hypervisor.” 2009. Web. 18 Oct 2019.

Vancouver:

Mulia WD. Dynamic Cache-Usage Profiler for the Xen Hypervisor. [Internet] [Thesis]. Oklahoma State University; 2009. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/11244/10247.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mulia WD. Dynamic Cache-Usage Profiler for the Xen Hypervisor. [Thesis]. Oklahoma State University; 2009. Available from: http://hdl.handle.net/11244/10247

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Adelaide

9. Ashenden, Peter J. An experimental system for evaluating cache coherence protocols in shared memory multiprocessors / Peter John Ashenden.

Degree: 1997, University of Adelaide

This thesis examines cache coherence protocols designed for use in bus connected shared memory multiprocessors. Advisors/Committee Members: Dept. of Computer Science (school).

Subjects/Keywords: Cache memory.

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APA (6th Edition):

Ashenden, P. J. (1997). An experimental system for evaluating cache coherence protocols in shared memory multiprocessors / Peter John Ashenden. (Thesis). University of Adelaide. Retrieved from http://hdl.handle.net/2440/19025

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ashenden, Peter J. “An experimental system for evaluating cache coherence protocols in shared memory multiprocessors / Peter John Ashenden.” 1997. Thesis, University of Adelaide. Accessed October 18, 2019. http://hdl.handle.net/2440/19025.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ashenden, Peter J. “An experimental system for evaluating cache coherence protocols in shared memory multiprocessors / Peter John Ashenden.” 1997. Web. 18 Oct 2019.

Vancouver:

Ashenden PJ. An experimental system for evaluating cache coherence protocols in shared memory multiprocessors / Peter John Ashenden. [Internet] [Thesis]. University of Adelaide; 1997. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/2440/19025.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ashenden PJ. An experimental system for evaluating cache coherence protocols in shared memory multiprocessors / Peter John Ashenden. [Thesis]. University of Adelaide; 1997. Available from: http://hdl.handle.net/2440/19025

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arizona

10. Simons, Brad. Set-Associative History-Aided Adaptive Replacement for On-Chip Caches .

Degree: 2016, University of Arizona

 Last Level Caches (LLCs) are critical to reducing processor stalls to off-chip memory and improving processing throughput, and replacement policy plays an important role in… (more)

Subjects/Keywords: Memory; Electrical & Computer Engineering; Cache

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APA (6th Edition):

Simons, B. (2016). Set-Associative History-Aided Adaptive Replacement for On-Chip Caches . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/621128

Chicago Manual of Style (16th Edition):

Simons, Brad. “Set-Associative History-Aided Adaptive Replacement for On-Chip Caches .” 2016. Masters Thesis, University of Arizona. Accessed October 18, 2019. http://hdl.handle.net/10150/621128.

MLA Handbook (7th Edition):

Simons, Brad. “Set-Associative History-Aided Adaptive Replacement for On-Chip Caches .” 2016. Web. 18 Oct 2019.

Vancouver:

Simons B. Set-Associative History-Aided Adaptive Replacement for On-Chip Caches . [Internet] [Masters thesis]. University of Arizona; 2016. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/10150/621128.

Council of Science Editors:

Simons B. Set-Associative History-Aided Adaptive Replacement for On-Chip Caches . [Masters Thesis]. University of Arizona; 2016. Available from: http://hdl.handle.net/10150/621128


Indian Institute of Science

11. Agarwal, Tanuj Kumar. Cache Coherence State Based Replacement Policies.

Degree: 2015, Indian Institute of Science

Cache replacement policies can play a pivotal role in the overall performance of a system by preserving data locality and thus limiting the o -chip… (more)

Subjects/Keywords: Cache Replacement Policy; Cache Coherence; Computer Architecture; Cache Memory; Computer Storage Devices; Cache Replacement Policies; Cache Coherence Protocol; Computer Science

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APA (6th Edition):

Agarwal, T. K. (2015). Cache Coherence State Based Replacement Policies. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3822 ; http://etd.iisc.ernet.in/abstracts/4693/G26974-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Agarwal, Tanuj Kumar. “Cache Coherence State Based Replacement Policies.” 2015. Thesis, Indian Institute of Science. Accessed October 18, 2019. http://etd.iisc.ernet.in/2005/3822 ; http://etd.iisc.ernet.in/abstracts/4693/G26974-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Agarwal, Tanuj Kumar. “Cache Coherence State Based Replacement Policies.” 2015. Web. 18 Oct 2019.

Vancouver:

Agarwal TK. Cache Coherence State Based Replacement Policies. [Internet] [Thesis]. Indian Institute of Science; 2015. [cited 2019 Oct 18]. Available from: http://etd.iisc.ernet.in/2005/3822 ; http://etd.iisc.ernet.in/abstracts/4693/G26974-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Agarwal TK. Cache Coherence State Based Replacement Policies. [Thesis]. Indian Institute of Science; 2015. Available from: http://etd.iisc.ernet.in/2005/3822 ; http://etd.iisc.ernet.in/abstracts/4693/G26974-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

12. Chen, Hung-Lun. A Hybrid SPM-Cache with Tag-Based Hot Cache Sets Support.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 Embedded system plays an important role in modern computer architecture since it can provide reliable performance with lower cost and area compared to the general… (more)

Subjects/Keywords: Conflict Miss; Hot Cache Set; Scratchpad Memory; Cache

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APA (6th Edition):

Chen, H. (2017). A Hybrid SPM-Cache with Tag-Based Hot Cache Sets Support. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721117-173334

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Hung-Lun. “A Hybrid SPM-Cache with Tag-Based Hot Cache Sets Support.” 2017. Thesis, NSYSU. Accessed October 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721117-173334.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Hung-Lun. “A Hybrid SPM-Cache with Tag-Based Hot Cache Sets Support.” 2017. Web. 18 Oct 2019.

Vancouver:

Chen H. A Hybrid SPM-Cache with Tag-Based Hot Cache Sets Support. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Oct 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721117-173334.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen H. A Hybrid SPM-Cache with Tag-Based Hot Cache Sets Support. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721117-173334

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

13. Ampntel-Kanter-Oikonomou, A.K. Design space exploration for a Local Object Store:.

Degree: 2015, Delft University of Technology

 Nowadays, modern Integrated Circuit (IC) technology allows processor manufacturers to produce complex designs with up to a few billions of transistors.Technology limitations and the end… (more)

Subjects/Keywords: Local Object Store Design; scratchpad; cache memory; management unit cache

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APA (6th Edition):

Ampntel-Kanter-Oikonomou, A. K. (2015). Design space exploration for a Local Object Store:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:ff0d73fa-339b-46c2-930c-f0e7b58625b6

Chicago Manual of Style (16th Edition):

Ampntel-Kanter-Oikonomou, A K. “Design space exploration for a Local Object Store:.” 2015. Masters Thesis, Delft University of Technology. Accessed October 18, 2019. http://resolver.tudelft.nl/uuid:ff0d73fa-339b-46c2-930c-f0e7b58625b6.

MLA Handbook (7th Edition):

Ampntel-Kanter-Oikonomou, A K. “Design space exploration for a Local Object Store:.” 2015. Web. 18 Oct 2019.

Vancouver:

Ampntel-Kanter-Oikonomou AK. Design space exploration for a Local Object Store:. [Internet] [Masters thesis]. Delft University of Technology; 2015. [cited 2019 Oct 18]. Available from: http://resolver.tudelft.nl/uuid:ff0d73fa-339b-46c2-930c-f0e7b58625b6.

Council of Science Editors:

Ampntel-Kanter-Oikonomou AK. Design space exploration for a Local Object Store:. [Masters Thesis]. Delft University of Technology; 2015. Available from: http://resolver.tudelft.nl/uuid:ff0d73fa-339b-46c2-930c-f0e7b58625b6


Université Montpellier II

14. Busseuil, Rémi. Exploration d'architecture d'accélérateurs à mémoire distribuée : Design space exploration of distributed-memory accelerators.

Degree: Docteur es, SYAM - Systèmes Automatiques et Microélectroniques, 2012, Université Montpellier II

Bien que le développement actuel d'accélérateurs se concentre principalement sur la création de puces Multiprocesseurs (MPSoC) hétérogènes, c'est-à-dire composés de processeurs spécialisées, de nombreux acteurs… (more)

Subjects/Keywords: Cohérence de cache; Mémoire Distribuée; MPSoC; Cache coherency; Distributed memory; MPSoC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Busseuil, R. (2012). Exploration d'architecture d'accélérateurs à mémoire distribuée : Design space exploration of distributed-memory accelerators. (Doctoral Dissertation). Université Montpellier II. Retrieved from http://www.theses.fr/2012MON20218

Chicago Manual of Style (16th Edition):

Busseuil, Rémi. “Exploration d'architecture d'accélérateurs à mémoire distribuée : Design space exploration of distributed-memory accelerators.” 2012. Doctoral Dissertation, Université Montpellier II. Accessed October 18, 2019. http://www.theses.fr/2012MON20218.

MLA Handbook (7th Edition):

Busseuil, Rémi. “Exploration d'architecture d'accélérateurs à mémoire distribuée : Design space exploration of distributed-memory accelerators.” 2012. Web. 18 Oct 2019.

Vancouver:

Busseuil R. Exploration d'architecture d'accélérateurs à mémoire distribuée : Design space exploration of distributed-memory accelerators. [Internet] [Doctoral dissertation]. Université Montpellier II; 2012. [cited 2019 Oct 18]. Available from: http://www.theses.fr/2012MON20218.

Council of Science Editors:

Busseuil R. Exploration d'architecture d'accélérateurs à mémoire distribuée : Design space exploration of distributed-memory accelerators. [Doctoral Dissertation]. Université Montpellier II; 2012. Available from: http://www.theses.fr/2012MON20218


University of Toronto

15. Nandakumar, Venkatesh. Transparent In-memory Cache for Hadoop-MapReduce.

Degree: 2014, University of Toronto

Many analytic applications built on Hadoop ecosystem have a propensity to iteratively perform repetitive operations on same input data. To remove the burden of these… (more)

Subjects/Keywords: Hadoop; Mapreduce; memory cache; persistent process; transparent cache; 0464

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APA (6th Edition):

Nandakumar, V. (2014). Transparent In-memory Cache for Hadoop-MapReduce. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/68071

Chicago Manual of Style (16th Edition):

Nandakumar, Venkatesh. “Transparent In-memory Cache for Hadoop-MapReduce.” 2014. Masters Thesis, University of Toronto. Accessed October 18, 2019. http://hdl.handle.net/1807/68071.

MLA Handbook (7th Edition):

Nandakumar, Venkatesh. “Transparent In-memory Cache for Hadoop-MapReduce.” 2014. Web. 18 Oct 2019.

Vancouver:

Nandakumar V. Transparent In-memory Cache for Hadoop-MapReduce. [Internet] [Masters thesis]. University of Toronto; 2014. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1807/68071.

Council of Science Editors:

Nandakumar V. Transparent In-memory Cache for Hadoop-MapReduce. [Masters Thesis]. University of Toronto; 2014. Available from: http://hdl.handle.net/1807/68071


University of Tasmania

16. Adamczewski, J. The Hoard: Paged virtual memory for the Cell BE SPE.

Degree: 2011, University of Tasmania

 The hoard is a paged virtual memory system for program data designed for the Cell Broadband Engine processor (Cell BE). The hoard makes it easier… (more)

Subjects/Keywords: CellBE; SPE; software cache; virtual memory

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APA (6th Edition):

Adamczewski, J. (2011). The Hoard: Paged virtual memory for the Cell BE SPE. (Thesis). University of Tasmania. Retrieved from https://eprints.utas.edu.au/11726/1/Adamczewski_thesis-pdf.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Adamczewski, J. “The Hoard: Paged virtual memory for the Cell BE SPE.” 2011. Thesis, University of Tasmania. Accessed October 18, 2019. https://eprints.utas.edu.au/11726/1/Adamczewski_thesis-pdf.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Adamczewski, J. “The Hoard: Paged virtual memory for the Cell BE SPE.” 2011. Web. 18 Oct 2019.

Vancouver:

Adamczewski J. The Hoard: Paged virtual memory for the Cell BE SPE. [Internet] [Thesis]. University of Tasmania; 2011. [cited 2019 Oct 18]. Available from: https://eprints.utas.edu.au/11726/1/Adamczewski_thesis-pdf.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Adamczewski J. The Hoard: Paged virtual memory for the Cell BE SPE. [Thesis]. University of Tasmania; 2011. Available from: https://eprints.utas.edu.au/11726/1/Adamczewski_thesis-pdf.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

17. Morrison, Roger Allen. Asymmetric clustering using a register cache.

Degree: MS, Electrical and Computer Engineering, 2006, Oregon State University

 Conventional register files spread porting resources uniformly across all registers. This paper proposes a method called Asymmetric Clustering using a Register Cache (ACRC). ACRC utilizes… (more)

Subjects/Keywords: register; Cache memory

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APA (6th Edition):

Morrison, R. A. (2006). Asymmetric clustering using a register cache. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/1689

Chicago Manual of Style (16th Edition):

Morrison, Roger Allen. “Asymmetric clustering using a register cache.” 2006. Masters Thesis, Oregon State University. Accessed October 18, 2019. http://hdl.handle.net/1957/1689.

MLA Handbook (7th Edition):

Morrison, Roger Allen. “Asymmetric clustering using a register cache.” 2006. Web. 18 Oct 2019.

Vancouver:

Morrison RA. Asymmetric clustering using a register cache. [Internet] [Masters thesis]. Oregon State University; 2006. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1957/1689.

Council of Science Editors:

Morrison RA. Asymmetric clustering using a register cache. [Masters Thesis]. Oregon State University; 2006. Available from: http://hdl.handle.net/1957/1689


University of North Carolina – Greensboro

18. Kong, Yuan. A Distributed Public Key Caching Scheme in Large Wireless Networks.

Degree: 2010, University of North Carolina – Greensboro

 When asymmetric cryptography techniques are used in wireless networks, the public keys of the nodes need to be widely available and signed by a Certificate… (more)

Subjects/Keywords: Wireless communication systems.; Telecommunication systems.; Cache memory.

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APA (6th Edition):

Kong, Y. (2010). A Distributed Public Key Caching Scheme in Large Wireless Networks. (Masters Thesis). University of North Carolina – Greensboro. Retrieved from http://libres.uncg.edu/ir/listing.aspx?styp=ti&id=3639

Chicago Manual of Style (16th Edition):

Kong, Yuan. “A Distributed Public Key Caching Scheme in Large Wireless Networks.” 2010. Masters Thesis, University of North Carolina – Greensboro. Accessed October 18, 2019. http://libres.uncg.edu/ir/listing.aspx?styp=ti&id=3639.

MLA Handbook (7th Edition):

Kong, Yuan. “A Distributed Public Key Caching Scheme in Large Wireless Networks.” 2010. Web. 18 Oct 2019.

Vancouver:

Kong Y. A Distributed Public Key Caching Scheme in Large Wireless Networks. [Internet] [Masters thesis]. University of North Carolina – Greensboro; 2010. [cited 2019 Oct 18]. Available from: http://libres.uncg.edu/ir/listing.aspx?styp=ti&id=3639.

Council of Science Editors:

Kong Y. A Distributed Public Key Caching Scheme in Large Wireless Networks. [Masters Thesis]. University of North Carolina – Greensboro; 2010. Available from: http://libres.uncg.edu/ir/listing.aspx?styp=ti&id=3639


California State University – Sacramento

19. Bandri Anand, Kiran. Design and implementation of a sensor hub interface using an ARM cortex m0 processor.

Degree: MS, Electrical and Electronic Engineering, 2019, California State University – Sacramento

 Smart Devices and the need for intelligent systems has brought about a revolution in Technology. With devices getting smaller, yet more effective, there is a… (more)

Subjects/Keywords: Sensor applications; Computer architecture; Cache memory system

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bandri Anand, K. (2019). Design and implementation of a sensor hub interface using an ARM cortex m0 processor. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/207768

Chicago Manual of Style (16th Edition):

Bandri Anand, Kiran. “Design and implementation of a sensor hub interface using an ARM cortex m0 processor.” 2019. Masters Thesis, California State University – Sacramento. Accessed October 18, 2019. http://hdl.handle.net/10211.3/207768.

MLA Handbook (7th Edition):

Bandri Anand, Kiran. “Design and implementation of a sensor hub interface using an ARM cortex m0 processor.” 2019. Web. 18 Oct 2019.

Vancouver:

Bandri Anand K. Design and implementation of a sensor hub interface using an ARM cortex m0 processor. [Internet] [Masters thesis]. California State University – Sacramento; 2019. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/10211.3/207768.

Council of Science Editors:

Bandri Anand K. Design and implementation of a sensor hub interface using an ARM cortex m0 processor. [Masters Thesis]. California State University – Sacramento; 2019. Available from: http://hdl.handle.net/10211.3/207768


University of New South Wales

20. Nawinne, Isuru. Hardware accelerated cache design space exploration for application specific MPSoCs.

Degree: Computer Science & Engineering, 2016, University of New South Wales

 The performance of a computing system heavily depends on the memory hierarchy. Fast but expensive cache memories are commonly employed to bridge the increasing performance… (more)

Subjects/Keywords: Design space exploration; Cache memory; FPGA acceleration

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APA (6th Edition):

Nawinne, I. (2016). Hardware accelerated cache design space exploration for application specific MPSoCs. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/56267 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:40412/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Nawinne, Isuru. “Hardware accelerated cache design space exploration for application specific MPSoCs.” 2016. Doctoral Dissertation, University of New South Wales. Accessed October 18, 2019. http://handle.unsw.edu.au/1959.4/56267 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:40412/SOURCE02?view=true.

MLA Handbook (7th Edition):

Nawinne, Isuru. “Hardware accelerated cache design space exploration for application specific MPSoCs.” 2016. Web. 18 Oct 2019.

Vancouver:

Nawinne I. Hardware accelerated cache design space exploration for application specific MPSoCs. [Internet] [Doctoral dissertation]. University of New South Wales; 2016. [cited 2019 Oct 18]. Available from: http://handle.unsw.edu.au/1959.4/56267 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:40412/SOURCE02?view=true.

Council of Science Editors:

Nawinne I. Hardware accelerated cache design space exploration for application specific MPSoCs. [Doctoral Dissertation]. University of New South Wales; 2016. Available from: http://handle.unsw.edu.au/1959.4/56267 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:40412/SOURCE02?view=true


Universitat Politècnica de València

21. Candel Margaix, Francisco. Efficient L2 Cache Management to Boost GPGPU Performance .

Degree: 2019, Universitat Politècnica de València

 [ES] En los últimos años, la creciente necesidad de la capacidad de cómputo ha supuesto un reto que ha llevado a la industria a buscar… (more)

Subjects/Keywords: GPU; MEMORY HIERARCHY; L2 CACHE MANAGEMENT

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APA (6th Edition):

Candel Margaix, F. (2019). Efficient L2 Cache Management to Boost GPGPU Performance . (Doctoral Dissertation). Universitat Politècnica de València. Retrieved from http://hdl.handle.net/10251/125477

Chicago Manual of Style (16th Edition):

Candel Margaix, Francisco. “Efficient L2 Cache Management to Boost GPGPU Performance .” 2019. Doctoral Dissertation, Universitat Politècnica de València. Accessed October 18, 2019. http://hdl.handle.net/10251/125477.

MLA Handbook (7th Edition):

Candel Margaix, Francisco. “Efficient L2 Cache Management to Boost GPGPU Performance .” 2019. Web. 18 Oct 2019.

Vancouver:

Candel Margaix F. Efficient L2 Cache Management to Boost GPGPU Performance . [Internet] [Doctoral dissertation]. Universitat Politècnica de València; 2019. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/10251/125477.

Council of Science Editors:

Candel Margaix F. Efficient L2 Cache Management to Boost GPGPU Performance . [Doctoral Dissertation]. Universitat Politècnica de València; 2019. Available from: http://hdl.handle.net/10251/125477


NSYSU

22. Yang, Jyun-sheng. Design and Implementation of Multi-Port Shared Cache in Multi-core Systems.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 Multi-port shared cache memory plays an important role in multi-core systems. Although single/dual-port SRAM can be realized using commercial standard cell library, multi-port shared cache(more)

Subjects/Keywords: multi-port shared cache memory; multi-port shared cache memory generator; multi-core system

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APA (6th Edition):

Yang, J. (2016). Design and Implementation of Multi-Port Shared Cache in Multi-core Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-150758

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Jyun-sheng. “Design and Implementation of Multi-Port Shared Cache in Multi-core Systems.” 2016. Thesis, NSYSU. Accessed October 18, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-150758.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Jyun-sheng. “Design and Implementation of Multi-Port Shared Cache in Multi-core Systems.” 2016. Web. 18 Oct 2019.

Vancouver:

Yang J. Design and Implementation of Multi-Port Shared Cache in Multi-core Systems. [Internet] [Thesis]. NSYSU; 2016. [cited 2019 Oct 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-150758.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang J. Design and Implementation of Multi-Port Shared Cache in Multi-core Systems. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-150758

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


The Ohio State University

23. Liang, Shuang. Algorithms Designs and Implementations for Page Allocation in SSD Firmware and SSD Caching in Storage Systems.

Degree: MS, Computer Science and Engineering, 2010, The Ohio State University

  The emerging flash memory based SSD technology poses a new challenge for us to effectively use it in storage systems. Despite of its many… (more)

Subjects/Keywords: Computer Science; flash memory; disk cache; cache algorithms; page allocation algorithm; firmware

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APA (6th Edition):

Liang, S. (2010). Algorithms Designs and Implementations for Page Allocation in SSD Firmware and SSD Caching in Storage Systems. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1268420517

Chicago Manual of Style (16th Edition):

Liang, Shuang. “Algorithms Designs and Implementations for Page Allocation in SSD Firmware and SSD Caching in Storage Systems.” 2010. Masters Thesis, The Ohio State University. Accessed October 18, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1268420517.

MLA Handbook (7th Edition):

Liang, Shuang. “Algorithms Designs and Implementations for Page Allocation in SSD Firmware and SSD Caching in Storage Systems.” 2010. Web. 18 Oct 2019.

Vancouver:

Liang S. Algorithms Designs and Implementations for Page Allocation in SSD Firmware and SSD Caching in Storage Systems. [Internet] [Masters thesis]. The Ohio State University; 2010. [cited 2019 Oct 18]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1268420517.

Council of Science Editors:

Liang S. Algorithms Designs and Implementations for Page Allocation in SSD Firmware and SSD Caching in Storage Systems. [Masters Thesis]. The Ohio State University; 2010. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1268420517


Colorado State University

24. Bhosale, Swapnil. High performance and energy efficient shared hybrid last level cache architecture in multicore systems.

Degree: MS(M.S.), Electrical and Computer Engineering, 2019, Colorado State University

 As the performance gap between CPU and main memory continues to increase, it causes a significant roadblock to exascale computing. Memory performance has not kept… (more)

Subjects/Keywords: Last level cache; Non-volatile memory; STTRAM; LLC energy; Cache coherency; Performance

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APA (6th Edition):

Bhosale, S. (2019). High performance and energy efficient shared hybrid last level cache architecture in multicore systems. (Masters Thesis). Colorado State University. Retrieved from http://hdl.handle.net/10217/193178

Chicago Manual of Style (16th Edition):

Bhosale, Swapnil. “High performance and energy efficient shared hybrid last level cache architecture in multicore systems.” 2019. Masters Thesis, Colorado State University. Accessed October 18, 2019. http://hdl.handle.net/10217/193178.

MLA Handbook (7th Edition):

Bhosale, Swapnil. “High performance and energy efficient shared hybrid last level cache architecture in multicore systems.” 2019. Web. 18 Oct 2019.

Vancouver:

Bhosale S. High performance and energy efficient shared hybrid last level cache architecture in multicore systems. [Internet] [Masters thesis]. Colorado State University; 2019. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/10217/193178.

Council of Science Editors:

Bhosale S. High performance and energy efficient shared hybrid last level cache architecture in multicore systems. [Masters Thesis]. Colorado State University; 2019. Available from: http://hdl.handle.net/10217/193178

25. Magnus, Åkerstedt Bergsten. Scene Graph Memory Management .

Degree: Chalmers tekniska högskola / Institutionen för data och informationsvetenskap, 2019, Chalmers University of Technology

 Due to the growing disparity in performance between memory and processors, it is becoming increasingly important to consider the layout of applications’ working set data… (more)

Subjects/Keywords: Computer; science; computer science; engineering; thesis; scene graph; memory management; cache friendly; cache efficient

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APA (6th Edition):

Magnus, . B. (2019). Scene Graph Memory Management . (Thesis). Chalmers University of Technology. Retrieved from http://hdl.handle.net/20.500.12380/300381

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Magnus, Åkerstedt Bergsten. “Scene Graph Memory Management .” 2019. Thesis, Chalmers University of Technology. Accessed October 18, 2019. http://hdl.handle.net/20.500.12380/300381.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Magnus, Åkerstedt Bergsten. “Scene Graph Memory Management .” 2019. Web. 18 Oct 2019.

Vancouver:

Magnus B. Scene Graph Memory Management . [Internet] [Thesis]. Chalmers University of Technology; 2019. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/20.500.12380/300381.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Magnus B. Scene Graph Memory Management . [Thesis]. Chalmers University of Technology; 2019. Available from: http://hdl.handle.net/20.500.12380/300381

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universitat Politècnica de València

26. Selfa Oliver, Vicent. Adaptive Prefetching and Cache Partitioning for Multicore Processors .

Degree: 2018, Universitat Politècnica de València

 El acceso a la memoria principal en los procesadores actuales supone un importante cuello de botella para las prestaciones, dado que los diferentes núcleos compiten… (more)

Subjects/Keywords: cache; cache partitioning; multicore; processors; prefetcher; memory; selective prefetcher; prefetching; caching; intel; cache allocation technology; cat

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APA (6th Edition):

Selfa Oliver, V. (2018). Adaptive Prefetching and Cache Partitioning for Multicore Processors . (Doctoral Dissertation). Universitat Politècnica de València. Retrieved from http://hdl.handle.net/10251/112423

Chicago Manual of Style (16th Edition):

Selfa Oliver, Vicent. “Adaptive Prefetching and Cache Partitioning for Multicore Processors .” 2018. Doctoral Dissertation, Universitat Politècnica de València. Accessed October 18, 2019. http://hdl.handle.net/10251/112423.

MLA Handbook (7th Edition):

Selfa Oliver, Vicent. “Adaptive Prefetching and Cache Partitioning for Multicore Processors .” 2018. Web. 18 Oct 2019.

Vancouver:

Selfa Oliver V. Adaptive Prefetching and Cache Partitioning for Multicore Processors . [Internet] [Doctoral dissertation]. Universitat Politècnica de València; 2018. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/10251/112423.

Council of Science Editors:

Selfa Oliver V. Adaptive Prefetching and Cache Partitioning for Multicore Processors . [Doctoral Dissertation]. Universitat Politècnica de València; 2018. Available from: http://hdl.handle.net/10251/112423


Rice University

27. Bhandari, Kumud. Evaluating the programmability and scalability of memory hierarchies with read-only data blocks.

Degree: MS, Engineering, 2015, Rice University

 This thesis evaluates the programmability and scalability of Fresh Breeze Memory (FBM), a unique memory hierarchy design with universally identifiable fixed-size read-only blocks. As a… (more)

Subjects/Keywords: Fresh Breeze Architecture; tree-based memory; memory model; cache-coherence; read-only memory; write-once

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APA (6th Edition):

Bhandari, K. (2015). Evaluating the programmability and scalability of memory hierarchies with read-only data blocks. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/87750

Chicago Manual of Style (16th Edition):

Bhandari, Kumud. “Evaluating the programmability and scalability of memory hierarchies with read-only data blocks.” 2015. Masters Thesis, Rice University. Accessed October 18, 2019. http://hdl.handle.net/1911/87750.

MLA Handbook (7th Edition):

Bhandari, Kumud. “Evaluating the programmability and scalability of memory hierarchies with read-only data blocks.” 2015. Web. 18 Oct 2019.

Vancouver:

Bhandari K. Evaluating the programmability and scalability of memory hierarchies with read-only data blocks. [Internet] [Masters thesis]. Rice University; 2015. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/1911/87750.

Council of Science Editors:

Bhandari K. Evaluating the programmability and scalability of memory hierarchies with read-only data blocks. [Masters Thesis]. Rice University; 2015. Available from: http://hdl.handle.net/1911/87750


Universidade do Rio Grande do Sul

28. Cruz, Eduardo Henrique Molina da. Dynamic detection of the communication pattern in shared memory environments for thread mapping.

Degree: 2012, Universidade do Rio Grande do Sul

As threads de aplicações paralelas cooperam a fim de cumprir suas tarefas, dessa forma, comunicação é realizada entre elas. A latência de comunicação entre os… (more)

Subjects/Keywords: Processamento paralelo; Thread mapping; Parallel computer architectures; Desempenho : Computadores; Shared memory; Processamento distribuido; Communication; Cache memory; Cache coherence protocols; TLB

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APA (6th Edition):

Cruz, E. H. M. d. (2012). Dynamic detection of the communication pattern in shared memory environments for thread mapping. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/49758

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cruz, Eduardo Henrique Molina da. “Dynamic detection of the communication pattern in shared memory environments for thread mapping.” 2012. Thesis, Universidade do Rio Grande do Sul. Accessed October 18, 2019. http://hdl.handle.net/10183/49758.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cruz, Eduardo Henrique Molina da. “Dynamic detection of the communication pattern in shared memory environments for thread mapping.” 2012. Web. 18 Oct 2019.

Vancouver:

Cruz EHMd. Dynamic detection of the communication pattern in shared memory environments for thread mapping. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2012. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/10183/49758.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cruz EHMd. Dynamic detection of the communication pattern in shared memory environments for thread mapping. [Thesis]. Universidade do Rio Grande do Sul; 2012. Available from: http://hdl.handle.net/10183/49758

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Vaumourin, Gregory. Gestion hétérogène des données dans les hiérarchies mémoires pour l’optimisation énergétique des architectures multi-coeurs : Read Only Data Specific Management for an Energy Efficient Memory System.

Degree: Docteur es, Informatique, 2016, Bordeaux

Les problématiques de consommation dans la hiérarchie mémoire sont très présentes dans les architectures actuelles que ce soit pour les systèmes embarqués limités par leurs… (more)

Subjects/Keywords: Hiérarchie mémoire; Protocoles de cohérence; Localité des données; Cache; Memory System; Coherence protocol; Data locality; Cache Memory

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APA (6th Edition):

Vaumourin, G. (2016). Gestion hétérogène des données dans les hiérarchies mémoires pour l’optimisation énergétique des architectures multi-coeurs : Read Only Data Specific Management for an Energy Efficient Memory System. (Doctoral Dissertation). Bordeaux. Retrieved from http://www.theses.fr/2016BORD0173

Chicago Manual of Style (16th Edition):

Vaumourin, Gregory. “Gestion hétérogène des données dans les hiérarchies mémoires pour l’optimisation énergétique des architectures multi-coeurs : Read Only Data Specific Management for an Energy Efficient Memory System.” 2016. Doctoral Dissertation, Bordeaux. Accessed October 18, 2019. http://www.theses.fr/2016BORD0173.

MLA Handbook (7th Edition):

Vaumourin, Gregory. “Gestion hétérogène des données dans les hiérarchies mémoires pour l’optimisation énergétique des architectures multi-coeurs : Read Only Data Specific Management for an Energy Efficient Memory System.” 2016. Web. 18 Oct 2019.

Vancouver:

Vaumourin G. Gestion hétérogène des données dans les hiérarchies mémoires pour l’optimisation énergétique des architectures multi-coeurs : Read Only Data Specific Management for an Energy Efficient Memory System. [Internet] [Doctoral dissertation]. Bordeaux; 2016. [cited 2019 Oct 18]. Available from: http://www.theses.fr/2016BORD0173.

Council of Science Editors:

Vaumourin G. Gestion hétérogène des données dans les hiérarchies mémoires pour l’optimisation énergétique des architectures multi-coeurs : Read Only Data Specific Management for an Energy Efficient Memory System. [Doctoral Dissertation]. Bordeaux; 2016. Available from: http://www.theses.fr/2016BORD0173


Virginia Tech

30. Iqbal, Muhammad Safdar. The Multi-tiered Future of Storage: Understanding Cost and Performance Trade-offs in Modern Storage Systems.

Degree: MS, Computer Science, 2017, Virginia Tech

 In the last decade, the landscape of storage hardware and software has changed considerably. Storage hardware has diversified from hard disk drives and solid state… (more)

Subjects/Keywords: multi-tier storage; persistent memory; cloud storage; in-memory cache; multi-level cache; MapReduce; analytics workflows; pricing games; dynamic pricing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Iqbal, M. S. (2017). The Multi-tiered Future of Storage: Understanding Cost and Performance Trade-offs in Modern Storage Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/79142

Chicago Manual of Style (16th Edition):

Iqbal, Muhammad Safdar. “The Multi-tiered Future of Storage: Understanding Cost and Performance Trade-offs in Modern Storage Systems.” 2017. Masters Thesis, Virginia Tech. Accessed October 18, 2019. http://hdl.handle.net/10919/79142.

MLA Handbook (7th Edition):

Iqbal, Muhammad Safdar. “The Multi-tiered Future of Storage: Understanding Cost and Performance Trade-offs in Modern Storage Systems.” 2017. Web. 18 Oct 2019.

Vancouver:

Iqbal MS. The Multi-tiered Future of Storage: Understanding Cost and Performance Trade-offs in Modern Storage Systems. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2019 Oct 18]. Available from: http://hdl.handle.net/10919/79142.

Council of Science Editors:

Iqbal MS. The Multi-tiered Future of Storage: Understanding Cost and Performance Trade-offs in Modern Storage Systems. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/79142

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